Electronic implant

Abstract

An electronic implant for implantation in an animal body and / or a human body, comprising: – a control unit, and – a data storage unit coupled to said control unit, whereby – said data storage unit comprises machine-readable instructions which, when executed by the control unit, cause the control unit to perform a therapeutic and / or a diagnostic method, and – whereby the control unit comprises an in-memory-accelerator, with at least one neural network layer, for controlling the therapeutic and / or diagnostic method.

Description

[0001] ELECTRONIC IMPLANT

[0002] The proposed solution relates to an electronic implant for implantation in an animal body and / or a human body, configured to perform a therapeutic and / or a diagnostic method.

[0003] Such implants are well known in the field of medical technology. Typically, such an electronic implant comprises a processor and a data storage that stores machine-readable code. When the code is read and executed by the processor, the processor is caused to perform a predetermined diagnostic and / or therapeutic method. Depending on the specific application, the performance of such methods may be enhanced by the use of algorithms utilizing neural networks. For example, if a therapeutic method is to be performed in response to a specific pattern in sensed data, the method may benefit from pattern recognition via a neural network.

[0004] However, such complex algorithms require extensive computation and data transfer. For implants with a limited energy budget, the possible complexity of these algorithms is therefore very limited, or these algorithms can only be activated in a very limited time window.

[0005] Therefore, there is a constant need for improvement in electronic implants.

[0006] This task is solved by an electronic implant for implantation in an animal body and / or a human body according to claim 1. Thereby, the proposed electronic implant comprises at least: a control unit, and a data storage unit coupled to said control unit, whereby - said data storage unit comprises machine-readable instructions which, when executed by the control unit, cause the control unit to perform a therapeutic and / or a diagnostic method, and

[0007] - whereby the control unit comprises an in-memory-accelerator, with at least one neural network layer, for controlling the therapeutic and / or diagnostic method.

[0008] The in-memory accelerator for machine learning consists of a memory array for the massively parallel analog implementation of multiply accumulate (MAC) operation in the at least one individual neural network layer. The memory array contains the weights and implements the vector matrix multiplication of the at least one respective neural network layer. Thereby, the in-memory accelerator can be an integral part of the control unit or provided as a separate chip coupled to the control unit. In particular, the in-memory accelerator can be coupled via a conductive structure, such as wires or a conductive pattern of an integrated circuit board. This can improve the reliability of the coupling.

[0009] A MAC operation is an important and expensive operation, which for example can be for convolution, discrete cosine transform, Fourier transform. The MAC can perform multiplication and accumulation processes, computing the product of two numbers and adds that product to an accumulator Z: Z = Z + A x B. Many basic operations, such as the dot product, matrix multiplication, digital filter operations, and even polynomial evaluation operations, can be decomposed into MAC operations.

[0010] Analog computation offers several important advantages. Compared to digitally implemented neural networks, there is no need for memory movement for the weights of the neural network. Since the information of the weights does not have to be loaded from a memory into the processor, but is processed directly in the memory, the energy consumption can be significantly reduced. Accordingly, the proposed implant offers the possibility of using neural networks to control therapeutic and / or diagnostic methods in energy-limited implants.

[0011] Regarding the proposed solution controlling can comprise one or several of the following steps: determining if a certain step of the method is to be performed, determining at which

[0012] 24.037P-WO / 04.06.2025 time a certain step is to be performed, activating further components for treatment or sensing, such as a sensor or an electrode, analyzing collected data and monitoring proper operation of the device. Typical fields of application would be pattern recognition in bio signals of any kind e.g. QRS morphologies or electrode error patterns. Hereby, using in-memory computing can reduce power consumption while providing comparatively enormous computing power.

[0013] Reducing energy consumption can be particularly important because the amount of energy provided by a power supply, such as a battery, is usually limited. Therefore, reducing power consumption can extend the life of the implant. Since the implant may not perform the intended procedures if the power supply runs out of power, reducing power consumption can also improve the reliability of the implant.

[0014] As in a digitally implemented neural network, a layer of the neural network of the proposed implant comprises at least one neuron or input entry. Based on the at least one input entry, an output can be calculated. The calculation of the output can comprise a multiplication of the input entry with at least one weight and a summation over all weighted input entries - if there is more than one entry. This can also be referred to as applying a transfer function to the input vector. Calculating the output can also involve applying a threshold and / or an activation function, which can introduce non-linear dependencies between the sum of the weighted input entries and the output value.

[0015] The activation function can be of one of the types: Unit step (threshold), sigmoid, piecewise linear, and Gaussian. The activation function can also be a combination of at least two of the above-mentioned types. The above-mentioned types are only examples and the list is not final. The skilled person is aware that other types are conceivable and possible.

[0016] According to an embodiment of the proposed implant, the in-memory-accelerator can be configured to be disconnected from any power supply without losing weights of the neural network. Thus, do not have a need for a finite operating voltage in order to retain weights of the neural network. This can reduce the energy consumption.

[0017] 24.037P-WO / 04.06.2025 Since an energy budget of electronic implants can be limited, the proposed electronic implant can have an improved lifetime. This means that the time that the proposed implant can function as intended with a given energy budget can be extended. Also, more complex methods can be implemented.

[0018] According to another embodiment of the proposed implant, the in-memory accelerator can be realized with at least one non-volatile resistive memory element. Thus, it is possible to realize an in-memory accelerator with hardware-implemented weights that can be arranged with a high surface density. In addition, the weights are stored independently on a power supply. This allows neural network operations to be computed directly in memory. This is possible, for example, by using the at least one non-volatile resistive memory element as an electronically tunable weight of the neural network, where non-volatile resistive memories provide the inputs as voltages and record the outputs as currents.

[0019] A non-volatile resistive memory element can be any kind of electronic component whose resistance can be manipulated electronically, which is non-volatile and suitable for storing information. Sometimes non-volatile resistive memory elements are referred to as memristive elements or memristors. As part of a training the resistance of the at least one non-volatile resistive element can be set via a programming pulse.

[0020] Naturally, neural networks usually comprise more than one neuron, which means also an input vector with several entries can be considered. Thereby, summation over weighted entries of the input vector corresponds to a multiplication, also known as matrix product, of the input vector x with a weight-matrix M. Accordingly, the vector y containing the sums yj of weighted input vector entries can be calculated as: li Xtrntj = yj.

[0021] In this formulation the number of rows of the weight-matrix corresponds to the number of entries in the input vector. The number of columns of the weight-matrix defines the number of entries in the vector with the weighted sums y.

[0022] 24.037P-WO / 04.06.2025 Accordingly, the in-memory accelerator according to the proposed solution can include more than one weight factor, which means that the in-memory accelerator can include multiple non-volatile resistive memory elements. These memory elements can represent the weights of all connections between two adjacent layers. To realize such an architecture, the memory elements can be arranged in a matrix-like multi-dimensional manner.

[0023] According to another embodiment of the proposed implant the non-volatile resistive memory element can be one of the following list:

[0024] - spin torque transfer magnetic random access memory (SST-MRAM), or

[0025] - phase change memory (PCM), or

[0026] - resistive switching random access memory (ReRAM), or

[0027] - conductive bridge random access memory (CBRAM).

[0028] SST-MRAM is a variant of MRAM in which weights can be stored by magnetic memory elements. SST-MRAM uses spin-aligned ("polarized") electrons to directly manipulate the spin orientation of a ferromagnetic domain of the memory element. Specifically, as the electrons flow into a layer, their spin interacts with the ferromagnetic domain, allowing the spin of the domain itself to be adjusted.

[0029] In PCM, the heat generated by passing an electric current through a heating element can be used to either rapidly heat and quench a glass element, making it amorphous, or to hold it at its crystallization temperature range for some time, making it crystalline. PCM also has the ability to achieve a number of different intermediate states, giving it the ability to hold multiple bits in a single cell.

[0030] ReRAM works by changing the resistance across a solid-state dielectric material. A ReRAM memory element may comprise at least one memory cell. In an embodiment, the at least one cell may consist of a normally non-conductive oxide into which artificial impurities are introduced, the electrical resistance of which can be continuously adjusted to values between two extremes by an electrical voltage applied during writing.

[0031] 24.037P-WO / 04.06.2025 CBRAM is an electrochemical metallization memory that relies on redox reactions to form and dissolve a conductive filament. The state of the device is determined by the resistance across the two terminals. The presence of a filament between the terminals can result in a low resistance state, while the absence of a filament can result in a high resistance state. Incomplete filaments can result in resistance values between these extremes.

[0032] Thus, the selection of one of the above-mentioned resistive memory technologies makes it possible to design the proposed implant for specific applications. In particular, one of the above-mentioned technologies may be more useful in view of an environment and / or condition in which the implant is intended to be used.

[0033] Of course, with respect to embodiments of the proposed solution comprising more than one non-volatile resistive memory element, not all of the different elements need to be of the same type. Again, this may enhance the adaptability of the proposed implant to a particular application.

[0034] According to a preferred embodiment of the proposed implant the at least one non-volatile resistive memory element is realized with ReRAM. This can lead to a further improvement of manufacturing costs, energy consumption and reliability of the implant.

[0035] Besides the calculation of the matrix product of an input vector with a weight-matrix other calculations such as processes for providing the input vector or performing a treatment based on the output vector data can be handled digitally by a processor of the control unit. Therefore, analog-digital and digital-analog converting can be necessary.

[0036] According to an embodiment of the proposed solution, the in-memory accelerator can comprise a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC). The DAC can be connected to the processor and configured to receive the input vector of the first layer of the neural network. The digital input vector can be converted to analog voltages by the DAC. The analog voltages can be fed into the neural network provided by the in-memory accelerator. The neural network provides an analog output vector that can be converted back to digital signals using the ADC. The processor can be configured to receive the digital

[0037] 24.037P-WO / 04.06.2025 version of the output vector for further processing. This eliminates the Von Neumann bottleneck for arithmetic operations such as matrix multiplication.

[0038] Naturally, the in-memory accelerator of the proposed implant can comprise several DAC and ADC. In particular, the in-memory accelerator can comprise one DAC per entry of the input vector and one ADC per entry of the output vector.

[0039] In principle, an ADC can convert analog signals, such as currents, below a threshold to a 0 bit and signals above a threshold to a 1 bit. Thus, the ADC implements a unit-step or threshold function applied to the weighted sum of the input entries. Accordingly, an ADC can be thought of as implementing a unit-step type activation function.

[0040] According to another embodiment of the proposed implant the in-memory-accelerator can comprise at least two layer processor units configured to apply an activation function. Those units can be configured to perform calculations for all neurons of one layer.

[0041] For example, the in-memory accelerator may include a first layer processor unit for performing input layer calculations. These calculations can include receiving the input vector, multiplying with the weight-matrix, applying the activation function, parsing the output vector to the next layer processor unit. The next layer processor unit can be the last layer processor unit for performing calculations on the output layer, or a layer processor unit between the input and output for performing a hidden layer calculation.

[0042] In principle, the in-memory-accelerator of the proposed solution can comprise an arbitrary number of layer processor units each representing on layer of a neural network.

[0043] According to an embodiment of the proposed implant, the in-memory accelerator can comprise at least one weight-matrix of non-volatile memory elements arranged in a 2D array connecting two of the at least two layer processor units. Thus, the in-memory accelerator can be configured to perform the multiplication of the input vector with a weight-matrix by applying the voltages representing the entries of the input vector to input contacts of the 2D array of non-volatile memory elements. The weighted sums of the input vector entries are provided as currents at the output contacts of the 2D array.

[0044] 24.037P-WO / 04.06.2025 According to one example the non-volatile memory elements are arranged in m rows and n columns. All n memory elements of one of the m rows can be connected with one common write line. Thus, the proposed array would comprise m write lines. All m memory elements of one of the n columns can be connected with one common sense line. Thus, the proposed array would comprise n write lines. The input contacts of such an 2d-array can be represented by the m write lines. The output contacts can be represented by the n sense lines.

[0045] Accordingly, the sum over m input values xt, which are a voltages, each multiplied with a weight rriij can be performed by providing to the i-th write line and receiving the current yj of the / -th row. Thereby, the resistance R of each non-volatile resistive memory element determines the ration between voltage xtand current / at each memory element according to Ohm’s law: xt= R x yj.

[0046] The weighted sum can be adapted during training by setting the resistances of the resistive memory elements via programming pulses to match the training data.

[0047] According to an embodiment of the proposed implant the in-memory accelerator can comprise more than one weight-matrix. In particular, the number of weights-matrices can be the number of layer of the neural network minus 1.

[0048] According to another embodiment of the proposed implant the in-memory-accelerator can comprise at least one hidden-layer. This enables more complex applications of the neural network such as pattern recognition in multidimensional arrays.

[0049] According to yet another embodiment of the proposed implant the in-memory-accelerator can be configured to realize a feed-forward network or a feed-backward network.

[0050] A feed-forward network is a non-recurrent network containing an input layer, an output layer, and optionally hidden layers. Here, the signals can only travel in a direction from input

[0051] 24.037P-WO / 04.06.2025 layer to output layer. Input data is passed onto a layer of processing elements where it performs calculations. Each processing element makes its computation based upon a weighted sum of its inputs. The new calculated values then become the new input values that feed the next layer. This process continues until it has gone through all the layers and determines the output. A threshold and / or an activation function can also be used.

[0052] A feedback network, sometimes called a recurrent neural network or RNN, has feedback paths. This means that there are signals that travel in both directions. All possible connections between neurons are allowed. This type of network represents a nonlinear dynamic system that continuously changes until it reaches a state of equilibrium. Feedback networks are often used in associative memory and optimization problems, where the network searches for the best arrangement of connected factors.

[0053] According to another embodiment of the proposed implant the in-memory-accelerator is manufactured with a sub 22 nm technology. This can improve a potential for miniaturization and / or for complexity of the realized neural network.

[0054] According to another embodiment of the proposed implant the implant comprises at least one analog switch for disconnecting the in-memory-accelerator from power supply. This can reduce the power consumption in case of leakage currents through the in-memory accelerator. As the weights are realized with memory elements which do not need an operative voltage, trained weights are stored whether the in-memory accelerator is connected or disconnected.

[0055] An analog switch can also be called bilateral switch. Such a switch can conduct analog or digital signals between two terminals in either direction when it is in a “on” state. The switch can block signals between the two terminals if it is in a “off’ state. The switch can be configured to be electronically switched between the “on” and the “off’ state.

[0056] In an exemplarily embodiment the analog switch can comprise a pair of MOSFET transistors, one a N-channel device, the other a P-channel device.

[0057] 24.037P-WO / 04.06.2025 Accordingly, in an embodiment of the proposed implant the in-memory accelerator can be configured to be disconnected from a power supply of the implant. This can reduce power consumption in the case of leakage currents. In particular, the implant can be configured to detect an unused state of the in-memory accelerator. In reaction of detecting an unused state the implant can be configured to automatically disconnect the in-memory accelerator form the power supply.

[0058] According to another embodiment of the proposed implant the in-memory-accelerator can be configured to has a power consumption of less than 100 pW during continuous operation. In preferred embodiments it has less than 50 pW, further preferred less than 20 pW, further preferred less than 10 pW, even further preferred less than 5, or 2.5 or 1 pW. One conceivable and possible embodiment of the in-memory accelerator is operator with a voltage of 0.5 V and a current consumption of 5 pA performing 0.01 Terra operations per second.

[0059] According to an embodiment of the proposed implant, the in-memory accelerator can be trained with historical data of sensed signals indicating a need for a particular therapeutic treatment and / or sensed signals associated with a particular diagnosis. Such training data can be used to provide input data corresponding to input vectors that the in-memory accelerator would process in an intended operation, and output vectors that the in-memory accelerator should provide based on the given input vectors. For example, the input vectors of the training data can be associated with a biosignal, such as an ECD. The output vector of the training data can be connected to a specific pattern contained in the signal, such as an arrythmia. During training, the neural network can be set to reproduce the output vectors of the training data for the input vectors by programming the resistances of the weights accordingly.

[0060] According to an embodiment of the proposed implant the in-memory-accelerator can be an integral part of the control unit. This can reduce the size of the implant.

[0061] According to yet another embodiment of the proposed implantable in-memory accelerator, the chip is separate from the control unit. This means that the in-memory accelerator is not

[0062] 24.037P-WO / 04.06.2025 an integral part of the control unit. Nevertheless, the in-memory accelerator can be connected to the control unit via an integrated circuit board. Thus, the proposed implant can be manufactured using manufacturing techniques known to those skilled in the art. This can reduce manufacturing costs and improve the ability to replace defective parts of the implant.

[0063] According to further embodiments the proposed implant can be one of the list:

[0064] - an implantable pulse generator (IPG);

[0065] - an implantable cardioverter defibrillator (ICD),

[0066] - an implant for cardiac resynchronization therapy (CRT),

[0067] - a non-transvenous ICD,

[0068] - a neurostimulator,

[0069] - a sensor implant,

[0070] - a ventricular assist device (VAD),

[0071] - a pacemaker,

[0072] - an implantable loop recorder, or

[0073] - a medication pump.

[0074] Implantable pulse generators (IPGs) are characterized by the capability of delivering electrical pulses to tissue, primarily for therapeutic purposes. An IPG is characterized by a device which comprises a electrical pulse generator module, a processor, a memory unit and electrodes for delivering the electrical pulse.

[0075] With respect to the embodiment for IPG, the storage unit can comprise machine-readable instructions that cause the processor of the implant to perform a method for monitoring impedance changes. For this purpose, the proposed implant can comprise four electrodes. Two electrodes (also called current electrodes) deliver a constant high-frequency alternating current (about 60 - 100 kHz) with a very low amplitude (about 1 mA). This current is not felt by the implanted animal or human and does not cause any physiological interaction. Two additional electrodes (also known as measuring electrodes) are placed between the current electrodes and measure the voltage produced when the current flows through the body part. This voltage corresponds to the impedance of the body part, which changes as a function of blood flow. Blood flow can thus be recorded and analyzed. The processor can be configured to provide an input value based on the sensed data to the in-memory accelerator for detecting

[0076] 24.037P-WO / 04.06.2025 pathological derivations from normal blood. The processor can also be configured to determine, based on the output value, whether the neural network has detected pathological derivations.

[0077] An ICD is a device that is placed in the chest. It detects and stops irregular heartbeats, also known as arrhythmias. An ICD continuously monitors the heartbeat. If necessary, it delivers electrical shocks to restore a regular heart rhythm.

[0078] With respect to the embodiment as an ICD, the storage unit can comprise machine-readable instructions that cause the processor of the implant to execute a method for detecting and stopping arrhythmias. For this purpose, the proposed implant can comprise at least two electrodes configured to sense the electrical activity of the myocardium and to deliver an electrical pulse to the myocardium in response to the detection of an arrhythmia. At least one of the electrodes can be of the wire type. The processor can be configured to provide an input value based on the sensed data to the in-memory accelerator for detecting arrhythmias and to receive the output value. The processor may also be configured to determine, based on the output value, whether the neural network has detected an arrhythmia.

[0079] In terms of CRT delivery, the implant can monitor cardiac activity, detect irregularities, and correct them by delivering targeted electrical pulses. Like an ICD, a CRT implant can stop life-threatening ventricular flutter or ventricular fibrillation by delivering relatively weak and painless pacing or electrical shocks. The difference with an ICD is that a CRT device can synchronize and improve the work of the ventricles.

[0080] With respect to the CRT embodiment, the storage unit can comprise machine-readable instructions that cause the processor of the implant to execute a method for detecting and stopping irregularities in cardiac activity. For this purpose, the implant can comprise three lead wires that emit electrical impulses instead of one or two wires as in the ICD. The processor can be configured to provide an input value based on the sensed data to the inmemory accelerator for detecting irregularities in cardiac activity and to receive the output value. The processor may also be configured to determine, based on the output value, whether the neural network has detected irregularities in cardiac activity. Non-transvenous

[0081] 24.037P-WO / 04.06.2025 ICDs do not require transvenous placed electrodes. They can be inserted subcutaneously or extravascularly instead.

[0082] A neurostimulator can be implanted under the skin and send electrical impulses to nerves. For example, chronic pain that is resistant to therapy can be permanently eliminated or reduced. The electrical impulses can alter the perception of pain without damaging the nerves. With respect to the embodiment as a neurostimulator, the memory unit can comprise machine-readable instructions that cause the processor of the implant to execute a method for spinal cord stimulation (SCS) therapy.

[0083] A sensor implant is an implantable sensor that monitors certain parameters and provides the sensed data or information derived from the sensed data to an external user or to other functions of the implant itself. With respect to the embodiment as a neurostimulator, the storage unit can comprise machine-readable instructions that cause the processor of the implant to acquire data via a sensor and optionally to use the acquired data for a therapeutic or diagnostic method. For this purpose, the implant may comprise at least one sensor coupled to the processor.

[0084] A VAD is an electromechanical circulatory support device that is used to either partially or completely replace the function of a failing heart. With respect to the embodiment as a VAD, the storage unit can comprise machine-readable instructions that cause the processor of the implant to determine operating parameters, such as pump performance, based on data sensed via at least one sensor, and to operate a pump based on the operating parameters. For this purpose, the implant may comprise at least one sensor and one pump, each coupled to the processor.

[0085] A drug pump delivers a drug from an internal reservoir directly into a body, in particular into the cerebrospinal fluid space where fluid surrounds the spinal cord.

[0086] With respect to the medication pump embodiment, the storage unit can comprise machine- readable instructions that cause the processor of the implant to operate a pump to deliver the medication. For this purpose, the implant may comprise a pump and a drug reservoir.

[0087] 24.037P-WO / 04.06.2025 An implantable loop recorder is an implantable device which is capable of sensing physiological signals and storing them in memory. For instance, the stored data can be transferred to an external device or external server periodically. The data is analyzed to derive a patient’s health status for remote monitoring purposes. For instance, a cardiac loop recorder allows monitoring of cardiac signals of a patient across months. Using a cardiac loop recorder instead of 24h-holter monitor provides several advantages, as for instance having no issues for the patient in device handling, and the possibility to perform measurements over long time periods, i.e. weeks and months instead of a couple of days.

[0088] With respect to the manner in which the memory unit is coupled to the processor, "coupled" means any type of connection that can be used to transfer data between the memory unit and the processor. In particular, the memory unit can be coupled through a conductive structure, such as wires or a conductive pattern of an integrated circuit board. This can improve the reliability of the coupling and further reduce the power consumption.

[0089] Wireless coupling is also conceivable and possible. This can allow the processor and the memory unit to be located at a distance, which can improve access to the memory unit for a person.

[0090] According to one further embodiment of the proposed solution data storage unit comprises at least one non-volatile resistive memory element. Thus, the power consumption can be further improved and also an amount of stored data can be improved.

[0091] The proposed implant can comprise a power supply, in particular a battery. Thus, the amount of energy available for the method the implant is configured for, is limited.

[0092] The accompanying Figures illustrate examples of possible embodiments of the proposed solution.

[0093] They show:

[0094] 24.037P-WO / 04.06.2025 Figure 1 a schematic representation of a first embodiment of the proposed implant;

[0095] Figure 2 a schematic representation of a neural network with two layers;

[0096] Figure 3 a block diagram of an in-memory accelerator with two layers;

[0097] Figure 4 a schematic representation of a 2d-array of ReRAM memory elements;

[0098] Figure 5 a schematic representation of a neural network with three layers;

[0099] Figure 6 a schematic representation of a hardware-based realization of a neural network with three layers;

[0100] Figure 7 a schematic representation of a further embodiment of the proposed implant;

[0101] Figure 8 a schematic representation of a further embodiment of the proposed implant configured for IPG; and

[0102] Figure 9 a schematic representation of a further embodiment of the proposed implant configured as ICD.

[0103] Figure l is a schematic representation of a first embodiment the proposed electronic implant 100 for implantation in an animal body and / or a human body. The proposed electronic implant 100 comprises inter alia a control unit 110, a data storage unit 112 and a power supply 140 in form of a battery. The power supply 140 is wired with the control unit 110 to provide energy for proper function of the control unit 110 and the data storage unit 112. The data storage unit 112 is coupled to the control unit 110 and comprises machine-readable instructions which, when executed by the control unit 110, cause the control unit 110 to perform a therapeutic and / or a diagnostic method. Furthermore, the control unit 110 comprises an in-memory-accelerator, with at least one neural network 130 layer, for controlling the therapeutic and / or diagnostic method. To perform a certain method the

[0104] 24.037P-WO / 04.06.2025 proposed implant 100 can comprise further elements such as sensors or electrodes 102, 104, 105. Embodiments with different further elements are displayed in figures 7 and 8.

[0105] The in-memory accelerator 120 for machine learning consists of a memory array for the massively parallel analog implementation of multiply accumulate (MAC) operation in the at least one individual neural network 130 layer. The memory array contains the weights 137 and implements the vector matrix multiplication of the at least one respective neural network 130 layer. As shown in figure 1 the in-memory accelerator 120 can be provided as a separate chip coupled to the control unit 110 via a conductive structure, such as wires or a conductive pattern of an integrated circuit board. Alternatively, the in-memory accelerator 120 can be an integral part of the control unit 110.

[0106] Figure 2 shows a schematic representation of an artificial neural network 130 with an input layer 132 and an output layer 134 each consisting of several neurons. The individual neurons are connected to each other via a weight-matrix 138. The neurons of the input layer 132 are processed and the output is passed to the neurons of the output layer 134. Calculating the output comprises a multiplication of the input entries with the weight-matrix 138, summation over all input entries, as well as applying a threshold and / or an activation function. Accordingly, the neural network 130 of figure 2 is configured to calculate output entries, such as the output entry 136, based on all input entries, such as input entry 135 and the respective weights, such as the weight 137.

[0107] For in-memory computing, the weight-matrix 138 can be realized with a 2d array of non-volatile resistive memory elements, wherein the inputs of each memory element in each of the rows are connected to each other and the outputs of each element in each of the columns are connected to each other. Thereby, each of the resistive memory elements provides an output current based on an input voltage and a resistance of the memory element. The summed currents of all connected elements with connected outputs, i.e. all elements of a column, can be received via the wire connecting the outputs. Thus, the 2d array of non-volatile elements realizes a matrix multiplication of a weight-matrix 138 with an analog input.

[0108] 24.037P-WO / 04.06.2025 With respect to such a 2d-array, Figure 3 shows a block diagram of a possible realization of an in-memory accelerator 120 with a two-layer network. The weights are set by a 3x3 weight-matrix 138, of ReRAM resistors. Accordingly, the in-memory neural network 130 is configured to read digital input vectors with three entries and provide an digital output vector with three entries after processing.

[0109] At the beginning, the digital input vector with three entries is transformed into three analog signals 135, such as voltages. For this purpose, the in-memory neural network 130 includes three DAC 124. Each of the voltages 135 is applied to one of the neurons in the input layer 132. All three memory elements of one of the three rows are connected to a common write line. All three elements of one of the three columns are connected to a common sense line. Thus, the proposed array consists of three write lines and three sense lines. The input contacts of this 2d array are represented by the three write lines. The output contacts are the three sense lines. At the output of each memory element there is a current I which, according to Ohm's law, is based on the input voltage U and the resistance R of the memory element:

[0110] Accordingly, each memory element supplies a current equal to the supplied voltage multiplied by the inverse resistance 1 / R representing the weight. All the currents of the elements in a column are summed. Thus, the output that can be received at the j -th column corresponds to the sum of the three not necessarily identical voltages 135, where each of the voltage values 135 is weighted with the inverse resistance of the memristor in the respective row. To convert the current 136 into a digital signal, an analog-to-digital converter (ADC 128) is connected to each contact of the output layer 134. The ADCs 128 represent a threshold function. Accordingly, the ADCs 128 already implement a kind of activation function, and a layer processor unit configured to apply an activation function to the weighted sum can be omitted.

[0111] Figure 4 shows a block diagram of another possible realization of a weight-matrix 138 with an arbitrary number of rows m and columns n. Each of the non-volatile resistive memories are realized with a ReRAM resistor. Accordingly, the weight-matrix 138 is configured to

[0112] 24.037P-WO / 04.06.2025 read input vectors with m entries 135 and provides an output vector with n entries 136 after processing. In contrast to the weight-matrix 138 in Figure 3, no DAC 124 or ADC 128 is shown. Accordingly, the input vector provided to the weight-matrix 138 of Figure 4 must first be converted into an analog vector of m voltages 135. Each of these voltages is applied to one of the neurons in the input layer 132. All n memory elements 137 of one of the m rows are connected to a common write line. All m elements of one of the n columns are connected by a common sense line. Thus, the proposed array consists of m write lines and n sense lines. The input contacts of this 2d array are the m write lines. The output contacts are the n sense lines. Accordingly, the sum over all m input entries each multiplied with the weights 137 of the j-th column is performed by providing the voltages to the input contacts and receiving the current of the j-th column.

[0113] In other embodiments it is also possible to provide currents on the input side and receive voltages on the output side.

[0114] In principle, not all layer of a neural network 130 according to the proposed solution necessarily comprise the same number of neurons. In particular, the number of neurons, or entries 135, 136, in the input layer 132 and output layer 134 may differ. Furthermore, in alternative realization of the in-memory accelerator 120 the neural network 130 can comprise hidden layers 133, which are arranged in between the input layer 132 and the output layer 134.

[0115] A possible embodiment is shown in figure 5 in which a schematic representation of a neural network 130 with three layers is depicted. The network comprises an input layer 132, a hidden layer 133 and an output layer 134, each connected via weights 137 which can be represented with two weight-matrices 138, 139.

[0116] In further embodiments there also can be more than just one hidden layer 133. Thus, network architectures of any depth and any network topographies can be mapped.

[0117] Figure 6 shows a block diagram of a possible realization of an in-memory accelerator 120 with a three-layer network consisting of a three-layer processor units 125, 126, 127 and two

[0118] 24.037P-WO / 04.06.2025 weight 137 matrices. The activation functions and / or thresholds of the neurons of the input layer 132 are first mapped into a first layer processor unit 125, which also includes m DAC 124 for converting a digital input vector as provided by the processor of the control unit 110 into an analog input vector. The analog input vector is then connected to a first ReRAM weight-matrix 138, which in turn is connected to a second layer processor unit 126 for the hidden layer 133. The second layer processor unit 126 receives the entries of the output vector from the first weight-matrix 138 and applies an activation function and / or threshold. The processed output entry is then fed into a second weight-matrix 139, which is similar to a second generation input vector. The output layer of the second weight-matrix 139 is connected to the third layer processor unit 127. The third layer processor unit 127 receives the entries of the output vector from the second weight-matrix 139 and applies an activation function and / or thresholds. The third layer processor unit 127 also includes an ADC 128 for converting an analog output to a digital output that can be provided to the processor of the control unit 110.

[0119] In principle, it is also possible that the in-memory accelerator 120 comprises the ADC 128 and / or DAC 124 separately from the at least on layer processor unit 125, 126, 127.

[0120] A schematic representation of such an embodiment is shown in figure 7. The in-memory accelerator 120 comprises a DAC 124 and an ADC 128 provided separately to two layer processor units 125, 126. The DAC 124 is directly or indirectly coupled to the processor of the control unit 110. The DAC 124 is configured to receive a digital input vector of the processor and convert said vector into an analog vector. The entries of such an analog vector are represented by currents or voltages. The DAC 124 is connected to the first layer processor unit 125 and configured to send the analog input vector to said processor unit 125. The first layer processor unit 125 comprises a weight-matrix 138 and is configured to perform the transfer function as well as optionally an activation function and / or thresholds. Thereby, the first layer processor unit 125 calculates an output vector. The first layer processor unit 125, is connected to a second layer processor unit 126 and configured to send the output vector to the second layer processor unit 126. The second layer processor unit 126 receives the output vector as input vector. The second layer processor unit 126 is configured to apply an activation function and / or thresholds and thus calculates a final analog output vector.

[0121] 24.037P-WO / 04.06.2025 Furthermore, the second layer processor unit 126 is connected to a ADC 128 and configured to send the final analog output vector to the ADC 128 in order to convert the analog output vector to a digital output vector. The ADC 128 is directly or indirectly coupled to the processor of the control unit 110 and configured to send the digital output vector to the processor.

[0122] Figure 8 shows another embodiment of the proposed implantable pulse generator (IPG) 100 . In contrast to the embodiment of figure 7 the embodiment of figure 8 comprises an analogue switch 122 for disconnecting the in-memory accelerator 120 from the power supply 140. The control unit 110 is also configured to detect leakage of the in-memory accelerator 120 and to detect that the in-memory accelerator 120 unit is unused. In reaction of one of the aforementioned detection events the control unit 110 disconnects the in-memory accelerator 120 via the analog switch 122.

[0123] Furthermore, the embodiment of figure 8 also comprises four electrodes 102, 104 connected to the component interface 150. The component interface 150 is connected to the control unit 110 and the power supply 140. The control unit 110 is configured to perform instructions stored on the data storage unit 112 and in accordance with the instructions to perform a method which includes feeding a constant high-frequency alternating current with a very low amplitude into tissue of a body via the outer electrodes 102. The method also includes measuring the voltage that arises when the current flows through the body section via the electrodes 104. This voltage corresponds to the impedance of the body section, which changes depending on the blood flow. The measured voltages can be analyzed via the inmemory accelerator 120 in order to detect anomalies.

[0124] Figure 9 shows another embodiment of the proposed implant 100 which is configured as implantable cardioverter defibrillator (ICD). Thereby, in contrast to the embodiment shown in figure 8 the ICD implant 100 comprises only two electrodes 105 connected to the component interface 150. Via the electrodes 105 the implant 100 is configured to sense the electrical activity of the heart muscle and to deliver an electric pulse to the heart muscle in reaction of detecting an arrhythmia.

[0125] 24.037P-WO / 04.06.2025 In principle, the data storage unit 112 can comprise several non-volatile memory elements, which can be arranged in a multidimensional array as known to the skilled person from traditional memory elements. Independent of a number of non-volatile resistive memory elements, the at least one memory element can be a spin torque transfer magnetic random access memory (SST-MRAM) element, or a phase change memory (PCM) element, or a resistive switching random access memory (ReRAM) element, or a conductive bridge random access memory (CBRAM) element.

[0126] In alternative embodiments the data storage unit 112 comprises a non-volatile resistive memory element. A non-volatile resistive memory element can be any kind of electronic component whose resistance can be manipulated electronically, is non-volatile and suitable for storing information. Sometimes non-volatile resistive memory elements are referred to as memristive elements or memristors. The proposed solution is not limited to the embodiments discussed in detail here. Rather, the proposed solution also comprises any combination of features of the discussed embodiments, insofar as these can be combined in executable references for the person skilled in the art.

[0127] 24.037P-WO / 04.06.2025 Reference numerals

[0128] 100 implant

[0129] 102, 104, 105 electrode

[0130] 110 control unit

[0131] 112 data storage unit

[0132] 120 in-memory accelerator

[0133] 122 switch

[0134] 124 DAC

[0135] 125, 126, 127 layer processor unit

[0136] 128 ADC

[0137] 130 neural network

[0138] 132 input layer

[0139] 133 hidden layer

[0140] 134 output layer

[0141] 135 input entry

[0142] 136 output entry

[0143] 137 weight

[0144] 138, 139 weight-matrix

[0145] 140 power supply

[0146] 150 component interface

[0147] 24.037P-WO / 04.06.2025

Claims

Claims1. An electronic implant (100) for implantation in an animal body and / or a human body, comprising:- a control unit (110), and- a data storage unit (112) coupled to said control unit (110), whereby- said data storage unit (112) comprises machine-readable instructions which, when executed by the control unit (110), cause the control unit (110) to perform a therapeutic and / or a diagnostic method, and- whereby the control unit (110) comprises an in-memory-accelerator, with at least one neural network (130) layer, for controlling the therapeutic and / or diagnostic method.

2. The electronic implant (100) according to any one of the preceding claims, characterized in that, the in-memory-accelerator is configured to be disconnected from any power supply (140) without losing weights (137) of the neural network (130).

3. The electronic implant (100) according to any one of the preceding claims, characterized in that, the in-memory-accelerator is realized with at least on nonvolatile resistive memory element.

4. The electronic implant (100) according to claim 3, characterized in that, the non-volatile resistive memory element is a ReRAM element.

5. The electronic implant (100) according to any one the preceding claims, characterized in that, the in-memory-accelerator comprises a digital-analog-converter (124) and an analog-digital-converter (128).

6. The electronic implant (100) according to any one the preceding claims, characterized in that, the in-memory-accelerator comprises at least two layer processor units (125, 126, 127) configured to apply an activation function.24.037P-WO / 04.06.20257. The electronic implant (100) according to claim 6, characterized in that, the in- memory-accelerator comprises at least one weight-matrix (138, 139) of non-volatile memory elements arranged in a 2d-array connecting two of the at least two layer processor units (125, 126, 127).

8. The electronic implant (100) according to any one the preceding claims, characterized in that, the in-memory-accelerator comprises at least one hidden-layer.

9. The electronic implant (100) according to any one the preceding claims, characterized in that, the in-memory-accelerator is configured to realize a feed-forward network or a feed-backward network.

10. The electronic implant (100) according to any one of the preceding claims, characterized in that, the in-memory-accelerator is manufactured with a sub 22 nm technology.

11. The electronic implant (100) according to any one the preceding claims, characterized in that, the implant (100) comprises at least one analog switch (122) for disconnecting the in-memory-accelerator from power supply (1 0).

12. The electronic implant (100) according to any one of the preceding claims, characterized in that, the in-memory-accelerator is configured to has a power consumption of less than 100 pW during continuous operation.

13. The electronic implant (100) according to any one of the preceding claims, characterized in that, the in-memory-accelerator was trained with historic data of sensed signals indicating a need of certain therapeutic treatment and / or sensed signals connected with a certain diagnosis.

14. The electronic implant (100) according to any one of the preceding claims, characterized in that, the in-memory-accelerator is an integral part of the control unit (HO).24.037P-WO / 04.06.202515. The electronic implant (100) according to any one of the preceding claims, characterized in that, the implant (100) is one of the list:- an implantable pulse generator (IPG) (100), - an implantable cardioverter defibrillator (ICD),- an implant (100) for cardiac resynchronization therapy (CRT),- a Non-transvenous ICD,- a neurostimulator,- a sensor-implant (100), - a ventricular assist device (VAD),- a pacemaker,- an implantable loop recorder, or- a medication pump.24.037P-WO / 04.06.2025

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