Electronic implant

Abstract

An electronic implant for implantation in an animal body and / or a human body, comprising: – a processor, and – a data storage unit coupled to said processor, whereby – said data storage unit comprises machine-readable instructions which, when executed by the processor, cause the processor to perform a therapeutic and / or a diagnostic method, and – said data storage unit comprises at least one non-volatile resistive memory element.

Description

[0001] ELECTRONIC IMPLANT

[0002] The proposed solution relates to an electronic implant for implantation in an animal body and / or a human body, configured to perform a therapeutic method and / or a diagnostic method.

[0003] Such implants are well known in the field of medical technology. Typically, such an electronic implant comprises a processor and a data storage that stores machine-readable code. When the code is read and executed by the processor, the processor is caused to perform a predetermined diagnostic and / or therapeutic method. The data storage can be realized with static random access memory (SRAM) elements and / or NAND flash memory. For complex medical procedures, the limited storage density and power consumption of such storage technologies can be a limiting factor.

[0004] Therefore, there is a constant need for improvement in electronic implants.

[0005] This task is solved by an electronic implant for implantation in an animal body and / or a human body according to claim 1. Thereby, the proposed electronic implant comprises at least:

[0006] - a processor, and

[0007] - a data storage unit coupled to said processor, whereby

[0008] - said data storage unit comprises machine-readable instructions which, when executed by the processor, cause the processor to perform a therapeutic and / or a diagnostic method, and

[0009] - said data storage unit comprises at least one non-volatile resistive memory element, wherein the non-volatile resistive memory element is a memristor. A non-volatile resistive memory element can be any kind of electronic component whose resistance can be manipulated electronically, which is non-volatile and suitable for storing information. Sometimes non-volatile resistive memory elements are referred to as memristive elements or memristors. Compared to SRAM, non-volatile resistive memory elements do not have a need for a finite operating voltage in order to retain data stored on the memory elements. With respect to NAND flash, resistive memory elements can offer shorter read and write access times, a longer lifetime and a higher storage density. Since an energy budget of electronic implants can be limited, by using non-volatile resistive memory the proposed electronic implant can exhibit an improved service life. This means that the time during which the proposed implant can function as intended with a given energy budget can be extended. Also, the amount of data that can be stored on a memory of a given size can be improved. This can increase the potential for miniaturization and / or implementation of more complex methods.

[0010] With respect to the manner in which the storage unit is coupled to the processor, "coupled" means any type of connection that can be used to transfer data between the storage unit and the processor. In particular, the storage unit can be coupled via a conductive structure, such as wires or a conductive pattern of an integrated circuit board. This can improve the reliability of the coupling and further reduce the power consumption.

[0011] Wireless coupling is also conceivable and possible. This would allow the processor and the storage unit to be placed at a distance from each other, which could improve a person's access to the storage unit.

[0012] In case of more than one memory element, at least one of the memory elements but not necessarily all of them can be non-volatile resistive memory elements. If not all of the several memory elements are non-volatile resistive memory elements, the remaining memory elements can be of another memory type such as NAND flash and / or SRAM. This allows the memory unit to be designed for specific types of data to be stored and accessed by the processor. If the storage unit comprises several memory elements they can be arranged in a multidimensional array as known to the skilled person from traditional memory elements. In particular they can be arranged as a 2 dimensional (2d) Array.

[0013] According to an embodiment of the proposed solution the storage unit comprises at least one volatile memory element such as SRAM for data to be temporary stored and a at least another non-volatile resistive element for data to be permanent stored. This can improve manufacturing costs and / or a wiring and / or a data access time.

[0014] According to another embodiment of the proposed solution, the non-volatile resistive memory element can be one of the following list:

[0015] - spin torque transfer magnetic random access memory (SST-MRAM), or

[0016] - phase change memory (PCM), or

[0017] - resistive switching random access memory (ReRAM), or

[0018] - conductive bridge random access memory (CBRAM).

[0019] SST-MRAM is a variant of MRAM in which data can be stored by magnetic memory elements. SST-MRAM uses spin-aligned ("polarized") electrons to directly manipulate the spin orientation of a ferromagnetic domain of the memory element. Specifically, when electrons enter a layer, their spin interacts with the ferromagnetic domain, allowing the spin of the domain itself to be adjusted.

[0020] In PCM, the heat generated by passing an electric current through a heating element can be used to either rapidly heat and quench a glass element, making it amorphous, or to hold it in its crystallization temperature range for some time, making it crystalline. PCM also has the ability to achieve a number of different intermediate states, giving it the ability to hold multiple bits in a single cell.

[0021] ReRAM works by changing the resistance across a solid state dielectric material. A ReRAM memory element may comprise at least one memory cell configured to store the information quantity of one bit. In one embodiment, the at least one cell can consist of a normally non- conductive oxide in which artificial impurities are introduced whose electrical resistance can be switched between two extreme values by an electrical voltage applied during writing. The two resistance values represent the two possible logical 0 or logical 1 states of a bit.

[0022] CBRAM is an electrochemical metallization memory that relies on redox reactions to form and dissolve a conductive filament. The state of the device is determined by the resistance across the two terminals. The presence of a filament between the terminals can produce a low resistance state, while the absence of a filament can produce a high resistance state.

[0023] The selection of one of the above-mentioned resistive memory technologies allows the design of the proposed implant for specific applications. In particular, one of the above- mentioned technologies may be more useful in light of an environment and / or condition in which the implant is intended to be used.

[0024] Naturally, with respect to embodiments of the proposed solution comprising more than one non-volatile resistive memory element not all of the several elements have to be of the same type. Again, this might improve the adaptability of the proposed implant to a certain application.

[0025] According to a preferred embodiment of the proposed implant the at least one non-volatile resistive memory element is realized with ReRAM. This can lead to a further improvement of manufacturing costs, energy consumption and reliability of the implant. It is also possible that the future availability of common memory devices such as SRAM or FLASH will deteriorate. Therefore, the use of non-volatile resistive memory devices can improve manufacturing and maintenance capabilities.

[0026] In order to use non-volatile resistive memory elements in implant systems, additional measures can be implemented to improve reliability and current consumption over the entire service life of the implant.

[0027] Accordingly, in an embodiment of the proposed implant the storage unit can be configured to be disconnected from a power supply of the implant. This can reduce power consumption in the case of leakage currents. In particular, the implant can be configured to detect an unused state of the storage unit. In reaction of detecting an unused state the implant can be configured to automatically disconnect the storage unit form the power supply.

[0028] Reducing energy consumption can be particularly important because the amount of energy provided by the power supply is usually limited. Therefore, reducing power consumption can extend the life of the implant. Since the implant may not perform the intended procedures if the power supply runs out of power, reducing power consumption can also improve the reliability of the implant.

[0029] According to one embodiment of the proposed implant, the implant can be configured to detect an unused state if the storage unit is not accessed for a predetermined time, for example 2s. Thus, detection of an unused state can be implemented simply by counting a time since the last access to the storage unit. Thereby, it is conceivable and possible that one element of the implant, in particular the processor or the storage unit or a disconnecting unit, is configured to detect accesses to the storage unit, count the time since the last access, compare the counted time with a predetermined time limit and disconnect the storage unit if the counted time reaches the time limit. Said element can also be configured to connect the storage unit if after disconnecting the storage unit an access, or an access attempt, is detected.

[0030] Additionally or alternatively, the implant can be configured to detect an unused state if no access to the storage unit is predicted for a predetermined time, for example 2s. Thus, if after a first access no second access occurs for a time longer than the predetermined time, the storage unit can be disconnected immediately after the first access without waiting the predetermined time. This can improve power consumption.

[0031] It is conceivable and possible that an element of the implant, in particular the processor or the storage unit or a disconnecting unit of the implant, is configured to predict a time until the next access to the storage unit, to compare the predicted time with a predetermined time limit and to disconnect the storage unit if the predicted time exceeds the time limit. Said element can also be configured to connect the storage unit if after disconnecting the storage unit an access, or an access attempt, is detected. According to another embodiment of the proposed implant, the storage unit can comprise at least one analog switch for disconnecting the storage unit from the power supply and / or for disconnecting an individual non-volatile resistive memory element from the power supply. Thereby, the disconnectability from the power supply can be realized in a simple and cost- effective manner.

[0032] An analog switch can also be called bilateral switch. Such a switch can conduct analog or digital signals between two terminals in either direction when it is in a “on” state. The switch can block signals between the two terminals if it is in a “off’ state. The switch can be configured to be electronically switched between the “on” and the “off’ state.

[0033] In an exemplarily embodiment the analog switch can comprise a pair of MOSFET transistors, one a N-channel device, the other a P-channel device.

[0034] In case of several non-volatile resistive memory elements the implant might comprise several analog switches, each configured to disconnect one of the non-volatile resistive memory elements. Thus, the implant might comprise a mechanism for the leakage current suppression for individual elements of the storage unit. The implant can be configured to detect leakage of individual elements and in reaction of a detection shut the respective element down by disconnecting it via the analog switch of the element.

[0035] According to another embodiment of the proposed implant the storage unit can comprise a programmable control unit for controlling a maximum power consumption and / or an access time limit. Access time limit can relate to at least one certain time slot the storage unit is accessible and / or the predetermined time for detecting an unused state and / or a minimal time between two access. Accordingly, setting the access time limit can result in lower or higher power consumption and affect a time in which data is provided from the storage unit. In this way, the control unit can be used to balance the power consumption and performance of the implant.

[0036] The balance between power consumption and performance can be changed by programming the control unit. For example, different conditions of the implant and / or the body in which the implant is implanted can be considered to favor either higher performance or lower power consumption. In particular, there may be reasons to change the balance at different times of use. For example, at the end of the service life, low power consumption may be preferred to avoid failure just before the implant can be replaced.

[0037] The maximum number of write cycles of non-volatile resistive memory can be limited. As very different types of data can be stored in this memory, there can be areas of the at least one memory element with very frequent and very infrequent write accesses. It is therefore advisable to balance the number of write accesses over the runtime by automatically swapping memory areas with frequent write accesses and memory areas with infrequent write accesses.

[0038] Therefore, according to another embodiment of the implant the storage unit is configured for a write cycle address balancing. This means, that the implant can be configured to actively control to which areas of the at least one non-volatile resistive memory element data is written. Thereby, degradation of memory areas can be actively controlled, for example via controlling addresses for write operations via address mapping.

[0039] For this purpose, the proposed implant can comprise a write address controller coupled to the storage, said address controller is configured to control addresses for write operations. In particular, the proposed implant can be configured for mapping addresses by hardware, whereby the addresses are also automatically remapped so that mapping does not have to be taken into account by software.

[0040] According to another embodiment of the implant the proposed implant is configured to detect defective memory elements and / or and memory elements with excessive leakage current during runtime and to disconnect defective and / or leaking memory elements. Additionally, the disconnected memory elements can be replaced by “spare elements”, for example via remapping of addresses.

[0041] According to another embodiment of the proposed implant the storage unit can be realized with an auto mapping range for allocation of memory locations on hardware side. This can reduce time for accessing data and can reduce energy consumption as memory mapping is not performed via energy consuming software processes.

[0042] According to another embodiment of the proposed implant the storage unit can be realized with a hardware based write protection. This means that at least a part of the at least one memory element can be protected with respect to write operations. This can improve the reliability.

[0043] According to another embodiment of the proposed implant, the implant can comprise a built- in self-test. Via the built-in self-test, the implant can be configured to monitor an operability of the implant. This can include detecting whether an energy level is below a predetermined limit, and / or whether a number of defective / leaking memory elements exceeds a predetermined limit, and / or whether the energy consumption exceeds a predetermined limit, and / or whether the machine-readable instructions for performing the therapy or diagnoses are present and executable as intended. In response to a malfunction being detected during the built-in self-test, the proposed implant may be configured to send a signal indicating the detected malfunction. For example, the implant may be configured to send an audible signal, which may be useful for a built-in preimplantation test.

[0044] According to yet another embodiment of the storage unit comprises a separate memory chip. This means, that the storage unit is not an integral part of a system chip which comprises also the processor. Nevertheless, the separate memory chip can be connected to the processor via an integrated circuit board, in particular the processor and the memory both can be part of a system on a chip. Thus, the proposed implant might be produced using manufacturing technologies well known to the skilled person. This can reduce manufacturing costs and improve a possibility of replacing defect parts of the implant.

[0045] According to another embodiment of the proposed implant the storage unit is an integral part of the processor unit. This means, that the storage unit can be an integral part of a system chip which comprises also the processor. This can reduce the size of the implant. According to another embodiment of the proposed implant, the implant can comprise a storage control unit for automatic error detection and correction. In particular, the storage control unit can be configured to detect and correct permanent data and / or leakage errors. In particular, the storage control unit can be a part of the storage unit.

[0046] According to another embodiment of the proposed implant, the at least one memory element is realized with a sub 22 nm technology. This may increase the potential for miniaturization and / or the amount of data that can be stored by the memory device.

[0047] According to another embodiment of the proposed implant, the storage unit can comprise a low pin count interface.

[0048] According to another embodiment of the proposed implant, the storage unit can comprise a serial I / O-Interface with at least one, in particular two, preferred four ports. Via the I / O- interface the data storage unit can be coupled to the processor.

[0049] In addition, the implant can comprise a component interface for easy integration of further components used for the therapeutic and / or diagnostic method of the implant. The component interface can be coupled to the processor and the power supply. The processor can be configured to control a power supply provided via the component interface and can be configured to receive data from a component connected to the component interface. Various functional components can be integrated into the implant via the component interface. Thus, different embodiments of the proposed implant, which can be configured to perform different methods, can share some common parts. This can reduce manufacturing and development costs. In particular, the common parts can be the processor and / or the data storage unit.

[0050] According to another embodiment of the proposed implant the storage unit comprises a cascade of non-volatile resistive memory elements. This can enable in-memory computing for multiply accumulate (MAC) operations. By in-memory computing the energy consumption can be further improved. A MAC operation is an important and expensive operation, which for example can be for convolution, discrete cosine transform, Fourier transform. The MAC can perform multiplication and accumulation processes, computing the product of two numbers and adds that product to an accumulator Z: Z = Z + A x B. Many basic operations, such as the dot product, matrix multiplication, digital filter operations, and even polynomial evaluation operations, can be decomposed into MAC operations.

[0051] According to another embodiment of the proposed implant all non-volatile resistive elements of the cascade can be identical memory elements. This can reduce manufacturing costs and improve performance for in-memory computing.

[0052] According to another embodiment of the proposed implant, the storage unit can be realized with a redundant array of independent memory elements (RAID). Thus, the reliability of the proposed implant can be improved. In particular the storage unit can be realized with a RAID 0, RAID 1, RAID 4 or RAID5.

[0053] In particular the storage unit can be realized with a hardware raid with a raid controller. This can improve the energy consumption.

[0054] Usually, a filesystem is typically implemented in software as part of the operating system. However, according to another embodiment of the proposed implant the storage unit can be realized with a hardware-filesystem. Thereby, the filesystem can be migrated into hardware. Hereby, the data do not necessarily have to go through all of the traditional layers of an operating system, such as driver and filesystem interface, just to have the application then forward it to the processor. Instead, the processor can simply open the file and access it directly. This frees the processor from handling I / O requests.

[0055] The proposed implant can comprise a power supply, in particular a battery. Thus, the amount of energy available for the method the implant is configured for, is limited.

[0056] According to another embodiment of the proposed implant, the implant is one of the following list: - an implantable pulse generator (IPG),

[0057] - an implantable cardioverter defibrillator (ICD),

[0058] - an implant for cardiac resynchronization therapy (CRT),

[0059] - a non-transvenous ICD,

[0060] - a neurostimulator,

[0061] - a sensor implant,

[0062] - a ventricular assist device (VAD),

[0063] - a pacemaker,

[0064] - an implantable loop recorder, or

[0065] - a medication pump.

[0066] Implantable pulse generators (IPGs) are characterized by the capability of delivering electrical pulses to tissue, primarily for therapeutic purposes. An IPG is characterized by a device which comprises a electrical pulse generator module, a processor, a memory unit and electrodes for delivering the electrical pulse.

[0067] With respect to the embodiment for IPG, the storage unit can comprise machine-readable instructions that cause the processor of the implant to perform a method for monitoring impedance changes. For this purpose, the proposed implant may comprise four electrodes. Two electrodes (also called current electrodes) deliver a constant high-frequency alternating current (about 60 - 100 kHz) with a very low amplitude (about 1 mA). This current is not felt by the implanted animal or human and does not cause any physiological interaction. Two additional electrodes (also known as measuring electrodes) are placed between the current electrodes and measure the voltage produced when the current flows through the body part. This voltage corresponds to the impedance of the body part, which changes as a function of blood flow. In this way, blood flow can be recorded and analyzed.

[0068] An ICD is a device that is placed in the chest. It detects and stops irregular heartbeats, also known as arrhythmias. An ICD constantly monitors the heartbeat. If necessary, it delivers electrical shocks to restore a normal heart rhythm. With respect to the embodiment as an ICD, the storage unit can comprise machine-readable instructions that cause the processor of the implant to execute a method for detecting and stopping arrhythmias. For this purpose, the proposed implant can comprise at least two electrodes configured to sense the electrical activity of the myocardium and to deliver an electrical pulse to the myocardium in response to the detection of an arrhythmia. At least one of the electrodes can be of the wire type.

[0069] In terms of performing CRT, the implant can monitor cardiac activity, detect irregularities, and correct them by delivering targeted electrical pulses. Like an ICD, a CRT implant can stop life-threatening ventricular flutter or ventricular fibrillation by delivering relatively weak and painless pacing or electrical shocks. The difference with an ICD is that a CRT device can synchronize and improve the work of the ventricles.

[0070] With respect to the CRT embodiment, the storage unit can comprise machine-readable instructions that cause the processor of the implant to execute a method for detecting and stopping irregularities in cardiac activity. For this purpose, the implant can comprise three lead wires that emit electrical impulses instead of one or two wires as in the ICD.

[0071] Non-transvenous ICDs do not require transvenous leads. Instead, they can be placed subcutaneously or extravascularly.

[0072] A neurostimulator can be implanted under the skin and send electrical impulses to nerves. For example, chronic pain that is resistant to therapy can be permanently eliminated or reduced. The electrical impulses can alter the perception of pain without damaging the nerves. With respect to the embodiment as a neurostimulator, the memory unit can comprise machine-readable instructions that cause the processor of the implant to execute a method for spinal cord stimulation (SCS) therapy.

[0073] A sensor implant is an implantable sensor that monitors certain parameters and provides the sensed data or information derived from the sensed data to an external user or to other functions of the implant itself. With respect to the embodiment as a neurostimulator, the storage unit can comprise machine-readable instructions that cause the processor of the implant to acquire data via a sensor and optionally to use the acquired data for a therapeutic or diagnostic method. For this purpose, the implant may comprise at least one sensor coupled to the processor.

[0074] A VAD is an electromechanical circulatory support device that is used to either partially or completely replace the function of a failing heart. With respect to the embodiment as a VAD, the storage unit can comprise machine-readable instructions that cause the processor of the implant to determine operating parameters, such as pump performance, based on data sensed via at least one sensor, and to operate a pump based on the operating parameters. For this purpose, the implant may comprise at least one sensor and one pump, each coupled to the processor.

[0075] A drug pump delivers a drug from an internal reservoir directly into a body, in particular into the cerebrospinal fluid space where fluid surrounds the spinal cord.

[0076] With respect to the medication pump embodiment, the storage unit can comprise machine- readable instructions that cause the processor of the implant to operate a pump to deliver the medication. For this purpose, the implant may comprise a pump and a drug reservoir.

[0077] An implantable loop recorder is an implantable device which is capable of sensing physiological signals and storing them in memory. For instance, the stored data can be transferred to an external device or external server periodically. The data is analyzed to derive a patient’s health status for remote monitoring purposes. For instance, a cardiac loop recorder allows monitoring of cardiac signals of a patient across months. Using a cardiac loop recorder instead of 24h-holter monitor provides several advantages, as for instance having no issues for the patient in device handling, and the possibility to perform measurements over long time periods, i.e. weeks and months instead of a couple of days.

[0078] According to another embodiment of the proposed implant the storage unit can comprise at least one of the list:

[0079] - diagnostic data,

[0080] - executable backup code which is executed in the case a malfunction is detected, - executable code relating to a specific operating mode that is loaded when the operating mode is changed to the specified operating mode,

[0081] - cybersecurity keys or certificates,

[0082] - artificial intelligence algorithms for reloading,

[0083] - executable code with complex algorithms that are rarely used.

[0084] The accompanying Figures illustrate examples of possible embodiments of the proposed solution.

[0085] They show:

[0086] Figure 1 a schematic representation of a first embodiment of the proposed implant;

[0087] Figure 2 a schematic representation of a further embodiment of the proposed implant configured for IPG;

[0088] Figure 3 a schematic representation of a further embodiment of the proposed implant configured as ICD;

[0089] Figure 4 a schematic representation of a further embodiment of the proposed implant configured as medication pump; and

[0090] Figure 5 a schematic representation of a 2d-array of ReRAM memory elements.

[0091] Figure l is a schematic representation of a first embodiment the proposed electronic implant 100 for implantation in an animal body and / or a human body. The proposed electronic implant 100 comprises a processor 110 which is coupled with a data storage unit 120 and a power supply 130 in form of a battery. The power supply 130 is wired with both the processor 110 and the data storage unit 120 in order to provide energy for proper function. The data storage unit 120 comprises machine-readable instructions which, when they are executed by the processor 110, cause the processor 110 to perform a therapeutic and / or a diagnostic method. To perform a certain method the proposed implant 100 can comprise further elements such as sensors, electrodes 102, 104, 105, pumps 106 or medication reservoirs 108. Embodiments with different further elements are displayed in Figures 2 to 4.

[0092] In all embodiments in Figures 1 to 4 the data storage unit 120 comprises a non-volatile resistive memory element 1200, 12i0, 12n0, 120j, 120n. A non-volatile resistive memory element 1200, 12i0, 12n0, 120j, 120n can be any kind of electronic component whose resistance can be manipulated electronically, which is non-volatile and suitable for storing information. Sometimes non-volatile resistive memory elements 1200, 12i0, 12n0, 120j, 120n are referred to as memristive elements or memristors.

[0093] In alternative embodiments the power supply 130 may also be wired only with the processor 110 whereby the processor 110 is configured to provide the energy needed by the data storage device.

[0094] Furthermore, the proposed implant 100 can be configured to disconnect the data storage unit 120 from the power supply 130 in order to reduce power consumption in the case of leakage currents or if the data storage unit 120 is in an unused state. In case of several memory elements 1200, 12i0, 12n0, 120j, 120n the implant 100 can be configured to disconnect each memory element 1200, 12i0, 12n0, 120j, 120n individually.

[0095] In accordance with this aspect, Figure 2 shows another embodiment of the proposed implantable pulse generator 100. In contrast to the embodiment of Figure 1 the embodiment of Figure 2 comprises an analog switch 122 for disconnecting the storage unit 120 from the power supply 130. The embodiment of Figure 2 is also configured to detect leakage of the data storage unit 120 and to detect that the data storage unit 120 is unused. In reaction of one of the aforementioned detection events the implant 100 disconnects the data storage unit 120 via the analog switch 122. In case of several memory elements 1200, 12i0, 12n0, 120j, 120n the implant 100 can be configured to detect leakage of the individual memory elements 1200, 12i0, 12n0, 120j, 120n and to disconnect only the respective leaking memory element 1200, 12i0, 12n0, 120j, 120n. The embodiment of Figure 2 further comprises a programmable control unit 124 for controlling a maximum power consumption and / or an access time limit. Setting the access time limit can result in lower or higher power consumption and affect a time in which data is provided from the storage unit 120. In this way, the control unit 124 can be used to balance power consumption and performance of the implant 100. The balance between power consumption and performance can be changed by programming the control unit 124. For example, different conditions of the implant 100 and / or of the organism in which the implant 100 is implanted can be taken into account in order to prefer either higher performance or lower power consumption. In particular, there may be reasons to change the balance at different times of operation. The control unit 124 is realized as part of the storage unit 120, but could also be realized as a separate element or part of the processor 110 or as a software module.

[0096] The embodiment depicted in Figure 2 also exhibits a write address controller 126 realized as part of the data storage unit 120. The write address controller 126 is configured to control addresses for write operations by mapping addresses so that mapping does not have to be taken into account by software in particular the software running on the processor 110. Just as the control unit 124 the write address controller 126 can be realized also as separate component as long as it is coupled to other parts of the implant 100 such that the controller can perform hardware address mapping.

[0097] Besides the switch 122, the control unit 124 and the write address controller 126, the embodiment of Figure 2 also differs by a component interface 140 and four electrodes 102, 104, to the component interface 140. The component interface 140 is connected to the processor 110 and the power supply 130. The processor 110 is configured to execute instructions stored on the data storage unit 120 and in accordance with the instructions to perform a method which includes feeding a constant high-frequency alternating current with a very low amplitude into tissue of a body via the outer electrodes 102. The method also includes measuring the voltage that arises when the current flows through the body section. This voltage corresponds to the impedance of the body section, which changes depending on the blood flow. Via the electrodes 104 the implant 100 is configured to record and analyze the blood flow. Figure 3 shows another embodiment of the proposed implant 100 configured as an implantable cardioverter defibrillator (ICD). In contrast to the embodiment shown in Figure 2, the ICD implant 100 comprises only two electrodes 105 connected to the device. Via the electrodes 105, the implant 100 is configured to sense the electrical activity of the heart muscle and to deliver an electrical pulse to the heart muscle in response to the detection of an arrhythmia.

[0098] Figure 4 shows another embodiment of the proposed implant 100 configured as a medical pump 106. The implant 100 comprises a component interface 140 as in the embodiments of Figures 2 and 3. A pump 106 is connected to the component interface 140, which in turn is connected to a power supply 130 and a drug reservoir 108. The processor 110 is configured to execute some instructions received from the storage data unit and, in response to executing them, to perform a method including determining whether and how much drug should be injected into a body. In accordance with the determination, the processor 110 sends a signal to the pump 106 to deliver the determined amount of drug. The pump 106 is configured to receive the signal, to convey drug in accordance with the determined amount, and to deliver the amount into the body.

[0099] According to other embodiments the functional components such as the pump 106 and the electrodes 102, 104, 105 might be directly coupled to the processor 110. Thus, no component interface 140 would be needed.

[0100] Regarding all embodiments of Figures 1 to 4 the data storage unit 120 can comprise several non-volatile memory elements 1200, 12i0, 12n0, 120j, 120n, which can be arranged in a multidimensional array as known to the skilled person from traditional memory elements 1200, 12i0, 12n0, 120j, 120n. Independent of a number of non-volatile resistive memory elements 1200, 12i0, 12n0, 120j, 120n, the at least one memory element 1200, 12i0, 12n0, 120j, 120n can be a spin torque transfer magnetic random-access memory (SST-MRAM) element, or a phase change memory (PCM) element, or a resistive switching random access memory (ReRAM) element, or a conductive bridge random access memory (CBRAM) element. Figure 5 shows a schematic representation of m times n ReRAM elements arranged in a 2d- array. Thus, each memory element 1200, 12i0, 12m0, 120j, 120n can be allocated with its number of row i, or row index, and number of column j, or column index. Thereby, the number of row i is in the interval [0,m] and the number of column j is in the interval [0,n], In the embodiment shown in Figure 5 each memory element 1200, 12i0, 12m0, 120j , 120n in the same row is connected to a common bit line BLO, BLi, BLm and write line WLO, WLi, WLm. For example, the memory elements 1200, 120j, 120n are in the O-th row sharing the bit line BLO and the write line WLO. All memory elements 1200, 12i0, 12n0, 120j, 120n of the same column are connected to a common sense line SLO, SLj, SLn. Accordingly, the memory elements 1200, 12i0, 12m0 are arranged in the O-th column sharing on sense line SLO. Thus, the resistance of each memory element 1200, 12i0, 12m0, 120j, 120n can be written and sensed by a unique combination of the corresponding bit line BLO, BLi, BLm and sense line SLO, SLj, SLn or write line WLO, WLi, WLm with the respective row and column indices of the memory element 1200, 12i0, 12m0, 120j, 120n to be addressed.

[0101] According to an alternative embodiment n can equal m.

[0102] The proposed solution is not limited to the embodiments discussed in detail here. Rather, the proposed solution also comprises any combination of features of the discussed embodiments, insofar as these can be combined in executable references for the person skilled in the art.

[0103] Reference numerals

[0104] 100 implant

[0105] 102, 104, 105 electrode

[0106] 106 pump

[0107] 108 reservoir

[0108] 110 processor

[0109] 120 storage unit

[0110] 122 switch

[0111] 124 control unit

[0112] 126 write address controller

[0113] 1200, 12i0, 12n0, 120j, 120n memory element

[0114] SL0, SLj, SLm sense line

[0115] WL0, WLi, WLn write line

[0116] BL0, BLi, BLm bit line

[0117] 130 power supply

[0118] 140 component interface

Claims

Claims1. An electronic implant (100) for implantation in an animal body and / or a human body, comprising:- a processor (110), and- a data storage unit (120) coupled to said processor (110), whereby- said data storage unit (120) comprises machine-readable instructions which, when executed by the processor (110), cause the processor (110) to perform a therapeutic and / or a diagnostic method, and- said data storage unit (120) comprises at least one non-volatile resistive memory element (1200, 12i0, 12n0, 120j, 120n), wherein the non-volatile resistive memory element is a memristor.

2. The electronic implant (100) according to claim 1, characterized in that, the nonvolatile resistive memory element (1200, 12i0, 12n0, 120j, 120n) is realized with resistive random-access memory (ReRAM).

3. The electronic implant (100) according to claim 1 or 2, characterized in that, the storage unit (120) is configured to be disconnected from a power supply (130).

4. The electronic implant (100) according to any one of claims 1 to 3, characterized in that, the storage unit (120) comprises at least one analog switch (122) for disconnecting the storage unit (120) from power supply (130) and / or for disconnecting an individual non-volatile resistive memory element (1200, 12i0, 12n0, 120j, 120n) from power supply (130).

5. The electronic implant (100) according to any one of the preceding claims, characterized in that, the storage unit (120) comprises a programmable control unit (124) for controlling a maximum power consumption and / or an access time limit.

6. The electronic implant (100) according to any one of the preceding claims, characterized in that, the storage unit (120) is configured for a write cycle address balancing.

7. The electronic implant (100) according to any one of the preceding claims, characterized in that, the storage unit (120) is realized with an auto mapping range for allocation of memory locations on hardware side.

8. The electronic implant (100) according to any one of the preceding claims, characterized in that, the storage unit (120) is realized with a hardware based write protection.

9. The electronic implant (100) according to any one of the preceding claims, characterized in that, the storage unit (120) is an integral part of the processor (110) unit.

10. The electronic implant (100) according to any one of the preceding claims, characterized in that, the at least one memory element (1200, 12i0, 12n0, 120j, 120n) is manufactured with a sub 22 nm technology.

11. The electronic implant (100) according to any one of the preceding claims, characterized in that, the storage unit (120) comprises a low pin count interface.

12. The electronic implant (100) according to any one of the preceding claims, characterized in that, the storage unit (120) comprises a serial I / O-Interface with at least one, in particular 2, preferred 4 ports.

13. The electronic implant (100) according to any one of the preceding claims, characterized in that, the storage unit (120) comprises a cascade of non-volatile resistive memory elements (1200, 12i0, 12n0, 120j, 120n).

14. The electronic implant (100) according to any one of the preceding claims, characterized in that, the implant (100) is one of the list:- an implantable pulse generator (IPG) (100),- an implantable cardioverter defibrillator (ICD),- an implant (100) for cardiac resynchronization therapy (CRT),- a non-transvenous ICD,- a neurostimulator,- a sensor-implant (100),- a ventricular assist device (VAD),- a pacemaker,- an implantable loop recorder, or- a medication pump (106).

15. The electronic implant (100) according to any one of the preceding claims, characterized in that, the storage unit (120) comprises at least one of the list:- diagnostic data;- executable backup code which is executed in the case a malfunction is detected by the processor (110);- executable code relating to a specific operating mode that is loaded when the operating mode is changed to the specified operating mode;- cybersecurity keys or certificates;- Al algorithms for reloading;- executable code with complex algorithms that are rarely used.

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