Encapsulated sensor

Abstract

A photodetector comprising a sensor which is configured to sense infrared radiation. The sensor comprises an infrared-absorbing structure on a CMOS die and an encapsulation structure which is arranged to form an enclosure on the CMOS die so that the infrared-5 absorbing structure is located inside the enclosure. The infrared-absorbing structure comprises colloidal quantum dots. The encapsulation structure comprises a silicon die.

Description

[0001] ENCAPSULATED SENSOR

[0002] FIELD OF THE DISCLOSURE

[0003] This disclosure relates to sensors, and more particularly to sensors which are configured to sense infrared radiation. The disclosure also relates to the encapsulation of such sensors.

[0004] BACKGROUND OF THE DISCLOSURE

[0005] CMOS-based image sensors are abundant in consumer and industrial applications. CMOS image sensors offer high sensitivity and extreme pixel resolution with few-micrometer pixel size enabling imager arrays comprising several millions of pixels in a small sensor footprint.

[0006] Colloidal quantum dot (CQD) image sensors have emerged as competitive technology providing broadband photodetection extending into near-infrared (NIR), short-wave infrared (SWIR) and mid-wave infrared (MWIR) wavelengths while offering the benefits of monolithic integration on CMOS wafer surfaces.

[0007] The reliability and stability of colloidal quantum dot image sensor requires encapsulation of the active photosensitive materials. This is typically achieved by multi-level encapsulation, which may for example include 1 ) thin-film encapsulation of photosensitive materials, and 2) second-level packaging into a hermetically sealed enclosure. Document US20220231244 illustrates various multi-level encapsulation schemes.

[0008] There are many challenges in multi-level encapsulation. Firstly, the cost of the encapsulation can be high. Secondly, the hermetic enclosure sometimes enlarges the encapsulated image sensor so much that it becomes difficult to integrate it with smaller products (for example wearable devices). Thirdly, materials which are commonly used in multi-level packages are often transparent to visible and UV radiation. Exposure to such radiation can degrade the colloidal quantum dot materials and reduce the lifetime of the sensors, and / or make the sensors unusable in applications where radiation levels are high.

[0009] Fourthly, the not-fully-encapsulated image sensor samples typically have to be moved away from the primary growth environment of the colloidal quantum dots (which is typically a protective gas environment) during multi-level encapsulation. The encapsulation is then completed in a different environment. This increases the risk that the sensitive quantum dots will be damaged before the encapsulation is complete, which leads to lower yield. Multi-level encapsulation can also have adverse effects on the sensor due to ingress of solvents and chemicals when encapsulation layers are deposited.

[0010] BRIEF DESCRIPTION OF THE DISCLOSURE

[0011] An object of the present disclosure is to provide an apparatus which overcomes at least some of the above problems.

[0012] The object of the disclosure is achieved by an apparatus which is characterized by what is stated in the independent claims. The preferred embodiments of the disclosure are disclosed in the dependent claims.

[0013] The disclosure is based on the idea of encapsulating a colloidal quantum dot image sensor with a silicon wafer.

[0014] BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In the following the disclosure will be described in greater detail by means of preferred embodiments with reference to the accompanying drawings, in which

[0016] Figure 1 a illustrates a sensor which comprise a CMOS die.

[0017] Figures 1 b - 1d illustrate photodetectors which comprise the sensor.

[0018] Figure 2 illustrates a photodetector.

[0019] Figures 3a - 3b illustrates photodetectors where the encapsulation structure is in contact with the sensor.

[0020] Figure 4a illustrates a photodetector with an antireflective coating.

[0021] Figure 4b illustrates a photodetector with a grating structure.

[0022] Figures 5, 6a - 6c, 7a - 7f and 8a - 8d illustrate methods.

[0023] Figure 9a - 9c illustrate the use of silicon wafers which are SOI wafers. Figure 10a illustrates an example of the detailed structure of the sensor.

[0024] Figure 10b illustrates an apparatus where a photodetector die has been mounted within a secondary package.

[0025] Figure 10c illustrates a photodetector with a microlens array.

[0026] DETAILED DESCRIPTION OF THE DISCLOSURE

[0027] This disclosure describes a photodetector comprising a sensor which is configured to sense infrared radiation. The sensor comprises a CMOS die with a top surface. The CMOS die comprises electric circuitry. The sensor also comprises an infrared-absorbing structure on the top surface of the CMOS die. The infrared-absorbing structure is electrically connected to the electric circuitry in the CMOS die.

[0028] The photodetector also comprises an encapsulation structure. The encapsulation structure is arranged to form an enclosure on the top surface of the CMOS die so that the infraredabsorbing structure is located inside the enclosure. The infrared-absorbing structure comprises colloidal quantum dots. The encapsulation structure comprises a silicon die with a bottom surface. The bottom surface of the silicon die is fixed to the top surface of the CMOS die so that the enclosure is formed between the silicon die and the CMOS die.

[0029] Figure 1 a illustrates schematically a sensor which comprises a CMOS die 12. The sensor may in some applications be called an image sensor, but the photodetectors described in this disclosure may also be used for applications where no imaging is performed. The CMOS die 12 has a top surface 121 and a bottom surface 123. The CMOS die is made of silicon. There is electric circuitry 19 inside the CMOS die 12. The silicon die may alternatively be called a silicon chip. The CMOS die may alternatively be called a CMOS chip.

[0030] The top surface 121 of the CMOS die 12 may form a plane, which is labelled the xy-plane in the figures of this disclosure. A z-axis may be perpendicular to the xy-plane. The figures of this disclosure illustrate primarily xz-cross sections, that is, they illustrate parts that are stacked on top of each other in the z-direction.

[0031] An infrared-absorbing structure 13 is attached to the CMOS die 12. As mentioned above, the infrared-absorbing structure 13 includes colloidal quantum dots. The colloidal quantum dots may form a layer which is parallel to the top surface 121 of the CMOS die 12. The colloidal quantum dots form the optically active part, or at least one of the optically active parts, of the infrared-absorbing structure 13. The colloidal quantum dots may for example be configured to absorb radiation in a near-infrared (NIR) wavelength range, a short-wave infrared (SWIR) wavelength range or in a mid-wave infrared (MWIR) wavelength range.

[0032] In any embodiment presented in this disclosure, the infrared-absorbing structure 13 may for example comprise any of the following colloidal quantum dot materials: PbS, HgTe, InAs, Ag2Se, Ag2Te, Bi2S3. Alternatively, the infrared-absorbing structure 13 may comprise HgE (where E may stand for S, Se, Te or varying compositions of S, Se, Te), or alloys of CdE, ZnE and HgE. Alternatively, it may comprise CuInE2, AgBiE2, CuZnSnE; Sb2E3, Bi2E3; Cu2E, Ag2E. Alternatively, it may comprise Al, In or Ga in varying compositions combined with varying compositions of N, P, As or Sb. Alternatively, infrared-absorbing structure 13 may comprise Pb or Sn in varying compositions combined with varying compositions of S, Se, Te. Other quantum dot materials may also be used. The infrared-absorbing structure 13 may comprise particles of any material listed above, and the diameter of the particles may be in the range 2 nm - 20 nm, or in the range 2 nm - 25 nm, or in the range 1 nm - 50 nm.

[0033] The infrared-absorbing structure 13 may also include other parts, such as one or more electrodes which facilitate the electrical contact between the colloidal quantum dots and the circuitry 19 in the CMOS die 12. Such electrical contacts may for example comprise transparent conductive materials such as MoO3, ZnO or TiO2. The electrical contact is illustrated by a line which connects the circuitry 19 to the infrared-absorbing structure 13. The electrodes may form layers below and / or above the layer of colloidal quantum dots in the infrared-absorbing structure 13. The infrared-absorbing structure 13 may also comprise electron-transport layers and / or hole transport layers between the colloidal quantum dots and the electrodes.

[0034] Some of the various layers which may form the infrared-absorbing structure 13 are illustrated separately in figure 9. In other figures, the infrared-absorbing structure 13 is illustrated as a single block, even though it may comprise different layers.

[0035] The infrared-absorbing structure 13 may, but does not have to be, pixellated. In other words, the various parts of the infrared-absorbing structure 13 in the sensor may be divided into two or more pixels which lie adjacent to each other in the xy-plane. The infraredabsorbing structure 13 and the electrical connection to the CMOS circuitry 19 may be configured so that an individual output signal can be read from each of the two or more pixels. Figure 1 b illustrates a photodetector 1 which comprises the sensor described above. The photodetector 1 also comprises an encapsulation structure 18 which is attached to the top surface 121 of the CMOS die 12. An enclosure 14 is formed when the encapsulation structure 18 is placed onto the CMOS die 12. The infrared-absorbing structure 13 lies within the enclosure 14. Consequently, the infrared-absorbing structure is encapsulated within the enclosure when the encapsulation structure 18 is attached to the CMOS die 12.

[0036] The encapsulation structure 18 comprises a silicon die 11. In other words, the die 11 is made of silicon. The silicon die 11 may extend over the entire enclosure 14. The encapsulation structure 18 also comprises optional bonding means 15 for bonding the silicon die 11 to the CMOS die 12. The bottom surface 111 of the silicon die 11 faces the top surface 121 of the CMOS die 12. The silicon die also has a top surface 112. The CMOS die 12 and the silicon die 11 may in practice be bonded to each other before they are cut into individual dies. In other words, as described in more detail below, a silicon wafer may be bonded to a CMOS wafer, and then the bonded CMOS+silicon structure may be diced. In any embodiment defined in this disclosure, the silicon die 11 may also comprise a CMOS circuit. If the silicon die 11 comprises a CMOS circuit, then the CMOS die 12 may be called a first CMOS die, and the silicon die 11 may be called a second CMOS die.

[0037] There are many benefits in using a silicon die 11 in the encapsulation structure 18. Silicon blocks ultraviolet radiation and visible light but is nearly transparent for radiation at wavelengths over 1200 nm. Furthermore, the CMOS die 12 is also made of silicon, so the two bonded dies 11 and 12 will exhibit the same thermal expansion I contraction behaviour when the temperature varies. This reduces the risk of temperature-induced failure. Furthermore, it is in some cases possible to perform wafer bonding directly after the infrared-absorbing structure 13 is built onto the CMOS die 12 without bringing the wafer out of inert gas atmosphere. The infrared-absorbing structure 13 can therefore be sealed inside the enclosure 14 before the photodetector 1 is removed from inert gas atmosphere.

[0038] In any embodiment presented in this disclosure, the sensor may be illuminated from the top side. In other words, the infrared radiation may enter the sensor through the silicon die 11 . Alternatively, it is also possible in some that the sensor may be illuminated from the bottom side, so that the infrared radiation enters the sensor through the CMOS die 12.

[0039] In any embodiment presented in this disclosure, the bonding means 15 for bonding the silicon die 11 to the CMOS die 12 may form a hermetic seal around the enclosure 14. The bonding means 15 may also be called a sealing structure or a bonding structure. The bonding means 15 may form a sealing ring around the enclosure 14 in the xy-plane, so that the enclosure 14 is surrounded by the bonding means 15 on all sides in the xy-plane. This is illustrated in figure 1c. In any embodiment presented in this disclosure, the width of the sealing ring in the xy-plane may for example be in the range 5 - 100 pm.

[0040] The bonding means 15 may for example a first layer of metal which is initially deposited on the bottom surface 111 of the silicon die 11 , and a second layer of metal which is initially deposited on the top surface 121 of the CMOS die 12. The silicon die 11 and the CMOS die 12 may then be bonded to each other in a metal-metal bonding process where the metal layers form the bond. Other bonding options are also possible. Some of them are presented below when a method is discussed.

[0041] Figure 1d illustrates a photodetector 1 which also comprises one or more wirebonding pads 17 on the top surface 121 of the CMOS die 12. The one or more wirebonding pads 17 may be outside of the enclosure 14. The wirebonding pads 17 may be electrically connected to the sensor. The wirebonding pads 17 may for example connected to the electric circuitry 19 in the CMOS die 12. The wirebonding pads 17 may be formed in a region of the top surface 121 which will not be covered by the encapsulation structure 18. The wirebonding pads 17 are therefore easily accessible.

[0042] The photodetector 1 may also comprise a circuit board 21 with an electric circuit. The CMOS die 12 may be mounted on the circuit board. The photodetector 1 may comprise one or more wirebonds 23 which extend from the one or more wirebonding pads 17 to the circuit board 21 and connect the wirebonding pads 17 to the electric circuit in the circuit board 21. This is illustrated in figure 2. The embodiments presented in figures 1 b and 2 can be combined with any other embodiments presented in this disclosure.

[0043] The photodetector may comprise a control unit (not illustrated), which may for example be mounted on the circuit board 21 . The control unit may be configured to send one or more control signals to the sensor and to retrieve one or more sensor output signals, containing measurement data, from the sensor. Both control signals and output signals may be transmitted between the control unit and the sensor via the electric circuitry 19 in the CMOS die 12.

[0044] The photodetector does not necessarily have to comprise a circuit board. Other arrangements, where the photodetector die may for example be mounted within a secondary package, are also possible. This is illustrated in figure 10b below.

[0045] As the preceding figures illustrate, there may be a gap between the sensor and the encapsulation structure 18 in the enclosure 14. In other words, the topmost part the infrared-absorbing structure 13, which may for example be an electrode layer, may be separated by a gap from the bottom of the encapsulation structure 18. The bottom of the encapsulation structure may be formed by the bottom surface 111 of the silicon die 11 , but it may alternatively be formed by a layer which has been deposited on the bottom surface 111. This gap is filled by the gas or vacuum which fills the enclosure 14, so there is no electrical contact or direct physical contact between the sensor and the encapsulation structure 18.

[0046] However, for best optical performance, the gap between the sensor and the encapsulation structure may be minimised to reduce reflections. This may reduce unwanted angle dependencies and unwanted lateral waveguiding in the encapsulation structure. Consequently, in some applications the encapsulation structure 18 may be in direct physical contact with the sensor in the enclosure 14. The contact takes place between the lowermost layer on the bottom surface 111 of the silicon die and the topmost layer on the infrared-absorbing structure 13, which may for example be a layer of colloidal quantum dots, an electrode layer, or an insulating layer.

[0047] The direct contact between the sensor and the encapsulation structure 18 may (but does not have to) be used for contacting purposes.

[0048] Figure 3a illustrates a photodetector where the encapsulation structure 18 comprises an electrical contact layer 115 on the bottom surface of the silicon die 11. The electrical contact layer 115 is in electrical contact with the sensor. The silicon die 11 is bonded to the top surface of the CMOS die 12 with one or more electrically conducting bonding structures 151. The electrical contact layer 115 is electrically connected to the electric circuitry 19 in the CMOS die 12 via the one or more electrically conducting bonding structures 15. The electrical contact layer 115 is electrically conducting. The electrical contact layer 115 may also be called an electrode.

[0049] In practice, the electrical contact layer 115 may be in contact with the uppermost layer in the sensor, which may for example be a hole-transport layer or electron-transport layer, or a layer of colloidal quantum dots. The hole- or electron-transport layer could alternatively be included in the electrical contact layer - in other words, it could be manufactured on the silicon wafer. In any case, the electric potential on the top side of the infrared-absorbing structure 13 can then be set through the electrical contact layer 115 via the electrically conducting bonding structures 151 , for example by transmitting a control signal to the electrically conducting bonding structures 151 .

[0050] Other layers could also be formed on the bottom surface of the silicon die. These layers may include an antireflective coating layer, a filter layer, or a lens layer. If an electrical contact layer 115 is utilized, then any of these layers may for example be located between the bottom surface of the silicon die 11 and the electrical contact layer 115.

[0051] Figure 3b illustrates a photodetector where the encapsulation structure is in direct physical contact with the sensor, but the encapsulation structure is not used for electrical contacting. The bonding structures 152 may in this case be insulating. In this configuration, the electric potential on the top side of the infrared-absorbing structure can be set by electrical contacts (not illustrated) located inside the enclosure 14.

[0052] The silicon die 11 has a top surface 112, illustrated in figure 1 b. The photodetector may comprise an antireflective coating 41 on the top surface of the silicon die 11 , as figure 4a illustrates. The photodetector may also comprise a microlens array on top of the antireflective coating (illustrated in figure 10c below). Alternatively, or in addition to the options presented in this paragraph, the photodetector may comprise a meta-optics based filter or lens on the top surface of the silicon die 11 .

[0053] Figure 4b illustrates an alternative device structure where the silicon die 11 comprises a grating structure 91 on its top surface. Such structures may alternatively be prepared on both the top and bottom surfaces of the silicon die 11 , or on only the bottom surface. They may lead to a gradual index of refraction gradient which reduces reflections. The grating structure 91 may be used instead of the antireflective coating but it may also be used together with an antireflective coating, or together with any of the layers mentioned in the previous paragraph.

[0054] This disclosure also describes a method for fabricating a photodetector. The method comprises:

[0055] - providing a CMOS wafer which comprises electric circuitry and a top surface,

[0056] - depositing an infrared-absorbing structure on the top surface of the CMOS wafer, so that the infrared-absorbing structure is connected to the electric circuitry to form a sensor which is configured to sense infrared radiation,

[0057] - forming an encapsulation structure on the top surface of the CMOS wafer so that the encapsulation structure forms an enclosure on the top surface of the CMOS wafer, and the infrared-absorbing structure is located inside the enclosure,

[0058] The infrared-absorbing structure comprises colloidal quantum dots, and the encapsulation structure comprises a silicon wafer with a bottom surface. Forming the encapsulation structure on the top surface of the CMOS wafer comprises: - bonding the bottom surface of the silicon wafer to the top surface of the CMOS wafer so that the enclosure is formed between the silicon wafer and the CMOS wafer,

[0059] The method also comprises dicing the bonded CMOS wafer and silicon wafer to form a photodetector die.

[0060] Figure 5 illustrates a CMOS wafer 50 which comprises electric circuitry 19 and a top surface 521. This CMOS wafer may be provided in the method, and deposition and patterning processes be conducted to form various structures on the top surface 521 of the CMOS wafer 50. Figure 5 illustrates the CMOS wafer 50 after the deposition and patterning steps have been completed.

[0061] An infrared-absorbing structure 13 has been deposited on the top surface 521 . All options that were presented above relating to the infrared-absorbing structure 13 apply to this the method also. Figure 5 illustrates an infrared-absorbing structure 13 with a set of bottom contacts 56. Each bottom contact 56 may define a pixel region, and each bottom contact 56 may be individually connected to the electric circuitry 19 so that each pixel can be addressed separately. The infrared-absorbing structure 13 also comprises other layers 53, one of which includes colloidal quantum dots, as discussed above. In other words, the deposition of the infrared-absorbing structure 13 on the top surface 521 of the CMOS wafer 50 may comprise depositing a layer of colloidal quantum dots. All layers that are included in the infrared-absorbing structure may be patterned so that they are confined to the intended absorber region in the xy-plane. An infrared sensor is thereby formed in and on the CMOS wafer.

[0062] The method may comprise deposition a first bonding means 55 on the top surface 521 . The first bonding means 55 may be formed by depositing a layer on the top surface 521 and patterning it. This deposition and patterning may be performed before or after the deposition of the infrared-absorbing structure. The first bonding means may comprise any of the material options discussed above, and it may surround the infrared-absorbing structure 13 in the xy-plane, as figure 1c illustrates.

[0063] Multiple image photodetector dies may be formed from a single CMOS wafer 50 and a single silicon wafer 60. Consequently, multiple substantially identical copies the device parts shown in the middle of figure 5 may be present on other regions of the CMOS wafer 50. This is illustrated on the edges of the CMOS wafer 50 in figure 5, where reference number 531 illustrates layers in an infrared-absorbing structure on the adjacent die, and 551 , 571 illustrate bonding means and wirebonding pads, respectively, on the adjacent dies. The same considerations also apply to the silicon wafer 60 in the figures below. Figure 5 shows two dotted lines 51 which define a die region on the CMOS wafer 50. In other words, the die region lies between the lines 51 . The same dotted lines 51 will be used to define the die region on the silicon wafer 60 in the next figures. As explained in more detail below, the CMOS wafer 50 and the silicon wafer 60 are diced along these lines to form a photodetector die comprising a CMOS die 12 and a silicon die 11 .

[0064] The method may comprise depositing one or more wirebonding pads 57 on the top surface 521 of the CMOS wafer 50, so that the one or more wirebonding pads are located outside of the enclosure. The wirebonding pads 57 lie within the die region, as figure 5 illustrates. The photodetector die will then correspond to the one illustrated in figure 1d, with wirebonding pad 17 outside of the enclosure 14. The wirebonding pads could alternatively be omitted, and the photodetector die would then correspond to figure 1 b when the method is finished. If no wirebonding pads are used, the circuitry 19 be connected to other external contacts on the photodetector die, for external contacts on the bottom surface of the CMOS die. The method described below will focus on devices where wirebonding pads are present.

[0065] Forming the encapsulation structure may comprise providing a silicon wafer. The silicon wafer may also be called a lid wafer or a cap wafer. Optionally, forming the encapsulation structure may comprise deposition, patterning and etching processes that are performed to form various structures on the bottom surface of the silicon wafer. Figure 6a illustrates an example silicon wafer 60 with a bottom surface 611 after the deposition, patterning steps and etching steps have been completed.

[0066] The silicon wafer 60 in figure 6a comprises a second bonding means 65 on its bottom surface 611 . The second bonding means may be formed by depositing a layer on the bottom surface 611 and patterning it. The second bonding means 65 may have the same size shape in the xy-plane as the first bonding means 55 on the CMOS wafer. The second bonding means 65 may be aligned with the first bonding means 55 in the z-direction when the CMOS wafer 50 is bonded to the silicon wafer 60, so that the first bonding means 55 and second bonding means 65 for a sealing ring around the enclosure where the infraredabsorbing structure is located.

[0067] The first bonding means 55 and second bonding means 65 may for example comprise bonding pads which are joined to each other in the bonding process. The bonding pads may be made of metal. The metal may be gold. The height of the first bonding means 55 in the z-direction in figure 5 may in some applications be greater than the height of any other structures prepared on the top surface of the CMOS wafer (this has not been illustrated).

[0068] Various bonding methods applicable to this invention include (i) anodic bonding, (ii) glass frit bonding, (iii) metallic alloy seal bonding including soft soldering and eutectic bonding, (iv) thermocompression bonding, (v) exothermic reaction bonding, (vi) laser microwelding, (vii) adhesive bonding, (vii) direct silicon-silicon bonding etc.

[0069] In the case of metal alloy seal bonding, the structure and process may be as follows:

[0070] Solder ring 65 on silicon wafer 60:

[0071] • Sputtering of field metal on the bonding side of wafer

[0072] • Photoresist lithography to define the solder ring and alignment markers

[0073] • Electroplating metal

[0074] • Photoresist stripping and etching of field metal (except under ring and markers)

[0075] Metal ring 55 on CMOS wafer 50:

[0076] • Shadow mask sputtering of metal ring matching the solder ring pattern 65

[0077] Bonding process:

[0078] • Alignment of wafers

[0079] • Tack bonding process

[0080] • Reflow oven

[0081] • Resulting gap between infrared-absorbing structure and lid may be ca. 15-20 pm

[0082] The thickness of the solder ring 65 and metal ring 55 in the z-direction may be larger than the thickness of any other features (such as the infrared-absorbing structure 13) on the CMOS wafer 60. This ensures a continuous contact between the two metal rings. The CMOS wafer 50 and silicon wafer 60 may in some cases be bonded to each other with bonding means deposited only on one of the two wafers. In other words, bonding means do not necessarily have to be deposited on both the CMOS wafer 50 and the silicon wafer 60 before bonding. It may in some cases be sufficient to attach bonding means to one of these wafers, but not the other.

[0083] Furthermore, the CMOS wafer 50 and silicon wafer 60 may in some cases be bonded to each other directly, by utilizing silicon-silicon bonding. The bonding may in this case be carried out without any bonding means deposited on either wafer. Alternatively, the first and / or second bonding means 55165 may in this case comprise a layer of silicon.

[0084] The method may also comprise forming a recess on the bottom surface of the silicon wafer 60 in the region which will form the enclosure before the silicon wafer 60 is bonded to the CMOS wafer 50. Figure 6a also illustrates a central recess 63 and side recesses 64 formed in the silicon wafer 60. These recesses may be formed by etching the silicon wafer 60, for example in an anisotropic KOH etching process. The central recess 63 raises the ceiling of the enclosure where the infrared-absorbing structure 13 is located after the silicon wafer is bonded to the CMOS wafer. The side recesses 64, on the other hand, form a temporary enclosure around the optional wirebonding pads 57 until the wafers are diced, as explained in more detail below. Consequently, the central recess 63 may be aligned with the infraredabsorbing structure 13 in the z-direction when the CMOS wafer 50 is bonded to the silicon wafer 60, and the side recesses 64 may be aligned with the wirebonding pads 57 in the z- direction. The side recesses 64 may surround the central recess 63 on all sides in the xy- plane. Alternatively, the side recesses 64 may be linear recesses which extend only in the y-direction (perpendicular to the plane illustrated in figure 6a).

[0085] The method may alternatively be performed without etching a central recess 63. No recessing may be needed if the height of the first and second bonding means 55 and 65 in the z-direction may be sufficient to accommodate the infrared-absorbing structure 13 inside the enclosure. A silicon wafer 60 with no recesses is illustrated in figure 6b.

[0086] Regardless of whether or not the bottom surface 611 is recessed, forming the encapsulation structure may comprise forming an electrical contact layer on the bottom surface of the silicon wafer 60 in the region which will form the enclosure before the silicon wafer 60 is bonded to the CMOS wafer 50. The electric contact layer 115 is transparent to infrared radiation. This option is illustrated in figure 6c, and it facilitates the contact arrangement presented in figure 3a.

[0087] It is also in some applications possible to utilize a silicon wafer 60 with high doping throughout the wafer, or with high doping near the bottom surface of the wafer 60. The wafer 60 may then itself conduct electricity sufficiently well to act as an electrode in the contact arrangement when it is brought into contact with the infrared-absorbing structure.

[0088] The following figures will illustrate a method which utilizes a silicon wafer (like the one in figure 6b) where there is no central recess no electrical contact layer 115. However, the same bonding options can be arranged when a recess and / or an electrical contact layer 115 is present. The same options also apply if there is a gap between the encapsulation structure and the infrared-absorbing structure.

[0089] Figure 7a illustrates the CMOS wafer 50 and the silicon wafer 60 after they have been bonded together. Optionally, the thickness of the silicon wafer 60 in the z-direction may be reduced after bonding by chemical - mechanical polishing of silicon. In other words, the method may comprise thinning the silicon wafer after it has been bonded to the CMOS wafer and before dicing. This is illustrated by the reduced thickness of wafer 60 in figures 7b (compared to figure 7a).

[0090] Figure 7b also illustrates that the method may comprise depositing an anti-reflective coating 601 on a top surface of the silicon wafer 60 after it has been bonded to the CMOS wafer 50 and before dicing.

[0091] Figures 7c, 7d and 7e illustrate a two-step dicing process. The CMOS wafer 50 and silicon wafer 60 comprise a dicing region close to the dotted line 51 . The wafers may be sawed in the dicing region. Figure 7c shows a first sawing step where first vertical trenches 72 are formed which are aligned in the z-direction with the cavity 78 formed by the side recesses 64 in the silicon wafer 60. This allows pieces of the silicon wafer to be removed from the regions which lie between the first vertical trenches 72. Figures 7c - 7e shows the silicon die 11 on top of the CMOS wafer after the pieces have been removed. Waferlevel testing of the image sensors may still be performed at this stage.

[0092] The dicing does not necessarily have to be carried out by sawing. It could alternatively be performed for example with laser stealth dicing.

[0093] Figure 7e shows a second sawing step where second vertical trenches 74 are sawed in the dicing region. This cuts the CMOS wafer 50 in parts and thereby separates the CMOS die 12 from other adjacent CMOS dies 75 and 76. The silicon die 11 and CMOS die 12 together form a photodetector die 71 .

[0094] In other words, the dicing may comprise a first dicing step and a second dicing step. The first dicing step may be performed before the second dicing step. The silicon wafer may be diced in the first dicing step, and the CMOS wafer may be diced in the second dicing step. Alternatively, the dicing may be performed in a single step where the silicon wafer and CMOS wafer are sawed in the same process.

[0095] The method may also comprise providing a circuit board 21 with an electric circuit, mounting the photodetector die 71 on the circuit board 21 , and connecting the one or more wirebonding pads to the electric circuit in the circuit board with one or more wire bonds. This is illustrated in figure 7f. Additional protection may be provided for the wire bonds for example with glob-top encapsulation.

[0096] One benefit in the encapsulation described in this disclosure is that the infrared-absorbing structure is already fully encapsulated when the dicing is performed. It is in some cases possible to bond the wafers 50 and 60 to each other in the same environment where the colloidal quantum dots were grown. The quantum dots will then be well-protected during subsequent steps where the wafers are brought to a different environment and diced.

[0097] Figure 8a illustrates an alternative structure where the silicon wafer 60 comprises an isolation trench 81 . The isolation trench 81 , which may be formed by etching, extends into the silicon wafer 60 in the z-direction. The isolation trench 81 may surround the infraredabsorbing structure in the xy-plane, and it may be located inside the sealing ring in the xy- plane.

[0098] Figures 8b - 8d illustrate another alternative where a layer getter material 82 has been deposited on the bottom surface of the silicon wafer 60 before it is bonded to the CMOS wafer 50 in figure 8c. The layer of getter material 82 may for example be formed as a ring, so as not to impede the infrared radiation from reaching the active area of the sensor. The layer of getter material 82 be located inside the sealing ring in the xy-plane.

[0099] The getter may be configured to absorb gases (e.g. oxygen, water vapour), which may either (i) outgas from components internal to the sealed package or (ii) leak into the sealed package in small quantities over the lifetime of the device. The getter material may be a metal element alloy, for example a zirconium alloy.

[0100] The method may comprise activating the getter material 82 by local heating using an infrared laser through the encapsulation structure after the bonding process is completed. This activation is illustrated by arrows in figure 8d. Figure 9a illustrates an alternative device structure where the silicon wafer 60 is a silicon-on-insulator (SOI) wafer. The SOI wafer may comprise a support wafer 605, a bottom layer 606 and an insulating layer 607 between the support wafer 605 and the bottom layer 606. Both the support wafer 605 and the bottom layer 606 may be made of silicon. The insulating layer 607 may be made of silicon dioxide. The bottom layer 606 may be much thinner than the support wafer 605. Figure 9a shows a structure where the bottom layer 606 comprises optional side recesses 64. Figure 9b shows an alternative structure where the bottom layer has been prepared without any side recesses.

[0101] The manufacturing method may comprise, after bonding the silicon wafer 60 to the CMOS wafer 50, removing the support wafer 605, and removing the insulating layer 607. The encapsulation structure will then comprise a thin silicon die, formed only by the bottom layer 606. This is illustrated in figure 9c. The thickness of the silicon die 11 may in this case be for example 10 - 50 pm. All additional processing options described above, such as the deposition of extra layers or other structures on the top and / or bottom of the silicon die, can be performed also when the silicon wafer 60 is a SOI wafer. However, the top surface of the bottom layer 606 does not become available for processing until the SOI wafer has been bonded to the CMOS wafer 50 and the support wafer 605 and insulating layer 607 have been removed, as figure 9c illustrates.

[0102] The options described in figures 8a - 9c may be implemented together with any other options presented and discussed with reference to figures 6a - 6c or 7a - 7f.

[0103] Figure 10a illustrates the structure of the sensor in more detail. The options presented in figure 10a apply to all embodiments presented in this disclosure, but they are just an illustrative example. The circuitry 19 in the CMOS die 12 may in practice be much more complex, and the infrared-absorbing structure 13 may alternatively comprise any other options listed above.

[0104] The image sensor in figure 10a comprises an electrical circuit stack 129. The stack 129 may form the top part of the CMOS substrate, and the other parts of the sensor may be built on this stack. In other words, the electrical circuit stack 129 may form the top surface

[0105] 121 of the CMOS die 12.

[0106] The electrical circuit stack 129 may comprise insulating layers 127 and electric conductors 124 which extend through and between the insulating layers in the x-, y and / or z-directions. In other words, the electrical circuit stack 129 may be a multilayer electrical circuit which extends in the xy-plane and in the z-direction. The circuit may be much more complex than the schematic illustration in figure 10a indicates.

[0107] The infrared-absorbing structure 13 may for example comprise a photodiode formed on top of the electrical circuit stack 129. The photodiode 16 may comprise a layer 131 of colloidal quantum dots (CQD) sandwiched between two electrodes 135 and 136. The electrode 135 may for example be the electrical contact layer 115 mentioned earlier, or it may be a top contact layer deposited on the CMOS wafer after the other device structures have been built. The photodiode may also comprise either an electron transport layer 132 or a hole transport layer 132 between the layer 131 and each of the adjacent electrodes 115 and 136. The infrared-absorbing structure 13 does not necessarily have to be a photodiode. Other electrical configurations can also be utilized.

[0108] The circuitry 19 in the CMOS die 12, which is connected to the infrared-absorbing structure 13, may for example comprise floating diffusion capacitors, pn-junction capacitors, depletion capacitors, transistor capacitors, MOS capacitors, varactor diodes, trench capacitors or deep trench capacitors. The sensor may also comprise readout capacitors

[0109] 122 in the electrical circuit stack 129. These readout capacitors 122 may for example be metal-insulator-metal (MIM) capacitors, metal-oxide-metal capacitors (MOM) or metal- oxide-poly (MOP) capacitors. The readout capacitors 122 may be connected to the infrared-absorbing structure 13 via the circuitry 19. The readout capacitors 122 may be configured to generate one or more sensor output signals.

[0110] Figure 10b illustrates an apparatus where the photodetector die 71 has been mounted within a secondary package 92. The secondary package 92 can for example be made of a ceramic material or metal. The secondary package 92 may form a secondary enclosure 93 around the photodetector die 71. The secondary enclosure 93 may be filled with a protective gas, or with vacuum. The secondary package 92 may comprise an optical window 99 which is transparent to the desired radiation wavelengths.

[0111] The secondary package 92 may also comprise contact pins 96 which extend from the inside of the secondary package 92 to the outside of the secondary package 92. The contact pins 96 may be electrically connected to the photodetector die 71. The photodetector die 71 may for example be mounted on a thermoelectric cooler 94. The arrangement may also comprise one or more interposers 95 within the secondary package 92. The photodetector die 71 may be connected to the pins 96 via the one or more interposers.

[0112] Wavelength-selective optical filters (multilayer interference or metamaterial type, for example) may also be implemented on the silicon wafer to allow hyperspectral imaging. These may be placed on the bottom of the silicon wafer to place them as close as possible to the sensors. These filters may ideally be combined with the needed AR coating, most likely with the antireflective coating on the top surface of the silicon wafer, and selective filtering on the bottom surface. The antireflective coating may alternatively be placed on both the top and bottom surfaces.

[0113] In the case of back-side illumination through the CMOS die, optical filters may be fabricated in the CMOS die bulk using patterning of metal interconnect layers in the CMOS die.

[0114] Figure 10c illustrates a photodetector with a microlens array 109 on top of the silicon die.

Claims

CLAIMS1 . A photodetector comprising :- a sensor which is configured to sense infrared radiation, wherein the sensor comprises a CMOS die with a top surface, and the CMOS die comprises electric circuitry, and the sensor also comprises an infrared-absorbing structure on the top surface of the CMOS die, and the infrared-absorbing structure is electrically connected to the electric circuitry in the CMOS die,- an encapsulation structure, wherein the encapsulation structure is arranged to form an enclosure on the top surface of the CMOS die so that the infrared-absorbing structure is located inside the enclosure, characterized in that the infrared-absorbing structure comprises colloidal quantum dots, and the encapsulation structure comprises a silicon die with a bottom surface, and the bottom surface of the silicon die is fixed to the top surface of the CMOS die so that the enclosure is formed between the silicon die and the CMOS die.

2. A photodetector according to claim 1 , wherein the photodetector also comprises one or more wirebonding pads on the top surface of the CMOS die, and the one or more wirebonding pads are outside of the enclosure, and the one or more wirebonding pads are electrically connected to the sensor.

3. A photodetector according to claim 2, wherein the photodetector also comprises a circuit board with an electric circuit, and the CMOS die is mounted on the circuit board, and the photodetector comprises one or more wirebonds which extend from the one or more wirebonding pads to the circuit board and connect the wirebonding pads to the electric circuit in the circuit board.

4. A photodetector according to any preceding claim, wherein there is a gap between the sensor and the encapsulation structure in the enclosure.

5. A photodetector according to any of claims 1 -3, wherein the encapsulation structure is in direct physical contact with the sensor in the enclosure.

6. A photodetector according to claim 5, wherein the encapsulation structure comprises an electrical contact layer on the bottom surface of the silicon die, and the electrical contact layer is in electrical contact with the sensor, and the silicon die is bonded tothe top surface of the CMOS die with one or more electrically conducting bonding structures, and the electrical contact layer is electrically connected to the electric circuitry in the CMOS die via the one or more electrically conducting bonding structures.

7. A photodetector according to any preceding claim, wherein the silicon die has a top surface, and the photodetector comprises an antireflective coating on the top surface of the silicon die.

8. A method for fabricating a photodetector, comprising:- providing a CMOS wafer which comprises electric circuitry and a top surface,- depositing an infrared-absorbing structure on the top surface of the CMOS wafer, so that the infrared-absorbing structure is connected to the electric circuitry to form a sensor which is configured to sense infrared radiation,- forming an encapsulation structure on the top surface of the CMOS wafer so that the encapsulation structure forms an enclosure on the top surface of the CMOS wafer, and the infrared-absorbing structure is located inside the enclosure, characterized in that the infrared-absorbing structure comprises colloidal quantum dots, and the encapsulation structure comprises a silicon wafer with a bottom surface, and forming the encapsulation structure on the top surface of the CMOS wafer comprises:- bonding the bottom surface of the silicon wafer to the top surface of the CMOS wafer so that the enclosure is formed between the silicon wafer and the CMOS wafer, and the method also comprises dicing the bonded CMOS wafer and silicon wafer to form a photodetector die.

9. A method according to claim 8, wherein the method also comprises:- depositing one or more wirebonding pads on the top surface of the CMOS wafer, so that the one or more wirebonding pads are located outside of the enclosure.

10. A method according to claim 9, wherein the method also comprises:providing a circuit board with an electric circuit,- mounting the photodetector die on the circuit board,- connecting the one or more wirebonding pads to the electric circuit in the circuit board with one or more wirebonds.11 . A method according to any of claims 8-10, wherein the method also comprises forming a recess on the bottom surface of the silicon wafer in a region which will form the enclosure before the silicon wafer is bonded to the CMOS wafer.

12. A method according to any of claims 8-10, wherein the method also comprises forming an electrical contact layer on the bottom surface of the silicon wafer in the region which will form the enclosure before the silicon wafer is bonded to the CMOS wafer.

13. A method according to any of claims 8-12, wherein the method comprises thinning the silicon wafer after it has been bonded to the CMOS wafer and before dicing.

14. A method according to any of claims 8-13, wherein the method comprises depositing an anti-reflective coating on a top surface of the silicon wafer after it has been bonded to the CMOS wafer and before dicing.

15. A method according to any of claims 8-14, wherein the dicing comprises a first dicing step and a second dicing step, wherein the first dicing step is performed before the second dicing step, and the silicon wafer is diced in the first dicing step, and the CMOS wafer is diced in the second dicing step.

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