Display substrate and driving method therefor, and display device

Abstract

A display substrate and a driving method therefor, and a display device. The display substrate comprises a plurality of repeating units (CF). At least one repeating unit (CF) comprises M circuit units (Q) and one insertion unit (CQ), wherein M is a positive integer greater than or equal to 3. Each circuit unit (Q) comprises a first circuit, and the first circuit at least comprises a third transistor (T3) serving as a driving transistor. The insertion unit (CQ) comprises a second circuit, and the second circuit at least comprises a fifth transistor (T5) serving as a first light-emitting control transistor and a first power line (81). A first electrode of the fifth transistor (T5) is connected to the first power line (81), and a second electrode of the fifth transistor (T5) is separately connected to third transistors (T3) in M first circuits by means of a node connection line (48) to form M pixel driving circuits.

Description

Display substrate, driving method thereof, and display device TECHNICAL FIELD

[0001] The present document relates to, but is not limited to, the technical field of display, in particular to a display substrate, a driving method thereof and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In one aspect, the present disclosure provides a display substrate, comprising a plurality of repeating units, at least one repeating unit comprising M circuit units and 1 insertion unit arranged in sequence along a first direction, M being a positive integer greater than or equal to 3; the circuit unit comprises a first circuit, the first circuit comprising at least a third transistor as a driving transistor, the insertion unit comprising a second circuit, the second circuit comprising at least a fifth transistor as a first light-emitting control transistor and a first power supply line extending along a second direction, the first direction and the second direction intersecting; the first electrode of the fifth transistor is connected with the first power supply line, and the second electrode of the fifth transistor is connected with the third transistor in M first circuits through a node connection line, forming M pixel driving circuits.

[0006] In an exemplary embodiment, M = 3.

[0007] In an exemplary embodiment, the ratio of the width of the insertion unit to the width of the circuit unit is 0.3 to 0.5, and the width is the size in the first direction.

[0008] In an exemplary embodiment, the repeating unit further includes a node connection electrode, a first end of the node connection electrode is connected with the second electrode of the fifth transistor, and a second end of the node connection electrode is connected with the node connection line, the node connection line is in a shape of a straight line or a zigzag line with a main body part extending along the first direction, and the node connection line is connected with the first electrode of the third transistor in the M circuit units respectively.

[0009] In an exemplary embodiment, the at least one circuit unit further includes a node connection block, a first end of the node connection block is connected with the node connection line, and a second end of the node connection block is connected with the first electrode of the third transistor.

[0010] In an exemplary embodiment, in the at least one circuit unit, the second end of the node connection electrode is connected with the node connection block, and the node connection electrode is connected with the node connection line through the node connection block.

[0011] In an exemplary embodiment, in the at least one circuit unit, the first circuit further includes a first capacitor, a second capacitor, a first transistor as a first reset transistor, a second transistor as a second reset transistor, a fourth transistor as a data write transistor, a sixth transistor as a second light emitting control transistor, and a seventh transistor as a third reset transistor; a first electrode of the first transistor and a first electrode of the second transistor are connected with a first initial signal line respectively, a second electrode of the first transistor is connected with a second electrode plate of the first capacitor and a third electrode plate of the second capacitor respectively, a second electrode of the second transistor is connected with a gate electrode of the third transistor, a second electrode of the fourth transistor, and a first electrode plate of the first capacitor respectively, a first electrode of the third transistor is connected with a second electrode of the fifth transistor, a second electrode of the third transistor is connected with a first electrode of the sixth transistor and a fourth electrode plate of the second capacitor respectively, a first electrode of the fourth transistor is connected with a data signal line, a second electrode of the sixth transistor is connected with a second electrode of the seventh transistor, and a first electrode of the seventh transistor is connected with a second initial signal line; a projection of the data signal line on a display substrate does not overlap with a projection of an active layer of the first transistor to the fourth transistor and a projection of an active layer of the sixth transistor to the seventh transistor on the display substrate.

[0012] In an exemplary embodiment, in the at least one circuit unit, a projection of the data signal line on a display substrate does not overlap with a projection of the gate electrode of the third transistor on the display substrate.

[0013] In an exemplary embodiment, the first initial signal line has a shape of a straight line or a zigzag line with a main body extending along the first direction, and the at least one repeating unit further comprises at least one first initial connection line extending along the second direction, the first initial signal line and the first initial connection line being connected to form a mesh structure for transmitting the first initial signal.

[0014] In an exemplary embodiment, the first initial connection line is arranged in the insertion unit.

[0015] In an exemplary embodiment, the second initial signal line has a shape of a straight line or a zigzag line with a main body extending along the first direction, and the at least one repeating unit further comprises at least one second initial connection line extending along the second direction, the second initial signal line and the second initial connection line being connected to form a mesh structure for transmitting the second initial signal.

[0016] In an exemplary embodiment, in the at least one circuit unit, a projection of the second initial connection line on the display substrate at least partially overlaps with a projection of the active layer of the first transistor to the fourth transistor and the active layer of the sixth transistor to the seventh transistor on the display substrate.

[0017] In an exemplary embodiment, the at least one repeating unit further comprises at least one power supply connection line extending along the first direction and at least one second power supply line extending along the second direction, the power supply connection line and the second power supply line being connected to form a mesh structure for transmitting a second power supply signal.

[0018] In an exemplary embodiment, in the at least one circuit unit, a projection of the second power supply line on the display substrate at least partially overlaps with a projection of the active layer of the first transistor to the fourth transistor and the active layer of the sixth transistor to the seventh transistor on the display substrate.

[0019] In another aspect, the present disclosure also provides a display device comprising the aforementioned display substrate.

[0020] In another aspect, the present disclosure also provides a driving method of the display substrate. The pixel driving circuit includes at least a first node, a second node, a third node, a fourth node and a fifth node. The first node is connected with the second electrode of the second transistor, the gate electrode of the third transistor, the second electrode of the fourth transistor and the first end of the first capacitor respectively. The second node is connected with the first electrode of the third transistor and the second electrode of the fifth transistor respectively. The third node is connected with the second electrode of the third transistor, the first electrode of the sixth transistor and the first end of the second capacitor respectively. The fourth node is connected with the second electrode of the first transistor, the second end of the first capacitor and the second end of the second capacitor respectively. The fifth node is connected with the second electrode of the sixth transistor and the second electrode of the seventh transistor respectively. The driving method includes at least a reset stage. In the reset stage, the second transistor is turned on, and the first node is reset. Then the seventh transistor is turned on, and the fifth node is reset. Then the first transistor is turned on, and the fourth node is reset. Then the sixth transistor is turned on, and the third node is reset.

[0021] In an exemplary embodiment, the driving method further includes a data writing stage. In the data writing stage, the second transistor is turned off, then the fourth transistor is turned on, and a data signal is written into the first node, then the first transistor is turned off.

[0022] Other aspects can become apparent from the following detailed description when read in conjunction with the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0023] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and serve to explain the principles of the present disclosure, and should not be considered limiting of the present disclosure's scope.

[0024] FIG. 1 is a structural schematic diagram of a display device;

[0025] FIG. 2 is a plan structural schematic diagram of a display substrate;

[0026] FIG. 3 is a cross-sectional structural schematic diagram of a display substrate;

[0027] FIG. 4 is a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0028] FIG. 5 is an equivalent circuit diagram of a pixel driving circuit in a repeat unit according to an exemplary embodiment of the present disclosure;

[0029] FIG. 6 is a driving timing diagram of the pixel driving circuit shown in FIG. 5;

[0030] FIG. 7 is a plan structural schematic diagram of a repeat unit according to an exemplary embodiment of the present disclosure; and

[0031] FIG. 8 is a schematic diagram of a grid structure according to an exemplary embodiment of the present disclosure;

[0032] FIG. 9 is a schematic diagram of a first conductive layer pattern formed in a repeating unit according to the present disclosure;

[0033] FIGS. 10A and 10B are schematic diagrams of a second conductive layer pattern formed in a repeating unit according to the present disclosure;

[0034] FIGS. 11A and 11B are schematic diagrams of a semiconductor layer pattern formed in a repeating unit according to the present disclosure;

[0035] FIGS. 12A and 12B are schematic diagrams of a third conductive layer pattern formed in a repeating unit according to the present disclosure;

[0036] FIG. 13 is a schematic diagram of a fourth insulating layer pattern formed in a repeating unit according to the present disclosure;

[0037] FIGS. 14A and 14B are schematic diagrams of a fourth conductive layer pattern formed in a repeating unit according to the present disclosure;

[0038] FIG. 15 is a schematic diagram of a first planar layer pattern formed in a repeating unit according to the present disclosure;

[0039] FIGS. 16A and 16B are schematic diagrams of a fifth conductive layer pattern formed in a repeating unit according to the present disclosure;

[0040] FIG. 17 is a schematic diagram of a planar structure of another repeating unit according to an exemplary embodiment of the present disclosure;

[0041] FIG. 18 is a schematic diagram of a semiconductor layer pattern formed in another repeating unit according to the present disclosure;

[0042] FIG. 19 is a schematic diagram of a third conductive layer pattern formed in another repeating unit according to the present disclosure;

[0043] FIG. 20 is a schematic diagram of a fourth insulating layer pattern formed in another repeating unit according to the present disclosure;

[0044] FIG. 21 is a schematic diagram of a fourth conductive layer pattern formed in another repeating unit according to the present disclosure;

[0045] FIG. 22 is a schematic diagram of a first planar layer pattern formed in another repeating unit according to the present disclosure;

[0046] FIG. 23 is a schematic diagram of a fifth conductive layer pattern formed in another repeating unit according to the present disclosure.

[0047] Explanation of reference numerals: 10 - first capacitor; 11 - first electrode plate; 12 - second electrode plate; 13 - third electrode plate; 14 - fourth electrode plate; 15 - first electrode plate connecting block; 16 - third electrode plate connecting block; 20 - second capacitor; 21 - first initial connecting line; 22 - second initial connecting line; 23 - fifth node electrode; 24 - power supply connecting line; 31 - first active layer; 32 - second active layer; 33 - third active layer; 34 - fourth active layer; 35 - fifth active layer; 36 - sixth active layer; 37 - seventh active layer; 38 - active connecting electrode; 41 - first gate electrode; 42 - second gate electrode; 43 - third gate electrode; 44 - fourth gate electrode; 45 - fifth gate electrode; 46 - sixth gate electrode; 47 - seventh gate electrode; 48 - node connecting line; 51 - first connecting electrode; 52 - second connecting electrode; 53 - third connecting electrode; 54 - fourth connecting electrode; 55 - fifth connecting electrode; 56 - sixth connecting electrode; 57 - seventh connecting electrode; 58 - eighth connecting electrode; 59 - ninth connecting electrode; 60 - tenth connecting electrode; 61 - first scan signal line; 62 - second scan signal line; 63 - third scan signal line; 64 - fourth scan signal line; 65 - first light-emitting signal line; 66 - first initial signal line; 71 - first initial signal line; 72 - second initial signal line; 73 - initial connecting electrode; 81 - first power supply line; 82 - second power supply line; 83 - data signal line; 84 - anode connecting electrode; 101 - substrate; 102 - driving circuit layer; 103 - light-emitting structure layer; 104 - encapsulation structure layer. DETAILED DESCRIPTION

[0048] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the following will be used to specifically explain the embodiments of the present disclosure with reference to the drawings. It should be noted that the embodiments can be implemented in a variety of different forms. Those skilled in the art can easily understand that the modes and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict.

[0049] The proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0050] In the present specification, ordinal numbers such as "first", "second", and "third" are provided to avoid confusion of constituent elements, and are not intended to be limiting in terms of numbers.

[0051] In the present specification, words indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the constituent elements with reference to the drawings, and are only for the convenience of describing the present specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction of describing each constituent element. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0052] In the present specification, unless explicitly specified and limited, the terms "mount", "connect", "connection" should be understood broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or the communication inside two elements. Those skilled in the art can understand the specific meaning of the above terms in the present disclosure according to the specific circumstances.

[0053] In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region means a region where current flows mainly.

[0054] In this specification, the first terminal can be a drain electrode and the second terminal can be a source electrode, or the first terminal can be a source electrode and the second terminal can be a drain electrode. The functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other in the case of using a transistor whose polarity is reversed or in the case where the direction of current flowing in a circuit is changed, and the like. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other, and the "source terminal" and the "drain terminal" can be interchanged with each other.

[0055] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between components to be connected. Examples of the element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having some function.

[0056] In this specification, "parallel" means a state where the angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" means a state where the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0057] In this specification, a "film" and a "layer" can be interchanged with each other. For example, a "conductive layer" can be replaced with a "conductive film". Similarly, an "insulating film" can be replaced with an "insulating layer".

[0058] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not necessarily a strict one, and can be an approximate triangle, rectangle, trapezoid, pentagon, or hexagon. There can be some small deformation due to a tolerance, a rounded corner, a rounded side, or the like. In the present disclosure, "about" means that a value is not strictly limited to a certain value, and a value within a range of a process and measurement error is allowed.

[0059] FIG. 1 is a structural schematic diagram of a display device. As shown in FIG. 1, the display device can include a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, the timing controller is connected with the data driver, the scan driver, and the light emitting driver respectively, the data driver is connected with a plurality of data signal lines (D1 to Dn) respectively, the scan driver is connected with a plurality of scan signal lines (S1 to Sm) respectively, and the light emitting driver is connected with a plurality of first light emitting signal lines (E1 to Eo) respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and a light emitting unit, the circuit unit can include at least a pixel driving circuit, the pixel driving circuit is connected with the scan signal line, the first light emitting signal line, and the data signal line respectively, and the light emitting unit can include a light emitting device connected with the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide a gray value and a control signal suitable for the specification of the data driver to the data driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan driver to the scan driver, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emitting driver to the light emitting driver. The data driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn by using the gray value and the control signal received from the timing controller. For example, the data driver can sample the gray value by using the clock signal, and apply data voltages corresponding to the gray value to the data signal lines D1 to Dn in units of a pixel row. n can be a natural number. The scan driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan driver can sequentially provide the scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register, and can generate the scan signal in a manner that sequentially transfers the scan start signal provided in the form of an on-level pulse to a next stage circuit under the control of the clock signal. m can be a natural number. The light emitting driver can generate emission signals to be provided to the first light emitting signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emitting driver can sequentially provide the emission signal having an off-level pulse to the first light emitting signal lines E1 to Eo. For example, the light emitting driver can be configured in the form of a shift register, and can generate the emission signal in a manner that sequentially transfers the emission stop signal provided in the form of an off-level pulse to a next stage circuit under the control of the clock signal. o can be a natural number. In an exemplary embodiment, the pixel array can be disposed on a display substrate.

[0060] FIG. 2 is a schematic diagram of a planar structure of a display substrate. As shown in FIG. 2, the display substrate can include a plurality of pixel units P arranged in a matrix manner, and at least one pixel unit P can include a first sub-pixel P1, a second sub-pixel P2 and a third sub-pixel P3. Each sub-pixel can include a circuit unit and a light-emitting unit, and the circuit unit can include at least a pixel driving circuit. The pixel driving circuit is connected with a scan signal line, a light-emitting signal line and a data signal line respectively, and is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit can include a light-emitting device connected with the pixel driving circuit of the sub-pixel where the light-emitting device is located, and the light-emitting device is configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel where the light-emitting device is located.

[0061] In an example embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a green sub-pixel (G) emitting green light, and the third sub-pixel P3 can be a blue sub-pixel (B) emitting blue light. In an example embodiment, the shape of the sub-pixel can be rectangular, diamond, pentagonal or hexagonal, and the three sub-pixels can be arranged in a horizontal parallel, vertical parallel or triangular manner.

[0062] In other example embodiments, the pixel unit can include four sub-pixels, and the four sub-pixels can be arranged in a horizontal parallel, vertical parallel or square manner, which is not limited in the present disclosure.

[0063] FIG. 3 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels in the display substrate. As shown in FIG. 3, in a direction perpendicular to the plane of the display substrate, the display area can include a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display area can include other film layers, such as a touch structure layer, which is not limited in the present disclosure.

[0064] In an example embodiment, the substrate 101 can be a flexible substrate, or can be a rigid substrate. The driving circuit layer 102 can include a plurality of circuit units, each of which can include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light emitting structure layer 103 can include a plurality of light emitting units, each of which can include a light emitting device, which can include at least an anode, an organic light emitting layer, and a cathode, the anode being connected to the pixel driving circuit, the organic light emitting layer being connected to the anode, and the cathode being connected to the organic light emitting layer, the organic light emitting layer emitting light of a corresponding color under the driving of the anode and the cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer can be made of inorganic material, the second encapsulation layer can be made of organic material, the second encapsulation layer being disposed between the first encapsulation layer and the third encapsulation layer, forming an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light emitting structure layer 103.

[0065] An example embodiment of the present disclosure provides a display substrate. In an example embodiment, the display substrate can include a plurality of repeating units, at least one repeating unit including M circuit units and 1 insertion unit arranged in sequence along a first direction, M being a positive integer greater than or equal to 3; the circuit unit including a first circuit, the first circuit including at least a third transistor as a driving transistor, the insertion unit including a second circuit, the second circuit including at least a fifth transistor as a first light emitting control transistor and a first power supply line extending along a second direction, the first direction and the second direction intersecting; the first electrode of the fifth transistor being connected to the first power supply line, the second electrode of the fifth transistor being connected to the third transistor in M first circuits through a node connection line, forming M pixel driving circuits.

[0066] In an example embodiment, M = 3.

[0067] In an example embodiment, the ratio of the width of the insertion unit to the width of the circuit unit is 0.3 to 0.5, the width being the size in the first direction.

[0068] In an exemplary embodiment, in the at least one circuit unit, the first circuit further comprises a first capacitor, a second capacitor, a first transistor as a first reset transistor, a second transistor as a second reset transistor, a fourth transistor as a data write transistor, a sixth transistor as a second light emitting control transistor, and a seventh transistor as a third reset transistor; a first electrode of the first transistor and a first electrode of the second transistor are connected with a first initial signal line respectively, a second electrode of the first transistor is connected with a second electrode plate of the first capacitor and a third electrode plate of the second capacitor respectively, a second electrode of the second transistor is connected with a gate electrode of the third transistor, a second electrode of the fourth transistor and a first electrode plate of the first capacitor respectively, a first electrode of the third transistor is connected with a second electrode of the fifth transistor, a second electrode of the third transistor is connected with a first electrode of the sixth transistor and a fourth electrode plate of the second capacitor respectively, a first electrode of the fourth transistor is connected with a data signal line, a second electrode of the sixth transistor is connected with a second electrode of the seventh transistor, and a first electrode of the seventh transistor is connected with a second initial signal line; a projection of the data signal line on a display substrate does not overlap with a projection of an active layer of the first transistor to the fourth transistor and a projection of an active layer of the sixth transistor to the seventh transistor on the display substrate.

[0069] In an exemplary embodiment, a projection of the data signal line on a display substrate does not overlap with a projection of the gate electrode of the third transistor on the display substrate.

[0070] In an exemplary embodiment, the first initial signal line has a shape of a straight line or a broken line with a main body part extending along the first direction, and the at least one repeating unit further comprises at least one first initial connection line extending along the second direction, the first initial signal line and the first initial connection line being connected to form a mesh structure for transmitting the first initial signal.

[0071] In an exemplary embodiment, the second initial signal line has a shape of a straight line or a broken line with a main body part extending along the first direction, and the at least one repeating unit further comprises at least one second initial connection line extending along the second direction, the second initial signal line and the second initial connection line being connected to form a mesh structure for transmitting the second initial signal.

[0072] In an exemplary embodiment, the at least one repeating unit further comprises at least one power supply connection line extending along the first direction and at least one second power supply line extending along the second direction, the power supply connection line and the second power supply line being connected to form a mesh structure for transmitting a second power supply signal.

[0073] The display substrate of the present embodiment is illustrated below by some examples.

[0074] The exemplary embodiments of the present disclosure provide a display substrate. In a direction perpendicular to the display substrate, the display substrate can include at least a driving structure layer disposed on a base and a light emitting structure layer disposed on a side of the driving structure layer away from the base. In a plane parallel to the display substrate, the driving structure layer can include a plurality of circuit repeating units. The circuit repeating unit is a basic unit constituting the driving structure layer, and the driving structure layer can be constituted by repeatedly and continuously disposing the circuit repeating units along a first direction X and a second direction Y. The light emitting structure layer can include a plurality of light emitting repeating units. The light emitting repeating unit is a basic unit constituting the light emitting structure layer, and the light emitting structure layer can be constituted by repeatedly and continuously disposing the light emitting repeating units along the first direction X and the second direction Y.

[0075] In the exemplary embodiments, positions of the plurality of circuit repeating units and the plurality of light emitting repeating units can be substantially corresponding, a first area of an orthographic projection of at least one circuit repeating unit on the base, and a second area of an orthographic projection of at least one light emitting repeating unit on the base, a ratio of the first area to the second area can be about 0.95 to 1.05, that is, the area of the orthographic projection of the circuit repeating unit on the base and the area of the orthographic projection of the light emitting repeating unit on the base can be substantially the same.

[0076] In the exemplary embodiments, a size of the first direction X of the at least one circuit repeating unit and a size of the first direction X of the at least one light emitting repeating unit can be substantially the same, and a size of the second direction Y of the at least one circuit repeating unit and a size of the second direction Y of the at least one light emitting repeating unit can be substantially the same.

[0077] In the exemplary embodiments, the at least one circuit repeating unit can include M circuit units and one insertion unit disposed in sequence along the first direction X, and the circuit unit can include at least a first circuit, and the insertion unit can include a second circuit. The at least one light emitting repeating unit can include M light emitting units disposed in sequence along the first direction X, and the light emitting unit can include at least a light emitting device. The area of the orthographic projection of the M first circuits and the second circuit on the base and the area of the orthographic projection of the M light emitting devices on the base can be substantially the same.

[0078] In the exemplary embodiments, the circuit unit refers to a region divided according to the first circuit, and the light emitting unit refers to a region divided according to the light emitting device. In the exemplary embodiments, the position of the orthographic projection of the light emitting unit on the base and the position of the orthographic projection of the circuit unit on the base can be corresponding, or the position of the orthographic projection of the light emitting unit on the base and the position of the orthographic projection of the circuit unit on the base can be non-corresponding.

[0079] In an exemplary embodiment, the sizes of the plurality of first circuits in the at least one circuit repeating unit can be substantially the same. The sizes of the plurality of light emitting devices in the at least one light emitting repeating unit can be substantially the same.

[0080] In the present disclosure, the size of a first circuit refers to the size of the orthographic projection of the first circuit on a substrate, and the size of a light emitting device refers to the size of the orthographic projection of the light emitting device on the substrate. When the orthographic projection of the first circuit and the light emitting device on the substrate is rectangular, the size can include any one or more of the following: the length of the orthographic projection in a first direction X, the length of the orthographic projection in a second direction Y, and the area of the orthographic projection. When the orthographic projection of the first circuit and the light emitting device on the substrate is circular or elliptical, the size can include any one or more of the following: the radius of the orthographic projection, the major axis and the minor axis of the orthographic projection, and the area of the orthographic projection.

[0081] In an exemplary embodiment, the driving structure layer can set the circuit units in a compressed manner, and the light emitting structure layer can set the light emitting units in a normal (non-compressed) manner. For example, in the normal manner, one circuit repeating unit can be provided with M circuit units, and one light emitting repeating unit can be provided with M light emitting units. In the compressed manner, by using a lateral compression manner, one additional unit is added in the area where the M circuit units are previously arranged, so that one circuit repeating unit can be provided with M circuit units + 1 additional unit. Since the light emitting structure layer uses the normal manner, the light emitting repeating unit is still provided with M light emitting devices, and the area occupied by the M circuit units + 1 additional unit is substantially the same as the area occupied by the M light emitting units.

[0082] In an exemplary embodiment, for the pixel arrangement being an RGB arrangement, M can be an integer multiple of 3, such as 3, 6 or 9. In the present embodiment, M is equal to 3, i.e., the display substrate of the present embodiment uses a 3-in-1 structure.

[0083] FIG. 4 is a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure. As shown in FIG. 4, the driving structure layer can include a plurality of circuit repeating units CF, and at least one circuit repeating unit CF can include three circuit units Q and one additional unit CQ arranged in sequence along a first direction X. The circuit unit Q can include at least a first circuit, and the additional unit CQ can include at least a second circuit.

[0084] In an exemplary embodiment, the first width L1 of the circuit unit Q can be greater than the second width L2 of the additional unit CQ. The first width L1 can be the size of the circuit unit Q in the first direction X, and the second width L2 can be the size of the additional unit CQ in the first direction X.

[0085] In an exemplary embodiment, the ratio of the second width L2 to the first width L1 can be about 0.3 to 0.5.

[0086] In an example embodiment, the ratio of the second width L2 to the first width L1 can be about 0.42 or so. For example, the first width L1 can be about 24 pm to 32 pm, and the second width L2 can be about 10 pm to 14 pm. For another example, the first width L1 can be about 28.29 pm or so, and the second width L2 can be about 12 pm or so.

[0087] In an example embodiment, the size of the circuit unit Q in the second direction Y and the size of the insertion unit CQ in the second direction Y can be substantially the same. For example, the size of the circuit unit Q and the size of the insertion unit CQ in the second direction Y can be about 85 pm to 105 pm. For another example, the size of the circuit unit Q and the size of the insertion unit CQ in the second direction Y can be about 96.87 pm or so.

[0088] In an example embodiment, the second circuit can include at least one transistor and at least one signal line. The at least one transistor is a transistor shared by the three first circuits, and the at least one signal line is a signal line shared by the three first circuits, i.e., the second circuit and the three first circuits together constitute three pixel driving circuits.

[0089] In an example embodiment, the at least one pixel driving circuit is connected to the at least one light emitting unit, the orthographic projection of the at least one pixel driving circuit on the substrate at least partially overlaps the orthographic projection of the at least one light emitting device on the substrate, and the pixel driving circuit is configured to provide a driving signal to the connected light emitting device to drive the corresponding light emitting device to emit light.

[0090] FIG. 5 is an equivalent circuit diagram of a pixel driving circuit in a repeating unit according to an example embodiment of the present disclosure. As shown in FIG. 5, the repeating unit can include three first circuits and one second circuit, the three first circuits and the one second circuit are sequentially arranged along the first direction X, and the three first circuits and the one second circuit together constitute three pixel driving circuits.

[0091] In an example embodiment, the pixel driving circuit according to an example embodiment of the present disclosure adopts a 7T2C structure, each pixel driving circuit can include seven transistors (first transistor T1 to seventh transistor T7) and two capacitors (first capacitor C1 and second capacitor C2), and the pixel driving circuit is connected to ten signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, first emission signal line EM1, second emission signal line EM2, first initial signal line INIT1, second initial signal line INIT2, data signal line DATA, and first power supply line VDD).

[0092] In the example embodiment, the pixel driving circuit can include a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5. The first node N1 is connected with the second electrode of the second transistor T2, the gate electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the first end of the first capacitor C1, respectively. The second node N2 is connected with the first electrode of the third transistor T3 and the second electrode of the fifth transistor T5, respectively. The third node N3 is connected with the second electrode of the third transistor T3, the first electrode of the sixth transistor T6, and the first end of the second capacitor C2, respectively. The fourth node N4 is connected with the second electrode of the first transistor T1, the second end of the first capacitor C1, and the second end of the second capacitor C2, respectively. The fifth node N5 is connected with the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively.

[0093] In the example embodiment, the first transistor T1 can be referred to as a first reset transistor. The gate electrode of the first transistor T1 is connected with the third scan signal line S3. The first electrode of the first transistor T1 is connected with the first initial signal line INIT1. The second electrode of the first transistor T1 is connected with the fourth node N4.

[0094] In the example embodiment, the second transistor T2 can be referred to as a second reset transistor. The gate electrode of the second transistor T2 is connected with the second scan signal line S2. The first electrode of the second transistor T2 is connected with the first initial signal line INIT1. The second electrode of the second transistor T2 is connected with the first node N1.

[0095] In the example embodiment, the third transistor T3 can be referred to as a driving transistor. The gate electrode of the third transistor T3 is connected with the first node N1. The first electrode of the third transistor T3 is connected with the second node N2. The second electrode of the third transistor T3 is connected with the third node N3.

[0096] In the example embodiment, the fourth transistor T4 can be referred to as a data writing transistor. The gate electrode of the fourth transistor T4 is connected with the fourth scan signal line S4. The first electrode of the fourth transistor T4 is connected with the data signal line DATA. The second electrode of the fourth transistor T4 is connected with the first node N1.

[0097] In the example embodiment, the fifth transistor T5 can be referred to as a first light emitting control transistor. The gate electrode of the fifth transistor T5 is connected with the first light emitting signal line EM1. The first electrode of the fifth transistor T5 is connected with the first power supply line VDD. The second electrode of the fifth transistor T5 is connected with the second node N2. The fifth transistor T5 is a transistor shared by three first circuits in the repeating unit. The first power supply line VDD is a signal line shared by three first circuits in the repeating unit. The fifth transistor T5 and the first power supply line VDD constitute a second circuit.

[0098] In an exemplary embodiment, the sixth transistor T6 can be referred to as a second light-emitting control transistor, the gate electrode of the sixth transistor T6 is connected with the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is connected with the third node N3, and the second electrode of the sixth transistor T6 is connected with the fifth node N5.

[0099] In an exemplary embodiment, the seventh transistor T7 can be referred to as a third reset transistor, the gate electrode of the seventh transistor T7 is connected with the first scan signal line S1, the first electrode of the seventh transistor T7 is connected with the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected with the fifth node N5.

[0100] In an exemplary embodiment, the first end of the first capacitor C1 is connected with the first node N1, and the second end of the first capacitor C1 is connected with the fourth node N4. The first end of the second capacitor C2 is connected with the third node N3, and the second end of the second capacitor C2 is connected with the fourth node N4.

[0101] In an exemplary embodiment, the first electrode of the light-emitting device EL is connected with the fifth node N5, and the second electrode of the light-emitting device EL is connected with the second power supply line VSS. The light-emitting device EL can be an OLED including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked, or can be a QLED including a first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode) stacked.

[0102] In an exemplary embodiment, the pixel driving circuit can further include at least one parasitic capacitor c f , the first end of the parasitic capacitor c f is connected with the fifth node N5, and the second end of the parasitic capacitor c f is connected with the second power supply line VSS.

[0103] In an exemplary embodiment, the seven transistors of the pixel driving circuit can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product.

[0104] In an exemplary embodiment, the seven transistors of the pixel driving circuit can all be oxide transistors. The active layer of the oxide transistor can be an oxide semiconductor (Oxide). The oxide transistor has advantages such as high electron mobility, low operating voltage, and low leakage characteristics. Using a display substrate provided with oxide transistors can achieve low-frequency driving, reduce power consumption, and improve display quality.

[0105] In an example embodiment, the first power line VDD can be configured to provide a constant first voltage signal to the pixel driving circuit, the second power line VSS can be configured to provide a constant second voltage signal to the light emitting device, and the first voltage signal is a high level signal and the second voltage signal is a low level signal. The first initial signal line INIT1 and the second initial signal line INIT2 can be configured to provide a constant signal to the pixel driving circuit, which is not limited in the present disclosure.

[0106] FIG. 6 is a driving timing diagram of the pixel driving circuit shown in FIG. 5. As shown in FIG. 6, in an example embodiment, the working process of the pixel driving circuit can include:

[0107] The first stage A1 is called a reset stage. The signals of the first scan signal line S1, the second scan signal line S2, the third scan signal line S3 and the second emission signal line EM2 are high level signals, and the signals of the fourth scan signal line S4 and the first emission signal line EM1 are low level signals, so that the first transistor T1, the second transistor T2, the sixth transistor T6 and the seventh transistor T7 are turned on, and other switch transistors are turned off.

[0108] The turn-on of the first transistor T1 and the second transistor T2 enables the first initial signal provided by the first initial signal line INIT1 to be provided to the first node N1 and the fourth node N4, so that the first node N1 and the fourth node N4 are initialized, and the potentials of the first node N1 and the fourth node N4 are Vinit1. The turn-on of the sixth transistor T6 and the seventh transistor T7 enables the second initial signal provided by the second initial signal line INIT2 to be provided to the third node N3 and the fifth node N5, so that the third node N3 and the fifth node N5 are initialized, and the potentials of the third node N3 and the fifth node N5 are Vinit2. At the same time, the third transistor T3 can be turned on by the voltage difference (Vinit1-Vinit2) between the first node N1 and the third node N3, so that the second node N2 is connected to the third node N3, and the second node N2 is initialized, and the potential of the second node N2 is Vinit2.

[0109] In an example embodiment, Vinit1 is the voltage of the first initial signal, and Vinit2 is the voltage of the second initial signal. For example, Vinit1 can be 1.5V to 3.5V, and Vinit2 can be 0.5V to 2.5V. For another example, Vinit1 can be about 2.5V, and Vinit2 can be about 1.5V.

[0110] In the example embodiment, the reset of the first node N1, the third node N3, the fourth node N4 and the fifth node N5 can be performed in stages. For example, at a first time, the second scan signal line S2 changes from a low level signal to a high level signal, the second transistor T2 is turned on, and the first node N1 is reset. At a second time, the first scan signal line S1 changes from a low level signal to a high level signal, the seventh transistor T7 is turned on, and the fifth node N5 is reset. At a third time, the third scan signal line S3 changes from a low level signal to a high level signal, the first transistor T1 is turned on, and the fourth node N4 is reset. At a fourth time, the second emission signal line EM2 changes from a low level signal to a high level signal, the sixth transistor T6 is turned on, and the third node N3 is reset.

[0111] The second stage A2 is called a compensation stage. The signals of the second scan signal line S2, the third scan signal line S3 and the first emission signal line EM1 are high level signals, the signals of the first scan signal line S1 and the fourth scan signal line S4 are low level signals, the first transistor T1, the second transistor T2 and the fifth transistor T5 are turned on, and the other switch transistors are turned off.

[0112] The turn-on of the first transistor T1 and the second transistor T2 makes the potentials of the first node N1 and the fourth node N4 continue to be Vinit1, the turn-on of the fifth transistor T5 makes the first power signal output by the first power supply line VDD be written into the second node N2 through the turned-on fifth transistor T5, and the turn-on of the third transistor T3 makes the potential of the third node N3 gradually increase to Vinit1-Vth, where Vth is the threshold voltage of the third transistor T3. At this time, since the potential of the fourth node N4 is Vinit1, the potential stored by the second capacitor C2 is the threshold voltage Vth, that is, the threshold voltage Vth of the third transistor T3 is written into the second capacitor C2.

[0113] The third stage A3 is called a data writing stage. The signals of the second scan signal line S2 and the third scan signal line S3 are high level signals for a period of time and then change to low level signals, the signal of the fourth scan signal line S4 is a high level signal for a short time, the signals of the first scan signal line S1, the first emission signal line EM1 and the second emission signal line EM2 are low level signals, the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned on and then turned off.

[0114] At the first time, the second scan signal line S2 changes from a high level signal to a low level signal, the second transistor T2 is turned off, the potential of the first node N1 is slightly fluctuated, but the potentials of the third node N3 and the fourth node N4 are less disturbed.

[0115] At the second moment, the signal of the fourth scan signal line S4 changes from low level signal to high level signal, the fourth transistor T4 is turned on so that the data signal outputted by the data signal line DATA is written into the first node N1, i.e. stored in the first capacitor C1, the potential of the first node N1 becomes Vd, Vd is the voltage of the data signal outputted by the data signal line DATA. When the data signal is written into the first node N1, the fourth node N4 is stabilized at the Vinit1 potential because the first transistor T1 is turned on, so the potential of the third node N3 is Vinit1-Vth. In addition, because the third transistor T3 between the first node N1 and the third node N3 is turned off, the writing of the data signal into the first node N1 does not disturb the potential of the third node N3.

[0116] At the third moment, the third scan signal line S3 changes from high level signal to low level signal, the first transistor T1 is turned off, and because the data writing has been completed at this moment, the potential of the first node N1 does not change.

[0117] The fourth stage A4 is called the light emitting stage. The signals of the first emitting signal line EM1 and the second emitting signal line EM2 are high level signals, and the signals of the first scan signal line S1, the second scan signal line S2, the third scan signal line S3 and the fourth scan signal line S4 are low level signals, so the fifth transistor T5 and the sixth transistor T6 are turned on.

[0118] At the first moment, the second emitting signal line EM2 changes from low level signal to high level signal, the sixth transistor T6 is turned on, and the potential of the third node N3 is written into the fifth node N5, so the fifth node N5 is pre-charged in advance. At the second moment, the first emitting signal line EM1 changes from low level signal to high level signal, the fifth transistor T5 is turned on, so that the first power signal outputted by the first power supply line VDD provides driving voltage to the first electrode of the light emitting element EL through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, and drives the light emitting element EL to emit light.

[0119] The output current I of the third transistor T3 OLED satisfies the following formula: I OLED =1 / 2*K1*[Vd-[Vinit1-Vth]-Vth] 2 =1 / 2*K2*(Vd-Vinit1) 2 .

[0120] wherein K1 is a constant related to process and design.

[0121] According to the formula of the output current of the third transistor T3, it can be seen that the output current of the pixel driving circuit is irrelevant to the threshold voltage Vth of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the output current, and the control of the output current can be realized by controlling the voltage Vd of the data signal to control the brightness of the light emitting device EL.

[0122] FIG. 7 is a schematic diagram of a planar structure of a repeating unit according to an exemplary embodiment of the present disclosure. In a plane perpendicular to the display substrate, the display substrate can include a driving structure layer disposed on a base, a light emitting structure layer disposed on a side of the driving structure layer away from the base, and an encapsulation structure layer disposed on a side of the light emitting structure layer away from the base. In a plane parallel to the display substrate, the driving structure layer can include a plurality of repeating units, and the light emitting structure layer can include a plurality of light emitting devices.

[0123] As shown in FIG. 7, at least one repeating unit can include 3 circuit units (a first circuit unit, a second circuit unit, and a third circuit unit) and 1 insertion unit, and the first circuit unit, the second circuit unit, the third circuit unit, and the insertion unit can be sequentially disposed along a first direction X, i.e., the second circuit unit can be disposed on a side of the first circuit unit in the first direction X, the third circuit unit can be disposed on a side of the second circuit unit in the first direction X, and the insertion unit can be disposed on a side of the third circuit unit in the first direction X.

[0124] In the exemplary implementation, the first circuit unit, the second circuit unit, and the third circuit unit can each include a first circuit, and at least one first circuit can include at least a first capacitor 10, a second capacitor 20, a first transistor T1 as a first reset transistor, a second transistor T2 as a second reset transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a sixth transistor T6 as a second light emitting control transistor, and a seventh transistor T7 as a third reset transistor. In the exemplary implementation, the first circuit can be connected with a first scan signal line 61, a second scan signal line 62, a third scan signal line 63, a fourth scan signal line 64, a second light emitting signal line 66, a first initial signal line 71, a second initial signal line 72, and a data signal line 83, respectively.

[0125] In the exemplary implementation, the insertion unit can include a second circuit, and the second circuit can include at least a fifth transistor T5 as a first light emitting control transistor and a first power supply line 81, a gate electrode of the fifth transistor T5 can be connected with the first light emitting signal line 65, and a first electrode of the fifth transistor T5 can be connected with the first power supply line 81.

[0126] In an example embodiment, the second circuit can be a circuit portion shared by the three first circuits in the repeating unit, that is, the fifth transistor T5 is a transistor shared by the three first circuits in the repeating unit, and the first power supply line VDD is a signal line shared by the three first circuits in the repeating unit. The first circuit of the first circuit unit and the second circuit of the insertion unit together constitute a first pixel driving circuit, the first circuit of the second circuit unit and the second circuit of the insertion unit together constitute a second pixel driving circuit, and the first circuit of the third circuit unit and the second circuit of the insertion unit together constitute a third pixel driving circuit. The first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit are configured to output corresponding currents to the connected light emitting devices.

[0127] In an example embodiment, the first to fourth scan signal lines 61 to 64 are configured to provide the first to fourth scan signals to the pixel driving circuits, respectively, the first and second light emitting signal lines 65 and 66 are configured to provide the first and second light emitting control signals to the pixel driving circuits, respectively, the first and second initial signal lines 71 and 72 are configured to provide the first and second initial signals to the pixel driving circuits, respectively, the data signal line 83 is configured to provide the data signal to the pixel driving circuit, and the first power supply line 81 is configured to provide the first power supply signal to the pixel driving circuit.

[0128] In an example embodiment, the first to seventh transistors T1 to T7 can be oxide transistors, the first capacitor can include a first plate and a second plate stacked, and the second capacitor can include a third plate and a fourth plate stacked.

[0129] In the exemplary embodiment, the gate electrode of the first transistor T1 is connected to the third scan signal line 63, the first electrode of the first transistor T1 is connected to the first initial signal line 71, and the second electrode of the first transistor T1 is connected to the second electrode plate of the first capacitor 10 and the third electrode plate of the second capacitor 20. The gate electrode of the second transistor T2 is connected to the second scan signal line 62, the first electrode of the second transistor T2 is connected to the first initial signal line 71, and the second electrode of the second transistor T2 is connected to the gate electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the first electrode plate of the first capacitor 10, respectively. The first electrode of the third transistor T3 is connected to the second electrode of the fifth transistor T5, and the second electrode of the third transistor T3 is connected to the first electrode of the sixth transistor T6 and the fourth electrode plate of the second capacitor 20, respectively. The gate electrode of the fourth transistor T4 is connected to the fourth scan signal line 64, and the first electrode of the fourth transistor T4 is connected to the data signal line 83. The gate electrode of the fifth transistor T5 is connected to the first emission signal line 65, and the first electrode of the fifth transistor T5 is connected to the first power supply line 81. The gate electrode of the sixth transistor T6 is connected to the second emission signal line 66, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7. The gate electrode of the seventh transistor T7 is connected to the first scan signal line 61, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 72.

[0130] In the exemplary embodiment, the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the first emission signal line 65, the second emission signal line 66, the first initial signal line 71, and the second initial signal line 72 can have a shape of a straight line or a broken line in which a main portion extends along the first direction X. The first power supply line 81 and the data signal line 83 can have a shape of a straight line or a broken line in which a main portion extends along the second direction Y.

[0131] In the present disclosure, A extending along a direction B means that A can include a main portion and a sub-portion connected to the main portion, the main portion is a line, a line segment, or a bar-shaped body, the main portion extends along the direction B, and the length of the main portion extending along the direction B is greater than the length of the sub-portion extending along other directions. In the following description, A extending along the direction B means that the main portion of A extends along the direction B.

[0132] In an exemplary embodiment, in at least one of the circuit units, the orthogonal projection of the data signal line 83 on the substrate does not overlap with the orthogonal projection of the active layer of the first transistor T1 on the substrate, the orthogonal projection of the data signal line 83 on the substrate does not overlap with the orthogonal projection of the active layer of the second transistor T2 on the substrate, the orthogonal projection of the data signal line 83 on the substrate does not overlap with the orthogonal projection of the active layer of the third transistor T3 on the substrate, the orthogonal projection of the data signal line 83 on the substrate does not overlap with the orthogonal projection of the active layer of the fourth transistor T4 on the substrate, the orthogonal projection of the data signal line 83 on the substrate does not overlap with the orthogonal projection of the active layer of the sixth transistor T6 on the substrate, and the orthogonal projection of the data signal line 83 on the substrate does not overlap with the orthogonal projection of the active layer of the seventh transistor T7 on the substrate.

[0133] In an exemplary embodiment, in at least one of the circuit units, the orthogonal projection of the data signal line 83 on the substrate does not overlap with the orthogonal projection of the gate electrode of the third transistor T3 on the substrate.

[0134] In an exemplary embodiment, the first pole of the third transistor T3 in the three circuit units can be connected with the second pole of the fifth transistor T5 through a node connecting line 48. The shape of the node connecting line 48 can be a straight line or a broken line extending along the first direction X, and the node connecting line 48 can be arranged on the side of the circuit unit away from the first capacitor 10.

[0135] In an exemplary embodiment, in at least one of the circuit units, the node connecting electrode 60 can be further included, the first end of the node connecting electrode 60 is connected with the second pole of the fifth transistor T5, and the second end of the node connecting electrode 60 is connected with the node connecting line 48, so as to realize the connection between the node connecting line 48 and the second pole of the fifth transistor T5.

[0136] In an exemplary embodiment, in at least one of the circuit units, the node connecting block 59 can be further included, the first end of the node connecting block 59 is connected with the node connecting line 48, and the second end of the node connecting block 59 is connected with the first pole of the third transistor T3, so as to realize the connection between the node connecting line 48 and the first pole of the third transistor T3.

[0137] In an exemplary embodiment, in at least one of the circuit units, the second end of the node connecting electrode 60 is connected with the node connecting block 59, that is, the node connecting electrode 60 is connected with the node connecting line 48 through the node connecting block 59.

[0138] In an exemplary embodiment, the third transistor T3 can include at least a third active layer, and the first pole of the third transistor T3 refers to a first region of the third active layer. The fifth transistor T5 can include at least a fifth active layer, and the second pole of the fifth transistor T5 refers to a second region of the fifth active layer.

[0139] FIG. 8 is a schematic diagram of a mesh structure according to an example embodiment of the present disclosure. As shown in FIGS. 7 and 8, the at least one repeating unit can further include at least one power connection line 24 extending along the first direction X and at least one second power line 82 extending along the second direction Y, and the power connection line 24 is connected with the second power line 82 to form a mesh structure for transmitting a second power signal.

[0140] In an example embodiment, the second power line 82 can be disposed in the at least one circuit unit. For example, the second power line 82 can be disposed in the first circuit unit and the third circuit unit, respectively.

[0141] In an example embodiment, in the at least one circuit unit, a projection of the second power line 82 on the substrate at least partially overlaps with a projection of the active layers of the first transistor T1 to the fourth transistor T4 and the active layers of the sixth transistor T6 to the seventh transistor T7 on the substrate.

[0142] In an example embodiment, the at least one repeating unit can further include at least one first initial connection line 21 extending along the second direction Y, and the first initial connection line 21 is connected with the first initial signal line 71 to form a mesh structure for transmitting a first initial signal.

[0143] In an example embodiment, the first initial connection line 21 is disposed in the insertion unit and located on one side of the first power line 81 in the first direction X.

[0144] In an example embodiment, the at least one repeating unit can further include at least one second initial connection line 22 extending along the second direction Y, and the second initial connection line 22 is connected with the second initial signal line 72 to form a mesh structure for transmitting a second initial signal.

[0145] In an example embodiment, the second initial connection line 22 can be disposed in the at least one circuit unit. For example, the second initial connection line 22 can be disposed in the second circuit unit.

[0146] In an example embodiment, in the at least one circuit unit, a projection of the second initial connection line 22 on the substrate at least partially overlaps with a projection of the active layers of the first transistor T1 to the fourth transistor T4 and the active layers of the sixth transistor T6 to the seventh transistor T7 on the substrate.

[0147] In the exemplary embodiment, in the direction perpendicular to the substrate, the driving circuit layer can include, in sequence from the direction away from the substrate, a first conductive layer (first gate metal layer), a second conductive layer (second gate metal layer), a semiconductor layer, a third conductive layer (third gate metal layer), a fourth conductive layer (first source-drain metal layer), and a fifth conductive layer (second source-drain metal layer). The first plate of the first capacitor 10, the third plate of the second capacitor 20, and the power connection line 24 can be disposed in the first conductive layer, the second plate of the first capacitor 10, the fourth plate of the second capacitor 20, and the first initial connection line 21 can be disposed in the second conductive layer, the gate electrodes of the first transistor T1 to the seventh transistor T7 can be disposed in the third conductive layer, the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the first light-emitting signal line 65, the second light-emitting signal line 66, the first initial signal line 71, and the second initial signal line 72 can be disposed in the fourth conductive layer, and the first power line 81, the second power line 82, the data signal line 83, and the second initial connection line 22 can be disposed in the fifth conductive layer.

[0148] The preparation process of the substrate is exemplarily illustrated below by the present exemplary embodiment. The "patterning process" of the present disclosure includes, for metal materials, inorganic materials, or transparent conductive materials, deposition of a film layer, coating photoresist on the film layer, mask exposure, development, etching, stripping of photoresist, and the like, and for organic materials, coating of organic materials, mask exposure, development, and the like. The deposition can use any one or more of sputtering, evaporation, chemical vapor deposition, the coating can use any one or more of spraying, spin coating, and inkjet printing, and the etching can use any one or more of dry etching and wet etching, which are not limited by the present disclosure. The "thin film" refers to a thin film of a certain material made on a substrate by deposition, coating, or other processes. If the "thin film" does not need a patterning process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" needs a patterning process during the entire manufacturing process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are disposed in the same layer" of the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiment of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.

[0149] In the example embodiment, taking four circuit units of one unit row (Mth unit row) and three unit columns (Nth unit column, N+1th unit column, N+2th unit column) as an example, the preparation process of the substrate can include the following operations.

[0150] (11) Forming a first conductive layer pattern. In the example embodiment, forming the first conductive layer pattern can include: depositing a first conductive film on the substrate, patterning the first conductive film through a patterning process, and forming the first conductive layer pattern on the substrate, as shown in FIG. 9. In the example embodiment, the first conductive layer can be referred to as a first gate metal (GATE1) layer.

[0151] In the example embodiment, the first conductive layer pattern of each circuit unit in the display substrate can at least include a first plate 11 of a first capacitor, a third plate 13 of a second capacitor, a first plate connecting block 15, a third plate connecting block 16, and a power supply connecting line 24.

[0152] In the example embodiment, the shape of the first plate 11 of the first capacitor can be a rectangular shape, and the first plate 11 is configured as a lower plate of the first capacitor.

[0153] In the example embodiment, the corner (upper left corner) formed by the side opposite to the first direction X and the side opposite to the second direction Y of the first plate 11 can be provided with a first recess, and the first recess is configured to accommodate the first plate connecting block 15.

[0154] In the example embodiment, the shape of the third plate 13 of the second capacitor can be a rectangular shape, and the third plate 13 is configured as a lower plate of the second capacitor.

[0155] In the example embodiment, the third plate 13 can be arranged on the side opposite to the second direction Y of the first plate 11, and the corner (lower right corner) formed by the side of the first direction X and the side of the second direction Y of the third plate 13 can be provided with a third recess, and the third recess is configured to accommodate the third plate connecting block 16.

[0156] In the example embodiment, the shape of the first plate connecting block 15 can be a strip shape extending along the second direction Y, and arranged in the first recess. The first end of the first plate connecting block 15 is connected to the first plate 11, and the second end of the first plate connecting block 15 extends in the direction away from the first plate 11 along the direction opposite to the second direction Y, and the first plate connecting block 15 is configured to be connected to the first connecting electrode formed subsequently.

[0157] In the example embodiment, the third plate connecting block 16 can have a shape of a bar extending along the first direction X and be disposed in the third groove. The first end of the third plate connecting block 16 is connected to the third plate 13, and the second end of the third plate connecting block 16 extends along the first direction X away from the third plate 13, and the third plate connecting block 16 is configured to be connected to the fifth connecting electrode formed later.

[0158] In the example embodiment, the power supply connecting line 24 can have a shape of a broken line extending along the first direction X or a broken line shape, and be disposed on the side of the first plate 11 away from the third plate 13, and the power supply connecting line 24 is configured to be connected to the sixth connecting electrode formed later.

[0159] (12) Forming a second conductive layer pattern. In the example embodiment, forming the second conductive layer pattern can include: sequentially depositing a first insulating thin film and a second conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the second conductive thin film by a patterning process, forming a first insulating layer covering the first conductive layer pattern, and a second conductive layer pattern disposed on the first insulating layer, as shown in FIGS. 10A and 10B, FIG. 10B is a plan view of the second conductive layer in FIG. 10A. In the example embodiment, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0160] In the example embodiment, the second conductive layer pattern of each circuit unit in the display substrate at least includes: the second plate 12 of the first capacitor, the fourth plate 14 of the second capacitor, the first initial connecting line 21, and the fifth node electrode 23.

[0161] In the example embodiment, the second plate 12 of the first capacitor can have a rectangular shape, and the orthographic projection of the second plate 12 on the substrate at least partially overlaps the orthographic projection of the first plate 11 on the substrate, and the second plate 12 is configured as the upper plate of the first capacitor, and the first plate 11 and the second plate 12 constitute the first capacitor.

[0162] In the example embodiment, the orthographic projection of the first plate 11 on the substrate is within the range of the orthographic projection of the second plate 12 on the substrate.

[0163] In the example embodiment, the corner (top left corner) formed by the side of the second plate 12 in the opposite direction of the first direction X and the side of the second plate 12 in the opposite direction of the second direction Y can be provided with a second groove, and the second groove exposes the first plate connecting block 15.

[0164] In an exemplary embodiment, the fourth plate 14 of the second capacitor can be rectangular in shape, the orthographic projection of the fourth plate 14 on the substrate at least partially overlaps the orthographic projection of the third plate 13 on the substrate, the fourth plate 14 is configured as the upper plate of the second capacitor, and the third plate 13 and the fourth plate 14 constitute the second capacitor.

[0165] In an exemplary embodiment, the orthographic projection of the third plate 13 on the substrate is within the range of the orthographic projection of the fourth plate 14 on the substrate.

[0166] In an exemplary embodiment, the fourth plate 14 can be disposed on the side opposite to the second direction Y of the second plate 12, and the corner (lower right corner) formed by the side of the first direction X and the side of the second direction Y of the fourth plate 14 can be provided with a fourth groove, and the fourth groove exposes the third plate connecting block 16.

[0167] In an exemplary embodiment, the first initial connection line 21 can be a broken line shape extending along the second direction Y or a broken line shape, and can be disposed in the insertion unit, and the first initial connection line 21 is configured to be connected with the first initial signal line formed subsequently.

[0168] In an exemplary embodiment, the fifth node electrode 23 can be a strip shape extending along the first direction X, and can be disposed on the side of the second plate 12 away from the fourth plate 14, and the fifth node electrode 23 is configured to be connected with the seventh connection electrode formed subsequently.

[0169] In an exemplary embodiment, the orthographic projection of the fifth node electrode 23 on the substrate at least partially overlaps the orthographic projection of the power connection line 24 on the substrate, and the fifth node electrode 23 and the power connection line 24 are configured to form a parasitic capacitor c f .

[0170] (13) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern can include: on the substrate on which the aforementioned pattern is formed, sequentially depositing a second insulating thin film and a semiconductor thin film, patterning the semiconductor thin film by a patterning process, forming a second insulating layer covering the second conductive layer, and a semiconductor layer pattern disposed on the second insulating layer, as shown in FIGS. 11A and 11B, FIG. 11B is a plan view of the semiconductor layer in FIG. 11A.

[0171] In an example embodiment, the semiconductor layer pattern of each circuit unit in the display substrate can include a first active layer 31 of the first transistor T1 to a fourth active layer 34 of the fourth transistor T4, a sixth active layer 36 of the sixth transistor T6, and a seventh active layer 37 of the seventh transistor T7, and the first active layer 31, the second active layer 32, and the fourth active layer 34 can be an integral structure connected to each other, and the third active layer 33, the sixth active layer 36, and the seventh active layer 37 can be an integral structure connected to each other.

[0172] In an example embodiment, the fifth active layer 35 of the fifth transistor T5 can be disposed in the insertion unit.

[0173] In an example embodiment, in the first direction X, the first active layer 31, the second active layer 32, and the fourth active layer 34 can be located on the same side of the third active layer 33 in the first direction X. In the second direction Y, the first active layer 31, the second active layer 32, the sixth active layer 36, and the seventh active layer 37 can be located on one side of the third active layer 33 in the second direction Y.

[0174] In an example embodiment, the first active layer 31 to the sixth active layer 36 can have a strip shape extending along the second direction Y, and the seventh active layer 37 can have an "L" shape.

[0175] In an example embodiment, the orthographic projection of the third active layer 33 on the base can at least partially overlap the orthographic projection of the fourth plate 14 on the base, and the fourth plate 14 can also serve as the bottom gate electrode of the third transistor.

[0176] In an example embodiment, the orthographic projection of the third active layer 33 on the base can be located within the range of the orthographic projection of the fourth plate 14 on the base.

[0177] In the example embodiment, the active layer of each transistor can include a first region, a second region, and a channel region between the first region and the second region. In the example embodiment, the first region 31-1 of the first active layer and the first region 32-1 of the second active layer can be connected to each other, and the first region 31-1 of the first active layer can serve as the first region 32-1 of the second active layer. The second region 33-2 of the third active layer and the first region 36-1 of the sixth active layer can be connected to each other, and the second region 33-2 of the third active layer can serve as the first region 36-1 of the sixth active layer. The second region 36-2 of the sixth active layer and the second region 37-2 of the seventh active layer can be connected to each other, and the second region 36-2 of the sixth active layer can serve as the second region 37-2 of the seventh active layer. The second region 31-2 of the first active layer, the second region 32-2 of the second active layer, the first region 33-1 of the third active layer, the first region 34-1 of the fourth active layer 34, the second region 34-2 of the fourth active layer, the first region of the fifth active layer, the second region 35-2 of the fifth active layer, and the first region 37-1 of the seventh active layer can be provided separately, but the second region 32-2 of the second active layer and the second region 34-2 of the fourth active layer can be connected to each other.

[0178] In the example embodiment, the semiconductor layer can employ an oxide, i.e., the first transistor T1 to the seventh transistor T7 are oxide transistors, which have advantages such as high electron mobility, low operating voltage, low leakage characteristics, etc. In the example embodiment, the oxide can be any one or more of indium gallium zinc oxide (InGaZnO), indium gallium zinc nitrogen oxide (InGaZnON), zinc oxide (ZnO), zinc nitrogen oxide (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper oxide sulfur oxide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). In some possible implementations, the semiconductor thin film can employ indium gallium zinc oxide (IGZO), which has higher electron mobility than amorphous silicon.

[0179] (14) forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern can include: sequentially depositing a third insulating thin film and a third conductive thin film on the substrate on which the aforementioned patterns are formed, patterning the third conductive thin film by a patterning process, forming a third insulating layer covering the semiconductor layer pattern, and a third conductive layer pattern disposed on the third insulating layer, as shown in FIGS. 12A and 12B, which is a schematic view of the third conductive layer in FIG. 12A. In an exemplary embodiment, the third conductive layer can be referred to as a third gate metal (GATE3) layer.

[0180] In an exemplary embodiment, the third conductive layer pattern of each circuit unit in the display substrate at least includes: a first gate electrode 41, a second gate electrode 42, a third gate electrode 43, a fourth gate electrode 44, a sixth gate electrode 46, and a seventh gate electrode 47.

[0181] In an exemplary embodiment, the first gate electrode 41 can be in a block shape (e.g., a rectangular shape), a normal projection of the first gate electrode 41 on the substrate at least partially overlaps a normal projection of the first active layer on the substrate, and the first gate electrode 41 can serve as a gate electrode of the first transistor T1.

[0182] In an exemplary embodiment, the second gate electrode 42 can be in a block shape (e.g., a rectangular shape), a normal projection of the second gate electrode 42 on the substrate at least partially overlaps a normal projection of the second active layer on the substrate, and the second gate electrode 42 can serve as a gate electrode of the second transistor T2.

[0183] In an exemplary embodiment, the third gate electrode 43 can be in a block shape (e.g., a rectangular shape), a normal projection of the third gate electrode 43 on the substrate at least partially overlaps a normal projection of the third active layer on the substrate, and the third gate electrode 43 can serve as a top gate electrode of the third transistor T3.

[0184] In an exemplary embodiment, the fourth gate electrode 44 can be in a block shape (e.g., a rectangular shape), a normal projection of the fourth gate electrode 44 on the substrate at least partially overlaps a normal projection of the fourth active layer on the substrate, and the fourth gate electrode 44 can serve as a gate electrode of the fourth transistor T4.

[0185] In an exemplary embodiment, the sixth gate electrode 46 can be in a block shape (e.g., a rectangular shape), a normal projection of the sixth gate electrode 46 on the substrate at least partially overlaps a normal projection of the sixth active layer on the substrate, and the sixth gate electrode 46 can serve as a gate electrode of the sixth transistor T6.

[0186] In an exemplary embodiment, the seventh gate electrode 47 can be in a block shape (e.g., a rectangular shape), and a normal projection of the seventh gate electrode 47 on the substrate at least partially overlaps a normal projection of the seventh active layer on the substrate. The seventh gate electrode 47 can serve as a gate electrode of the seventh transistor T7.

[0187] In an exemplary embodiment, the fifth gate electrode 45 can be disposed in the insertion unit. The fifth gate electrode 45 can be in a block shape (e.g., a rectangular shape), and a normal projection of the fifth gate electrode 45 on the substrate at least partially overlaps a normal projection of the fifth active layer on the substrate. The fifth gate electrode 45 can serve as a gate electrode of the fifth transistor T5.

[0188] In an exemplary embodiment, the third conductive layer pattern can further include a node connection line 48. The node connection line 48 can be in a straight line shape or a polyline shape extending along the first direction X and can be disposed on a side of the fourth plate 14 away from the second plate 12. The node connection line 48 can be provided with a second node connection block 48-1, which can be in a block shape. A first end of the second node connection block 48-1 is connected to the node connection line 48, and a second end of the second node connection block 48-1 extends toward the fourth plate 14. The second end of the second node connection block 48-1 is configured to be connected to a ninth connection electrode formed later.

[0189] In an exemplary embodiment, the second node connection block 48-1 can be disposed in each circuit unit, and a normal projection of the second node connection block 48-1 on the substrate at least partially overlaps a normal projection of the fourth plate 14 on the substrate.

[0190] (15) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern can include: depositing a fourth insulating thin film on the substrate on which the aforementioned patterns are formed, and patterning the fourth insulating thin film by using a patterning process to form a fourth insulating layer covering the third conductive layer, the fourth insulating layer being provided with a plurality of vias, as shown in FIG. 13.

[0191] In an exemplary embodiment, the plurality of vias of each circuit unit in the display substrate at least include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a nineteenth via V19, a twentieth via V20, a twenty-first via V21, and a twenty-second via V22.

[0192] In an example embodiment, the first via V1 is configured such that a first initial signal line formed subsequently is connected to the first region of the first active layer (also the first region of the second active layer) through the first via V1.

[0193] In an example embodiment, the second via V2 is configured such that the fourth connection electrode formed subsequently is connected to the second region of the first active layer through the second via V2.

[0194] In an example embodiment, the third via V3 is configured such that the first connection electrode formed subsequently is connected to the second region of the second active layer through the third via V3.

[0195] In an example embodiment, the fourth via V4 is configured such that the ninth connection electrode formed subsequently is connected to the first region of the third active layer through the fourth via V4.

[0196] In an example embodiment, the fifth via V5 is configured such that a third connection electrode formed subsequently is connected to the first region of the second region of the third active layer (also the first region of the sixth active layer) through the fifth via V5.

[0197] In an example embodiment, the sixth via V6 is configured such that the eighth connection electrode formed subsequently is connected to the first region of the fourth active layer through the sixth via V6.

[0198] In an example embodiment, the seventh via V7 is configured such that the second connection electrode formed subsequently is connected to the second region of the fourth active layer through the via.

[0199] In an example embodiment, the eighth via V8 is configured such that the seventh connection electrode formed subsequently is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the via.

[0200] In an example embodiment, the ninth via V9 is configured such that the second initial signal line formed subsequently is connected to the first region of the seventh active layer through the via.

[0201] In an example embodiment, the tenth via V10 is configured such that the ninth connection electrode formed subsequently is connected to the second node connection block 48-1 through the via.

[0202] In an example embodiment, the eleventh via V11 is configured such that the third scan signal line formed subsequently is connected to the first gate electrode 41 through the via.

[0203] In an example embodiment, the twelfth via V12 is configured such that the second scan signal line formed subsequently is connected to the second gate electrode 42 through the via.

[0204] In the example embodiment, the thirteenth via V13 is located within the range of the orthogonal projection of the third gate electrode 43 on the substrate, the fourth insulating layer in the thirteenth via V13 is etched away to expose the surface of the third gate electrode 43, and the thirteenth via V13 is configured to enable the second connection electrode formed subsequently to connect with the third gate electrode 43 through the via.

[0205] In the example embodiment, the fourteenth via V14 is located within the range of the orthogonal projection of the fourth gate electrode 44 on the substrate, the fourth insulating layer in the fourteenth via V14 is etched away to expose the surface of the fourth gate electrode 44, and the fourteenth via V14 is configured to enable the fourth scan signal line formed subsequently to connect with the fourth gate electrode 44 through the via.

[0206] In the example embodiment, the fifteenth via V15 is located within the range of the orthogonal projection of the sixth gate electrode 46 on the substrate, the fourth insulating layer in the fifteenth via V15 is etched away to expose the surface of the sixth gate electrode 46, and the fifteenth via V15 is configured to enable the second light-emitting signal line formed subsequently to connect with the sixth gate electrode 46 through the via.

[0207] In the example embodiment, the sixteenth via V16 is located within the range of the orthogonal projection of the seventh gate electrode 47 on the substrate, the fourth insulating layer in the sixteenth via V16 is etched away to expose the surface of the seventh gate electrode 47, and the sixteenth via V16 is configured to enable the first scan signal line formed subsequently to connect with the seventh gate electrode 47 through the via.

[0208] In the example embodiment, the seventeenth via V17 is located within the range of the orthogonal projection of the first plate connecting block 15 on the substrate, the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer in the seventeenth via V17 are etched away to expose the surface of the first plate connecting block 15, and the seventeenth via V17 is configured to enable the first connection electrode formed subsequently to connect with the first plate connecting block 15 through the via.

[0209] In the example embodiment, the eighteenth via V18 is located within the range of the orthogonal projection of the third plate connecting block 16 on the substrate, the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer in the seventeenth via V17 are etched away to expose the surface of the third plate connecting block 16, and the eighteenth via V18 is configured to enable the fifth connection electrode formed subsequently to connect with the third plate connecting block 16 through the via.

[0210] In the example embodiment, the normal projection of the nineteenth via V19 and the twentieth via V20 on the substrate is within the range of the normal projection of the second plate 12 on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the nineteenth via V19 and the twentieth via V20 are etched away, exposing the surface of the second plate 12. In the example embodiment, the nineteenth via V19 is located close to the second via V2, and the nineteenth via V19 is configured to connect the fourth connecting electrode formed subsequently therethrough to the second plate 12. The twentieth via V20 is located close to the eighteenth via V18, and the twentieth via V20 is configured to connect the fifth connecting electrode formed subsequently therethrough to the second plate 12.

[0211] In the example embodiment, the normal projection of the twenty-first via V21 on the substrate is within the range of the normal projection of the fourth plate 14 on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the twenty-first via V21 are etched away, exposing the surface of the fourth plate 14, and the twenty-first via V21 is configured to connect the third connecting electrode formed subsequently therethrough to the fourth plate 14.

[0212] In the example embodiment, the normal projection of the twenty-second via V22 on the substrate is within the range of the normal projection of the fifth node electrode 23 on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the twenty-second via V22 are etched away, exposing the surface of the fifth node electrode 23, and the twenty-second via V22 is configured to connect the seventh connecting electrode formed subsequently therethrough to the fifth node electrode 23.

[0213] In the example embodiment, the at least one circuit unit can further include a twenty-third via V23. The normal projection of the twenty-third via V23 on the substrate is within the range of the normal projection of the power connection line 24 on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the twenty-third via V23 are etched away, exposing the surface of the power connection line 24, and the twenty-third via V23 is configured to connect the sixth connecting electrode formed subsequently therethrough to the power connection line 24. In the example embodiment, the twenty-third via V23 can be provided in the circuit units of the Nth unit column and the N+2th unit column.

[0214] In the example embodiment, the insertion unit can further include a twenty-fourth via V24, a twenty-fifth via V25, a twenty-sixth via V26 and a twenty-seventh via V27.

[0215] In an example embodiment, the second twenty-fourth via V24 is configured to connect a power supply connection electrode formed subsequently therewith the first region of the fifth active layer through the via.

[0216] In an example embodiment, the second twenty-fifth via V25 is configured to connect a tenth connection electrode formed subsequently therewith the second region of the fifth active layer through the via.

[0217] In an example embodiment, the second twenty-sixth via V26 is configured to connect a first light emitting signal line formed subsequently therewith the fifth gate electrode 45 through the via.

[0218] In an example embodiment, the second twenty-seventh via V27 is configured to connect a first initial signal line formed subsequently therewith the first initial connection line 21 through the via.

[0219] (16) Forming a fourth conductive layer pattern. In an example embodiment, forming the fourth conductive layer can include: depositing a fourth conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive thin film using a patterning process, and forming the fourth conductive layer disposed on the fourth insulating layer. In an example embodiment, the fourth conductive layer can be referred to as a first source-drain metal (SD1) layer.

[0220] In the exemplary embodiment, the fourth conductive layer of each circuit unit includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a seventh connection electrode 57, an eighth connection electrode 58, a ninth connection electrode 59, a first scan signal line 61, a second scan signal line 62, a third scan signal line 63, a fourth scan signal line 64, a first light-emitting signal line 65, a second light-emitting signal line 66, a first initial signal line 71, and a second initial signal line 72.

[0221] In the exemplary embodiment, the first connection electrode 51 can have a strip shape extending along the first direction X, a first end of the first connection electrode 51 is connected to the second region of the second active layer through a third via V3, and a second end of the first connection electrode 51 is connected to the first plate connection block 15 through a seventeenth via V17. Since the first plate connection block 15 is connected to the first plate 11, the first connection electrode 51 realizes the connection between the second electrode of the second transistor T2 and the first plate 11.

[0222] In the exemplary embodiment, the second connection electrode 52 can have a strip shape extending along the first direction X, a first end of the second connection electrode 52 is connected to the second region of the fourth active layer through a seventh via V7, and a second end of the second connection electrode 52 is connected to the third gate electrode 43 through a thirteenth via V13. The second connection electrode 52 realizes the connection between the second electrode of the fourth transistor T4 and the gate electrode of the third transistor T3.

[0223] In the exemplary embodiment, since the second region of the second active layer and the second region of the fourth active layer are connected to each other, the first connection electrode 51 and the second connection electrode 52 realize the connection between the second electrode of the second transistor T2, the gate electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the first plate 11 of the first capacitor, forming a first node N1 of the pixel driving circuit.

[0224] In the exemplary embodiment, the third connection electrode 53 can have a strip shape extending along the first direction X, a first end of the third connection electrode 53 is connected to the first region of the second region of the third active layer (also the first region of the sixth active layer), and a second end of the third connection electrode 53 is connected to the fourth plate 14 through a twenty-first via V21, realizing the mutual connection between the second electrode of the third transistor T3, the first electrode of the sixth transistor T6, and the fourth plate 14, forming a third node N3 of the pixel driving circuit.

[0225] In the example embodiment, the fourth plate 14 has the potential of the third node N3 of the pixel driving circuit, and the fourth plate 14 serves as the bottom gate electrode of the third transistor, so that the bottom gate electrode of the third transistor has the potential of the third node N3 of the pixel driving circuit.

[0226] In the example embodiment, the fourth connection electrode 54 can have a strip shape extending along the first direction X, the first end of the fourth connection electrode 54 is connected to the second region of the first active layer through the second via V2, and the second end of the fourth connection electrode 54 is connected to the second plate 12 through the nineteenth via V19, thereby achieving the connection between the second plate 12 and the second electrode of the first transistor T1.

[0227] In the example embodiment, the fifth connection electrode 55 can have a strip shape extending along the second direction Y, the first end of the fifth connection electrode 55 is connected to the third plate connecting block 16 through the eighteenth via V18, and the second end of the fifth connection electrode 55 is connected to the second plate 12 through the twentieth via V20. Since the third plate connecting block 16 is connected to the third plate 13, the fifth connection electrode 55 achieves the connection between the second plate 12 and the third plate 13.

[0228] In the example embodiment, the fourth connection electrode 54 and the fifth connection electrode 55 achieve the mutual connection between the second plate 12 of the first capacitor, the third plate 13 of the second capacitor, and the second electrode of the first transistor T1, thereby forming the fourth node N4 of the pixel driving circuit.

[0229] In the example embodiment, the sixth connection electrode 56 can have a block shape (e.g., a rectangular shape), the sixth connection electrode 56 is connected to the power supply connection line 24 through the twenty-third via V23, and the sixth connection electrode 56 is configured to be connected to the second power supply line formed later. In the example embodiment, the sixth connection electrode 56 can be arranged in the circuit units of the Nth unit column and the N+2th unit column.

[0230] In the example embodiment, the seventh connection electrode 57 can have a strip shape extending along the first direction X, the first end of the seventh connection electrode 57 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the eighth via V8, thereby forming the fifth node N5 of the pixel driving circuit, and the seventh connection electrode 57 is configured to be connected to the anode connection electrode formed later. In the example embodiment, the second end of the seventh connection electrode 57 is connected to the fifth node electrode 23 through the twenty-second via V22, thereby forming the node electrode with a double-layer structure. The disclosure can improve the connection reliability of the fifth node N5 by arranging the node electrode with a double-layer structure.

[0231] In an exemplary embodiment, the eighth connection electrode 58 can have a shape of a strip extending along the first direction X, a first end of the eighth connection electrode 58 is connected with the first region of the fourth active layer through the sixth via V6, a second end of the eighth connection electrode 58 extends away from the fourth transistor T4, and the second end of the eighth connection electrode 58 is configured to be connected with a data signal line to be formed subsequently.

[0232] In an exemplary embodiment, the ninth connection electrode 59 can have a shape of a strip extending along the first direction X, a first end of the ninth connection electrode 59 is connected with the second node connection block 48-1 through the tenth via V10, and a second end of the ninth connection electrode 59 is connected with the first region of the third active layer through the fourth via V4. Since the second node connection block 48-1 is connected with the node connection line 48, the ninth connection electrode 59 realizes the connection of the node connection line 48 with the first electrode of the third transistor T3 in each circuit unit. In an exemplary embodiment, the ninth connection electrode 59 can be referred to as a node connection block.

[0233] In an exemplary embodiment, at least one circuit unit (such as a circuit unit close to the second circuit unit) can further include a tenth connection electrode 60. The tenth connection electrode 60 can have a shape of a strip extending along the first direction X, a first end of the tenth connection electrode 60 is connected with the second region of the fifth active layer in the insertion unit through the twenty-fifth via V25, and a second end of the tenth connection electrode 60 is connected with the ninth connection electrode 59 in the circuit unit. Since the ninth connection electrode 59 is connected with the node connection line 48, the node connection line 48 realizes the connection between the second electrode of the fifth transistor T5 and the first electrode of the third transistor T3 in each circuit unit, forming a second node N2 of the pixel driving circuit. In an exemplary embodiment, the ninth connection electrode 59 can be referred to as a node connection electrode.

[0234] In an exemplary embodiment, the fourth conductive layer of the insertion unit can further include a power supply connection electrode 70. The power supply connection electrode 70 can have a shape of a block (such as a rectangle), the power supply connection electrode 70 is connected with the first region of the fifth active layer through the twenty-fourth via V24, and the power supply connection electrode 70 is configured to be connected with a first power supply line to be formed subsequently.

[0235] In the example embodiment, since the first plate 11 is connected to the second electrode of the second transistor T2 through the first connection electrode 51, the first plate 11 has the potential of the first node N1 in the pixel drive circuit. Since the second plate 12 is connected to the second region of the first active layer through the fourth connection electrode 54, the second plate 12 has the potential of the fourth node N4 in the pixel drive circuit. In this way, the first plate 11 having the potential of the first node N1 (i.e., the first terminal of the first capacitor) and the second plate 12 having the potential of the fourth node N4 (i.e., the second terminal of the first capacitor) form the first capacitor.

[0236] In the example embodiment, since the second plate 12 and the third plate 13 are connected to each other through the fifth connection electrode 55, the third plate 13 has the potential of the fourth node N4 in the pixel drive circuit. Since the fourth plate 14 is connected to the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6 through the third connection electrode 53, the fourth plate 14 has the potential of the third node N3 in the pixel drive circuit. In this way, the third plate 13 having the potential of the fourth node N4 (i.e., the second terminal of the second capacitor) and the fourth plate 14 having the potential of the third node N3 (i.e., the first terminal of the second capacitor) form the second capacitor.

[0237] In the example embodiment, the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the first emission signal line 65, the second emission signal line 66, the first initial signal line 71, and the second initial signal line 72 can have a shape of a straight line or a broken line extending along the first direction X and can be continuously arranged in one unit row. The fourth scan signal line 64 and the first emission signal line 65 can be located on the side opposite to the second direction Y of the third gate electrode 43, and the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the second emission signal line 66, the first initial signal line 71, and the second initial signal line 72 can be located on the side of the second direction Y of the third gate electrode 43.

[0238] In the example embodiment, the fourth scan signal line 64 can be located on the side opposite to the second direction Y of the third gate electrode 43, and the first emission signal line 65 can be located on the side away from the third gate electrode 43 of the fourth scan signal line 64.

[0239] In the exemplary embodiment, the second scan signal line 62 can be located on the side of the third gate electrode 43 in the opposite direction of the second direction Y, the first initial signal line 71 can be located on the side of the second scan signal line 62 away from the third gate electrode 43, the third scan signal line 63 can be located on the side of the first initial signal line 71 away from the third gate electrode 43, the second light-emitting signal line 66 can be located on the side of the third scan signal line 63 away from the third gate electrode 43, the first scan signal line 61 can be located on the side of the second light-emitting signal line 66 away from the third gate electrode 43, and the second initial signal line 72 can be located on the side of the first scan signal line 61 away from the third gate electrode 43.

[0240] In the exemplary embodiment, the first scan signal line 61 is at least partially overlapped with the orthographic projection of the seventh gate electrode 47 on the substrate, and the first scan signal line 61 is connected to the seventh gate electrode 47 in each circuit unit through the sixteenth via V16, thereby realizing the connection of the first scan signal line 61 to the gate electrode of the seventh transistor T7, and the first scan signal line 61 can control the turn-on or turn-off of the seventh transistor T7.

[0241] In the exemplary embodiment, the second scan signal line 62 is at least partially overlapped with the orthographic projection of the second gate electrode 42 on the substrate, and the second scan signal line 62 is connected to the second gate electrode 42 in each circuit unit through the twelfth via V12, thereby realizing the connection of the second scan signal line 62 to the gate electrode of the second transistor T2, and the second scan signal line 62 can control the turn-on or turn-off of the second transistor T2.

[0242] In the exemplary embodiment, the third scan signal line 63 is at least partially overlapped with the orthographic projection of the first gate electrode 41 on the substrate, and the third scan signal line 63 is connected to the first gate electrode 41 in each circuit unit through the eleventh via V11, thereby realizing the connection of the third scan signal line 63 to the gate electrode of the first transistor T1, and the third scan signal line 63 can control the turn-on or turn-off of the first transistor T1.

[0243] In the exemplary embodiment, the fourth scan signal line 64 is at least partially overlapped with the orthographic projection of the fourth gate electrode 44 on the substrate, and the fourth scan signal line 64 is connected to the fourth gate electrode 44 in each circuit unit through the fourteenth via V14, thereby realizing the connection of the fourth scan signal line 64 to the gate electrode of the fourth transistor T4, and the fourth scan signal line 64 can control the turn-on or turn-off of the fourth transistor T4.

[0244] In the example embodiment, the first scan signal line 61, the second scan signal line 62, the third scan signal line 63 and the fourth scan signal line 64 are arranged in the first source-drain metal (SD1) layer, which effectively reduces the resistance of the scan signal line, reduces the voltage drop of the scan signal, improves the compensation speed, and improves the display quality.

[0245] In the example embodiment, the first light-emitting signal line 65 is at least partially overlapped with the fifth gate electrode 45 in the orthographic projection on the substrate, and the first light-emitting signal line 65 is connected to the fifth gate electrode 45 of the inserted unit through the twenty-sixth via V26, so that the connection between the first light-emitting signal line 65 and the gate electrode of the fifth transistor T5 is realized, and the first light-emitting signal line 65 can control the conduction or disconnection of the fifth transistor T5.

[0246] In the example embodiment, the second light-emitting signal line 66 is at least partially overlapped with the sixth gate electrode 46 in the orthographic projection on the substrate, and the second light-emitting signal line 66 is connected to the sixth gate electrode 46 in each circuit unit through the fifteenth via V15, so that the connection between the second light-emitting signal line 66 and the gate electrode of the sixth transistor T6 is realized, and the second light-emitting signal line 66 can control the conduction or disconnection of the sixth transistor T6.

[0247] In the example embodiment, the first initial signal line 71 is connected to the first region of the first active layer (also the first region of the second active layer) in each circuit unit through the first via V1, so that the first initial signal line 71 can write the first initial signal to the first electrode of the first transistor T1 and the first electrode of the second transistor T2 at the same time.

[0248] In the example embodiment, the first initial signal line 71 is also connected to the first initial connection line 21 of the inserted unit through the twenty-seventh via V27, realizing the mutual connection between the first initial signal line 71 extending along the first direction X and the first initial connection line 21 extending along the second direction Y in the main body part, and the first initial signal line 71 and the first initial connection line 21 form a mesh structure for transmitting the first initial signal in a network communication structure on the display substrate, which not only effectively reduces the resistance of the first initial signal line and reduces the voltage drop of the first initial signal, but also effectively improves the uniformity of the first initial signal in the display substrate, effectively improves the display uniformity, and improves the display quality and display performance.

[0249] In the example embodiment, the second initial signal line 72 is connected to the first region of the seventh active layer in each circuit unit through the ninth via V9, so that the second initial signal line 72 can write the second initial signal to the first electrode of the seventh transistor T7.

[0250] (17) forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern can include: on the substrate on which the aforementioned patterns are formed, coating a first planar film, patterning the first planar film using a patterning process, forming a first planar layer covering the fourth conductive layer pattern, the first planar layer being provided with a plurality of vias, as shown in FIG. 15.

[0251] In an exemplary embodiment, the plurality of vias in each circuit unit at least includes: a thirty-first via V31 and a thirty-second via V32.

[0252] In an exemplary embodiment, the thirty-first via V31 has a footprint on the substrate within the footprint of the second end of the eighth connection electrode 58 on the substrate, the first planar layer in the thirty-first via V31 is removed to expose the surface of the second end of the eighth connection electrode 58, and the thirty-first via V31 is configured to allow a data signal line formed subsequently to pass through the via and connect to the second end of the eighth connection electrode 58.

[0253] In an exemplary embodiment, the thirty-second via V32 has a footprint on the substrate within the footprint of the second end of the seventh connection electrode 57 on the substrate, the first planar layer in the thirty-second via V32 is removed to expose the surface of the second end of the seventh connection electrode 57, and the thirty-second via V32 is configured to allow an anode connection electrode formed subsequently to pass through the via and connect to the second end of the seventh connection electrode 57.

[0254] In an exemplary embodiment, the at least one circuit unit can further include a thirty-third via V33. The thirty-third via V33 has a footprint on the substrate within the footprint of the sixth connection electrode 56 on the substrate, the first planar layer in the thirty-third via V33 is removed to expose the surface of the sixth connection electrode 56, and the thirty-third via V33 is configured to allow a second power supply line formed subsequently to pass through the via and connect to the sixth connection electrode 56. In an exemplary embodiment, the thirty-third via V33 can be provided in the circuit units in the Nth unit column and the N+2th unit column.

[0255] In an exemplary embodiment, the at least one circuit unit can further include a thirty-fourth via V34. The thirty-fourth via V34 has a footprint on the substrate within the footprint of the second initial signal line 72 on the substrate, the first planar layer in the thirty-fourth via V34 is removed to expose the surface of the second initial signal line 72, and the thirty-fourth via V34 is configured to allow a second initial connection line formed subsequently to pass through the via and connect to the second initial signal line 72. In an exemplary embodiment, the thirty-fourth via V34 can be provided in the circuit units in the N+1th unit column.

[0256] In an exemplary embodiment, the insertion unit can further include a thirty-fifth via V35. A projection of the thirty-fifth via V35 on the substrate is within a projection of the power supply connection electrode 70 on the substrate, a first planar layer in the thirty-fifth via V35 is removed to expose a surface of the power supply connection electrode 70, and the thirty-fifth via V35 is configured to enable a first power supply line formed subsequently to connect to the power supply connection electrode 70 through the via.

[0257] (18) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer can include: on the substrate on which the aforementioned pattern is formed, depositing a fifth conductive thin film, and patterning the fifth conductive thin film using a patterning process to form a fifth conductive layer disposed on the first planar layer, as shown in FIGS. 16A and 16B, which is a plan view of the fifth conductive layer in FIG. 16A. In an exemplary embodiment, the fifth conductive layer can be referred to as a second source-drain metal (SD2) layer.

[0258] In an exemplary embodiment, the fifth conductive layer of each circuit unit at least includes: a data signal line 83 and an anode connection electrode 84.

[0259] In an exemplary embodiment, the data signal line 83 can have a shape of a straight line or a broken line with a main body portion extending along the second direction Y, and the data signal line 83 is connected to the second end of the eighth connection electrode 58 through a thirty-first via V31. Since the eighth connection electrode 58 is connected to the first region of the fourth active layer through the via, the data signal line 83 can write a data signal to the first electrode of the fourth transistor T4.

[0260] In an exemplary embodiment, a projection of the data signal line 83 on the substrate does not overlap with a projection of the active layer of the first transistor T1 to the seventh transistor T7 on the substrate, which can avoid signal crosstalk caused by a data voltage jump of the data signal line 83, avoid the influence of the data voltage jump on the first transistor T1 to the seventh transistor T7, improve the working stability of the pixel driving circuit, and improve the display effect.

[0261] In an exemplary embodiment, a projection of the data signal line 83 on the substrate does not overlap with a projection of the gate electrode of the third transistor T3 on the substrate, which can further avoid the influence of the data voltage jump on the driving transistor, and the crosstalk influence is smaller.

[0262] In an example embodiment, the anode connecting electrode 84 can have a shape of a block (e.g., a rectangular) shape, the anode connecting electrode 84 is connected with the second end of the seventh connecting electrode 57 through the thirty-second via V32, and the anode connecting electrode 84 is configured to be connected with the anode to be formed subsequently. Since the anode connecting electrode 84 is connected with the second region of the sixth active layer (also the second region of the seventh active layer) through the via, the pixel driving circuit can output a driving current to the light emitting device.

[0263] In an example embodiment, the fifth conductive layer of the at least one circuit unit can further include a second power supply line 82. In an example embodiment, the second power supply line 82 can have a shape of a straight line or a broken line in which a main body portion extends along the second direction Y, and the second power supply line 82 is connected with the sixth connecting electrode 56 through the thirty-third via V33.

[0264] In an example embodiment, the second power supply line 82 can be provided with a recess configured to accommodate the anode connecting electrode 84.

[0265] In an example embodiment, since the second power supply line 82 is connected with the sixth connecting electrode 56 through the via, and the sixth connecting electrode 56 is connected with the power supply connecting line 24 through the via, the power supply connecting line 24 has the potential of the second power supply line. Since the anode connecting electrode 84 is connected with the seventh connecting electrode 57 through the via, and the seventh connecting electrode 57 is connected with the fifth node electrode 23 through the via and connected with the second region of the sixth active layer (also the second region of the seventh active layer) through the via, the fifth node electrode 23 has the potential of the fifth node N5. In this way, the power supply connecting line 24 in the first conductive layer (GATE1) and having the potential of the second power supply line and the fifth node electrode 23 in the second conductive layer (GATE2) and having the potential of the fifth node N5 form a parasitic capacitance c f In an example embodiment, the parasitic capacitance c f The potential of the anode can be adjusted, or the first capacitance C1 and the second capacitance C2 can be divided.

[0266] In the example embodiment, the second power supply line 82 can be arranged in the circuit units of the Nth unit column and the N+2th unit column. Since the sixth connection electrode 56 is connected with the power supply connection line 24 through the via hole, the interconnection of the power supply connection line 24 extending along the first direction X and the second power supply line 82 extending along the second direction Y is achieved, and the power supply connection line 24 and the second power supply line 82 form a mesh structure for transmitting the second power supply signal on the display substrate, which not only can effectively reduce the resistance of the second power supply line and reduce the voltage drop of the second power supply signal, but also can effectively improve the uniformity of the second power supply signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance. In addition, by arranging the second power supply line in the display area, the SIP (SIP: S in Panel) structure is achieved, which can greatly reduce the width of the frame power supply lead, greatly reduce the left and right frame widths, improve the screen-to-body ratio, and be conducive to realizing the full-screen display.

[0267] In the example embodiment, the orthographic projection of the second power supply line 82 on the substrate at least partially overlaps the orthographic projection of the first active layer to the fourth active layer and the sixth active layer to the seventh active layer in the circuit unit, that is, the orthographic projection of the second power supply line 82 on the substrate at least partially overlaps the orthographic projection of the first transistor T1 to the fourth transistor T4 and the sixth transistor T6 to the seventh transistor T7 on the substrate. The second power supply line 82 can block the light emission of the light emitting device and the reflection of the film layer to the oxide transistor, prevent the oxide transistor from drifting due to light, and improve the electrical properties of the oxide transistor.

[0268] In the example embodiment, the fifth conductive layer of at least one circuit unit can further include a second initial connection line 22. In the example embodiment, the second initial connection line 22 can be in the shape of a straight line or a broken line extending along the second direction Y, and the second initial connection line 22 is connected with the second initial signal line 72 through the thirty-fourth via hole V34, thereby achieving the interconnection of the second initial signal line 72 extending along the first direction X and the second initial connection line 22 extending along the second direction Y, and the second initial signal line 72 and the second initial connection line 22 form a mesh structure for transmitting the second initial signal on the display substrate, which not only can effectively reduce the resistance of the second initial signal line and reduce the voltage drop of the second initial signal, but also can effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0269] In the example embodiment, the second initial connection line 22 can be provided with a groove configured to accommodate the anode connection electrode 84.

[0270] In the example embodiment, the second initial connection line 22 can be arranged in the circuit unit of the N+1th unit column. The orthogonal projection of the second initial connection line 22 on the substrate at least partially overlaps the orthogonal projection of the first active layer to the fourth active layer and the sixth active layer to the seventh active layer in the circuit unit, that is, the orthogonal projection of the second initial connection line 22 on the substrate at least partially overlaps the orthogonal projection of the first transistor T1 to the fourth transistor T4 and the sixth transistor T6 to the seventh transistor T7. The second initial connection line 22 can block the light emitted by the light emitting device and the reflection of the film layer from shining on the oxide transistor, prevent the oxide transistor from drifting due to light, and improve the electrical characteristics of the oxide transistor.

[0271] In the example embodiment, the fifth conductive layer of the insertion unit can further include a first power line 81. The first power line 81 can have a shape of a straight line or a broken line with a main body extending along the second direction Y, and the first power line 81 is connected to the power connection electrode 70 through the thirty-fifth via hole V35. Since the power connection electrode 70 is connected to the first region of the fifth active layer through the via hole, the first power line 81 writes the first power signal to the first electrode of the fifth transistor T5.

[0272] In the example embodiment, the orthogonal projection of the first power line 81 on the substrate at least partially overlaps the orthogonal projection of the fifth active layer on the substrate, that is, the orthogonal projection of the first power line 81 on the substrate at least partially overlaps the orthogonal projection of the fifth transistor T5 on the substrate. The first power line 81 can block the light emitted by the light emitting device and the reflection of the film layer from shining on the oxide transistor, prevent the oxide transistor from drifting due to light, and improve the electrical characteristics of the oxide transistor.

[0273] In the example embodiment, the average width of the second power line 82 can be greater than the average width of the first power line 81, and the width can be the size of the first direction X. By arranging the second power line 82 with a wider wiring, the present disclosure not only effectively reduces the resistance of the second power line 82 and reduces the voltage drop of the second power signal transmission, but also effectively improves the uniformity of the second power signal in the display substrate, effectively improves the display uniformity, and improves the display quality and display performance.

[0274] In the example embodiment, the average width of the second initial connection line 22 can be substantially the same as the average width of the second power line 82.

[0275] The subsequent preparation process can include forming a second planar layer, the second planar layer being provided with an anode via hole, the anode via hole exposing a surface of the anode connection electrode 84, and the anode via hole being configured to allow the subsequent anode to be connected to the anode connection electrode through the via hole.

[0276] So far, the driving circuit layer of the present embodiment is prepared on the substrate. In a plane parallel to the display substrate, the driving circuit layer can include a plurality of circuit units, each of which can include a pixel driving circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a first light-emitting signal line, a second light-emitting signal line, a first initial signal line, a second initial signal line, a first power supply line, and a data signal line connected to the pixel driving circuit.

[0277] In a plane perpendicular to the display substrate, the driving circuit layer can include, sequentially arranged on the substrate, a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a semiconductor layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a first planarization layer, a fifth conductive layer, and a second planarization layer. The first conductive layer can include at least a first plate of a first capacitor and a third plate of a second capacitor, the second conductive layer can include at least a second plate of the first capacitor and a fourth plate of the second capacitor, the semiconductor layer can include at least an active layer of a first transistor T1 to a seventh transistor T7, the third conductive layer can include at least a gate electrode of the first transistor T1 to the seventh transistor T7, the fourth conductive layer can include at least the first scan signal line, the second scan signal line, the third scan signal line, the fourth scan signal line, the first light-emitting signal line, the second light-emitting signal line, the first initial signal line, the second initial signal line, and the fifth conductive layer can include at least the first power supply line and the data signal line.

[0278] In an example embodiment, the first conductive layer can further include a power supply connection line, the second conductive layer can further include a first initial connection line, the third conductive layer can further include a second node connection line, and the fifth conductive layer can further include a second power supply line and a second initial connection line.

[0279] In an example embodiment, the substrate can be a flexible substrate, or can be a rigid substrate. The rigid substrate can include, but is not limited to, one or more of glass, quartz, and the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an example embodiment, the flexible substrate can include, stacked on a glass carrier plate, a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc., the materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, the first and second inorganic material layers are also called barrier layers, and the material of the semiconductor layer can be amorphous silicon (a-si).

[0280] In the example embodiments, the first, second, third and fourth insulating layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, multiple layers or a composite layer. The first, second, third, fourth and fifth conductive layers can be a metal material such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) or molybdenum (Mo), or can be an alloy material composed of metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single layer structure or a multiple layer composite structure such as Ti / Al / Ti. The first and second planar layers can be an organic material such as resin or polyimide.

[0281] In the example embodiments, after the driving circuit layer is prepared, a light emitting structure layer can be prepared on the driving circuit layer, and an encapsulation structure layer can be prepared on the light emitting structure layer, which will not be described herein.

[0282] With the development of display technology, consumers have increasingly high requirements on display effect and display quality of display products, and high frequency and high resolution (Pixels Per Inch, PPI) display has gradually become a development trend of products. In a display substrate, since the pixel driving circuit of each circuit unit includes 7 transistors and 2 capacitors, it is difficult to reduce the size of the circuit unit, and it is difficult to improve the display resolution. In addition, with the increase of the resolution, the size of the circuit unit is reduced, the distance between each node in the pixel driving circuit and the distance between each node and the signal line are also reduced, the potential stability of the node is low during high frequency display, and the picture quality is reduced.

[0283] The example embodiments of the present disclosure provide a display substrate, which adopts a brand-new pixel driving circuit layout, optimizes the structure of the pixel driving circuit, not only improves the space utilization, but also increases the potential stability of each node in the pixel driving circuit, effectively improves the driving performance of the pixel driving circuit, effectively improves the display quality and display effect, and is conducive to realizing high frequency and high resolution display.

[0284] The display device of the embodiment of the present disclosure can effectively reduce the size of the circuit unit and improve the resolution of the display device by setting the first circuit of the plurality of circuit units to share the second circuit of the insertion unit. Compared with the prior structure in which three circuit units include 21 transistors and three first power lines, the embodiment includes only 19 transistors and one first power line in one repeating unit, effectively reducing the number of transistors and the number of first power lines, reducing the occupied area of the pixel driving circuit, and simplifying the structure of the pixel driving circuit. Therefore, the size of each circuit unit can be effectively reduced, the resolution of the display device can be effectively improved, the distance between each node in the pixel driving circuit and the distance between each node and the signal line can be ensured, the crosstalk can be effectively avoided, the potential stability of each node in the pixel driving circuit can be ensured, and the display quality and display performance can be effectively improved.

[0285] The embodiment of the present disclosure can effectively improve the layout space utilization, the structure arrangement is more reasonable, the signal line connection structure is simple, and the product yield can be effectively improved and the production cost can be reduced by setting the insertion unit and arranging the first power line in the insertion unit and separately arranging the direct-current signal wire area.

[0286] The embodiment of the present disclosure can effectively reduce the resistance of the second power line, reduce the voltage drop of the second power signal, effectively improve the uniformity of the second power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance by setting the power connection line and the second power line and forming a mesh structure of the second power signal on the display substrate.

[0287] The embodiment of the present disclosure can greatly reduce the width of the frame power lead, greatly reduce the left and right frame widths, improve the screen ratio, and be conducive to realizing the full-screen display by setting the second power line in the display area to realize the second power line in the panel (VSS in Panel, SIP for short) structure.

[0288] The embodiment of the present disclosure can effectively reduce the resistance of the initial signal line, reduce the voltage drop of the initial signal, effectively improve the uniformity of the initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance by setting the first initial connection line and the second initial connection line, forming a mesh structure of the first initial signal on the display substrate, and forming a mesh structure of the second initial signal on the display substrate.

[0289] The second power line and the second initial connection line cover multiple transistors, so that the light emitted by the light-emitting device and the reflected light of the film layer can be effectively blocked from irradiating the oxide transistor, the oxide transistor can be prevented from characteristic drift due to light irradiation, and the electrical characteristics of the oxide transistor are improved.

[0290] The data signal line does not overlap the active layer of the multiple transistors, and the data signal line does not overlap the gate electrode of the driving transistor, so that signal crosstalk caused by data voltage jump of the data signal line can be avoided, the influence of the data voltage jump on the transistor can be avoided, the working stability of the pixel driving circuit is improved, and the display effect is improved.

[0291] The multiple scan signal lines are arranged in the first source-drain metal layer, so that the resistance of the scan signal line is effectively reduced, the voltage drop of the scan signal is reduced, the compensation speed is improved, and the display quality is improved.

[0292] The preparation process of the display substrate of the embodiment of the present disclosure is compatible with the existing preparation process, the process is simple to implement, the production efficiency is high, the production cost is low, and the yield is high.

[0293] FIG. 17 is a schematic view of a planar structure of another repeat unit according to an example embodiment of the present disclosure. As shown in FIG. 17, the main structure of the repeat unit of the present embodiment can be substantially the same as that of the embodiment shown in FIG. 7, except that the second initial connection line 22 is connected to the second initial signal line 72 through the active connection electrode 38 and the initial connection electrode 73.

[0294] In an example implementation, the active connection electrode 38 can be arranged in the semiconductor layer, and the active connection electrode 38 is connected to the first region of the seventh active layer. The initial connection electrode 73 can be arranged in the fourth conductive layer, and the initial connection electrode 73 is connected to the active connection electrode 38 through a via. The second initial connection line 22 in the fifth conductive layer can be connected to the initial connection electrode 73 through a via, so that the connection between the second initial signal line 72 and the second initial connection line 22 is realized.

[0295] In an example implementation, the preparation process of the display substrate of the present embodiment can include the following operations.

[0296] (21-22) Form the first conductive layer and the second conductive layer pattern in sequence. In an example implementation, the process of forming the first conductive layer and the second conductive layer pattern and the structure of the formed first conductive layer and second conductive layer are substantially the same as those of the foregoing embodiments, which will not be repeated here.

[0297] (23) Forming a semiconductor layer pattern. In an example embodiment, the process of forming a semiconductor layer pattern and the structure of the formed semiconductor layer are substantially the same as those of the foregoing embodiments, except that the semiconductor layer can further include an active connection electrode 38, as shown in FIG. 18.

[0298] In an example embodiment, the active connection electrode 38 can have a strip shape extending along the second direction Y and can be disposed on the side of the seventh active layer 37 opposite to the first direction X. The first end of the active connection electrode 38 is connected to the first region 37-1 of the seventh active layer, the second end of the active connection electrode 38 extends toward the direction close to the power supply connection line 24, and the orthogonal projection of the second end of the active connection electrode 38 on the substrate at least partially overlaps the orthogonal projection of the power supply connection line 24 on the substrate.

[0299] In an example embodiment, the active connection electrode 38 and the seventh active layer 37 can be an integrated structure connected to each other.

[0300] In an example embodiment, the active connection electrode 38 can be disposed in part of the circuit units. For example, the active connection electrode 38 can be disposed in the circuit units of the (N+1)th unit column.

[0301] (24) Forming a third conductive layer pattern. In an example embodiment, the process of forming a third conductive layer pattern and the structure of the formed third conductive layer are substantially the same as those of the foregoing embodiments, as shown in FIG. 19.

[0302] (25) Forming a fourth insulating layer pattern. In an example embodiment, the process of forming a fourth insulating layer and the structure of the formed plurality of vias are substantially the same as those of the foregoing embodiments, except that at least one circuit unit can further include a twenty-eighth via V28, as shown in FIG. 20.

[0303] In an example embodiment, the orthogonal projection of the twenty-eighth via V28 on the substrate is within the range of the orthogonal projection of the active connection electrode 38 on the substrate, the third insulating layer and the fourth insulating layer within the twenty-eighth via V28 are etched away, exposing the surface of the second end of the active connection electrode 38, and the twenty-eighth via V28 is configured to allow a subsequently formed initial connection electrode to connect to the second end of the active connection electrode 38 through the via.

[0304] In an example embodiment, the twenty-eighth via V28 can be disposed in part of the circuit units. For example, the twenty-eighth via V28 can be disposed in the circuit units of the (N+1)th unit column.

[0305] (26) A fourth conductive layer pattern is formed. In an exemplary embodiment, the process of forming the fourth conductive layer and the structure of the formed fourth conductive layer are substantially the same as those of the foregoing embodiments, except that at least one circuit unit can further include an initial connection electrode 73, as shown in FIG. 21.

[0306] In an exemplary embodiment, the initial connection electrode 73 can have a strip shape extending along the first direction X, the initial connection electrode 73 can be connected to the second end of the active connection electrode 38 through a twenty-eighth via V28, and the initial connection electrode 73 is configured to be connected to a second initial connection line formed later.

[0307] In an exemplary embodiment, the initial connection electrode 73 can be provided in part of the circuit units. For example, the initial connection electrode 73 can be provided in the circuit units of the (N+1)th unit column.

[0308] (27) A first planar layer pattern is formed. In an exemplary embodiment, the process of forming the first planar layer and the structure of the formed plurality of vias are substantially the same as those of the foregoing embodiments, except that the third-fourth via V34 is provided at a different position, as shown in FIG. 22.

[0309] In an exemplary embodiment, the orthographic projection of the third-fourth via V34 on the substrate is within the range of the orthographic projection of the initial connection electrode 73 on the substrate, the first planar layer within the third-fourth via V34 is removed, exposing the surface of the initial connection electrode 73, and the third-fourth via V34 is configured to allow the second initial connection line formed later to be connected to the second initial signal line 72 through the via.

[0310] In an exemplary embodiment, the third-fourth via V34 can be provided in part of the circuit units. For example, the third-fourth via V34 can be provided in the circuit units of the (N+1)th unit column.

[0311] (28) A fifth conductive layer pattern is formed. In an exemplary embodiment, the process of forming the fifth conductive layer and the structure of the formed fifth conductive layer are substantially the same as those of the foregoing embodiments, except that the second initial connection line 22 is connected to the initial connection electrode 73 through the third-fourth via V34, as shown in FIG. 23.

[0312] In the example embodiment, since the initial connection electrode 73 is connected to the active connection electrode 38 through the via hole, the active connection electrode 38 is connected to the first region of the seventh active layer, and the first region of the seventh active layer is connected to the second initial signal line 72, the mutual connection of the second initial signal line 72 extending along the first direction X and the second initial connection line 22 extending along the second direction Y of the body part is achieved, and the second initial signal line 72 and the second initial connection line 22 form a mesh structure of the transmission second initial signal on the display substrate, which not only can effectively reduce the resistance of the second initial signal line and reduce the voltage drop of the second initial signal, but also can effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0313] In the example embodiment, the second initial connection line 22 can be arranged in the circuit unit of the N+1 unit column.

[0314] In the example embodiment, the circuit unit (second circuit unit) of the N+1 unit column can correspond to the green sub-pixel emitting green light, or the circuit unit of the N+1 unit column can correspond to the red sub-pixel emitting red light and the blue sub-pixel emitting blue light, which is not limited in the present disclosure.

[0315] The subsequent preparation process can include forming a second planar layer, the second planar layer being provided with an anode via hole, the anode via hole exposing the surface of the anode connection electrode 84, and the anode via hole being configured to connect the anode to the anode connection electrode through the via hole in subsequent formation, which is not described here.

[0316] The foregoing structure and its preparation process of the present disclosure are only an example, and in the example embodiment, the corresponding structure can be changed and the patterning process can be increased or reduced according to actual needs, which is not limited in the present disclosure.

[0317] In the example embodiment, the display substrate of the present disclosure can be applied to a display device with a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED), or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0318] The display substrate driving method comprises the following steps.

[0319] The driving method further comprises a data writing stage. In the data writing stage, the second transistor is turned off, then the fourth transistor is turned on, a data signal is written into the first node, and then the first transistor is turned off.

[0320] In the exemplary embodiment, the driving method further comprises a data writing stage. In the data writing stage, the second transistor is turned off, then the fourth transistor is turned on, a data signal is written into the first node, and then the first transistor is turned off.

[0321] In the exemplary embodiment, the display substrate driving method provided by the present disclosure effectively reduces the interference on each node by sequentially resetting each node in the reset stage and sequentially turning off the first transistor and the second transistor in the data writing stage, effectively ensures the potential stability of each node inside the pixel driving circuit, and effectively improves the display quality and display performance.

[0322] The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, and the embodiments of the present application are not limited thereto.

[0323] Although the embodiments disclosed in the present disclosure are as above, it should be noted that the above embodiments are merely exemplary and are not limiting. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions can be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising a plurality of repeating units, at least one of the repeating units comprising M circuit units and one insertion unit arranged in sequence along a first direction, M being a positive integer greater than or equal to 3; the circuit unit comprising a first circuit, the first circuit comprising at least a third transistor as a driving transistor, the insertion unit comprising a second circuit, the second circuit comprising at least a fifth transistor as a first light emitting control transistor and a first power line extending along a second direction, the first direction and the second direction intersecting; a first electrode of the fifth transistor being connected with the first power line, a second electrode of the fifth transistor being connected with the third transistor in M first circuits respectively through a node connection line, forming M pixel driving circuits. 2.The display substrate of claim 1, wherein, M＝3。 3.The display substrate of claim 1, wherein, A ratio of a width of the insertion unit to a width of the circuit unit is 0.3 to 0.5, the width being a size in the first direction. 4.The display substrate of claim 1, wherein, The repeating unit further comprises a node connection electrode, a first end of the node connection electrode being connected with the second electrode of the fifth transistor, a second end of the node connection electrode being connected with the node connection line, the node connection line being in a shape of a straight line or a broken line with a main part extending along the first direction, the node connection line being connected with the first electrode of the third transistor in M circuit units respectively. 5.The display substrate of claim 4, wherein, At least one of the circuit units further comprises a node connection block, a first end of the node connection block being connected with the node connection line, a second end of the node connection block being connected with the first electrode of the third transistor. 6.The display substrate of claim 5, wherein, In at least one of the circuit units, the second end of the node connection electrode is connected with the node connection block, the node connection electrode being connected with the node connection line through the node connection block. 7.The display substrate according to any one of claims 1 to 6, wherein In at least one of the circuit units, the first circuit further comprises a first capacitor, a second capacitor, a first transistor as a first reset transistor, a second transistor as a second reset transistor, a fourth transistor as a data writing transistor, a sixth transistor as a second light emitting control transistor and a seventh transistor as a third reset transistor; a first electrode of the first transistor and a first electrode of the second transistor are connected with a first initial signal line respectively, a second electrode of the first transistor is connected with a second electrode plate of the first capacitor and a third electrode plate of the second capacitor respectively, a second electrode of the second transistor is connected with a gate electrode of the third transistor, a second electrode of the fourth transistor and a first electrode plate of the first capacitor respectively, a first electrode of the third transistor is connected with a second electrode of the fifth transistor, a second electrode of the third transistor is connected with a first electrode of the sixth transistor and a fourth electrode plate of the second capacitor respectively, a first electrode of the fourth transistor is connected with a data signal line, a second electrode of the sixth transistor is connected with a second electrode of the seventh transistor, a first electrode of the seventh transistor is connected with a second initial signal line; a normal projection of the data signal line on the display substrate does not overlap with normal projections of active layers of the first transistor to the fourth transistor and active layers of the sixth transistor to the seventh transistor on the display substrate. 8.The display substrate of claim 7, wherein, A projection of the data signal line on the display substrate does not overlap with a projection of the gate electrode of the third transistor on the display substrate in the at least one circuit unit. 9.The display substrate of claim 7, wherein, The first initial signal line is in a shape of a straight line or a broken line with a main body extending along the first direction, and the at least one repeating unit further includes at least one first initial connection line extending along the second direction, the first initial signal line and the first initial connection line being connected to form a mesh structure for transmitting a first initial signal. 10.The display substrate of claim 9, wherein, The first initial connection line is arranged in the insertion unit. 11.The display substrate of claim 7, wherein, The second initial signal line is in a shape of a straight line or a broken line with a main body extending along the first direction, and the at least one repeating unit further includes at least one second initial connection line extending along the second direction, the second initial signal line and the second initial connection line being connected to form a mesh structure for transmitting a second initial signal. 12.The display substrate of claim 11, wherein, A projection of the second initial connection line on the display substrate at least partially overlaps with projections of the active layers of the first transistor to the fourth transistor and the active layers of the sixth transistor to the seventh transistor on the display substrate in the at least one circuit unit. 13.The display substrate of claim 7, wherein, The at least one repeating unit further includes at least one power supply connection line extending along the first direction and at least one second power supply line extending along the second direction, the power supply connection line and the second power supply line being connected to form a mesh structure for transmitting a second power supply signal. 14.The display substrate of claim 13, wherein, A projection of the second power supply line on the display substrate at least partially overlaps with projections of the active layers of the first transistor to the fourth transistor and the active layers of the sixth transistor to the seventh transistor on the display substrate in the at least one circuit unit.

15. A display device, comprising the display substrate according to any one of claims 1 to 14.

16. A driving method of a display substrate, the display substrate being driven by the display substrate according to any one of claims 1 to 14, the pixel driving circuit comprising at least a first node, a second node, a third node, a fourth node and a fifth node, the first node being connected with a second electrode of a second transistor, a gate electrode of a third transistor, a second electrode of a fourth transistor and a first terminal of a first capacitor respectively, the second node being connected with a first electrode of the third transistor and a second electrode of a fifth transistor respectively, the third node being connected with a second electrode of the third transistor, a first electrode of a sixth transistor and a first terminal of a second capacitor respectively, the fourth node being connected with a second electrode of the first transistor, a second terminal of the first capacitor and a second terminal of the second capacitor respectively, the fifth node being connected with a second electrode of the sixth transistor and a second electrode of a seventh transistor respectively; the driving method comprising at least a reset stage, in the reset stage, the second transistor is turned on, and the first node is reset. The seventh transistor is then turned on to reset the fifth node; The first transistor is then turned on to reset the fourth node; The sixth transistor is then turned on to reset the third node. 17.The display substrate of claim 16, wherein, The driving method further includes a data writing stage, in which the second transistor is turned off, the fourth transistor is then turned on, a data signal is written into the first node, and the first transistor is then turned off. The driving method further includes a data writing stage, in which the second transistor is turned off, the fourth transistor is then turned on, a data signal is written into the first node, and the first transistor is then turned off.

Images