Driving method for display panel, and display apparatus and driver therefor

Abstract

A driving method for a display panel, and a display apparatus and a driver therefor, which belong to the technical field of display. The driving method for a display panel comprises: during a first time period (F1), using a first driving mode to drive pixel driving circuits (S110); and during a second time period (S1), using a second driving mode to drive the pixel driving circuits (S120), wherein the first time period (F1) is a time period in which first one or more image frames are displayed; the second time period (S1) comes after the first time period (F1); and the sub-pixel brightness when the pixel driving circuits use the first driving mode during the second time period (S1) to drive sub-pixels is greater than the sub-pixel brightness when the pixel driving circuits use the second driving mode during the second time period (S1) to drive the same sub-pixels at the same gray level. A display panel that applies the driving method, and the display apparatus have better display quality.

Description

Driving method of display panel, display device and driver thereof TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a driving method of display panel, display device and driver thereof. BACKGROUND

[0002] In the field of display, consumers have higher requirements for the display quality of display products. With the proposal of high-precision frequency conversion demand, in order to achieve better flicker effect, in the related technology, the timing of the pixel driving circuit can be optimized (for example, multiple resets are performed within one frame of the display product), and the display is reset multiple times, which can reduce the flicker phenomenon of the display product, but will cause the display product to take longer to start lighting, affecting the display effect of the display product.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art.

[0004] SUMMARY

[0005] The purpose of the present disclosure is to overcome the shortcomings of the prior art, and to provide a driving method of display panel, display device and driver thereof.

[0006] According to one aspect of the present disclosure, a driving method of display panel is provided, comprising driving a pixel driving circuit of each sub-pixel; wherein the method of driving any one pixel driving circuit comprises:

[0007] in a first time period, driving the pixel driving circuit by using a first driving mode;

[0008] in a second time period, driving the pixel driving circuit by using a second driving mode;

[0009] wherein the first time period is a time period for displaying the first one or more frames of pictures; and the second time period is after the first time period.

[0010] When the pixel driving circuit drives a sub-pixel by using the first driving mode in the second time period, the sub-pixel brightness is greater than that when the pixel driving circuit drives the same sub-pixel of the same gray scale by using the second driving mode in the second time period.

[0011] According to one embodiment of the present disclosure, the first time period is a time period for displaying the first frame of picture, a time period for displaying the first two frames of picture, a time period for displaying the first three frames of picture, or a time period for displaying the first four frames of picture.

[0012] According to an embodiment of the present disclosure, the driving method comprises: resetting the first electrode of the driving transistor, the second electrode of the driving transistor and the pixel electrode once or multiple times each time the pixel driving circuit is driven:

[0013] In the first driving mode, the number of times of resetting the first electrode of the driving transistor, the second electrode of the driving transistor and the pixel electrode each time the pixel driving circuit is driven is less than the number of times of resetting the first electrode of the driving transistor, the second electrode of the driving transistor and the pixel electrode each time the pixel driving circuit is driven in the second driving mode.

[0014] According to an embodiment of the present disclosure, the first driving mode comprises:

[0015] resetting the first electrode of the driving transistor, the second electrode of the driving transistor and the pixel electrode only once each time the pixel driving circuit is driven;

[0016] The second driving mode comprises:

[0017] resetting the first electrode of the driving transistor, the second electrode of the driving transistor and the pixel electrode multiple times each time the pixel driving circuit is driven.

[0018] According to an embodiment of the present disclosure, at least three light-emitting signal cutoff levels and at least two light-emitting signal on levels between the light-emitting signal cutoff levels are loaded to the pixel driving circuit each time the pixel driving circuit is driven;

[0019] The first driving mode comprises:

[0020] In the process of loading the light-emitting signal cutoff level for the first time, a data voltage is written to the pixel driving circuit, and the first electrode of the driving transistor, the second electrode of the driving transistor and the pixel electrode are reset;

[0021] The second driving mode comprises:

[0022] In the process of loading the light-emitting signal cutoff level for the first time, a data voltage is written to the pixel driving circuit, and the first electrode of the driving transistor, the second electrode of the driving transistor and the pixel electrode are reset;

[0023] At least one reset is performed on the first electrode of the driving transistor, the second electrode of the driving transistor and the pixel electrode when the remaining light-emitting signal cutoff levels are loaded.

[0024] According to an embodiment of the present disclosure, the pixel driving circuit comprises a first reset transistor, a threshold compensation transistor, a driving transistor, a data writing transistor, a first light-emitting transistor, a second light-emitting transistor, an electrode reset transistor, a node control transistor, and a storage capacitor;

[0025] The second electrode of the data writing transistor, the second electrode of the node control transistor, and the second electrode of the first light-emitting transistor are electrically connected to the first electrode of the driving transistor;

[0026] The second electrode of the first reset transistor, the first electrode of the threshold compensation transistor, and the first electrode of the second light-emitting transistor are electrically connected to the second electrode of the driving transistor;

[0027] The second electrode of the threshold compensation transistor and the first electrode plate of the storage capacitor are electrically connected to the gate electrode of the driving transistor;

[0028] The first electrode of the first light-emitting transistor is electrically connected to the second electrode of the storage capacitor;

[0029] The gate electrode of the first reset transistor is used to load a first reset signal;

[0030] The gate electrode of the threshold compensation transistor is used to load a first scan signal;

[0031] The gate electrode of the data writing transistor is used to load a second scan signal;

[0032] The gate electrodes of the first light-emitting transistor and the second light-emitting transistor are used to load a light-emitting signal;

[0033] The gate electrode of the electrode reset transistor is used to load a second reset signal;

[0034] The gate electrode of the node control transistor is used to load a second reset signal;

[0035] At least three light-emitting signal cutoff levels and at least two light-emitting signal on levels between the light-emitting signal cutoff levels are loaded to the pixel driving circuit each time the pixel driving circuit is driven;

[0036] The first driving mode comprises: during the first time of loading the light-emitting signal cutoff level, the first scan signal is written to the gate electrode of the threshold compensation transistor once, the second scan signal is written to the gate electrode of the data writing transistor once, the first reset signal is written to the first reset transistor, the second reset signal is written to the gate electrode of the electrode reset transistor once, and the second reset signal is written to the gate electrode of the node control transistor once;

[0037] The second driving mode comprises: in the first time of loading the light emitting signal cutoff level, writing the first scan signal to the gate of the threshold compensation transistor once, writing the second scan signal to the gate of the data write transistor once, writing the second reset signal to the gate of the electrode reset transistor once, writing the second reset signal to the gate of the node control transistor once, in the loading of the remaining light emitting signal cutoff level, writing the first reset signal to the first reset transistor, writing the second reset signal to the gate of the electrode reset transistor once, and writing the second reset signal to the gate of the node control transistor once.

[0038] According to an embodiment of the present disclosure, the first driving mode comprises:

[0039] When loading the data voltage to the pixel driving circuit, the data voltage loading time length is a first time length;

[0040] The second driving mode comprises:

[0041] When loading the data voltage to the pixel driving circuit, the data voltage loading time length is a second time length;

[0042] The first time length is less than the second time length.

[0043] According to an embodiment of the present disclosure, a second scan signal for controlling a data write transistor is loaded to the driving circuit, and the data write transistor is used to write a data voltage to the pixel driving circuit in response to the second scan signal;

[0044] The first driving mode comprises:

[0045] The second scan signal has a third time length;

[0046] The second driving mode comprises:

[0047] The second scan signal has a fourth time length;

[0048] The third time length is less than the fourth time length.

[0049] According to an embodiment of the present disclosure, the first driving mode comprises:

[0050] The corrected gray scale of the pixel driving circuit is determined according to the gray scale corresponding to the pixel driving circuit and a gray scale correction table, and the corrected gray scale of the pixel driving circuit is greater than the gray scale of the pixel driving circuit;

[0051] According to the modified gray scale of the pixel driving circuit, a data voltage corresponding to the pixel driving circuit is determined, and the data voltage is written into the pixel driving circuit in a data writing stage;

[0052] The second driving mode comprises:

[0053] According to the gray scale of the pixel driving circuit, a data voltage corresponding to the pixel driving circuit is determined, and the data voltage is written into the pixel driving circuit in a data writing stage.

[0054] According to an embodiment of the present disclosure, at least one light-emitting signal on time is loaded to the pixel driving circuit each time the pixel driving circuit is driven;

[0055] The first driving mode further comprises:

[0056] The total length of the light-emitting signal on time each time the pixel driving circuit is driven is a fifth time length;

[0057] The second driving mode further comprises:

[0058] The total length of the light-emitting signal on time each time the pixel driving circuit is driven is a sixth time length;

[0059] The fifth time length is greater than the sixth time length.

[0060] According to an embodiment of the present disclosure, the refresh rate frequency of the pixel driving circuit is less than 60 Hz.

[0061] According to another aspect of the present disclosure, a driving method of a display panel is provided, comprising driving pixel driving circuits of respective sub-pixels; wherein the method of driving any one pixel driving circuit comprises:

[0062] In a first time period, the pixel driving circuit is driven by a first driving mode;

[0063] In a second time period, the pixel driving circuit is driven by a second driving mode;

[0064] The first time period is a time period of displaying the first one or more frames of pictures, and the second time period is after the first time period.

[0065] The first electrode of the driving transistor, the second electrode of the driving transistor and the pixel electrode are reset one or more times each time the pixel driving circuit is driven: in the first driving mode, the number of times the first electrode of the driving transistor, the second electrode of the driving transistor and the pixel electrode are reset each time the pixel driving circuit is driven is less than the number of times the first electrode of the driving transistor, the second electrode of the driving transistor and the pixel electrode are reset each time the pixel driving circuit is driven in the second driving mode.

[0066] According to another aspect of the present disclosure, there is provided a driver of a display device configured to drive a display panel, the display panel comprising a pixel driving circuit driving each sub-pixel; the driver is configured to enable the display panel to drive the pixel driving circuit in the following manner:

[0067] in a first time period, the pixel driving circuit is driven in a first driving mode;

[0068] in a second time period, the pixel driving circuit is driven in a second driving mode;

[0069] wherein the first time period is a time period in which the first one or more frames of images are displayed; and the second time period is after the first time period.

[0070] the sub-pixel brightness when the pixel driving circuit drives a sub-pixel in the second time period in the first driving mode is greater than the sub-pixel brightness when the pixel driving circuit drives a sub-pixel of the same gray scale in the second time period in the second driving mode.

[0071] According to another aspect of the present disclosure, there is provided a display device comprising the driver.

[0072] It should be understood that the general description above and the detailed description below are only exemplary and explanatory, and are not intended to limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0073] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure. It is readily apparent to one skilled in the art that the following description is merely exemplary and explanatory, and other embodiments can be readily derived from the accompanying drawings without inventive effort.

[0074] FIG. 1 is a schematic diagram of a film layer structure of a display panel in an embodiment of the present disclosure.

[0075] FIG. 2 is a schematic diagram of a pixel driving circuit in an embodiment of the present disclosure.

[0076] FIG. 3 is a timing diagram of the pixel driving circuit in one embodiment of the present disclosure.

[0077] FIG. 4 is a state diagram of the pixel driving circuit in an initialization stage in one embodiment of the present disclosure.

[0078] FIG. 5 is a state diagram of the pixel driving circuit in a data writing stage in one embodiment of the present disclosure.

[0079] FIG. 6 is a state diagram of the pixel driving circuit in a reset stage in one embodiment of the present disclosure.

[0080] FIG. 7 is a state diagram of the pixel driving circuit in an emission stage in one embodiment of the present disclosure.

[0081] FIG. 8 is a timing diagram of the pixel driving circuit in one embodiment of the present disclosure.

[0082] FIG. 9 is a schematic diagram of a pixel electrode overlapping a source-drain metal layer in a display panel in one embodiment of the present disclosure.

[0083] FIG. 10 is a schematic diagram of the current in each part of the pixel driving circuit in one embodiment of the present disclosure.

[0084] FIG. 11 is a flowchart of a method of driving any one sub-pixel in one embodiment of the present disclosure.

[0085] FIG. 12 is a timing diagram of the pixel driving circuit in one embodiment of the present disclosure.

[0086] Legend: SBT, substrate; BSM, metal light shielding layer; DRL, driving layer; PSCL, polysilicon semiconductor layer; Buff1, first buffer layer; Buff2, second buffer layer; GI1, first gate insulating layer; GI2, second gate insulating layer; GT1, first gate layer; GT2, second gate layer; GT3, third gate layer; ILD, interlayer dielectric layer; SD1, first source-drain metal layer; SD2, second source-drain metal layer; SD3, third source-drain metal layer; PLN1, first planarization layer; PLN2, second planarization layer; PLN3, third planarization layer; OSCL, metal-oxide semiconductor layer; PDL, pixel definition layer; COML, common electrode layer; EL, light-emitting functional layer; ANL, pixel electrode layer; PIXL, pixel layer; PIX, sub-pixel; TFE, thin-film encapsulation layer; GI3, third gate insulating layer; T1, first reset transistor; T2, threshold compensation transistor; T3, driving transistor; T4, data write transistor; T5, first light-emitting transistor; T6, second light-emitting transistor; T7, electrode reset transistor; T8, node control transistor; CST, storage capacitor; Vinit1, first initialization voltage; Vinit2, second initialization voltage; Vinit3, third initialization voltage; RP, first reset signal; GN, first scan signal; Vdata, data voltage; GP, second scan signal; VDD, power voltage; EM, light-emitting signal; RH, second reset signal; VSS, reference voltage; N1, first node; N2, second node; N3, third node; N4, fourth node; N5, fifth node; F1, first time period; F2, second time period; ta, first time length; tb, second time length; tc, third time length; td, fourth time length; A1, overlapping area; t1, first initialization stage; t2, data write stage; t3, first reset stage; t4, light-emitting stage; t5, second initialization stage; t6, second reset stage; t7, third initialization stage; t8, third reset stage; EM10, first light-emitting signal on level; EM11, first light-emitting signal off level; EM20, second light-emitting signal on level; EM21, second light-emitting signal off level; EM31, third light-emitting signal off level; M5, fifth time length; t51, first light-emitting signal on time length; t52, first light-emitting signal on time length; t53, third light-emitting signal on time length; M6, sixth time length; t61, fourth light-emitting signal on time length; t62, fifth light-emitting signal on time length; t63, sixth light-emitting signal on time length. DETAILED DESCRIPTION

[0087] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations can be implemented in any of various forms, and are not limited to the implementations set forth in this document; rather, the implementations are provided as non-limiting examples so that this disclosure will be thorough and complete, and will fully convey the scope of the example implementations to those skilled in the art. Like reference numerals may be used to refer to like elements throughout and detailed descriptions of the like elements will not be repeated. Additionally, the drawings are schematic and not necessarily to scale.

[0088] Although relative terms such as "upper," "lower," are used herein to describe one component's relationship to another component of the icon, these terms are used herein for convenience only and are not intended to be limiting. It is to be understood that if the icon were turned over so that its upper and lower sides were reversed, as described herein the component previously described as being "upper" would be "lower." When a structure is "on" another structure, it can mean that the structure is formed integrally with the other structure, or that the structure is "directly" on the other structure, or that the structure is "indirectly" on the other structure by being on the other structure via another structure.

[0089] The terms "one," "a," "an," "the," and "said" are used to mean that "at least one" or "one or more" unless otherwise indicated. The terms "including" and "having" are used to mean "comprising" or "including" and are used open-ended in that additional elements / limitations can be present beyond those listed in the description of the example. The terms "first," "second," and "third," etc. are used only as labels, and do not mean a limitation as to the number. The terms "exemplary," "for example," and "e.g." are used to mean "an example of."

[0090] OLED (Organic Light Emitting Diode) display panels can have a phenomenon of smearing due to hysteresis of driving transistors. A test method for whether the display panel has smearing is to record a waveform curve of the display panel from turning on to stable brightness, and to observe the difference between the first frame brightness and the stable brightness.

[0091] The inventors analyzed the smearing phenomenon in the display panel, and found that the main reason for the smearing of the display panel is that the first frame actual brightness of a high gray scale pattern is lower than the actual brightness of each subsequent frame when the OLED display panel switches from a low gray scale pattern to a high gray scale pattern. In other words, the first frame of the high gray scale pattern is dark, and the rest of the frames are basically normal, which leads to the smearing of part of the moving pattern. In particular, when the OLED display panel switches from a black picture to a white picture, the first frame brightness of the white picture is significantly lower than the brightness of each subsequent frame.

[0092] In the related art, with the demand for high-precision variable-frequency display products, in order to improve the flicker problem of the display product, a timing optimization scheme is generally adopted, for example, a plurality of reset signals can be provided by a gate driving circuit to perform a plurality of reset operations on the pixel driving circuit, so that the flicker change of the display panel is difficult for the human eye to perceive, thereby improving the flicker problem of the display product. However, the plurality of resets of the reset signal in this timing optimization will cause the current used for light emission of the light emitting element to be small in a low gray scale state (see FIG. 10, I1 = I2 + I3 + I4, where I1 is the driving current theoretically generated in the pixel driving circuit; I2 is the current consumed for resetting the pixel electrode PE; I3 is the current consumed for resetting the parasitic capacitance existing between the pixel electrode PE and the source-drain metal layer (see FIG. 9, the overlapping area A1 between the pixel electrode PE and the source-drain metal layer forms a parasitic capacitance); and I4 is the current actually emitted by the light emitting element. It can be seen that the current actually emitted by the light emitting element is closely related to the number of times of resetting the pixel electrode). The plurality of times of resetting the pixel electrode will cause the first frame to take more time to light up, or cause the first frame to have a small brightness, which effectively alleviates the flicker phenomenon of the display product to a certain extent, but is still not conducive to the trailing phenomenon of the display product, affecting the display quality of the display product.

[0093] Based on this, the display device provided by the embodiments of the present disclosure includes a display panel and a driver for driving the display panel. The embodiments of the present disclosure also provide a driving method for the display panel, which adjusts the driving mode of the pixel driving circuit at different time periods. The driver can control the display panel so that the display panel can implement the driving method in the embodiments of the present disclosure. The driving method for driving the display panel can improve the brightness of the display panel when it is lighted up, reduce the difference between the brightness of the display panel when it is lighted up and the stable brightness, and help to reduce the phenomenon of trailing of the display panel on the basis of alleviating the flicker phenomenon of the display panel, thereby improving the display quality of the display panel.

[0094] In some embodiments of the present disclosure, referring to FIG. 1, the display panel can include a substrate SBT, a driving layer DRL, and a pixel layer PIXL which are sequentially stacked.

[0095] The display panel will be described in detail below in combination with the hierarchical structure of each layer in the display panel:

[0096] In some embodiments of the present disclosure, the substrate SBT can be a substrate of inorganic material or a substrate of organic material. For example, in one embodiment of the present disclosure, the material of the substrate SBT can be a glass material such as soda-lime glass, quartz glass, sapphire glass, etc., or a metal material such as stainless steel, aluminum, nickel, etc. In another embodiment of the present disclosure, the material of the substrate SBT can be Polymethyl methacrylate (PMMA), Polyvinyl alcohol (PVA), Polyvinyl phenol (PVP), Polyether sulfone (PES), polyimide, polyamide, polyacetal, Poly carbonate (PC), Polyethylene terephthalate (PET), Polyethylene naphthalate (PEN), or a combination thereof. In another embodiment of the present disclosure, the substrate SBT can also be a flexible substrate, for example, the material of the substrate SBT can be polyimide (PI). The substrate SBT can also be a composite of multiple layers, for example, in one embodiment of the present disclosure, the substrate SBT can include a bottom film layer, a pressure-sensitive adhesive layer, a first polyimide layer, and a second polyimide layer which are sequentially stacked.

[0097] Optionally, referring to FIG. 1, in the driving layer DRL, any one pixel driving circuit can include a thin film transistor and a storage capacitor CST (not shown in the drawings of the present disclosure). Further, the thin film transistor can be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor; the material of the active layer of the thin film transistor can be amorphous silicon semiconductor material, low-temperature polysilicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material, or other types of semiconductor material; and the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor.

[0098] It can be understood that in each of the pixel driving circuits, the types of any two transistors can be the same or different. For example, in some embodiments, in one pixel driving circuit, some of the transistors can be N-type transistors and some of the transistors can be P-type transistors. For another example, in some other embodiments, in one pixel driving circuit, the materials of the active layers of some of the transistors can be low-temperature polysilicon semiconductor materials, and the materials of the active layers of some of the transistors can be metal oxide semiconductor materials. In some embodiments of the present disclosure, the thin film transistors are low-temperature polysilicon transistors. In some other embodiments of the present disclosure, some of the thin film transistors are low-temperature polysilicon transistors, and some of the thin film transistors are metal oxide transistors.

[0099] Optionally, referring to FIG. 1, the driving layer DRL can include a semiconductor layer (e.g., a polysilicon semiconductor layer PSCL and a metal oxide semiconductor layer OSCL), a gate insulating layer (e.g., a first gate insulating layer GI1, a second gate insulating layer GI2, and a third gate insulating layer GI3), a gate layer (e.g., a first gate layer GT1, a second gate layer GT2, and a third gate layer GT3), an interlayer dielectric layer ILD, a source-drain metal layer (e.g., a first source-drain metal layer SD1, a second source-drain metal layer SD2, and a third source-drain metal layer SD3), a planarization layer (e.g., a first planarization layer PLN1, a second planarization layer PLN2, and a third planarization layer PLN3), and the like, which are stacked between the substrate base plate SBT and the pixel layer PIXL. Each of the thin film transistors and the storage capacitor CST can be formed by the semiconductor layer, the gate insulating layer, the gate layer, the interlayer dielectric layer ILD, the source-drain metal layer, and the like; of course, other film layers can also be used. The positional relationship of each of the film layers can be determined according to the film layer structure of the thin film transistor. Further, the semiconductor layer can be used to form the active layer of the transistor (including the first electrode, the second electrode, and the channel region of the transistor), and can also be used to form part of the wiring or the conductive structure by being made conductive when necessary. The first source-drain metal layer SD1 can be used to form the scanning signal wiring; the gate layer can be used to form one or more of the reset control wiring, the light-emitting control wiring, and the like, and can also be used to form the gate electrode of the transistor, and can also be used to form part or all of the electrode plate of the storage capacitor CST. The source-drain metal layer can be used to form the data wiring, the driving power voltage wiring, and the like, and can also be used to form part of the electrode plate of the storage capacitor CST.

[0100] Of course, in other embodiments of the present disclosure, the driving layer DRL can also include other film layers as needed, for example, it can also include a metal light shielding layer BSM between the semiconductor layer and the substrate SBT, etc. Any one of the above-mentioned semiconductor layer, gate layer, source-drain metal layer, etc. film layer can also be multi-layered as needed, for example, the driving layer DRL can include two different semiconductor layers, or include two or three source-drain metal layers, or include two or three gate layers; accordingly, the insulating film layer in the driving layer DRL (such as the gate insulating layer, the interlayer dielectric layer ILD, the planarization layer, etc.) can be adaptively increased or decreased, or a new insulating film layer can be added as needed.

[0101] Optionally, the pixel layer PIXL can include a pixel electrode layer PEL, a light-emitting functional layer EL, and a common electrode layer COML which are sequentially stacked. The pixel electrode layer PEL has a plurality of pixel electrodes PE in the display area of the display panel. The pixel definition layer PDL has a plurality of through pixel openings corresponding to the plurality of pixel electrodes PE, and any one pixel opening exposes at least a partial area of the corresponding pixel electrode PE. For example, the pixel definition layer PDL covers the edges of the pixel electrode PE and exposes at least a partial internal area of the pixel electrode PE, so that the pixel definition layer PDL can effectively define the actual effective area of the pixel electrode (the area directly connected to the light-emitting functional layer EL), and further define the light-emitting area and light-emitting area of the sub-pixel. The common electrode layer COML covers the light-emitting functional layer EL as a common electrode. The pixel electrode PE and the common electrode layer COML provide carriers such as electrons and holes to the light-emitting functional layer EL, so that the light-emitting functional layer EL emits light. The part of the light-emitting functional layer EL between the pixel electrode and the common electrode layer COML can serve as a light-emitting functional unit of the sub-pixel. The pixel electrode PE, the common electrode layer COML, and the light-emitting functional unit form a light-emitting element as a sub-pixel. Among them, one of the pixel electrode PE and the common electrode layer COML serves as an anode of the sub-pixel, and the other serves as a cathode of the sub-pixel.

[0102] In this example, the display panel is an OLED (Organic Light Emitting Diode) display panel. The light-emitting functional layer EL can include an organic light-emitting layer, and can include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. Further, the organic light-emitting layer can include a light-emitting layer host material and a light-emitting layer guest material, which can be a fluorescent dopant or a phosphorescent dopant, and in particular can be a thermally activated delayed fluorescence material.

[0103] It can be understood that the display panel can also be other types of display panels, such as a QLED display panel, a QD-OLED display panel, or other types of display panels.

[0104] Referring to FIG. 1, the display panel can further include a thin film encapsulation layer TFE, which can be disposed on a surface of the pixel layer PIXL away from the substrate base plate SBT, and can include inorganic encapsulation layers and organic encapsulation layers which are alternately stacked. The inorganic encapsulation layers can effectively block moisture and oxygen from the outside, so as to avoid water and oxygen from invading the pixel layer PIXL and causing the materials in the pixel layer PIXL to age. Optionally, the edges of the inorganic encapsulation layers can be located in the peripheral area. The organic encapsulation layers are located between two adjacent inorganic encapsulation layers, so as to achieve planarization and weaken the stress between the inorganic encapsulation layers. The edges of the organic encapsulation layers can be located between the edges of the display area and the edges of the inorganic encapsulation layers.

[0105] Exemplarily, the thin film encapsulation layer TFE includes a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer which are sequentially stacked on a side of the pixel layer PIXL away from the substrate base plate SBT (not specifically shown in the figure). The first inorganic encapsulation layer covers the display area and extends to the outside of the barrier wall; the organic encapsulation layer covers the display area and extends to the inside of the barrier wall; and the second inorganic encapsulation layer covers the organic encapsulation layer and extends to the outside of the barrier wall. On the outside of the barrier wall, the second inorganic encapsulation layer is in contact with the first inorganic encapsulation layer. In this way, the organic encapsulation layer is enclosed by the first inorganic encapsulation layer and the second inorganic encapsulation layer, and the stress of the first inorganic encapsulation layer and the second inorganic encapsulation layer is balanced. The first inorganic encapsulation layer and the second inorganic encapsulation layer enclose the organic encapsulation layer, so as to isolate the organic encapsulation layer from water and oxygen. Of course, in other embodiments of the present disclosure, the display panel can also not be provided with the thin film encapsulation layer TFE, but other ways can be used to encapsulate and protect the pixel layer.

[0106] The display panel includes a pixel driving circuit for driving each sub-pixel. FIG. 2 shows an equivalent circuit diagram of a pixel driving circuit in an embodiment of the present disclosure. It can be understood that the pixel driving circuit in the embodiment of the present disclosure can also be a pixel driving circuit of other structures. When the structure of the pixel driving circuit changes, the structures of the various film layers in the example of the present disclosure can also be adjusted adaptively. It can be understood that in the embodiment of the present disclosure, the pixel circuit can also be 8T1C (8 transistors and 1 storage capacitor), 9T1C (9 transistors and 1 storage capacitor), 10T1C (10 transistors and 1 storage capacitor), etc., and the present embodiment does not specifically limit this.

[0107] The basic principle of the pixel circuit will be described below in combination with the equivalent circuit diagram of the pixel circuit:

[0108] Referring to FIG. 2, the pixel driving circuit includes a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emitting transistor T5, a second light emitting transistor T6, an electrode reset transistor T7, a node control transistor T8, and a storage capacitor CST. The threshold compensation transistor T2 is an N-type thin film transistor, such as a metal oxide thin film transistor. The remaining thin film transistors are P-type thin film transistors, such as low temperature poly-silicon thin film transistors. The pixel driving circuit PDC further includes a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5.

[0109] In an embodiment of the present disclosure, the threshold compensation transistors can each be an N-type thin film transistor, such as a metal oxide thin film transistor. The remaining thin film transistors are P-type thin film transistors, such as low temperature poly-silicon thin film transistors.

[0110] The first electrode of the first reset transistor T1 is connected to a first initialization voltage Vinit1, and is configured to load the first initialization voltage Vinit1. The gate electrode of the first reset transistor T1 is configured to load a first reset signal RP. The second electrode of the first reset transistor T1 is connected to the third node N3. The first reset transistor T1 is configured to load the first initialization voltage Vinit1 to the third node N3 in response to the first reset signal RP.

[0111] The first electrode of the threshold compensation transistor T2 is electrically connected to the third node N3. The second electrode of the threshold compensation transistor T2 is electrically connected to the first node N1. The gate electrode of the threshold compensation transistor T2 is configured to load a first scan signal GN. The threshold compensation transistor T2 is configured to turn on in response to the first scan signal GN, and write the first initialization voltage Vinit1 loaded by the first electrode of the first reset transistor T1 to the first node N1.

[0112] The first electrode of the driving transistor T3 is connected to the second node N2. The second electrode of the driving transistor T3 is connected to the third node N3. The gate electrode of the driving transistor T3 is connected to the first node N1. The driving transistor T3 is configured to output a driving current under the control of a voltage at the first node N1.

[0113] The first electrode of the data writing transistor T4 is connected to a data voltage Vdata, and is configured to load the data voltage Vdata. The second electrode of the data writing transistor T4 is electrically connected to the second node N2. The gate electrode of the data writing transistor T4 is configured to load a second scan signal GP. The data writing transistor T4 is configured to load the data voltage Vdata to the second node N2 in response to the second scan signal GP.

[0114] The first electrode of the first light-emitting transistor T5 is connected with the fifth node N5, the first electrode of the first light-emitting transistor T5 is used to load the power supply voltage VDD, the second electrode of the first light-emitting transistor T5 is connected with the second node N2, and the gate electrode of the first light-emitting transistor T5 is used to load the light-emitting signal EM.

[0115] The first electrode of the second light-emitting transistor T6 is connected with the third node N3, the second electrode of the second light-emitting transistor T6 is connected with the fourth node N4, and the gate electrode of the second light-emitting transistor T6 is used to load the light-emitting signal EM. The first light-emitting transistor T5 and the second light-emitting transistor T6 are used to be turned on in response to the light-emitting signal EM.

[0116] In the above-mentioned example embodiment, the first light-emitting transistor T5 and the second light-emitting transistor T6 work in response to the same light-emitting signal EM. In one example, the gate electrode of the first light-emitting transistor T5 and the gate electrode of the second light-emitting transistor T6 can be connected on the same light-emitting signal wire (not specifically marked in the drawings of the present application). It can be understood that in another example, the gate electrode of the first light-emitting transistor T5 and the gate electrode of the second light-emitting transistor T6 can also be respectively connected to different light-emitting signal wires. In this embodiment, the light-emitting signal wires to which the gate electrode of the first light-emitting transistor T5 and the gate electrode of the second light-emitting transistor T6 are respectively connected can load the light-emitting signal EM respectively, for example, load the light-emitting signal EM at different times respectively, which makes the first light-emitting transistor T5 and the second light-emitting transistor T6 can be turned on at different times. Of course, in some other embodiments of the present disclosure, the gate electrode of the first light-emitting transistor T5 and the gate electrode of the second light-emitting transistor T6 can also be respectively connected to different light-emitting signal wires, and the two light-emitting signal wires can load the light-emitting signal EM at the same time.

[0117] The first electrode of the electrode reset transistor T7 is connected with the second initialization voltage Vinit2, the first electrode of the electrode reset transistor T7 is used to load the second initialization voltage Vinit2, the gate electrode of the electrode reset transistor T7 is used to load the second reset signal RH, and the second electrode of the electrode reset transistor T7 is connected with the fourth node N4. The electrode reset transistor T7 is used to load the second initialization voltage Vinit2 to the fourth node N4 in response to the second reset signal RH.

[0118] The first electrode of the node control transistor T8 is connected with the third initialization voltage Vinit3, the first electrode of the node control transistor T8 is used to load the third initialization voltage Vinit3, the gate electrode of the node control transistor T8 is used to load the second reset signal RH, and the second electrode of the node control transistor T8 is connected with the second node N2. The node control transistor T8 is used to load the third initialization voltage Vinit3 to the second node N2 in response to the second reset signal RH.

[0119] The light emitting element (not shown in the drawings) is electrically connected to the pixel driving circuit. The common electrode is used to load a reference voltage VSS, one end of the storage capacitor CST is connected to the first node N1, and the other end is connected to the fifth node N5.

[0120] In the display panel of the present disclosure, by setting the threshold compensation transistor T2 as a metal oxide transistor, the leakage of the first node N1 can be reduced, thereby improving the voltage holding capability of the pixel driving circuit, reducing the flicker risk of the display panel under low frequency driving, and reducing the power consumption of the display panel. The remaining transistors can be set as P-type transistors.

[0121] In the embodiment of the present disclosure, referring to FIG. 11, the driving method of the pixel driving circuit driving any one of the sub-pixels in the display panel includes:

[0122] Step S110: driving the pixel driving circuit in a first time period F1 by using a first driving mode;

[0123] Step S120: driving the pixel driving circuit in a second time period S1 by using a second driving mode;

[0124] The first time period F1 is a time period for displaying the first one or more frames of pictures; the second time period S1 is after the first time period F1; the brightness of the sub-pixel when the pixel driving circuit drives the sub-pixel in the second time period S1 by using the first driving mode is greater than the brightness of the sub-pixel when the pixel driving circuit drives the same sub-pixel of the same gray scale in the second time period S1 by using the second driving mode.

[0125] In the embodiment of the present disclosure, the brightness of the sub-pixel can be determined by a direct measurement method, for example, using a high-precision camera (especially a high-speed camera) to measure the brightness of each sub-pixel. In an example, the display panel can be caused to display a single-color picture to measure the brightness of the sub-pixel. For example, each green sub-pixel can be caused to emit light while the other sub-pixels do not emit light to measure the brightness of the green sub-pixel. For another example, each red sub-pixel can be caused to emit light while the other sub-pixels do not emit light to measure the brightness of the red sub-pixel. For another example, each blue sub-pixel can be caused to emit light while the other sub-pixels do not emit light to measure the brightness of the blue sub-pixel. It can be understood that other technical indicators related to the brightness of the sub-pixel can also be used to characterize or determine the brightness change of the sub-pixel; that is, the brightness change of the sub-pixel is indirectly and explicitly determined by measuring other indicators.

[0126] In an indirect strategy, the luminance change of a sub-pixel can be determined by measuring the change of the anode potential of the sub-pixel. The anode potential change of a sub-pixel has a correlation with the luminance change, and the change trend is related to the specific driving mode, and the driving mode is explicit. For example, it can be explicit by the relationship between the gray scale of the display panel and the gray scale voltage. When the anode potential of a sub-pixel is positively correlated with the luminance of the sub-pixel, when it is detected that the anode potential of the sub-pixel is higher in a first time period than in a second time period, it can be determined that the luminance of the sub-pixel in the first time period is greater. When the anode potential of a sub-pixel is negatively correlated with the luminance of the sub-pixel, when it is detected that the anode potential of the sub-pixel is lower in a first time period than in a second time period, it can be determined that the luminance of the sub-pixel in the first time period is greater.

[0127] In another indirect strategy, the luminance of a sub-pixel can be determined by measuring the length of the light-emitting time of the sub-pixel. Under other conditions, the longer the light-emitting time of a sub-pixel, the greater the luminance of the sub-pixel. It can be understood that the length of the light-emitting time of a sub-pixel can be determined by observing the light-emitting of the sub-pixel, or by detecting the anode potential of the sub-pixel.

[0128] In an embodiment of the present disclosure, the first frame displayed at the beginning refers to the first picture after the display panel is powered on, and the time period of the first frame displayed at the beginning refers to the time period of displaying the first picture. Similarly, the second frame displayed at the beginning refers to the second picture after the display panel is powered on, and the time period of the second frame displayed at the beginning refers to the time period of displaying the second picture. Similarly, the Xth frame displayed at the beginning refers to the Xth picture after the display panel is powered on. In an example, whether the display panel is powered on can be determined according to whether the driving chip of the display panel is powered on.

[0129] In the related art, the pixel driving circuit drives the sub-pixel in the first time period F1 and the second time period S1, and the second driving mode is used to drive the sub-pixel. When the pixel driving circuit is driven by the second driving mode in the first time period F1, the pixel electrode in the display panel is reset multiple times, which causes the display panel to take a longer time to reach the bright state (first frame) or the first frame brightness of the display panel is lower under the same time, which causes a large difference between the bright state and the stable state of the display panel, and further causes the display panel to have a trailing phenomenon, which reduces the display quality of the display panel. According to the driving method of the display panel provided in the present disclosure, in step S110, the first driving mode is used to drive the sub-pixel in the first time period F1, and in step S120 of the embodiment of the present disclosure, the second driving mode is used to drive the sub-pixel in the second time period S1, which helps to reduce the difference between the bright state and the stable state of the display panel, and can alleviate the trailing phenomenon of the display panel. In addition, driving the sub-pixel by the second driving mode can also alleviate the flicker phenomenon of the display panel, and thus driving the sub-pixel by the first driving mode in the first time period F1 and the second driving mode in the second time period S1 helps to improve the display quality of the display panel.

[0130] In an embodiment of the present disclosure, the driver of the display device is configured to drive the display panel, the display panel comprising a pixel driving circuit driving each sub-pixel, and the driver is configured to enable the display panel to drive the pixel driving circuit in the following manner:

[0131] In the first time period F1, the first driving mode is used to drive the pixel driving circuit;

[0132] In the second time period S1, the first driving mode is used to drive the pixel driving circuit;

[0133] The first time period F1 is the time period of the first frame or multiple frames of display; and the second time period S1 is after the first time period F1.

[0134] The sub-pixel brightness when the pixel driving circuit drives the sub-pixel by the first driving mode in the second time period S1 is greater than the sub-pixel brightness when the pixel driving circuit drives the same gray scale of the same sub-pixel by the second driving mode in the second time period S1. In this way, the driver of the display device can implement the above-mentioned driving method, and the display panel provided with the driver can help to improve the trailing problem of the display panel and improve the display quality of the display panel in reducing the flicker phenomenon.

[0135] In some embodiments of the present disclosure, the driver can be a timing controller. The timing controller can receive information (e.g., picture information) from a host computer (e.g., a main computer, a main board, etc.), and generate control signals for controlling the display panel according to the received information and a selected driving mode; the display panel responds to the control signals provided by the timing controller to implement driving of each pixel driving circuit according to the selected driving mode (e.g., the first driving mode or the second driving mode).

[0136] The control signals generated by the timing controller can include, but are not limited to, one or more of signals for controlling the gate driving circuit (e.g., a time length of a gate driving circuit start signal of an emission signal EM, a time length of a gate driving circuit start signal for controlling the second scan signal GP), signals for controlling the source driving circuit (e.g., a time length of loading a data voltage Vdata to a data signal wire), and the like. The principles and processes of the driving method of the display panel are exemplarily introduced and analyzed as follows in combination with the related drawings and examples.

[0137] In some embodiments of the present disclosure, the display panel includes pixel driving circuits for driving respective sub-pixels; and a method for driving any one of the pixel driving circuits includes: in a first time period, driving the pixel driving circuit using a first driving mode; in a second time period, driving the pixel driving circuit using a second driving mode; the first time period is a time period for displaying a first one or more frames of pictures; the second time period is after the first time period; and each time the pixel driving circuit is driven, the first electrode of the driving transistor, the second electrode of the driving transistor, and the pixel electrode are reset one or more times; in the first driving mode, the number of times the first electrode of the driving transistor, the second electrode of the driving transistor, and the pixel electrode are reset each time the pixel driving circuit is driven is less than the number of times the first electrode of the driving transistor, the second electrode of the driving transistor, and the pixel electrode are reset each time the pixel driving circuit is driven in the second driving mode.

[0138] In some embodiments of the present disclosure, the first time period F1 is a time period for displaying a first frame of pictures, a time period for displaying a first two frames of pictures, a time period for displaying a first three frames of pictures, or a time period for displaying a first four frames of pictures.

[0139] In some examples, the first time period F1 can be a time period for displaying a first frame of pictures. In this way, when the first frame of pictures is displayed, the first driving mode is used to drive the sub-pixels, so that the brightness of the first frame of pictures in the display panel is increased, the difference between the brightness of the first frame of pictures and the brightness of the remaining frames of pictures is reduced, and the phenomenon of ghosting of the display panel is alleviated.

[0140] In some examples, the first time period F1 can be a time period for displaying the first two frames of images. Thus, when the first two frames of images are displayed, the first driving mode is used to drive the sub-pixel, so that the brightness of the first two frames of images in the display panel is increased, the difference between the brightness of the first two frames of images and the brightness of the remaining frames of images in the display panel is reduced, and the phenomenon of the display panel smearing is alleviated.

[0141] In some examples, the first time period F1 can be a time period for displaying the first three frames of images. Thus, when the first three frames of images are displayed, the first driving mode is used to drive the sub-pixel, so that the brightness of the first three frames of images in the display panel is increased, the difference between the brightness of the first three frames of images and the brightness of the remaining frames of images in the display panel is reduced, and the phenomenon of the display panel smearing is alleviated. Of course, the first time period F1 can also be a time period for displaying the first four frames of images. The present disclosure does not make specific limitations on this, as long as the difference between the brightness of the display panel starting to light up and the stable brightness of the display panel is reduced, and the phenomenon of the display panel smearing is improved.

[0142] In some embodiments of the present disclosure, the driving method comprises resetting the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE once or multiple times each time the pixel driving circuit is driven. In the first driving mode, the number of times of resetting the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE each time the pixel driving circuit is driven is less than the number of times of resetting the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE each time the pixel driving circuit is driven in the second driving mode. Thus, in the first driving mode, the current consumed for resetting in the pixel driving circuit is less than the current consumed for resetting in the pixel driving circuit in the second driving mode, and thus the current actually emitted by the light emitting element in the first driving mode is greater than the current actually emitted by the light emitting element in the second driving mode, which helps to increase the brightness of the sub-pixel in the first time period, and thus helps to improve the phenomenon of the display panel smearing.

[0143] In some embodiments, the first driving mode includes resetting the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE only once each time the pixel driving circuit is driven; and the second driving mode includes resetting the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE multiple times each time the pixel driving circuit is driven. In this way, in the first driving mode, the current consumed for resetting in the pixel driving circuit is less than that in the second driving mode, so that the actual current emitted by the light emitting element in the first driving mode is greater than that in the second driving mode, which helps to improve the brightness of the sub-pixel in the first time period, and further helps to improve the ghosting phenomenon of the display panel.

[0144] As an example, the first driving mode includes resetting the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE only once each time the pixel driving circuit is driven; and the second driving mode includes resetting the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE three times each time the pixel driving circuit is driven. In this way, in the first driving mode, resetting the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE once can improve the brightness of the display panel (compared to multiple times of resetting the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE); and in the second driving mode, multiple times of resetting the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE helps to alleviate the flicker phenomenon of the display panel. The first driving mode and the second driving mode drive the display panel in this way to achieve, in the case of alleviating the flicker of the display panel, reducing the difference between the brightness of the display panel in the on state and the brightness of the display panel in the stable state, which can alleviate the ghosting phenomenon of the display panel.

[0145] It can be understood that, when resetting the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE, the driver (the timing controller) loads a start signal to the gate driving circuit, and adjusts the reset signal (such as the first reset signal RP and the second reset signal RH) in the gate driving circuit according to the start signal loaded by the timing controller, so that the frequency of the reset signal loaded to the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE can be adjusted, and further, the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE can be reset once or multiple times. It should be noted that, in the second driving mode, the number of times of resetting the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE is not specifically limited in the embodiments of the present disclosure, and any number of times that can alleviate the flicker phenomenon of the display panel is acceptable.

[0146] In this embodiment, at least three emission signal EM cutoff levels and at least two emission signal EM conductive levels between the emission signal EM cutoff levels are loaded to the pixel driving circuit each time the pixel driving circuit is driven; the first driving mode includes writing the data voltage Vdata to the pixel driving circuit and resetting the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE during the first loading of the emission signal cutoff level (for example, the first emission signal cutoff level EM11); the second driving mode includes writing the data voltage Vdata to the pixel driving circuit and resetting the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE during the first loading of the emission signal cutoff level (for example, the first emission signal cutoff level EM11); at least one reset is performed on the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE when the remaining emission signal EM cutoff levels (for example, the second emission signal cutoff level EM21 and the third emission signal cutoff level EM31) are loaded. It can be understood that the number of times of resetting the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE when the remaining emission signal EM cutoff levels are loaded is not specifically limited.

[0147] It can be understood that the timing controller loads a start signal to the gate driving circuit, and according to the start signal loaded by the timing controller, the gate driving circuit loads the emission signal EM to the pixel driving circuit, so that at least three emission signal EM cutoff levels and at least two emission signal EM conductive levels between the emission signal EM cutoff levels can be loaded to the pixel driving circuit each time the pixel driving circuit is driven.

[0148] The principle and process of the driving method are exemplarily introduced and analyzed as follows in combination with the pixel driving circuit and the timing diagram. In the embodiments of the present disclosure, in order to better explain the pixel driving circuit provided by the present disclosure, the specific performance of the present disclosure is not limited, wherein “0” represents a low level and “1” represents a high level. It should be noted that for a P-type transistor, a low level is loaded to turn on and a high level is loaded to turn off; for an N-type transistor, a low level is loaded to turn off and a high level is loaded to turn on.

[0149] The driving mode of driving the pixel driving circuit in the first time period F1 by the first driving mode is as follows:

[0150] In the first emission signal cutoff level EM11:

[0151] Referring to FIG. 3 and FIG. 4, the state diagram of the pixel driving circuit in the initialization stage is shown. In the first initialization stage t1, EM=1, RP=0, GN=1, GP=1, RH=1; the first reset transistor T1 is turned on under the low level provided by the first reset signal RP, and the first initialization voltage Vinit1 is written into the second electrode (i.e. the third node N3) of the driving transistor T3; the threshold compensation transistor T2 is turned on under the high level provided by the first scan signal GN, and the first initialization voltage Vinit1 of the third node N3 is written into the gate electrode (i.e. the first node N1) of the driving transistor T3 and stored in the storage capacitor CST. The potential of the N1 node is Vg=Vinit1. In addition, the first light-emitting transistor T5 and the second light-emitting transistor T6 are turned off under the control of the high level provided by the light-emitting signal EM, and the light-emitting element does not emit light; the data writing transistor T4 is turned off under the high level provided by the second scan signal GP; the electrode reset transistor T7 is turned off under the control of the high level provided by the second reset signal RH; and the node control transistor T8 is turned off under the control of the high level provided by the second reset signal RH.

[0152] Referring to FIG. 3 and FIG. 5, the state diagram of the pixel driving circuit in the data writing stage t2 is shown. In the data writing stage t2, EM=1, RP=1, GN=0, GP=1, RH=1; the threshold compensation transistor T2 is turned on under the high level provided by the first scan signal GN; and the data writing transistor T4 is turned on under the low level provided by the second scan signal GP, so that the data voltage Vdata required by the light-emitting element can be written into the second electrode of the driving transistor T3 through the data voltage Vdata, and the threshold voltage of the driving transistor T3 and the data voltage Vdata can be written into the gate electrode of the driving transistor T3 through the threshold compensation transistor T2, until the potential of the N1 node is Vg=Vdata+Vth, wherein Vth represents the threshold voltage of the driving transistor T3. In addition, the storage in the gate electrode of the driving transistor T3 can also be stored in the storage capacitor CST, so that the driving transistor T3 forms a driving circuit under the action of the storage capacitor CST, thereby controlling the light-emitting element to emit light and ensuring the driving capability of the pixel driving circuit. Further, the electrode reset transistor T7 is turned off under the high level provided by the second reset signal RH; the first light-emitting transistor T5 and the second light-emitting transistor T6 are turned off under the control of the high level provided by the light-emitting signal EM, and the light-emitting element does not emit light; and the first reset transistor T1 is turned off under the high level provided by the first reset signal RP.

[0153] Referring to FIG. 3 and FIG. 6, a state diagram of the pixel driving circuit in the reset stage is shown. In the first reset stage t3, EM=1, RP=0, GN=0, GP=0, RH=0; the node control transistor T8 is turned on under the low level provided by the second reset signal RH, and the third initialization voltage Vinit3 loaded at the first electrode of the node control transistor T8 can be written into the first electrode (i.e. the second node N2) of the driving transistor T3; the electrode reset transistor T7 is turned on under the low level provided by the second reset signal RH, and the second initialization voltage Vinit2 can be written into the first electrode (i.e. the fourth node N4) of the light emitting element, which realizes the anode reset when the first electrode of the light emitting device is the anode, thereby ensuring the low frequency display. In addition, the first light emitting transistor T5 and the second light emitting transistor T6 are turned off under the control of the high level provided by the light emitting signal EM, and the light emitting element does not emit light; the first reset transistor T1 is turned off under the low level provided by the first reset signal RP. The threshold compensation transistor T2 is turned off under the low level of the first scan signal GN.

[0154] In the process of the first light emitting signal conduction level EM10:

[0155] Referring to FIG. 3 and FIG. 7, a state diagram of the pixel driving circuit in the light emitting stage t4 is shown. In the light emitting stage t4, EM=0, RP=1, GN=0, GP=1, RH=1; the first light emitting transistor T5 and the second light emitting transistor T6 are turned on under the control of the low level provided by the light emitting signal EM, and the light emitting element emits light. At the same time, the first reset transistor T1 is turned off under the control of the high level of the first reset signal RP; the threshold compensation transistor T2 is turned off under the low level of the first scan signal GN. The data writing transistor T4 is turned off under the control of the high level of the second scan signal GP; the electrode reset transistor T7 is turned off under the control of the high level of the second reset signal RH.

[0156] Referring to FIG. 3, in the process of the second light emitting signal cutoff level EM21 and the second light emitting signal conduction level EM20, the first scan signal GN, the second scan signal GP, the first reset signal RP and the second reset signal RH in the pixel driving circuit are all loaded with the cutoff level. In the process of the third light emitting signal cutoff level EM31 and the third light emitting signal conduction level EM30, the first scan signal GN, the second scan signal GP, the first reset signal RP and the second reset signal RH in the pixel driving circuit are not loaded.

[0157] In summary, in the first driving mode, the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode are reset once when the first light-emitting signal cutoff level is loaded; in the second light-emitting signal cutoff level EM21 and the third light-emitting signal cutoff level EM31, the first scan signal GN, the second scan signal GP, the first reset signal RP and the second reset signal RH are all loaded with the cutoff level, so that the reset frequency of the light-emitting element in the first time period is reduced, the current for light emission of the light-emitting element is increased, and the brightness of the display panel in the first time period F1 can be improved.

[0158] In the second time period S1, the driving mode of the pixel driving circuit is as follows:

[0159] In the first light-emitting signal cutoff level EM11:

[0160] Referring to FIGS. 3 and 4, the state of the pixel driving circuit in the initialization stage is shown. In the first initialization stage t1, EM = 1, RP = 0, GN = 0, GP = 1, RH = 1; the first reset transistor T1 is turned on under the low level of the first reset signal RP, and the first initialization voltage Vinit1 is written into the gate of the driving transistor T3 (i.e. N1 node) and stored in the storage capacitor CST when the driving transistor T3 is turned on. The potential of the N1 node is Vg = Vinit1. In addition, the first light-emitting transistor T5 and the second light-emitting transistor T6 are cut off under the control of the high level of the light-emitting signal EM, and the light-emitting element does not emit light; the data writing transistor T4 is cut off under the high level of the second scan signal GP; the electrode reset transistor T7 is cut off under the control of the high level of the second reset signal RH; the threshold compensation transistor T2 is cut off under the low level of the first scan signal GN; and the node control transistor T8 is cut off under the control of the high level of the second reset signal RH.

[0161] Referring to FIG. 3 and FIG. 5, a state diagram of the pixel driving circuit in the data writing stage t2 is shown. In the data writing stage t2, EM = 1, RP = 1, GN = 0, GP = 1, RH = 1; the threshold compensation transistor T2 is turned on under the high level control of the first scanning signal GN; the data writing transistor T4 is turned on under the low level control of the second scanning signal GP, at this time the data voltage Vdata required by the light emitting element can be written into the second electrode of the driving transistor T3 through the data voltage Vdata, and the threshold voltage of the driving transistor T3 and the data voltage Vdata can be written into the gate electrode of the driving transistor T3 through the threshold compensation transistor T2, so that the potential of the N1 node is Vg = Vdata + Vth, wherein Vth represents the threshold voltage of the driving transistor T3 and Vdata is the voltage of the data voltage. In addition, the storage in the storage capacitor CST written into the gate electrode of the driving transistor T3 can also be stored in the storage capacitor CST, so that the driving transistor T3 forms a driving circuit under the action of the storage capacitor CST, thereby the light emitting element can be controlled to emit light, and the driving capability of the pixel driving circuit is ensured. Further, the electrode reset transistor T7 is turned on under the low level of the second reset signal RH, and the second initialization voltage Vinit2 can be written into the first electrode (N4 node) of the light emitting element, and when the first electrode of the light emitting device is the anode, the anode reset is realized, thereby ensuring the low frequency display. In addition, the first light emitting transistor T5 and the second light emitting transistor T6 are turned off under the control of the high level of the light emitting signal EM, and the light emitting element does not emit light; the first reset transistor T1 is turned off under the low level of the first reset signal RP.

[0162] Referring to FIG. 3 and FIG. 6, a state diagram of the pixel driving circuit in the reset stage is shown. In the first reset stage t3, EM = 1, RP = 0, GN = 0, GP = 0, RH = 0; the node control transistor T8 is turned on under the low level of the second reset signal RH, and the third initialization voltage Vinit3 loaded in the first electrode of the node control transistor T8 can be written into the first electrode (i.e. the second node N2) of the driving transistor T3; the electrode reset transistor T7 is turned on under the low level of the second reset signal RH, and the second initialization voltage Vinit2 can be written into the first electrode (i.e. the fourth node N4) of the light emitting element, and when the first electrode of the light emitting device is the anode, the anode reset is realized, thereby ensuring the low frequency display. In addition, the first light emitting transistor T5 and the second light emitting transistor T6 are turned off under the control of the high level of the light emitting signal EM, and the light emitting element does not emit light; the first reset transistor T1 is turned off under the low level of the first reset signal RP. The threshold compensation transistor T2 is turned off under the low level control of the first scanning signal GN.

[0163] In the first light emitting signal on level EM10:

[0164] Referring to FIG. 3 and FIG. 7, a state diagram of the pixel driving circuit in the light emitting stage t4 is shown. In the light emitting stage t4, EM = 0, RP = 1, GN = 0, GP = 1, RH = 1; the first light emitting transistor T5 and the second light emitting transistor T6 are turned on under the control of the low level of the light emitting signal EM, and the light emitting element emits light. Meanwhile, the first reset transistor T1 is turned off under the control of the high level of the first reset signal RP; the threshold compensation transistor T2 is turned off under the control of the low level of the first scan signal GN. The data writing transistor T4 is turned off under the control of the high level of the second scan signal GP; the electrode reset transistor T7 is turned off under the control of the high level of the second reset signal RH.

[0165] In the second light emitting signal off level EM21, the first light emitting transistor T5 and the second light emitting transistor T6 are turned off, and the light emitting element does not emit light.

[0166] Referring to FIG. 3 and FIG. 4, a state diagram of the pixel driving circuit in the initialization stage is shown. In the second initialization stage t5, EM = 1, RP = 0, GN = 1, GP = 1, RH = 1; the first reset transistor T1 is turned on under the control of the low level of the first reset signal RP, and the first initialization voltage Vinit1 is written to the second electrode (i.e., the third node N3) of the driving transistor T3; the threshold compensation transistor T2 is turned on under the control of the high level of the first scan signal GN, and the first initialization voltage Vinit1 of the third node N3 is written to the gate electrode (i.e., the first node N1) of the driving transistor T3 and stored in the storage capacitor CST. The potential of the N1 node is Vg = Vinit1. In addition, the first light emitting transistor T5 and the second light emitting transistor T6 are turned off under the control of the high level of the light emitting signal EM, and the light emitting element does not emit light; the data writing transistor T4 is turned off under the control of the high level of the second scan signal GP; the electrode reset transistor T7 is turned off under the control of the high level of the second reset signal RH; and the node control transistor T8 is turned off under the control of the high level of the second reset signal RH.

[0167] Referring to FIG. 3, FIG. 6, a state diagram of the pixel driving circuit in the reset stage. In the second reset stage t6, EM = 1, RP = 0, GN = 0, GP = 0, RH = 0; the node control transistor T8 is turned on under the low level provided by the second reset signal RH, and the third initialization voltage Vinit3 loaded on the first electrode of the node control transistor T8 can be written to the first electrode (i.e. the second node N2) of the driving transistor T3; the electrode reset transistor T7 is turned on under the low level provided by the second reset signal RH, and the second initialization voltage Vinit2 can be written to the first electrode (i.e. the fourth node N4) of the light emitting element, which realizes anode reset when the first electrode of the light emitting device is anode, thereby ensuring low-frequency display. In addition, the first light emitting transistor T5 and the second light emitting transistor T6 are turned off under the control of the high level provided by the light emitting signal EM, and the light emitting element does not emit light; the first reset transistor T1 is turned off under the low level provided by the first reset signal RP. The threshold compensation transistor T2 is turned off under the low level control of the first scan signal GN.

[0168] In the third light emitting signal cutoff level EM31:

[0169] Referring to FIG. 3, FIG. 4, a state diagram of the pixel driving circuit in the initialization stage. In the third initialization stage t7, EM = 1, RP = 0, GN = 1, GP = 1, RH = 1; the first reset transistor T1 is turned on under the low level provided by the first reset signal RP, and the first initialization voltage Vinit1 is written to the second electrode (i.e. the third node N3) of the driving transistor T3; the threshold compensation transistor T2 is turned on under the control of the high level provided by the first scan signal GN, and the first initialization voltage Vinit1 of the third node N3 is written to the gate electrode (i.e. the first node N1) of the driving transistor T3 and stored in the storage capacitor CST. The potential of the N1 node is Vg = Vinit1. In addition, the first light emitting transistor T5 and the second light emitting transistor T6 are turned off under the control of the high level provided by the light emitting signal EM, and the light emitting element does not emit light; the data writing transistor T4 is turned off under the high level provided by the second scan signal GP; the electrode reset transistor T7 is turned off under the control of the high level provided by the second reset signal RH; the node control transistor T8 is turned off under the control of the high level provided by the second reset signal RH.

[0170] Referring to FIG. 3 and FIG. 6, a state diagram of the pixel driving circuit in the reset stage is shown. In the third reset stage t8, EM = 1, RP = 0, GN = 0, GP = 0, RH = 0; the node control transistor T8 is turned on under the low level provided by the second reset signal RH, and the third initialization voltage Vinit3 loaded at the first electrode of the node control transistor T8 can be written into the first electrode (i.e., the second node N2) of the driving transistor T3; the electrode reset transistor T7 is turned on under the low level provided by the second reset signal RH, and the second initialization voltage Vinit2 can be written into the first electrode (i.e., the fourth node N4) of the light emitting element, which realizes anode reset when the first electrode of the light emitting device is anode, thereby ensuring low-frequency display. In addition, the first light emitting transistor T5 and the second light emitting transistor T6 are turned off under the control of the high level provided by the light emitting signal EM, and the light emitting element does not emit light; the first reset transistor T1 is turned off under the low level provided by the first reset signal RP. The threshold compensation transistor T2 is turned off under the low level control of the first scan signal GN.

[0171] In summary, when the first light emitting signal cutoff level EM11 and the first light emitting signal on level EM10 are loaded in the second driving mode, the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE are reset once. When the second light emitting signal cutoff level EM21 and the second light emitting signal on level EM20 are loaded, the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE are reset once. When the third light emitting signal cutoff level EM31 and the first light emitting signal on level EM30 are loaded, the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE are reset once (that is, in the second driving mode, the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE are reset three times). In this way, multiple resets of the light emitting element in the second time period S1 are realized, the current used for light emission of the light emitting element is reduced, which helps to reduce the difference in display brightness between the first time period F1 and the second time period S1, and further helps to improve the ghosting phenomenon of the display panel. At the same time, the multiple reset mode in the second time period S1 can reduce the flicker phenomenon of the display panel in the second time period S1.

[0172] It should be noted that the time period of displaying the first frame of picture, the time period of displaying the first two frames of picture, the time period of displaying the first three frames of picture or the time period of displaying the first four frames of picture in the display panel can be driven by the first driving mode, and the rest frames can be driven by the second driving mode. For example, the first frame of picture displayed by the display panel can be driven by the first driving mode, and the second frame of picture displayed by the display panel can be driven by the second driving mode; or the second frame of picture displayed by the display panel can be driven by the first driving mode, and the rest frames after the second frame of picture displayed by the display panel can be driven by the second driving mode; or the third frame of picture displayed by the display panel can be driven by the first driving mode, and the rest frames after the third frame of picture displayed by the display panel can be driven by the second driving mode; or the fourth frame of picture displayed by the display panel can be driven by the first driving mode, and the rest frames after the fourth frame of picture displayed by the display panel can be driven by the second driving mode, which is not limited in the embodiments of the present disclosure.

[0173] In some embodiments of the present disclosure, the pixel driving circuit comprises a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting transistor T5, a second light-emitting transistor T6, an electrode reset transistor T7, a node control transistor T8, and a storage capacitor CST; the second electrode of the data writing transistor T4, the second electrode of the node control transistor T8, and the second electrode of the first light-emitting transistor T5 are electrically connected to the first electrode of the driving transistor T3; the second electrode of the first reset transistor T1, the first electrode of the threshold compensation transistor T2, and the first electrode of the second light-emitting transistor T6 are electrically connected to the second electrode of the driving transistor T3; the second electrode of the threshold compensation transistor T2 and the first electrode plate of the storage capacitor CST are electrically connected to the gate electrode of the driving transistor T3; the first electrode of the first light-emitting transistor T5 is electrically connected to the second electrode of the storage capacitor CST; the gate electrode of the first reset transistor T1 is used to load a first reset signal RP; the gate electrode of the threshold compensation transistor T2 is used to load a first scan signal GN; the gate electrode of the data writing transistor T4 is used to load a second scan signal GP; the gate electrodes of the first light-emitting transistor T5 and the second light-emitting transistor T6 are used to load a light-emitting signal EM; the gate electrode of the electrode reset transistor T7 is used to load a second reset signal RH; the gate electrode of the node control transistor T8 is used to load the second reset signal RH; at least three light-emitting signal EM cutoff levels and at least two light-emitting signal EM conduction levels between the light-emitting signal EM cutoff levels are loaded to the pixel driving circuit each time the pixel driving circuit is driven; wherein the first driving mode comprises: in the process of loading the light-emitting signal EM cutoff level for the first time, the first scan signal GN is written to the gate electrode of the threshold compensation transistor T2 once, the second scan signal GP is written to the gate electrode of the data writing transistor T4 once, the first reset signal RP is written to the first reset transistor T1, the second reset signal RH is written to the gate electrode of the electrode reset transistor T7 once, and the second reset signal RH is written to the gate electrode of the node control transistor T8 once; the second driving mode comprises: in the process of loading the light-emitting signal EM cutoff level for the first time, the first scan signal GN is written to the gate electrode of the threshold compensation transistor T2 once, the second scan signal GP is written to the gate electrode of the data writing transistor T4 once, the second reset signal RH is written to the gate electrode of the electrode reset transistor T7 once, and the second reset signal RH is written to the gate electrode of the node control transistor T8 once; in the process of loading the remaining light-emitting signal EM cutoff level, the first reset signal RP is written to the first reset transistor T1, the second reset signal RH is written to the gate electrode of the electrode reset transistor T7 once, and the second reset signal RH is written to the gate electrode of the node control transistor T8 once.In some embodiments, the first driving mode comprises that the loading time of the data voltage Vdata is the first time ta when the data voltage Vdata is loaded to the pixel driving circuit (not shown in the drawings); the second driving mode comprises that the loading time of the data voltage Vdata is the second time tb when the data voltage Vdata is loaded to the pixel driving circuit (not shown in the drawings); and the first time ta is less than the second time tb. In this way, in the data writing stage t2 of the first driving mode, the threshold compensation transistor T2 is turned on under the control of the high level of the first scan signal GN, at this time, the data voltage Vdata can be written to the second electrode of the driving transistor T3, and the threshold voltage of the driving transistor T3 and the data voltage Vdata can be written to the gate of the driving transistor through the threshold compensation transistor T2. Similarly, in the data writing stage t2 of the second driving mode, the threshold compensation transistor T2 is turned on under the control of the high level of the first scan signal GN, at this time, the data voltage Vdata can be written to the second electrode of the driving transistor T3, and the threshold voltage of the driving transistor T3 and the data voltage Vdata can be written to the gate of the driving transistor through the threshold compensation transistor T2. By setting the loading time of the data voltage Vdata in the first driving mode to be less than the loading time of the data voltage Vdata in the second driving mode, the voltage at the gate of the driving transistor T3 (i.e. the first node N1) can be reduced, thereby improving the driving current in the first time period F1 (compared with the second time period S1), which helps to improve the display brightness of the display panel in the first time period F1.

[0174] It should be noted that in this embodiment, the loading time of both the first time length ta and the second time length tb does not exceed the loading time of the second scan signal GP electrically connected to the gate of the data writing transistor T4. In this way, the time length of the data voltage Vdata loaded to the pixel driving circuit in the first driving mode is less than the time length of the data voltage Vdata loaded to the pixel driving circuit in the second driving mode in a true sense. At the same time, the timing controller sends a signal to the source driving circuit, and the source driving circuit loads the corresponding signal according to the timing controller to the data signal wire electrically connected thereto, so as to realize that the time length of the data voltage Vdata loaded to the pixel driving circuit in the first driving mode is less than the time length of the data voltage Vdata loaded to the pixel driving circuit in the second driving mode. In an example of this embodiment, when the first emission signal EM cutoff level (for example, the first emission signal cutoff level EM11) is loaded for the first time in the first time period F1, the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE are reset once; when the remaining emission signal cutoff levels (for example, the second emission signal cutoff level EM21 and the third emission signal cutoff level EM31) are loaded, the first scan signal GN, the second scan signal GP, the first reset signal RP and the second reset signal RH are all loaded to the cutoff level; when the emission signal EM cutoff level is loaded for the first time in the second time period S1, the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE are reset once, and when the emission signal EM cutoff level is loaded for the remaining time, the number of times of resetting the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE corresponds to the number of times of loading the emission signal EM cutoff level for the remaining time, wherein the time of loading the data voltage Vdata in the first driving mode is less than the time of loading the data voltage Vdata in the second driving mode. In this way, the gate voltage of the driving transistor T3 in the first time period F1 can be reduced, the driving current in the first time period F1 (compared with the second time period S1) can be improved, which helps to improve the display brightness of the display panel in the first time period F1, reduces the brightness difference of the display panel in the first time period F1 and the second time period S1, and helps to improve the ghosting phenomenon in the display panel.

[0175] In another example of the embodiment, when the light-emitting signal cutoff level (e.g., the first light-emitting signal cutoff level EM11) is loaded for the first time in the first time period F1, the first electrode of the driving transistor T3, the second electrode of the driving transistor T3, and the pixel electrode PE are reset once; when the light-emitting signal cutoff level (e.g., the second light-emitting signal cutoff level EM21, the third light-emitting signal cutoff level EM31) is loaded for the rest of the time, the first electrode of the driving transistor T3, the second electrode of the driving transistor T3, and the pixel electrode PE are reset multiple times, wherein the number of times of resetting the first electrode of the driving transistor T3, the second electrode of the driving transistor T3, and the pixel electrode PE corresponds to the number of times of loading the light-emitting signal cutoff level. Optionally, the first electrode of the driving transistor T3, the second electrode of the driving transistor T3, and the pixel electrode PE can be reset three times. In the second time period S1, when the light-emitting signal cutoff level is loaded for the first time, the first electrode of the driving transistor T3, the second electrode of the driving transistor T3, and the pixel electrode PE are reset once; when the light-emitting signal cutoff level is loaded for the rest of the time, the first electrode of the driving transistor T3, the second electrode of the driving transistor T3, and the pixel electrode PE are reset multiple times. Optionally, the first electrode of the driving transistor T3, the second electrode of the driving transistor T3, and the pixel electrode PE can be reset three times, wherein the number of times of resetting the first electrode of the driving transistor T3, the second electrode of the driving transistor T3, and the pixel electrode PE corresponds to the number of times of loading the light-emitting signal cutoff level. The time of loading the data voltage Vdata in the first driving mode is less than the time of loading the data voltage Vdata in the second driving mode. In this way, the gate voltage of the driving transistor T3 in the first time period F1 can be reduced, the driving current in the first time period F1 (compared to the second time period S1) can be increased, the display brightness of the display panel in the first time period F1 can be improved, the brightness difference between the first time period F1 and the second time period S1 of the display panel can be reduced, and the ghosting phenomenon in the display panel can be improved.

[0176] In some embodiments of the present disclosure, referring to FIG. 8, a second scan signal GP for controlling the data writing transistor T4 is loaded to the driving circuit, the data writing transistor T4 is used to write the data voltage Vdata to the pixel driving circuit in response to the second scan signal GP; the first driving mode includes that the duration of the second scan signal is a third time length tc; the second driving mode includes that the duration of the second scan signal is a fourth time length td; and the third time length tc is less than the fourth time length td. It can be understood that in the first driving mode, the duration of the second scan signal GP is less than the duration of the second scan signal GP in the second driving mode. In this way, the gate voltage of the driving transistor T3 can also be reduced by controlling the loading duration of the second scan signal GP, and the driving current in the first time period F1 (compared to the second time period S1) can be increased, which helps to improve the display brightness of the display panel in the first time period F1.

[0177] It should be noted that in this embodiment, the loading time of the third time length tc and the fourth time length td are both less than the loading time of the data voltage Vdata connected to the first electrode of the data writing transistor T4. In this way, the time length of the second scan signal GP loaded to the pixel driving circuit in the first driving mode is less than the time length of the second scan signal GP loaded to the pixel driving circuit in the second driving mode. Meanwhile, the timing controller sends a start signal to the gate driving circuit, and the gate driving circuit loads the corresponding second scan signal GP according to the start signal, so that the time length of the second scan signal GP loaded to the pixel driving circuit in the first driving mode is less than the time length of the second scan signal GP loaded to the pixel driving circuit in the second driving mode.

[0178] In an example of this embodiment, the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE are reset once when the first time period F1 is loaded with the first emission signal cutoff level (for example, the first emission signal cutoff level EM11); the first scan signal GN, the second scan signal GP, the first reset signal RP and the second reset signal RH are all loaded with the cutoff level when the remaining emission signal cutoff levels (for example, the second emission signal cutoff level EM21 and the third emission cutoff level EM31) are loaded; the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE are reset once when the second time period S1 is loaded with the first emission signal cutoff level EM11, and the number of times of resetting the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE corresponds to the number of times of loading the remaining emission signal cutoff levels (for example, the second emission signal cutoff level EM21 and the third emission cutoff level EM31) (optionally, the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE can be reset three times). The time of loading the second scan signal GP in the first driving mode is less than the time of loading the second scan signal GP in the second driving mode. In this way, the time of loading the data voltage Vdata in the first driving mode is less than the time of loading the data voltage Vdata in the second driving mode, thereby reducing the gate voltage of the driving transistor T3 in the first time period F1, improving the driving current in the first time period F1 (compared with the second time period S1), helping to improve the display brightness of the display panel in the first time period F1, reducing the brightness difference of the display panel between the first time period F1 and the second time period S1, and helping to improve the ghosting phenomenon in the display panel.

[0179] In another example of the embodiment, the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE are reset once when the first emission signal cutoff level (e.g. the first emission signal cutoff level EM11) is loaded in the first time period F1; the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE are reset multiple times when the remaining emission signal cutoff levels (e.g. the second emission signal cutoff level EM21, the third emission signal cutoff level EM31) are loaded, wherein the number of reset times corresponds to the number of the remaining emission signal cutoff levels; the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE are reset once when the first emission signal cutoff level (e.g. the first emission signal cutoff level EM11) is loaded in the second time period S1, and the first electrode of the driving transistor T3, the second electrode of the driving transistor T3 and the pixel electrode PE are reset multiple times when the remaining emission signal cutoff levels (e.g. the second emission signal cutoff level EM21, the third emission signal cutoff level EM31) are loaded, wherein the number of reset times corresponds to the number of the remaining emission signal cutoff levels. The time for loading the second scan signal GP in the first driving mode is less than the time for loading the second scan signal GP in the second driving mode. In this way, the gate voltage of the driving transistor T3 in the first time period F1 can be reduced, the driving current in the first time period F1 (compared to the second time period S1) can be increased, the display brightness of the display panel in the first time period F1 can be improved, the brightness difference between the first time period F1 and the second time period S1 can be reduced, and the ghosting phenomenon in the display panel can be improved.

[0180] In some embodiments of the present disclosure, at least one light-emitting signal on voltage (e.g., a first light-emitting signal on voltage EM10, a second light-emitting signal on voltage EM20) is loaded to the pixel driving circuit each time the pixel driving circuit is driven; the first driving mode includes that the total time length of the light-emitting signal on voltage is a fifth time length M5 (see FIG. 12, as an example, the fifth time length M5 can include a first light-emitting signal on time t51, a second light-emitting signal on time t52, and a third light-emitting signal on time t53); the second driving mode includes that the total time length of the light-emitting signal on voltage is a sixth time length M6 (see FIG. 12, as an example, the sixth time length M6 can include a fourth light-emitting signal on time t61, a fifth light-emitting signal on time t62, and a sixth light-emitting signal on time t63); and the fifth time length M5 is greater than the sixth time length M6. It can be understood that the total time length of the light-emitting signal on voltage in the first driving mode is greater than the total time length of the light-emitting signal on voltage in the second driving mode, so that the time length of the display panel in the first time period F1 (compared to the time length of the display panel in the second time period S1) can be increased, and the display brightness of the sub-pixel in the first time period F1 can be improved, which helps to improve the ghosting problem in the display panel.

[0181] In some embodiments of the present disclosure, the first driving mode includes: determining a corrected gray scale corresponding to the pixel driving circuit according to the gray scale corresponding to the pixel driving circuit and a gray scale correction table, the corrected gray scale corresponding to the pixel driving circuit being greater than the gray scale corresponding to the pixel driving circuit; determining a data voltage Vdata corresponding to the pixel driving circuit according to the corrected gray scale corresponding to the pixel driving circuit, and writing the data voltage Vdata into the pixel driving circuit in a data writing stage; and the second driving mode includes: determining a data voltage Vdata corresponding to the pixel driving circuit according to the gray scale corresponding to the pixel driving circuit, and writing the data voltage Vdata into the pixel driving circuit in a data writing stage.

[0182] It can be understood that in the detection stage of the display panel, an industrial camera can be used to scan and detect the display panel, and the actual data voltage Vdata loaded in the display panel is compared with the gray scale presented in the display panel in the detection (generally, the data voltage Vdata has loss in loading, and the actual gray scale generated by the display panel is less than the theoretical gray scale), and a gray scale correction table is prepared under different gray scales according to the compensation principle (for example, the gray scale displayed by the display panel is improved by increasing the pre-loaded data voltage Vdata, so as to realize the display of the required gray scale). Thus, according to the gray scale correction table, the gray scale in the first time period F1 and the second time period S1 can be reasonably adjusted, and thus the ghosting phenomenon of the display panel can be slowed down.

[0183] In some embodiments of the present disclosure, the refresh rate frequency of the pixel driving circuit is less than 60 Hz. Alternatively, the refresh rate frequency of the pixel driving circuit can be 60 Hz, the refresh rate of the pixel driving circuit can be 50 Hz, the refresh rate of the pixel driving circuit can be 40 Hz, the refresh rate of the pixel driving circuit can be 30 Hz, etc. The present application does not make specific limitations thereto, as long as the refresh rate of the pixel driving circuit is less than 60 Hz.

[0184] In the embodiments of the present disclosure, the display device can be a smart phone screen, a smart watch screen or other types of display devices. Since the display device has any one of the display panels described in the above display panel embodiments, it has the same beneficial effects, and the present disclosure will not be repeated here.

[0185] It should be noted that although the steps of the driving method of the display panel in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, certain steps can be omitted, multiple steps can be combined into one step, and / or one step can be divided into multiple steps, etc.

[0186] Other embodiments of the present disclosure will be apparent to those skilled in the art with the consideration of the specification and practice of the application disclosed herein. The present application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known equivalents or technical features in the art not specifically disclosed herein. The specification and examples are to be regarded as illustrative only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A driving method of a display panel, wherein, The pixel driving circuit drives each sub-pixel; wherein the method for driving any one pixel driving circuit comprises: In a first time period, the pixel driving circuit is driven by a first driving mode; In a second time period, the pixel driving circuit is driven by a second driving mode; The first time period is a time period for displaying the first frame of pictures or the first several frames of pictures; the second time period is after the first time period; The sub-pixel brightness of the pixel driving circuit driven by the first driving mode in the second time period is greater than the sub-pixel brightness of the same sub-pixel of the same gray scale driven by the second driving mode in the second time period.

2. The driving method according to claim 1, wherein The first time period is a time period for displaying the first frame of pictures, a time period for displaying the first two frames of pictures, a time period for displaying the first three frames of pictures, or a time period for displaying the first four frames of pictures.

3. The driving method according to claim 1, wherein The driving method comprises: resetting the first electrode of the driving transistor, the second electrode of the driving transistor and the pixel electrode once or multiple times each time the pixel driving circuit is driven: In the first driving mode, the number of times of resetting the first electrode of the driving transistor, the second electrode of the driving transistor and the pixel electrode each time the pixel driving circuit is driven is less than the number of times of resetting the first electrode of the driving transistor, the second electrode of the driving transistor and the pixel electrode each time the pixel driving circuit is driven in the second driving mode.

4. The driving method of claim 1, wherein The first driving mode comprises: resetting the first electrode of the driving transistor, the second electrode of the driving transistor and the pixel electrode only once each time the pixel driving circuit is driven; The second driving mode comprises: resetting the first electrode of the driving transistor, the second electrode of the driving transistor and the pixel electrode multiple times each time the pixel driving circuit is driven.

5. The driving method according to claim 1, wherein At least three light-emitting signal cutoff levels and at least two light-emitting signal on levels between the light-emitting signal cutoff levels are loaded to the pixel driving circuit each time the pixel driving circuit is driven; The first driving mode comprises: In the process of loading the light-emitting signal cutoff level for the first time, a data voltage is written to the pixel driving circuit, and the first electrode of the driving transistor, the second electrode of the driving transistor and the pixel electrode are reset; The second driving mode comprises: In the process of loading the light-emitting signal cutoff level for the first time, a data voltage is written to the pixel driving circuit, and the first electrode of the driving transistor, the second electrode of the driving transistor and the pixel electrode are reset; At least one reset is performed on the first electrode of the driving transistor, the second electrode of the driving transistor and the pixel electrode when the remaining light-emitting signal cutoff levels are loaded.

6. The driving method according to claim 5, wherein The pixel driving circuit comprises a first reset transistor, a threshold compensation transistor, a driving transistor, a data writing transistor, a first light-emitting transistor, a second light-emitting transistor, an electrode reset transistor, a node control transistor and a storage capacitor; The second electrode of the data writing transistor, the second electrode of the node control transistor, the second electrode of the first light emitting transistor and the first electrode of the driving transistor are electrically connected; The second electrode of the first reset transistor, the first electrode of the threshold compensation transistor, the first electrode of the second light emitting transistor and the second electrode of the driving transistor are electrically connected; The second electrode of the threshold compensation transistor, the first electrode plate of the storage capacitor and the gate of the driving transistor are electrically connected; The first electrode of the first light emitting transistor and the second electrode of the storage capacitor are electrically connected; The gate of the first reset transistor is used for loading a first reset signal; The gate of the threshold compensation transistor is used for loading a first scan signal; The gate of the data writing transistor is used for loading a second scan signal; The gates of the first light emitting transistor and the second light emitting transistor are used for loading a light emitting signal; The gate of the electrode reset transistor is used for loading a second reset signal; The gate of the node control transistor is used for loading a second reset signal; At least three light emitting signal cutoff levels and at least two light emitting signal on levels between the light emitting signal cutoff levels are loaded to the pixel driving circuit at least three times during driving the pixel driving circuit each time; The first driving mode includes: during the first time of loading the light emitting signal cutoff level, the first scan signal is written to the gate of the threshold compensation transistor once, the second scan signal is written to the gate of the data writing transistor once, the first reset signal is written to the first reset transistor, the second reset signal is written to the gate of the electrode reset transistor once, and the second reset signal is written to the gate of the node control transistor once; The second driving mode includes: during the first time of loading the light emitting signal cutoff level, the first scan signal is written to the gate of the threshold compensation transistor once, the second scan signal is written to the gate of the data writing transistor once, the second reset signal is written to the gate of the electrode reset transistor once, and the second reset signal is written to the gate of the node control transistor once; during loading of the remaining light emitting signal cutoff levels, the first reset signal is written to the first reset transistor, the second reset signal is written to the gate of the electrode reset transistor once, and the second reset signal is written to the gate of the node control transistor once.

7. The driving method according to claim 1, wherein, The first driving mode includes: When a data voltage is loaded to the pixel driving circuit, the data voltage loading duration is a first duration; The second driving mode includes: When a data voltage is loaded to the pixel driving circuit, the data voltage loading duration is a second duration; The first duration is less than the second duration. A second scan signal for controlling a data writing transistor is loaded to the driving circuit, and the data writing transistor is used for writing a data voltage to the pixel driving circuit in response to the second scan signal; 8. The driving method according to claim 1, wherein The first driving mode includes: ​ The second scanning signal duration is a third time length; The second driving mode comprises: The second scanning signal duration is a fourth time length; The third time length is less than the fourth time length.

9. The driving method of claim 1, wherein, The first driving mode comprises: determining a correction gray scale corresponding to the pixel driving circuit according to the gray scale corresponding to the pixel driving circuit and the gray scale correction table, the correction gray scale of the pixel driving circuit being greater than the gray scale of the pixel driving circuit; determining a data voltage corresponding to the pixel driving circuit according to the correction gray scale of the pixel driving circuit, and writing the data voltage into the pixel driving circuit in a data writing stage; The second driving mode comprises: determining a data voltage corresponding to the pixel driving circuit according to the gray scale of the pixel driving circuit, and writing the data voltage into the pixel driving circuit in a data writing stage.

10. The driving method according to claim 1, wherein At least one light-emitting signal on level is loaded to the pixel driving circuit each time the pixel driving circuit is driven; The first driving mode further comprises: The total time length of the light-emitting signal on level each time the pixel driving circuit is driven is a fifth time length; The second driving mode further comprises: The total time length of the light-emitting signal on level each time the pixel driving circuit is driven is a sixth time length; The fifth time length is greater than the sixth time length.

11. The driving method according to claim 1, wherein The refresh rate frequency of the pixel driving circuit is less than 60 Hz.

12. A driving method of a display panel, wherein, The display panel comprises pixel driving circuits for driving respective sub-pixels; and the driver is configured to enable the display panel to drive the pixel driving circuits in the following manner: in a first time period, a first driving mode is used to drive the pixel driving circuits; in a second time period, a second driving mode is used to drive the pixel driving circuits; The first time period is a time period in which the first one or more frames of images are displayed; and the second time period is after the first time period. Each time the pixel driving circuit is driven, the first electrode of the driving transistor, the second electrode of the driving transistor and the pixel electrode are reset one or more times: in the first driving mode, The number of times the first electrode of the driving transistor, the second electrode of the driving transistor and the pixel electrode are reset each time the pixel driving circuit is driven in the first driving mode is less than the number of times the first electrode of the driving transistor, the second electrode of the driving transistor and the pixel electrode are reset each time the pixel driving circuit is driven in the second driving mode.

13. A driver of a display device configured to drive a display panel: wherein The display panel comprises pixel driving circuits for driving respective sub-pixels; and the driver is configured to enable the display panel to drive the pixel driving circuits in the following manner: in a first time period, a first driving mode is used to drive the pixel driving circuits; in a second time period, a second driving mode is used to drive the pixel driving circuits; The first time period is a time period in which the first one or more frames of images are displayed; and the second time period is after the first time period. The sub-pixel brightness when the pixel driving circuit drives the sub-pixel in the first driving mode in the second time period is greater than the sub-pixel brightness when the pixel driving circuit drives the same sub-pixel of the same gray scale in the second driving mode in the second time period.

14. A display device, wherein, The display device comprises the driver as claimed in claim 13. The display device comprises the driver as claimed in claim 13.

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