Data encoding method and chip, data decoding method and chip, and display apparatus

Abstract

Disclosed in the present application are a data encoding method and chip, a data decoding method and chip, and a display apparatus. Second bit data is added after first bit data in first image sub-data so as to obtain second image sub-data; address information and numerical information of a first piece of consecutive bit data in the second image sub-data are written into predetermined bits of row configuration information of the second image sub-data; and address information and numerical information of an (N+1)th piece of consecutive bit data in the second image sub-data are written into bits where an N-th piece of consecutive bit data in the second image sub-data is located, thereby reducing extra overheads.

Description

Data encoding method and chip, data decoding method and chip, and display device

[0001] The present application claims priority to the Chinese patent application with the application date of 2024-07-05, the application number of 202410896662.5, and the invention title of "Data encoding method and chip, data decoding method and chip, and display device", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display devices, in particular to a data encoding method and chip, a data decoding method and chip, and a display device. BACKGROUND

[0003] The display device generally performs high-speed data transmission through a point-to-point transmission interface protocol. The point-to-point transmission interface protocol can be a new high-speed point-to-point interface transmission protocol (China Standard Point-to-Point Interface, CSPI).

[0004] In order to achieve direct current balance, the technical solution of the CSPI protocol uses 8b / 9b encoding technology to re-encode the data stream, so that the number of consecutive 1s or 0s in the encoded data stream does not exceed 5 bits, that is, 1-bit 0 is inserted after every 5 consecutive 1s, or 1-bit 1 is inserted after every 5 consecutive 0s. However, although the use of 8b / 9b encoding technology can achieve direct current balance, 9 bits of bandwidth are required to transmit 8 bits of data, and the additional overhead is 11.1%. When the additional overhead is larger, the bandwidth sacrificed is more, the additional power loss of the sending end is higher, and the power consumption of the receiving end for receiving data is higher. SUMMARY

[0005] Embodiments of the present application provide a data encoding method and chip, a data decoding method and chip, and a display device, which can solve the technical problem of consuming too much additional overhead in the encoding and decoding process.

[0006] Embodiments of the present application provide a data encoding method, comprising:

[0007] Obtaining image data to be input to a display panel, the image data comprising a plurality of first sub-image data, the first sub-image data being data to be input to a row of pixel units of the display panel;

[0008] Adding a second bit data with L bit positions after each first bit data with K bit positions in the first sub-image data to obtain second sub-image data, K and L are both positive integers;

[0009] acquire address information of continuous bit data in the second sub-image data, the continuous bit data being data with M bit positions and having values of 0 or 1, and M being an integer greater than or equal to 2;

[0010] write address information of the first continuous bit data in the second sub-image data and value information of the first continuous bit data into predetermined bit positions of row configuration information of the second sub-image data, the value information indicating 0 or 1;

[0011] write address information of the N+1th continuous bit data in the second sub-image data and value information of the N+1th continuous bit data into bit positions where the Nth continuous bit data in the second sub-image data is located, and N being an integer greater than or equal to 1.

[0012] Correspondingly, an embodiment of the present application provides a data decoding method, comprising:

[0013] receive encoded image data to be input to a display panel, the encoded image data comprising a plurality of third sub-image data, and the third sub-image data being data to be input to a row of pixel units of the display panel;

[0014] read address information of the first continuous bit data in the third sub-image data and value information of the first continuous bit data from row configuration information of the third sub-image data, the continuous bit data being data with M bit positions and having values of 0 or 1, and M being an integer greater than or equal to 2;

[0015] write value information of the first continuous bit data into M bit positions corresponding to the address information of the first continuous bit data;

[0016] read address information of the N+1th continuous bit data and value information of the N+1th continuous bit data from bit positions where the Nth continuous bit data in the third sub-image data is located, and N being an integer greater than or equal to 1;

[0017] write value information of the N+1th continuous bit data into M bit positions corresponding to the address information of the N+1th continuous bit data, to obtain fourth sub-image data;

[0018] remove a second bit data with L bit positions after each first bit data with K bit positions in the fourth sub-image data, and K and L being positive integers.

[0019] Correspondingly, an embodiment of the present application provides an encoding chip, the encoding chip comprising program code, and the program code being used to execute the data encoding method provided by the embodiment of the present application.

[0020] Accordingly, an embodiment of the present application provides a decoding chip, the decoding chip comprising program code, the program code being used to execute the data decoding method provided by the embodiment of the present application.

[0021] Accordingly, an embodiment of the present application provides a display device, the display device comprising a display panel, an encoding chip and a decoding chip, the encoding chip being used to execute the data encoding method provided by the embodiment of the present application and output encoded image data to the decoding chip, the decoding chip being used to execute the data decoding method provided by the embodiment of the present application for the encoded image data and output decoded image data to the display panel, and the display panel being used to display an image according to the decoded image data output by the decoding chip.

[0022] In an embodiment of the present application, image data to be input to a display panel is obtained, the image data comprising a plurality of first sub-image data, the first sub-image data being data to be input to a row of pixel units of the display panel, a first bit data with K bits in each of the first sub-image data being followed by a second bit data with L bits to obtain second sub-image data, K and L each being a positive integer, address information of continuous bit data in the second sub-image data being obtained, the continuous bit data being data with a value of M bits being 0 or 1, M being an integer greater than or equal to 2, address information and value information of a first continuous bit data in the second sub-image data being written into predetermined bit positions of row configuration information of the second sub-image data, the value information indicating 0 or 1, and address information and value information of an N+1th continuous bit data in the second sub-image data being written into bit positions where an Nth continuous bit data in the second sub-image data is located, N being an integer greater than or equal to 1, so that the continuous bit data in the first sub-image data is converted into address information and value information based on the predetermined bit positions of the row configuration information, and not only direct current balance can be achieved, but also additional overheads consumed in encoding can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0023] FIG. 1 is a schematic diagram of a display device provided by an embodiment of the present application;

[0024] FIG. 2 is a flowchart of a data encoding method provided by an embodiment of the present application;

[0025] FIG. 3 is a schematic diagram of first bit data and second bit data provided by an embodiment of the present application;

[0026] FIG. 4 is another schematic diagram of second bit data provided by an embodiment of the present application;

[0027] FIG. 5 is a schematic diagram of continuous bit data provided by an embodiment of the present application;

[0028] FIG. 6 is a schematic diagram of block address information according to an embodiment of the present application;

[0029] FIG. 7 is a schematic diagram of data address information according to an embodiment of the present application;

[0030] FIG. 8 is a schematic diagram of row configuration information according to an embodiment of the present application;

[0031] FIG. 9 is a schematic diagram of header bits according to an embodiment of the present application;

[0032] FIG. 10 is a schematic diagram of encoded image data according to an embodiment of the present application;

[0033] FIG. 11 is a schematic diagram of meanings of various instructions according to an embodiment of the present application;

[0034] FIG. 12 is a flowchart of another data encoding method according to an embodiment of the present application;

[0035] FIG. 13 is a flowchart of a data decoding method according to an embodiment of the present application;

[0036] FIG. 14 is a schematic diagram of third sub-image data according to an embodiment of the present application;

[0037] FIG. 15 is a schematic diagram of an encoding chip according to an embodiment of the present application;

[0038] FIG. 16 is a schematic diagram of a decoding chip according to an embodiment of the present application.

[0039] Embodiments of the present application

[0040] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings. The described technical solutions are only used to explain and describe the ideas of the present application, and should not be regarded as limiting the protection scope of the present application.

[0041] In addition, "multiple" in the embodiments of the present application refers to two or more. "First" and "second" and the like in the embodiments of the present application are used to distinguish different technical features, and do not represent any order, quantity or importance.

[0042] The various embodiments provided by the present application are similar, and the features in different embodiments can be combined with each other.

[0043] The sequence of the following embodiment descriptions is not regarded as a limitation on the preferred sequence of the embodiments.

[0044] Embodiments of the present application provide a data encoding method and chip, a data decoding method and chip, and a display device. The display device can be integrated in a display device, which can be a television, a smartphone, a tablet computer, a notebook computer, a desktop computer, a smart speaker, a smart watch, etc., but is not limited thereto.

[0045] The display device provided by the embodiments of the present application can be as shown in FIG. 1. The display device includes a display panel, an encoding chip, and a decoding chip. The encoding chip is configured to perform the steps in the data encoding method embodiments and output encoded image data to the decoding chip. The decoding chip is configured to perform the steps in the data decoding method embodiments on the encoded image data and output decoded image data to the display panel. The display panel is configured to display an image according to the decoded image data output by the decoding chip.

[0046] In the embodiments of the present application, the data encoding method provided by the present application is described from the perspective of the display device, that is, from the perspective of the display device as the execution subject.

[0047] Referring to FIG. 2, the data encoding method can include:

[0048] S201, obtaining image data to be input to a display panel, the image data including a plurality of first sub-image data, the first sub-image data being data of a row of pixel units to be input to the display panel.

[0049] The display panel refers to a component for displaying an image, which can include a plurality of pixel units, each of which can emit light, display color, or reflect light to generate an image. The type of display panel can be set according to actual conditions. For example, the display panel can be a liquid crystal panel (LCD), an organic light-emitting diode panel (OLED), a mini light-emitting diode display panel (Mini-LED), or a micro light-emitting diode display panel (Micro-LED).

[0050] The pixel units included in the display panel can exist in the form of rows and / or columns. For example, the display panel can include a plurality of rows of pixel units and a plurality of columns of pixel units.

[0051] The image data is data including 0 and 1. The first sub-image data is data including 0 and / or 1. Since the first sub-image data is data to be input to a row of pixel units for display, the number of first sub-image data included in the image data can be set according to the number of rows of pixel units of the display panel. For example, if the display panel includes A rows of pixel units, the image data can include A first sub-image data.

[0052] S202, adding a second bit data with L bit positions after each first bit data with K bit positions in the first sub-image data to obtain second sub-image data, K and L are positive integers.

[0053] Wherein, K and L can be set according to actual situation. For example, K can be 540, 522, 504, 486, 468, 450, 432, 414, 396, 378, 360, 342, 324 or 306, and L can be 9 or 10.

[0054] For example, when K is 504 and L is 9, the first sub-image data can include 16 first bit data with 504 bit positions, wherein the first first bit data with 504 bit positions (1 st 504bit) and the second first bit data with 504 bit positions (2 nd 504bit) can be shown in 301 of FIG. 3, and the second sub-image data can be obtained by adding a second bit data with 9 bit positions after each first bit data with 504 bit positions in the first sub-image data, wherein the first data combination (1 st 504bit+9bit) and the second data combination (2 nd 504bit+9bit) in the second sub-image data can be shown in 302 of FIG. 3, wherein one data combination includes one first bit data and one second bit data, that is, one data combination includes 504bit+9bit data.

[0055] In some embodiments, the second bit data is data with L bit positions, and the values of the data are all 0 or all 1. For example, when L is 9, the second bit data can be 000000000 or 111111111.

[0056] In some embodiments, when the value of each bit position of the second bit data is the same as the value of the last bit position of the first bit data, there can be continuous bit data between the first bit data and the second bit data, and the number of continuous bit data is increased.

[0057] For example, when K is 504 and L is 9, as shown in 401 of FIG. 4, the value of the last bit of the first bit data with 504 bits is 0, and if the second bit data added after the first bit data with 504 bits is 000000000, since the values of the last 3 bits of the first bit data with 504 bits are all 0, the data of the last 3 bits of the first bit data with 504 bits and the data of the first 6 bits of the second bit data can form a continuous bit data, and the second bit data forms another continuous bit data, at this time, there are two continuous bit data, which can be shown as 402 of FIG. 4.

[0058] Therefore, in the embodiment of the present application, the second bit data is data with L bits, and the values of all bits of the second bit data are 0 or 1, and the value of each bit of the second bit data is different from the value of the last bit of the first bit data, so as to avoid the existence of continuous bit data between the first bit data and the second bit data, reduce the number of continuous bit data, and thus reduce the number of encoding.

[0059] For example, when K is 504 and L is 9, as shown in 301 of FIG. 3, the value of the last bit of the first bit data with 504 bits is 0, and the second bit data added after the first bit data with 504 bits is 111111111, since the value of the last bit of the first bit data with 504 bits is 0, there is no continuous bit data between the data of the last bit of the first bit data with 504 bits and the second bit data, and only the second bit data forms a continuous bit data, at this time, there is one continuous bit data, which can be shown as 302 of FIG. 3.

[0060] S203, acquiring address information of continuous bit data in the second sub-image data, the continuous bit data being data with M bits, and the values of all bits of the continuous bit data being 0 or 1, M being an integer greater than or equal to 2.

[0061] Wherein, M can be set according to actual conditions, for example, M can be 9 or 10. For example, when M is 9, if the continuous bit data is data with M bits, and the values of all bits of the continuous bit data are 0, the continuous bit data can be 000000000, and if the continuous bit data is data with M bits, and the values of all bits of the continuous bit data are 1, the continuous bit data can be 111111111.

[0062] The address information of the continuous bit data is used to indicate the address of the continuous bit data in the second sub-image data. Optionally, the address information can directly include the data address information of the continuous bit data in the second sub-image data, or the second sub-image data includes a plurality of data combinations, each data combination includes a first bit data and a second bit data, the data combination includes a plurality of data blocks (Block), the address information includes the block address information of the data block where the continuous bit data is located and the data address information of the continuous bit data in the data block, and the address of the continuous bit data in the second sub-image data is indicated by the block address information of the data block where the continuous bit data is located and the data address information of the continuous bit data in the data block. At this time, the address information of the continuous bit data in the second sub-image data includes:

[0063] Finding the continuous bit data from the data combination;

[0064] After finding the continuous bit data, outputting the block address information of the data block where the continuous bit data is located and the data address information of the continuous bit data in the data block.

[0065] The number of data combinations and the number of first bit data can be the same. For example, the first sub-image data includes 16 first bit data, and the second sub-image data can include 16 data combinations. The number of data blocks can be set according to actual conditions. For example, when the first bit data includes 504 bit data, one data combination can include 6 data blocks.

[0066] The block address information of the data block can be determined according to the position of the data block in the data combination. For example, as shown in FIG. 5, the first data block Block (84 bit) in the data combination has a block address information of 001, the second data block Block (84 bit) in the data combination has a block address information of 010, the third data block Block (84 bit) in the data combination has a block address information of 011, the fourth data block Block (84 bit) in the data combination has a block address information of 100, the fifth data block Block (84 bit) in the data combination has a block address information of 101, and the sixth data block Block (84 bit+9 bit) in the data combination has a block address information of 110. st Block (84 bit) represents the first data block in the data combination, and the block address information of the first data block is 001. nd Block (84 bit) represents the second data block in the data combination, and the block address information of the second data block is 010. th Block (84 bit+9 bit) represents the sixth data block in the data combination, and the block address information of the sixth data block is 110. The block address information of each data block can be as shown in FIG. 6.

[0067] The data address information in the data block can be set according to actual conditions. For example, the data address information can be as shown in FIG. 7, at this time, the data address information is increased by 1 every two bit positions, and the data address information includes 1-28.

[0068] It should be noted that the data address information of the M-bit data in the data block can refer to the start data address information of the M-bit data in the data block. For example, as shown in FIG. 5, the first continuous bit data is located in the bit position corresponding to the data address information 4-6 of the first data block, the block address information of the first continuous bit data is 001, and the data address information is 00100 (binary 00100 represents decimal 4).

[0069] The block address assignment method and the data address assignment method can be preset in the display device, and then M-bit data is read from the Pth bit of the Oth data combination data block, O and P are both integers greater than or equal to 1, if the M-bit data is continuous 0 or continuous 1, the block address information of the data block where the continuous bit data is located is determined according to the reading times and the block address assignment method, and the data address information of the continuous bit data in the data block is determined according to the reading times and the data address assignment method.

[0070] For example, a data combination includes 504bit+9bit data, and 9-bit data is read from the first bit of the first data combination (1 st 504bit+9bit), when the 9-bit data read for the fourth time is continuous bit data, the reading times is the fourth time, according to the fourth time and the block address assignment method, it is determined that the data block where the 9-bit data read for the fourth time is located is the first data block, and the address of the first data block is 001, that is, the block address information of the data block where the 9-bit data read for the fourth time is located is 001, according to the fourth time and the data address assignment method, it is determined that the data address information of the 9-bit data read for the fourth time is 00100.

[0071] In the embodiment of the present application, the second sub-image data includes a plurality of data combinations, each data combination includes a first bit data and a second bit data, the data combination includes a plurality of data blocks (Block), the address information includes the block address information of the data block where the continuous bit data is located and the data address information of the continuous bit data in the data block, the continuous bit data is searched from the data combination, and the block address information of the data block where the continuous bit data is located and the data address information of the continuous bit data in the data block are output after the continuous bit data is searched, so that the block address information of the data block where the continuous bit data is located and the data address information of the continuous bit data in the data block are used to indicate the address of the continuous bit data in the second sub-image data, which can reduce the bit positions used for writing the address information, compared with the mode in which the address information directly includes the data address information of the continuous bit data in the second sub-image data.

[0072] In some embodiments, the searching of the continuous bit data from the data combination comprises:

[0073] reading M-bit data from a Pth bit in an Oth data combination, O and P are integers greater than or equal to 1;

[0074] judging whether the M-bit data is continuous 0 or continuous 1;

[0075] outputting block address information of a data block in which the continuous bit data is located and data address information of the continuous bit data in the data block after the searching of the continuous bit data;

[0076] in a case that the M-bit data is continuous 0 or continuous 1, outputting the block address information of the data block in which the M-bit data is located and the data address information of the M-bit data in the data block;

[0077] after judging whether the M-bit data is continuous 0 or continuous 1, the searching of the continuous bit data from the data combination further comprises:

[0078] in a case that the M-bit data is not continuous 0 or continuous 1, increasing P by R and returning to execute the step of reading M-bit data from a Pth bit in an Oth data combination, R is an integer greater than or equal to 1.

[0079] wherein R can be set according to actual conditions, for example, R can be 1, 2, 3 or 4. In a case that the M-bit data is not continuous 0 or continuous 1, the M-bit data can be directly outputted and P can be increased by R.

[0080] For example, R is 3, as shown in FIG. 5, one data combination comprises 504bit+9bit data, when P is 1 and the data combination is the 1st data combination, 9-bit data is read from the 1st bit in the 1st data combination (1 st search) for the first time, the 9-bit data read for the first time is 011111111, which is not continuous bit data, 011111111 is outputted, P is increased by 3, at this time, P is 4, 9-bit data is read from the 4th bit in the 1st data combination (1 st search) for the second time, the 9-bit data read for the second time is 111111000, which is not continuous bit data, 111111000 is outputted, P is increased by 3, at this time, P is 7, 9-bit data is read from the 7th bit in the 1st data combination (1 st search) for the third time, the 9-bit data read for the third time is 000000111, which is not continuous bit data, 000000111 is outputted, P is increased by 3, at this time, P is 10, 9-bit data is read from the 10th bit in the 1st data combination (1 nd search) for the fourth time, the 9-bit data read for the fourth time is 111111110, which is not continuous bit data, 111111110 is outputted, P is increased by 3, at this time, P is 13, 9-bit data is read from the 13th bit in the 1st data combination (1st 504bit+9bit) from the 7th bit, the third time reads 9-bit data (3 rd search) is 111000000, 111000000 is not continuous bit data, outputs 111000000, and increases P by 3, at this time, P is 10, the fourth time reads 9-bit data from the 10th bit of the first data combination (1 st 504bit+9bit) from the 7th bit, the third time reads 9-bit data (3 th search) is 111000000, 111000000 is not continuous bit data, outputs 111000000, and increases P by 3, at this time, P is 10, the fourth time reads 9-bit data from the 10th bit of the first data combination (1

[0081] In some embodiments, in the case that the M-bit data is continuous 0 or continuous 1, after outputting the block address information of the data block where the M-bit data is located and the data address information of the M-bit data in the data block, the M-bit data is read from the Pth bit of the Oth data combination, further comprising:

[0082] determining whether the data address information of the M-bit data is predetermined data address information;

[0083] in the case that the data address information of the M-bit data is not the predetermined data address information, increasing P by R, and returning to execute the step of reading the M-bit data from the Pth bit of the Oth data combination;

[0084] in the case that the data address information of the M-bit data is the predetermined data address information, increasing O by 1 and setting P to 1, and returning to execute the step of reading the M-bit data from the Pth bit of the Oth data combination.

[0085] The predetermined data address information can be the address information of the second bit data in the second sub-image data, that is, the predetermined data address information indicates the address of the second bit data in the second sub-image data.

[0086] For example, as shown in FIG. 5, the predetermined data address information can be 29, expressed in binary as 11101, when the fourth time reads 9-bit data from the 10th bit of the first data combination (1 stWhen reading 9 bits of data starting from the 10th bit of (504 bits + 9 bits), the fourth read reaches (4). th The 9 bits of data in the search are 000000000, which are consecutive bits. The block address of the data block containing 000000000 is 001, and the data address of 000000000 within the block is 00100. Therefore, output 001 and 00100. Since 00100 is not 11101, increment P by 3. Now, P is 13. The fifth time, starting from the first data combination (1... st Starting from the 13th bit of (504 bits + 9 bits), read 9 bits of data, repeating this process until the Sth time, starting from the first data combination (1... st When reading 9 bits of data from (504bit + 9bit) as the second bit of data, if the 9 bits of data are consecutive bits and the data address information of the 9 bits of data is 11101, then the 9 bits of data are read starting from the first bit of the second data combination.

[0087] In some embodiments, when a portion of the found consecutive bit data is located in the Qth data block and another portion is located in the Q+1th data block, the block address information of the data block where the consecutive bit data is located is the block address information of the Qth data block, and the data address information of the consecutive bit data within the data block is the data address information of the consecutive bit data within the Qth data block.

[0088] For example, as shown in Figure 5, Q is 1, and the first three bits of the second consecutive bit data are located in the first data block (1 st In Block (84 bits), the last six bits of the second consecutive data bit are located in the second data block (2). nd In a Block (84 bits), the block address information of the second consecutive bit data is the address information of the first data block. The address information of the first data block is 001 in binary. The data address information of the second consecutive bit data in the first data block is 28. The data address information of the second consecutive bit data in the first data block is 11100 in binary.

[0089] S204. Write the address information and value information of the first consecutive bit data in the second sub-image data into the predetermined bit position of the row configuration information of the second sub-image data, where the value information indicates 0 or 1.

[0090] When the values of the M bit positions in the continuous bit data are all 0, the value information of the continuous bit data is 0; when the values of the M bit positions in the continuous bit data are all 1, the value information of the continuous bit data is 1.

[0091] The line configuration information of the second sub-image data indicates the line configuration information corresponding to the line pixel unit of the second sub-image data. Each line pixel unit corresponds to one line configuration information (Line config), and the line configuration information corresponding to one line pixel unit is used to set the related parameters of the line pixel in the displayed image, which can include the data format or resolution of the pixel, etc.

[0092] In the embodiments of the present application, a predetermined bit position is added in the line configuration information, so as to write the address information and value information of the first continuous bit data in the second sub-image data in the predetermined bit position.

[0093] Optionally, the line configuration information can further include 1TCMD bit position, 1TPWRC bit position, 4T register (Reserve) bit position, the 1TCMD bit position is used to write the CMD instruction, and the PWRC bit position is used to write the power control information.

[0094] In some embodiments, the predetermined bit position includes a header bit position, and the address information and value information of the first continuous bit data in the second sub-image data are written into the predetermined bit position of the line configuration information of the second sub-image data, including:

[0095] The address information and value information of the first continuous bit data in the second sub-image data are written into the header bit position of the line configuration information of the second sub-image data.

[0096] The header bit position can also be referred to as a Header bit position. For example, when the line configuration information includes 1TCMD bit position, 1TPWRC bit position, 1Theader and 4T register (Reserve) bit position, the line configuration information can be as shown in FIG. 8.

[0097] In some embodiments, the header bit position includes a first bit combination, a second bit combination located after the first bit combination, and a third bit combination located after the second bit combination, and the address information and value information of the first continuous bit data in the second sub-image data are written into the header bit position of the line configuration information of the second sub-image data, including:

[0098] The block address information of the first continuous bit data in the second sub-image data is written into the first bit combination;

[0099] The value information of the first continuous bit data in the second sub-image data is written into the second bit combination;

[0100] write the data address information of the first continuous bit data in the second sub-image data into the third bit combination.

[0101] The number of bit positions included in the first bit combination, the number of bit positions included in the second bit combination, and the number of bit positions included in the third bit combination can be set according to actual conditions. For example, the first bit combination includes three bit positions, the second bit combination includes one bit position, and the third bit combination includes five bit positions, as shown in FIG. 9.

[0102] In the embodiments of the present application, the address information and the value information of the first continuous bit data in the second sub-image data are written into the header bit positions of the row configuration information of the second sub-image data. For example, as shown in FIG. 5, the first continuous bit data of the first data combination (1 st 504bit+9bit) in the second sub-image data is located in the first data block, the block address information of which is represented in binary as 001, the first continuous bit data includes data whose values are all 0, the data address information of the first continuous bit data is 4, which is represented in binary as 00100, therefore, 001 is written into the first bit combination of the header bit positions, 0 is written into the second bit combination, and 00100 is written into the third bit combination.

[0103] S205, write the address information and the value information of the (N+1)th continuous bit data in the second sub-image data into the bit positions where the Nth continuous bit data in the second sub-image data is located, N being an integer greater than or equal to 1.

[0104] For example, when N is equal to 1, the address information and the value information of the second continuous bit data are written into the bit positions where the second continuous bit data is located, when N is equal to 2, the address information and the value information of the third continuous bit data are written into the bit positions where the second continuous bit data is located, when N is equal to 3, the address information and the value information of the fourth continuous bit data are written into the bit positions where the third continuous bit data is located, and so on, until the address information and the value information of all the continuous bit data in the second sub-image data are written, the step is stopped.

[0105] In some embodiments, the address information and the value information of the first continuous bit data in the second sub-image data are written into predetermined bit positions of the row configuration information of the second sub-image data, including:

[0106] write the address information and the value information of the first continuous bit data of the first data combination in the second sub-image data into predetermined bit positions of the row configuration information of the second sub-image data;

[0107] writing address information and value information of the (N+1)th continuous bit data of the first data combination in the second sub-image data into bit positions where the Nth continuous bit data of the first data combination in the second sub-image data is located;

[0108] writing address information and value information of the (N+1)th continuous bit data of the first data combination in the second sub-image data into bit positions where the Nth continuous bit data of the first data combination in the second sub-image data is located;

[0109] writing address information and value information of the first continuous bit data of the first data combination in the second sub-image data into predetermined bit positions of line configuration information of the second sub-image data, further comprising:

[0110] writing address information and value information of the first continuous bit data of the (O+1)th data combination in the second sub-image data into bit positions where the second bit data of the Oth data combination in the second sub-image data is located;

[0111] writing address information and value information of the (N+1)th continuous bit data of the (O+1)th data combination in the second sub-image data into bit positions where the Nth continuous bit data of the (O+1)th data combination in the second sub-image data is located;

[0112] writing address information and value information of the (N+1)th continuous bit data of the (O+1)th data combination in the second sub-image data into bit positions where the Nth continuous bit data of the (O+1)th data combination in the second sub-image data is located.

[0113] wherein, since the second bit data is continuous bit data, the bit positions where the second bit data of the Oth data combination in the second sub-image data is located are the bit positions where the last continuous bit data of the Oth data combination in the second sub-image data is located.

[0114] writing address information and value information of the first continuous bit data of the (O+1)th data combination in the second sub-image data into bit positions where the second bit data of the Oth data combination in the second sub-image data is located, for example, the second sub-image data includes six data combinations, when O is 1, address information and value information of the first continuous bit data of the 2th data combination are written into bit positions where the second bit data of the 1th data combination is located, when O is 2, address information and value information of the first continuous bit data of the 3th data combination are written into bit positions where the second bit data of the 2th data combination is located, when O is 3, address information and value information of the first continuous bit data of the 4th data combination are written into bit positions where the second bit data of the 3th data combination is located, and when O is 5, address information and value information of the first continuous bit data of the 6th data combination are written into bit positions where the second bit data of the 5th data combination is located.

[0115] Next, based on Figure 5, the process of writing the address information and value information of the consecutive bit data in the first data combination and the process of writing the address information and value information of the first consecutive bit data in the second data combination will be explained.

[0116] As shown in Figure 5, the predetermined bit bits are the header bit bits. The process of writing the address information and value information of the consecutive bit data in the first data combination is as follows:

[0117] The first data combination (1) st The first consecutive bit data (504 bits + 9 bits) is located in the first data block. Its block address information is represented as 001 in binary. The first consecutive bit data includes data with all values ​​of 0. The data address information of the first consecutive bit data is 4, which is represented as 00100 in binary. Therefore, 001 is written on the first bit combination of the header bits, 0 is written on the second bit combination, and 00100 is written on the third bit combination.

[0118] When N equals 1, the first data combination (1 st The block address information of the second consecutive bit data (504 bits + 9 bits) is the address information of the first data block. Represented in binary, the address information of the first data block is 001. The data address information of the second consecutive bit data within the first data block is 28. Represented in binary, the data address information of the second consecutive bit data within the first data block is 11100. The second consecutive bit data includes data where all values ​​are 0. Therefore, 001, 0, and 11100 are written into the bits of the first consecutive bit data. When N equals 2, the first data combination (1... st The block address information of the third consecutive bit data (504 bits + 9 bits) (the third consecutive bit data is the second bit data in the first data combination) is the address information of the sixth data block, which is represented as 110 in binary. The data address information of the third consecutive bit data in the sixth data block is 29, which is represented as 11101 in binary. The third consecutive bit data includes data with values ​​of 1. Therefore, 110, 1 and 11101 are written in the bits of the second consecutive bit data.

[0119] The process of writing the address and value information of the first consecutive bit data in the second data combination is as follows:

[0120] When N equals 1, the second data combination (2 ndThe first continuous bit data of the 504 bit+9 bit is located in the first data block, the block address information of the first continuous bit data is 001 in binary, the first continuous bit data includes data with value 0, the data address information of the first continuous bit data is 4, which is 00100 in binary, and therefore, 001, 0 and 00100 are written in the bit position of the fifth continuous bit data of the first data combination.

[0121] It should be noted that, in the process of writing the address information and value information of the (N+1)th continuous bit data of the (O+1)th data combination in the second sub-image data into the bit position of the Nth continuous bit data of the (O+1)th data combination in the second sub-image data, when the (N+1)th continuous bit data of the (O+1)th data combination does not exist, O is increased by 1 and P is set to 1, and the process of writing the address information and value information of the first continuous bit data of the (O+1)th data combination in the second sub-image data into the bit position of the second bit data of the Oth data combination in the second sub-image data is executed.

[0122] In the process of increasing O by 1 and setting P to 1, and returning to execute the process of writing the address information and value information of the first continuous bit data of the (O+1)th data combination in the second sub-image data into the bit position of the second bit data of the Oth data combination in the second sub-image data, if the (O+1)th data combination does not exist continuous bit data, the step of writing the address information and value information of the first continuous bit data of the (O+1)th data combination in the second sub-image data into the bit position of the second bit data of the Oth data combination in the second sub-image data is stopped.

[0123] In some embodiments, when the (O+1)th data combination does not exist continuous bit data, the encoding method provided by the embodiments of the present application further includes:

[0124] In the case that the (O+1)th data combination in the second sub-image data does not exist continuous bit data, predetermined address information is written in the bit position of the second bit data of the Oth data combination in the second sub-image data.

[0125] The predetermined address information is preset address information, which is used to indicate that the encoding of the second sub-image data is completed. The predetermined address information can be set according to actual conditions, for example, the predetermined address information can be 000000001 or 111000000.

[0126] For example, the predetermined address information is 000000001, O is 15, and the (O+1)th data combination does not exist continuous bit data, and therefore, 000000001 is written in the bit position of the second bit data of the 15th data combination.

[0127] It should be understood that, after the address information and the value information of the first continuous bit data in the second sub-image data are written into the predetermined bit positions of the row configuration information of the second sub-image data, and the address information and the value information of the N+1th continuous bit data in the second sub-image data are written into the bit positions in which the Nth continuous bit data in the second sub-image data is located, the third sub-image data can be obtained, and then the encoded image data corresponding to the image data is generated according to the third sub-image data. The encoded image data can be, for example, as shown in FIG. 10. The RGB data shown in FIG. 10 is the third sub-image data, and the meanings of other symbols shown in FIG. 10 can be referred to FIG. 11.

[0128] In the embodiment of the present application, a second bit data with L bit positions is added after each first bit data with K bit positions in the first sub-image data to obtain the second sub-image data, the address information of continuous bit data in the second sub-image data is obtained, the continuous bit data is data with M bit positions and the values of which are all 0 or all 1, and M is an integer greater than or equal to 2; the address information and the value information of the first continuous bit data in the second sub-image data are written into the predetermined bit positions of the row configuration information of the second sub-image data, and the address information and the value information of the N+1th continuous bit data in the second sub-image data are written into the bit positions in which the Nth continuous bit data in the second sub-image data is located, so that there is no continuous bit data in the third sub-image data, direct current balance is achieved, the additional overhead (the additional overhead is 11.1% in the 8b / 9b encoding technology, and the additional overhead is 1.79% in the embodiment of the present application when K is 504 and L is 9) can be reduced, and since the row configuration information can be compatible with the original CSPI protocol, the original instructions in the CSPI protocol can not be updated, and the operability of the CSPI protocol is improved.

[0129] The encoding method provided by the embodiment of the present application is further described below with reference to FIG. 12.

[0130] The display device obtains image data to be input to a display panel, and the image data includes a plurality of first sub-image data, and the first sub-image data is data of a row of pixel units to be input to the display panel.

[0131] The display device adds a second bit data with L bit positions after each first bit data with K bit positions in the first sub-image data to obtain the second sub-image data, K and L are both positive integers, the second bit data is data with L bit positions and the values of which are all 0 or all 1, and the value of each bit position of the second bit data is different from the value of the last bit position of the first bit data.

[0132] The display device reads data of M bits from a Pth bit in an Oth data group, O and P are integers equal to or greater than 1, and judges whether the data of M bits is continuous 0 or continuous 1.

[0133] In a case where the data of M bits is not continuous 0 or continuous 1, the display device increases P by R, and returns to the step of reading data of M bits from a Pth bit in an Oth data group, R is an integer equal to or greater than 1.

[0134] In a case where the data of M bits is continuous 0 or continuous 1, the display device outputs block address information of a data block in which the data of M bits is located and data address information of the data of M bits in the data block.

[0135] The address information and value information of the first continuous bit data of the first data group are written in a header bit of the line configuration information of the second sub-image data, the address information and value information of an N+1th continuous bit data of the first data group are written in a bit in which an Nth continuous bit data of the first data group is located, the address information and value information of the first continuous bit data of an O+1th data group in the second sub-image data are written in a bit in which a second bit data of an Oth data group in the second sub-image data is located, and the address information and value information of an N+1th continuous bit data of the O+1th data group in the second sub-image data are written in a bit in which an Nth continuous bit data of the O+1th data group is located.

[0136] In a case where there is no continuous bit data in the O+1th data group in the second sub-image data, predetermined address information is written in a bit in which the second bit data of the Oth data group in the second sub-image data is located.

[0137] The display device judges whether the data address information of the data of M bits is predetermined data address information.

[0138] In a case where the data address information of the data of M bits is not predetermined data address information, the display device increases P by R, and returns to the step of reading data of M bits from a Pth bit in an Oth data group.

[0139] In a case where the data address information of the data of M bits is predetermined data address information, the display device increases O by 1 and sets P to 1, and returns to the step of reading data of M bits from a Pth bit in an Oth data group.

[0140] In the process of returning to the step of reading M bits of data from the Pth bit in the Oth data combination, if the Oth data combination cannot be read, it indicates that the encoding is completed, then the step of reading M bits of data from the Pth bit in the Oth data combination is stopped, or in the case that the data address information of the M bits of data is predetermined data address information, it is judged whether the Oth data combination is a predetermined data combination, if the Oth data combination is the predetermined data combination, it indicates that the encoding is completed, then the step of reading M bits of data from the Pth bit in the Oth data combination is performed (for example, the second sub-image data includes 16 data combinations, and the predetermined data combination can be the 16th data combination).

[0141] As can be seen from the above, in the embodiments of the present application, image data to be input to a display panel is obtained, the image data includes a plurality of first sub-image data, the first sub-image data is data to be input to a row of pixel units of the display panel, one first bit data with K bits in each of the first sub-image data is followed by one second bit data with L bits to obtain second sub-image data, K and L are both positive integers, address information of continuous bit data in the second sub-image data is obtained, the continuous bit data is data with M bits, the values of which are all 0 or all 1, M is an integer greater than or equal to 2, the address information and value information of the first continuous bit data in the second sub-image data are written into predetermined bit positions of row configuration information of the second sub-image data, the value information indicates 0 or 1, the address information and value information of the N+1th continuous bit data in the second sub-image data are written into bit positions where the Nth continuous bit data is located, N is an integer greater than or equal to 1, the first sub-image data is converted into address information and value information based on the predetermined bit positions of the row configuration information, so that not only direct current balance can be achieved, but also the additional overhead consumed in encoding can be reduced.

[0142] Next, the data decoding method provided by the embodiments of the present application will be described below with reference to FIG. 13.

[0143] S1301, receiving encoded image data to be input to a display panel, the encoded image data including a plurality of third sub-image data, the third sub-image data being data to be input to a row of pixel units of the display panel.

[0144] The third sub-image data is data obtained after the address information and value information of the first continuous bit data in the second sub-image data are written into predetermined bit positions of row configuration information of the second sub-image data, and the address information and value information of the N+1th continuous bit data in the second sub-image data are written into bit positions where the Nth continuous bit data is located.

[0145] For example, the second sub-image data can include 16 data combinations, the first data combination can be obtained as shown in FIG. 14 after the address information and the value information of the first continuous bit data in the second sub-image data are written into the predetermined bit positions of the row configuration information of the second sub-image data, and the address information and the value information of the N+1th continuous bit data in the second sub-image data are written into the bit positions where the Nth continuous bit data in the second sub-image data is located.

[0146] S1302, read the address information and the value information of the first continuous bit data in the third sub-image data from the row configuration information of the third sub-image data, the continuous bit data is data whose value is 0 or 1, and M is an integer greater than or equal to 2.

[0147] In some embodiments, the address information and the value information of the first continuous bit data in the third sub-image data are read from the predetermined bit positions of the row configuration information of the third sub-image data, and the predetermined bit positions are the header bit positions.

[0148] In some embodiments, the address information includes the block address information of the data block where the continuous bit data is located and the data address information of the continuous bit data in the data block, the data address information of the continuous bit data in the data block indicates the starting data address information of the continuous bit data in the data block, the header bit positions include a first bit combination, a second bit combination located after the first bit combination, and a third bit combination located after the second bit combination, and the process of reading the address information and the value information of the first continuous bit data in the third sub-image data from the row configuration information of the third sub-image data can be:

[0149] read the block address information of the first continuous bit data from the first bit combination;

[0150] read the value information of the first continuous bit data from the second bit combination;

[0151] read the data address information of the first continuous bit data from the third bit combination.

[0152] The data address information of the first continuous bit data indicates the starting data address information of the first continuous bit data.

[0153] S1303, write the value information of the first continuous bit data in the M bit positions corresponding to the address information of the first continuous bit data.

[0154] S1304, reading address information and value information of the (N+1)th continuous bit data from a bit position where the Nth continuous bit data in the third sub-image data is located, N being an integer equal to or greater than 1.

[0155] For example, when N is 1, the address information and the value information of the 2nd continuous bit data are read from a bit position where the 1st continuous bit data is located, and when N is 2, the address information and the value information of the 3rd continuous bit data are read from a bit position where the 2nd continuous bit data is located.

[0156] In some embodiments, the third sub-image data includes a plurality of data combinations, each data combination including a plurality of data blocks, and the address information includes block address information of a data block where the continuous bit data is located and data address information of the continuous bit data in the data block.

[0157] In some embodiments, the process of reading the address information and the value information of the (N+1)th continuous bit data from a bit position where the Nth continuous bit data in the third sub-image data is located can be:

[0158] reading data of M bit positions from a Pth bit position in an Oth data combination in the third sub-image data, O and P both being integers greater than or equal to 1;

[0159] determining whether address information where the M bit positions are located is address information of the Nth continuous bit data;

[0160] in a case where the address information where the M bit positions are located is the address information of the Nth continuous bit data, outputting the data of the M bit positions as the address information and the value information of the (N+1)th continuous bit data.

[0161] At this time, after determining whether the address information where the M bit positions are located is the address information of the Nth continuous bit data, reading the data of the M bit positions from the Pth bit position in the Oth data combination in the third sub-image data further includes:

[0162] in a case where the address information where the M bit positions are located is not the address information of the Nth continuous bit data, increasing P by R, and returning to execute the step of reading the data of the M bit positions from the Pth bit position in the Oth data combination in the third sub-image data, R being an integer greater than or equal to 1.

[0163] wherein the address information where the M bit positions are located indicates an address where the M bit positions are located. When the address information includes block address information and data address information, the data address information where the M bit positions are located is start data address information where the M bit positions are located.

[0164] For example, as shown in Fig. 14, the address information includes block address information and data address information, the predetermined bit is the header bit, M is 9, R is 3, O is 1, the address information and the value information of the first continuous bit data read from the row configuration information is 001000100, wherein the block address information is 001, the data address information is 00100, when P is 1 and N is 1, the first 9-bit data is read from the first bit of the first data combination (1 st 504bit+9bit), the first 9-bit data read is (1 st search) 011111111, the block address information of the bit of 011111111 is 001, the data address information is 00001, 00001 is not the data address information 00100 of the first continuous bit data, therefore, P is increased by 3, at this time, P is 4, the second 9-bit data is read from the fourth bit of the first data combination (1 st 504bit+9bit), the second 9-bit data read is (2 nd search) 111111001, the block address information of the bit of 111111001 is 001, the data address information is 00010, 00010 is not the data address information 00100 of the first continuous bit data, therefore, P is increased by 3, at this time, P is 7, the third 9-bit data is read from the seventh bit of the first data combination (1 st 504bit+9bit), the third 9-bit data read is (3 rd search) 111001011, the block address information of the bit of 111001011 is 001, the data address information is 00011, 00011 is not the data address information 00100 of the first continuous bit data, therefore, P is increased by 3, at this time, P is 10, the fourth 9-bit data is read from the tenth bit of the first data combination (1 st 504bit+9bit), the fourth 9-bit data read is (4 th search) 001011100, the block address information of the bit of 001011100 is 001, the data address information is 00100, 00100 is the data address information 00100 of the first continuous bit data, therefore, 001011100 is the address information and the value information of the second continuous bit data.

[0165] In some embodiments, in the case that the address information where the M bits are located is the address information of the Nth consecutive bit data, the data of the M bits is outputted as the address information and the value information of the N+1th consecutive bit data, comprising:

[0166] In the case that the address information where the M bits are located is the address information of the Nth consecutive bit data, judging whether the data address information where the M bits are located is the predetermined data address information;

[0167] In the case that the data address information where the M bits are located is not the predetermined data address information, outputting the data of the M bits as the address information and the value information of the N+1th consecutive bit data, increasing R by P, and returning to execute the step of reading the data of the M bits from the Pth bit in the Oth data combination in the third sub-image data.

[0168] At this time, after judging whether the data address information where the M bits are located is the predetermined data address information, reading the data of the M bits from the Pth bit in the Oth data combination in the third sub-image data, further comprising:

[0169] In the case that the data address information where the M bits are located is the predetermined data address information, increasing O by 1 and setting P as 1, and returning to execute the step of reading the data of the M bits from the Pth bit in the Oth data combination in the third sub-image data.

[0170] For example, as shown in FIG. 14, the predetermined data address information can be 29, which is expressed in binary as 11101, when the 9-bit data read for the fourth time (4 th search) is 001011100, the block address information where the bits of 001011100 are located is 001, the data address information is 00100, 00100 is the data address information 00100 of the first consecutive bit data and is not the predetermined data address information 11101, thus, 001011100 is the address information and the value information of the 2nd consecutive bit data, P is increased by 3, at this time, P is 13, the 9-bit data is read from the 13th bit in the 1st data combination (1 st 504bit+9bit) for the fifth time, and the process is cycled, when the 9-bit data read from the 1st data combination (1 st 504bit+9bit) for the Sth time is 001000100, the data address information where the bits of 001000100 are located is the predetermined data address information 11101, thus, the 9-bit data is read from the 1st bit in the 2nd data combination.

[0171] In some embodiments, in the case that the data address information where the M bits are located is predetermined data address information, O is increased by 1 and P is set to 1, and the step of reading the data of the M bits from the Pth bit in the Oth data group in the third sub-image data is executed again.

[0172] In the case that the data address information where the M bits are located is predetermined data address information, the data of the M bits is outputted as the address information and the value information of the first continuous bit data in the O+1th data group, and O is increased by 1 and P is set to 1, and the step of reading the data of the M bits from the Pth bit in the Oth data group in the third sub-image data is executed again.

[0173] For example, as shown in FIG. 14, when the data of 9 bits read from the 1st data group (1 st 504bit+9bit) in the Sth time is 001000100, the data address information where the bits of 001000100 are located is predetermined data address information 11101, thus, 001000100 is outputted as the address information and the value information of the first continuous bit data in the 2nd data group, and the data of 9 bits is read from the 1st bit in the 2nd data group.

[0174] In some embodiments, in the case that the data address information where the M bits are located is predetermined data address information, the data of the M bits is outputted as the address information and the value information of the first continuous bit data in the O+1th data group, including:

[0175] In the case that the data address information where the M bits are located is predetermined data address information, it is judged whether the data of the M bits is predetermined address information or not.

[0176] In the case that the data of the M bits is not predetermined address information, the data of the M bits is outputted as the address information and the value information of the first continuous bit data in the O+1th data group.

[0177] At this time, after judging whether the data of the M bits is predetermined address information or not, the data of the M bits is read from the Pth bit in the Oth data group in the third sub-image data, further including:

[0178] In the case that the data of the M bits is predetermined address information, the step of reading the data of the M bits from the Pth bit in the Oth data group in the third sub-image data is stopped.

[0179] S1305, write the value information of the N+1th continuous bit data on the M bit positions corresponding to the address information of the N+1th continuous bit data, to obtain the fourth sub-image data.

[0180] When the address information includes the block address information and the data address information, the data address information of the continuous bit data indicates the starting data address information of the continuous bit data, and after reading the data address information of the continuous bit data, it indicates that the values of the M bit positions starting from the bit position corresponding to the data address information are all the value information of the continuous bit data. For example, the address information and the value information of the first continuous bit data read from the row configuration information are 001000100, wherein the block address information is 001, the data address information is 00100, 00100 indicates decimal 4, and at this time, it indicates that the values of the 9 bit positions starting from the bit position corresponding to the fourth data address information of the first data block are all 0, so 0 is written on the bit positions corresponding to the fourth to sixth data address information of the first data block.

[0181] S1306, remove a second bit data with L bit positions after each first bit data with K bit positions in the fourth sub-image data, K and L are positive integers.

[0182] The display device can obtain the first sub-image data after removing a second bit data with L bit positions after each first bit data with K bit positions in the fourth sub-image data.

[0183] In the embodiment of the present application, encoded image data to be input to a display panel is received, the encoded image data comprising a plurality of third sub-image data, the third sub-image data being data to be input to a row of pixel units of the display panel, address information and value information of a first continuous bit data in the third sub-image data are read from row configuration information of the third sub-image data, the continuous bit data being data with M bit positions having values of 0 or 1, M being an integer greater than or equal to 2, the value information of the first continuous bit data is written in a bit position corresponding to the address information of the first continuous bit data, address information and value information of an (N+1)th continuous bit data are read from a bit position where an Nth continuous bit data in the third sub-image data is located, N being an integer equal to or greater than 1, the value information of the (N+1)th continuous bit data is written in a bit position corresponding to the address information of the (N+1)th continuous bit data, to obtain fourth sub-image data, a second bit data with L bit positions is removed after each first bit data with K bit positions in the fourth sub-image data, K and L are both positive integers. Since the third sub-image data does not include continuous bit data, direct current balance can be achieved, and since the row configuration information comprises the address information and the value information of the first continuous bit data and the data in the bit position where the Nth continuous bit data is located is the address information and the value information of the (N+1)th continuous bit data, additional overheads consumed in decoding can be reduced.

[0184] The term explanation, the specific implementation manner and the corresponding beneficial effects in the embodiment can be referred to the above-mentioned data encoding method embodiment.

[0185] In order to better implement the data encoding method provided by the embodiment of the present application, the embodiment of the present application further provides an encoding chip based on the above-mentioned data encoding method. The encoding chip comprises program code, and the program code can be used to execute the above-mentioned data encoding method. The meanings of the terms are the same as those in the above-mentioned data encoding method, and the specific implementation details can be referred to the description in the method embodiment.

[0186] For example, the encoding chip is shown in FIG. 15. The program code in the encoding chip can be located in the modules shown in FIG. 15. At this time, the encoding chip can comprise:

[0187] The data acquisition module 1501 is configured to acquire image data to be input to a display panel, the image data comprising a plurality of first sub-image data, the first sub-image data being data to be input to a row of pixel units of the display panel.

[0188] The data addition module 1502 is configured to add a second bit data with L bit positions after each first bit data with K bit positions in the first sub-image data to obtain second sub-image data, K and L being both positive integers.

[0189] The information obtaining module 1503 is configured to obtain address information of continuous bit data in the second sub-image data, the continuous bit data being data with M bit positions all being 0 or all being 1, M being an integer greater than or equal to 2.

[0190] The first information writing module 1504 is configured to write address information and value information of a first continuous bit data in the second sub-image data into predetermined bit positions of row configuration information of the second sub-image data, the value information indicating 0 or 1; and write address information and value information of an N+1th continuous bit data in the second sub-image data into bit positions where an Nth continuous bit data in the second sub-image data is located, N being an integer greater than or equal to 1.

[0191] In some embodiments, the second sub-image data includes a plurality of data combinations, each data combination including a first bit data and a second bit data, the data combination including a plurality of data blocks, and the address information including block address information of a data block where the continuous bit data is located and data address information of the continuous bit data in the data block, and the information obtaining module 1503 is specifically configured to perform:

[0192] searching for the continuous bit data from the data combination;

[0193] outputting, after searching for the continuous bit data, the block address information of the data block where the continuous bit data is located and the data address information of the continuous bit data in the data block.

[0194] In some embodiments, the information obtaining module 1503 is specifically configured to perform:

[0195] read M bit positions of data from a Pth bit position in an Oth data combination, O and P both being integers greater than or equal to 1;

[0196] determine whether the M bit positions of data are continuous 0 or continuous 1;

[0197] in a case where the M bit positions of data are continuous 0 or continuous 1, output block address information of a data block where the M bit positions of data are located and data address information of the M bit positions of data in the data block;

[0198] in a case where the M bit positions of data are not continuous 0 or continuous 1, increase P by R, and return to perform the step of reading M bit positions of data from a Pth bit position in an Oth data combination, R being an integer greater than or equal to 1.

[0199] In some embodiments, the information obtaining module 1503 is specifically configured to perform:

[0200] determining whether the data address information of the M-bit data is predetermined data address information;

[0201] in a case where the data address information of the M-bit data is not the predetermined data address information, increasing P by R, and returning to perform the step of reading the M-bit data starting from the Pth bit in the Oth data combination;

[0202] in a case where the data address information of the M-bit data is the predetermined data address information, increasing O by 1 and setting P as 1, and returning to perform the step of reading the M-bit data starting from the Pth bit in the Oth data combination.

[0203] In some embodiments, in a case where the part of the found continuous bit data is located in the Qth data block and the other part is located in the Q+1th data block, the block address information of the data block where the continuous bit data is located is the block address information of the Qth data block, the data address information of the continuous bit data in the data block is the data address information of the continuous bit data in the Qth data block, and Q is an integer equal to or greater than 1.

[0204] In some embodiments, the predetermined bit position includes a header bit position, and the information writing module 1504 is specifically configured to perform:

[0205] write the address information and the value information of the first continuous bit data in the second sub-image data into the header bit position of the row configuration information of the second sub-image data.

[0206] In some embodiments, the header bit position includes a first bit combination, a second bit combination located after the first bit combination, and a third bit combination located after the second bit combination, and the information writing module 1504 is specifically configured to perform:

[0207] write the block address information of the first continuous bit data in the second sub-image data into the first bit combination;

[0208] write the value information of the first continuous bit data in the second sub-image data into the second bit combination;

[0209] write the data address information of the first continuous bit data in the second sub-image data into the third bit combination.

[0210] In some embodiments, the second bit data is data with L-bit positions, the values of which are all 0 or all 1, and the value of each bit position of the second bit data is different from the value of the last bit position of the first bit data.

[0211] In some embodiments, the first information writing module 1504 is specifically configured to perform:

[0212] write address information and value information of the first continuous bit data of the first data combination in the second sub-image data into a predetermined bit of the line configuration information of the second sub-image data;

[0213] write address information and value information of the N+1th continuous bit data of the O+1th data combination in the second sub-image data into a bit where the Nth continuous bit data of the O+1th data combination is located.

[0214] write address information and value information of the first continuous bit data of the O+1th data combination in the second sub-image data into a bit where the second bit data of the Oth data combination in the second sub-image data is located.

[0215] write address information and value information of the N+1th continuous bit data of the O+1th data combination in the second sub-image data into a bit where the Nth continuous bit data of the O+1th data combination is located.

[0216] In some embodiments, the first information writing module 1504 is further configured to perform:

[0217] in the case that there is no continuous bit data in the O+1th data combination in the second sub-image data, write predetermined address information into a bit where the second bit data of the Oth data combination in the second sub-image data is located.

[0218] In implementation, the above modules can be implemented as independent entities, or can be combined in any manner, implemented as the same or several entities, and the specific implementation manners of the above modules and the corresponding beneficial effects can be referred to the method embodiments.

[0219] To better implement the data decoding method provided in the embodiments of the present application, the embodiments of the present application further provide a decoding chip based on the above data decoding method, which comprises program codes, and the program codes can be used to execute the above data decoding method, wherein the meanings of the terms are the same as those in the above data decoding method, and the specific implementation details can be referred to the description in the method embodiments.

[0220] For example, the decoding chip is shown in FIG. 16, and the program codes in the decoding chip can be located in the modules shown in FIG. 16, and at this time, the decoding chip can comprise:

[0221] a data receiving module 1601 configured to receive encoded image data to be input to a display panel, the encoded image data comprising a plurality of third sub-image data, the third sub-image data being data of a row of pixel units to be input to the display panel.

[0222] The information reading module 1602 is configured to read address information and value information of a first continuous bit data in the third sub-image data from row configuration information of the third sub-image data, the continuous bit data is data with M bit positions and the value of the data is 0 or 1, M is an integer greater than or equal to 2, and the address information and the value information of an (N+1)th continuous bit data are read from a bit position where the Nth continuous bit data is located in the third sub-image data, N is an integer equal to or greater than 1.

[0223] The second information writing module 1603 is configured to write the value information of the first continuous bit data on the M bit positions corresponding to the address information of the first continuous bit data, and write the value information of the (N+1)th continuous bit data on the M bit positions corresponding to the address information of the (N+1)th continuous bit data, to obtain fourth sub-image data.

[0224] The data removing module 1604 is configured to remove a second bit data with L bit positions after each first bit data with K bit positions in the fourth sub-image data, K and L are positive integers.

[0225] In specific implementation, the above modules can be implemented as independent entities, or can be combined as the same or several entities, and the specific implementation and corresponding advantages of the above modules can be referred to the method embodiments.

[0226] Those skilled in the art can understand that the above program code can be stored in a computer readable storage medium and loaded and executed by a processor.

[0227] To this end, an embodiment of the present application provides a computer readable storage medium, which stores program code capable of being loaded by a processor to execute steps in any data encoding method or steps in any data decoding method provided by the embodiments of the present application. For example, the program code can execute the following steps:

[0228] obtaining image data to be input to a display panel, the image data comprising a plurality of first sub-image data, the first sub-image data being data of a row of pixel units to be input to the display panel;

[0229] adding a second bit data with L bit positions after each first bit data with K bit positions in the first sub-image data to obtain second sub-image data, K and L being positive integers;

[0230] obtaining address information of continuous bit data in the second sub-image data, the continuous bit data being data with M bit positions and the value of the data being 0 or 1, M being an integer greater than or equal to 2;

[0231] write address information and value information of the first continuous bit data in the second sub-image data into predetermined bit positions of the line configuration information of the second sub-image data, the value information indicating 0 or 1;

[0232] write address information and value information of the N+1th continuous bit data in the second sub-image data into bit positions where the Nth continuous bit data in the second sub-image data is located, N being an integer greater than or equal to 1.

[0233] The specific implementation and corresponding beneficial effects of each operation above can be found in the foregoing embodiments.

[0234] The computer readable storage medium can include a read only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0235] Due to the program code stored in the computer readable storage medium, the steps of any one of the data encoding methods or the steps of any one of the data decoding methods provided by the embodiments of the present application can be executed, thus the beneficial effects of any one of the data encoding methods or the data decoding methods provided by the embodiments of the present application can be achieved, which are described in detail in the foregoing embodiments.

[0236] The data encoding method and chip, the data decoding method and chip, and the display device provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples; the foregoing embodiment descriptions are only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, the specific implementation manner and application range can be changed according to the idea of the present application, and the foregoing description should not be understood as a limitation of the present application.

Claims

1. A data encoding method, wherein, The method comprises the following steps: acquiring image data to be input to a display panel, the image data comprising a plurality of first sub-image data, the first sub-image data being data to be input to a row of pixel units of the display panel; adding a second bit data having L bit positions to a first bit data having K bit positions in each of the first sub-image data to obtain second sub-image data, K and L being positive integers; acquiring address information of continuous bit data in the second sub-image data, the continuous bit data being data having M bit positions and having values of 0 or 1, M being an integer greater than or equal to 2; writing address information and value information of a first continuous bit data in the second sub-image data into predetermined bit positions of row configuration information of the second sub-image data, the value information indicating 0 or 1; writing address information and value information of an N+1th continuous bit data in the second sub-image data into bit positions where an Nth continuous bit data in the second sub-image data is located, N being an integer greater than or equal to 1.

2. The data encoding method of claim 1, wherein, The second sub-image data comprises a plurality of data combinations, each of the data combinations comprising a first bit data and a second bit data, the data combinations comprising a plurality of data blocks, and the address information comprising block address information of a data block where the continuous bit data is located and data address information of the continuous bit data in the data block. The acquiring of the address information of the continuous bit data in the second sub-image data comprises: finding the continuous bit data from the data combinations; outputting the block address information of the data block where the continuous bit data is located and the data address information of the continuous bit data in the data block after finding the continuous bit data.

3. The data encoding method of claim 2, wherein, The finding of the continuous bit data from the data combinations comprises: reading M bit positions of data from a Pth bit position in an Oth data combination, O and P being integers greater than or equal to 1; judging whether the M bit positions of data are continuous 0 or continuous 1; The outputting of the block address information of the data block where the continuous bit data is located and the data address information of the continuous bit data in the data block after finding the continuous bit data comprises: outputting the block address information of the data block where the M bit positions of data are located and the data address information of the M bit positions of data in the data block in a case that the M bit positions of data are continuous 0 or continuous 1; after the judging of whether the M bit positions of data are continuous 0 or continuous 1, the finding of the continuous bit data from the data combinations further comprises: in a case that the M bit positions of data are not continuous 0 or continuous 1, increasing P by R and returning to execute the step of reading M bit positions of data from a Pth bit position in an Oth data combination, R being an integer greater than or equal to 1.

4. The data encoding method of claim 3, wherein, In a case that the M-bit data is continuous 0 or continuous 1, outputting the block address information of the data block where the M-bit data is located and the data address information of the M-bit data in the data block, and reading the M-bit data from the Pth bit in the Oth data combination, further comprises: judging whether the data address information of the M-bit data is predetermined data address information; in a case that the data address information of the M-bit data is not the predetermined data address information, increasing the P by R, and returning to execute the step of reading the M-bit data from the Pth bit in the Oth data combination; in a case that the data address information of the M-bit data is the predetermined data address information, increasing the O by 1 and setting the P as 1, and returning to execute the step of reading the M-bit data from the Pth bit in the Oth data combination.

5. The data encoding method of claim 2, wherein / in which, in a case that the found part of the continuous bit data is located in a Qth data block and another part is located in a Q+1th data block, the block address information of the data block where the continuous bit data is located is the block address information of the Qth data block, and the data address information of the continuous bit data in the data block is the data address information of the continuous bit data in the Qth data block, Q being an integer equal to or greater than 1.

6. The data encoding method of claim 2, wherein, The predetermined bit comprises a header bit, and the writing of the address information and the value information of the first continuous bit data in the second sub-image data into the predetermined bit of the row configuration information of the second sub-image data comprises: writing the address information and the value information of the first continuous bit data in the second sub-image data into the header bit of the row configuration information of the second sub-image data.

7. The data encoding method of claim 6, wherein, The header bit comprises a first bit combination, a second bit combination located after the first bit combination, and a third bit combination located after the second bit combination; The writing of the address information and the value information of the first continuous bit data in the second sub-image data into the header bit of the row configuration information of the second sub-image data comprises: writing the block address information of the first continuous bit data in the second sub-image data into the first bit combination; writing the value information of the first continuous bit data in the second sub-image data into the second bit combination; writing the data address information of the first continuous bit data in the second sub-image data into the third bit combination.

8. The data encoding method of claim 1, wherein, The second bit data is data with L bits, the value of each bit of which is 0 or 1, and the value of each bit of the second bit data is different from the value of the last bit of the first bit data.

9. The data encoding method of claim 1, wherein, The writing of the address information and the value information of the first continuous bit data in the second sub-image data into the predetermined bit of the row configuration information of the second sub-image data comprises: writing address information and value information of first continuous bit data of a first data combination in the second sub-image data into a predetermined bit position of row configuration information of the second sub-image data; the writing of the address information and the value information of the N+1th continuous bit data in the second sub-image data into the bit position where the Nth continuous bit data in the second sub-image data is located comprises: writing address information and value information of the N+1th continuous bit data of the first data combination in the second sub-image data into the bit position where the Nth continuous bit data of the first data combination is located; the writing of the address information and the value information of the first continuous bit data in the second sub-image data into the predetermined bit position of the row configuration information of the second sub-image data further comprises: writing address information and value information of the first continuous bit data of the O+1th data combination in the second sub-image data into the bit position where the second bit data of the Oth data combination in the second sub-image data is located; the writing of the address information and the value information of the N+1th continuous bit data in the second sub-image data into the bit position where the Nth continuous bit data in the second sub-image data is located further comprises: writing address information and value information of the N+1th continuous bit data of the O+1th data combination in the second sub-image data into the bit position where the Nth continuous bit data of the O+1th data combination is located.

10. The data encoding method of claim 9, wherein, the method further comprises: in the case that the continuous bit data does not exist in the O+1th data combination in the second sub-image data, writing predetermined address information into the bit position where the second bit data of the Oth data combination in the second sub-image data is located.

11. A data decoding method, wherein, comprises: receiving encoded image data to be input to a display panel, the encoded image data comprising a plurality of third sub-image data, the third sub-image data being data to be input to a row of pixel units of the display panel; reading address information and value information of first continuous bit data in the third sub-image data from row configuration information of the third sub-image data, the continuous bit data being data whose value is all 0 or all 1 and having M bit positions, the M being an integer greater than or equal to 2; writing value information of the first continuous bit data on the M bit positions corresponding to the address information of the first continuous bit data; reading address information and value information of N+1th continuous bit data from a bit position where Nth continuous bit data in the third sub-image data is located, the N being an integer equal to or greater than 1; writing value information of the N+1th continuous bit data on the M bit positions corresponding to the address information of the N+1th continuous bit data, to obtain fourth sub-image data; A second bit data with L bit positions is removed from a first bit data with K bit positions in each of the fourth sub-image data, and the K and the L are positive integers.

12. The data decoding method of claim 11, wherein, The third sub-image data comprises a plurality of data combinations, and the address information and the value information of the N+1 continuous bit data are read from the N continuous bit data in the third sub-image data, comprising: M bit data is read from the P bit position in the O data combination in the third sub-image data, and the O and the P are integers greater than or equal to 1; It is judged whether the address information where the M bit positions are located is the address information of the N continuous bit data; In the case that the address information where the M bit positions are located is the address information of the N continuous bit data, the M bit data is outputted as the address information and the value information of the N+1 continuous bit data; After the judgment of whether the address information where the M bit positions are located is the address information of the N continuous bit data, the M bit data is read from the P bit position in the O data combination in the third sub-image data, further comprising: In the case that the address information where the M bit positions are located is not the address information of the N continuous bit data, the P is increased by R, and the step of reading the M bit data from the P bit position in the O data combination in the third sub-image data is executed again, and the R is an integer greater than or equal to 1.

13. The data decoding method of claim 12, wherein, The data combination comprises a plurality of data blocks, the address information comprises the block address information of the data block where the continuous bit data is located and the data address information of the continuous bit data in the data block, and in the case that the address information where the M bit positions are located is the address information of the N continuous bit data, the M bit data is outputted as the address information and the value information of the N+1 continuous bit data, comprising: In the case that the address information where the M bit positions are located is the address information of the N continuous bit data, it is judged whether the data address information where the M bit positions are located is predetermined data address information; In the case that the data address information where the M bit positions are located is not the predetermined data address information, the M bit data is outputted as the address information and the value information of the N+1 continuous bit data, the P is increased by R, and the step of reading the M bit data from the P bit position in the O data combination in the third sub-image data is executed again; After the judgment of whether the data address information where the M bit positions are located is predetermined data address information, the M bit data is read from the P bit position in the O data combination in the third sub-image data, further comprising: In the case that the data address information where the M bit positions are located is the predetermined data address information, the O is increased by 1 and the P is set to 1, and the step of reading the M bit data from the P bit position in the O data combination in the third sub-image data is executed again.

14. The data decoding method of claim 13, wherein, The step of increasing the O by 1 and setting the P to 1 and returning to execute the step of reading M bits of data from the Pth bit in the Oth data group in the third sub-image data, in the case that the data address information where the M bits of data are located is the predetermined data address information, comprises: The step of outputting the M bits of data as address information and value information of the first continuous bit data in the O+1th data group and increasing the O by 1 and setting the P to 1 and returning to execute the step of reading M bits of data from the Pth bit in the Oth data group in the third sub-image data, in the case that the data address information where the M bits of data are located is the predetermined data address information.

15. The data decoding method of claim 14, wherein, The step of outputting the M bits of data as address information and value information of the first continuous bit data in the O+1th data group and increasing the O by 1 and setting the P to 1 and returning to execute the step of reading M bits of data from the Pth bit in the Oth data group in the third sub-image data, in the case that the data address information where the M bits of data are located is the predetermined data address information, comprises: The step of judging whether the M bits of data are predetermined address information, in the case that the data address information where the M bits of data are located is the predetermined data address information; The step of outputting the M bits of data as address information and value information of the first continuous bit data in the O+1th data group and increasing the O by 1 and setting the P to 1 and returning to execute the step of reading M bits of data from the Pth bit in the Oth data group in the third sub-image data, in the case that the M bits of data are not predetermined address information; The step of reading M bits of data from the Pth bit in the Oth data group in the third sub-image data after the step of judging whether the M bits of data are predetermined address information, further comprises: The step of stopping the step of reading M bits of data from the Pth bit in the Oth data group in the third sub-image data, in the case that the M bits of data are the predetermined address information.

16. The data decoding method of claim 11, wherein, The step of reading address information and value information of the first continuous bit data in the third sub-image data from the row configuration information of the third sub-image data, comprises: The step of reading address information and value information of the first continuous bit data in the third sub-image data from a header bit of the row configuration information of the third sub-image data.

17. The data decoding method of claim 16, wherein, The address information comprises block address information of a data block where the continuous bit data is located and data address information of the continuous bit data in the data block, the header bit comprises a first bit group, a second bit group located after the first bit group and a third bit group located after the second bit group, and the step of reading address information and value information of the first continuous bit data in the third sub-image data from the header bit of the row configuration information of the third sub-image data, comprises: The step of reading address information and value information of the first continuous bit data in the third sub-image data from a header bit of the row configuration information of the third sub-image data. reading block address information of the first continuous bit data from the first bit combination; reading value information of the first continuous bit data from the second bit combination; reading data address information of the first continuous bit data from the third bit combination.

18. An encoding chip, wherein, The encoding chip comprises program codes for executing the data encoding method according to any one of claims 1-10.

19. A decoding chip, wherein, The decoding chip comprises program codes for executing the data decoding method according to any one of claims 11-17.

20. A display device comprising: The display panel, the encoding chip and the decoding chip are included, the encoding chip is used for executing the data encoding method according to any one of claims 1-10 and outputting encoded image data to the decoding chip, the decoding chip is used for executing the data decoding method according to any one of claims 11-17 on the encoded image data and outputting decoded image data to the display panel, and the display panel is used for displaying an image according to the decoded image data output by the decoding chip.

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