Data encoding method and chip, data decoding method and chip, and display device

Abstract

The present application discloses a data encoding method and chip, a data decoding method and chip, and a display device. The data encoding method comprises: acquiring image data for input to a display panel, wherein the image data comprises a plurality of pieces of sub-image data, and each piece of sub-image data comprises a plurality of data combinations; acquiring addresses of specific data in each data combination of each piece of sub-image data, wherein the specific data has M bits, and the bit values of the M bits are all 0 or 1, M being an integer greater than or equal to 2; writing the address and bit value of the first piece of specific data in the data combination to a preset bit combination among a plurality of preset bit combinations of line configuration information of the sub-image data; and writing the address and bit value of the (N+1)-th piece of specific data in the data combination to a bit where the N-th piece of specific data in the data combination is located.

Description

Data encoding method and chip, data decoding method and chip, and display device

[0001] This application claims priority to Chinese Patent Application No. 202410882823.5, filed on July 3, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a data encoding method and chip, a data decoding method and chip, and a display device. BACKGROUND

[0003] The display device generally performs high-speed data transmission through a point-to-point transmission interface protocol, which can be a new high-speed point-to-point interface transmission protocol (China Standard Point-to-Point Interface, CSPI).

[0004] The technical solution of the CSPI protocol uses 8b / 9b encoding to re-encode the data stream, so that consecutive 1s or 0s in the data stream will not exceed 5 bits, i.e., after every 5 consecutive 1s, a 0 bit must be inserted, or after every 5 consecutive 0s, a 1 bit must be inserted, to achieve direct current balance. SUMMARY

[0005] Although the use of 8b / 9b encoding technology can achieve direct current balance, transmitting 8-bit data requires 9-bit bandwidth, with an additional overhead of 11.1%. The larger the additional overhead, the more bandwidth is sacrificed, resulting in more power consumption at the transmitting end and the receiving end.

[0006] Embodiments of the present application provide a data encoding method, comprising:

[0007] Obtaining image data for input to a display panel; wherein the image data comprises a plurality of sub-image data, each of the sub-image data being used for input to a row of pixel units of the display panel, and each of the sub-image data comprising a plurality of data combinations;

[0008] Obtaining the address of a specific data in each data combination of each sub-image data; wherein the specific data has M bits, and the bit values on the M bits are all 0 or all 1, and M is an integer greater than or equal to 2;

[0009] Writing the address and bit value of the first specific data in the data combination to one of a plurality of preset bit position combinations of row configuration information of the sub-image data; and

[0010] write the address and bit value of the (N+1)th specific data in the data combination into the bit position where the Nth specific data in the data combination is located; wherein N is a positive integer.

[0011] Embodiments of the present application also provide a data decoding method, comprising:

[0012] receiving encoded image data; wherein the image data comprises a plurality of sub-image data, each of the sub-image data is used to input into a row of pixel units of a display panel, and each of the sub-image data comprises a plurality of data combinations;

[0013] restoring a first replacement data in at least one of the data combinations to a specific data according to data written on at least one preset bit position combination of the row configuration information of the sub-image data; wherein the specific data has M bit positions, and the bit values on the M bit positions are all 0 or all 1, and M is an integer greater than or equal to 2; and

[0014] restoring an (N+1)th replacement data in the data combination to the specific data according to an Nth replacement data in the data combination; wherein the Nth replacement data comprises the address and restored bit value of the (N+1)th replacement data, and N is a positive integer.

[0015] Embodiments of the present application also provide an encoding chip, comprising computer instructions for performing:

[0016] obtaining image data used to input into a display panel; wherein the image data comprises a plurality of sub-image data, each of the sub-image data is used to input into a row of pixel units of the display panel, and each of the sub-image data comprises a plurality of data combinations;

[0017] obtaining the address of a specific data in each of the data combinations of each of the sub-image data; wherein the specific data has M bit positions, and the bit values on the M bit positions are all 0 or all 1, and M is an integer greater than or equal to 2;

[0018] writing the address and bit value of a first specific data in the data combination into one of a plurality of preset bit position combinations of the row configuration information of the sub-image data; and

[0019] write the address and bit value of the (N+1)th specific data in the data combination into the bit position where the Nth specific data in the data combination is located; wherein N is a positive integer.

[0020] Embodiments of the present application also provide a decoding chip, which comprises computer instructions for executing the following steps:

[0021] receiving encoded image data; wherein the image data comprises a plurality of sub-image data, each of the sub-image data is used for inputting to a row of pixel units of a display panel, and each of the sub-image data comprises a plurality of data combinations;

[0022] restoring a first replacement data in at least one of the data combinations to specific data according to data written on at least one preset bit combination of the row configuration information of the sub-image data; wherein the specific data has M bits, and bit values on the M bits are all 0 or all 1, and the M is an integer greater than or equal to 2; and

[0023] restoring an (N+1)th replacement data in the data combination to the specific data according to an Nth replacement data in the data combination; wherein the Nth replacement data comprises an address of the (N+1)th replacement data and a restored bit value, and the N is a positive integer.

[0024] Embodiments of the present application also provide a display device, which comprises a display panel, an encoding chip and a decoding chip, the encoding chip is used for executing the data encoding method provided by the embodiments of the present application, and outputs encoded image data to the decoding chip, the decoding chip is used for executing the data decoding method provided by the embodiments of the present application for the encoded image data, and outputs decoded image data to the display panel, and the display panel is used for displaying images according to the decoded image data output by the decoding chip. BRIEF DESCRIPTION OF DRAWINGS

[0025] FIG. 1 is a flowchart of the data encoding method provided by the embodiments of the present application;

[0026] FIG. 2 is a schematic diagram of a pixel unit provided by the embodiments of the present application;

[0027] FIG. 3 is a schematic diagram of a definition manner of a data block address provided by the embodiments of the present application;

[0028] FIG. 4 is a schematic diagram of a definition manner of an intra-data block address provided by the embodiments of the present application;

[0029] FIG. 5 is a schematic diagram of a bit structure of a preset bit combination provided by the embodiments of the present application;

[0030] FIG. 6 is a schematic diagram of a definition manner of row configuration information provided by the embodiments of the present application;

[0031] FIG. 7 is a schematic diagram of encoded image data provided by the embodiments of the present application;

[0032] FIG. 8 is a schematic diagram of encoded sub-image data according to an embodiment of the present application;

[0033] FIG. 9 is a schematic diagram of instruction meaning according to an embodiment of the present application;

[0034] FIG. 10 is a schematic diagram of encoded image data according to an embodiment of the present application;

[0035] FIG. 11 is a schematic diagram of a data encoding process according to an embodiment of the present application;

[0036] FIG. 12 is a schematic diagram of an address mark within a data block according to an embodiment of the present application;

[0037] FIG. 13 is a flowchart of a data decoding method according to an embodiment of the present application;

[0038] FIG. 14 is a schematic diagram of an encoding chip according to an embodiment of the present application;

[0039] FIG. 15 is a schematic diagram of a decoding chip according to an embodiment of the present application;

[0040] FIG. 16 is a schematic diagram of a display device according to an embodiment of the present application. Embodiments of the present application

[0041] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings of the embodiments of the present application. The described technical solutions are only used to explain and illustrate the ideas of the present application, and should not be regarded as limiting the protection scope of the present application.

[0042] In addition, “multiple” in the embodiments of the present application refers to two or more. “First” and “second” and the like in the embodiments of the present application are used to distinguish different technical features, and do not represent any order, quantity or importance.

[0043] The various embodiments provided by the present application are similar, and the features in different embodiments can be combined with each other.

[0044] The sequence of the following embodiments is not regarded as a limitation on the preferred sequence of the embodiments.

[0045] The embodiments of the present application provide a data encoding method and chip, a data decoding method and chip, and a display device. The display device can be integrated in a display device, which can be a television, a smart phone, a tablet computer, a notebook computer, a desktop computer, a smart speaker, a smart watch, etc., but is not limited thereto.

[0046] In the embodiments of the present application, the data encoding method provided by the present application is described from the perspective of the display device, that is, the display device is taken as the execution subject.

[0047] Referring to FIG. 1, FIG. 1 is a flowchart of a data encoding method according to an embodiment of the present disclosure. The data encoding method can include at least one of the following steps 110-140.

[0048] At step 110, image data for inputting to a display panel is obtained, the image data including a plurality of sub-image data, each of the sub-image data being for inputting to a row of pixel units of the display panel, and each of the sub-image data including a plurality of data combinations.

[0049] The display panel refers to a component for displaying images, which can include a plurality of pixel units, each of which can emit light, display color, or reflect light to generate images. The type of the display panel can be set according to actual conditions, for example, the display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), a mini light-emitting diode display panel (Mini-LED), or a micro light-emitting diode display panel (Micro-LED), which are not limited in the embodiments of the present disclosure. The pixel units included in the display panel can exist in the form of rows and / or columns. For example, the display panel includes a plurality of rows of pixel units and a plurality of columns of pixel units, as shown in FIG. 2.

[0050] In the embodiments of the present disclosure, the image data for inputting to the display panel includes a plurality of bits, and the bit values of each bit in the image data and the sub-image data are 0 or 1. Since the sub-image data is for inputting to a row of pixel units of the display panel, the division of the sub-image data in the image data can be consistent with the division of the number of rows of pixel units in the display panel. For example, if the display panel includes L rows of pixel units, L being a positive integer, the image data can include L sub-image data.

[0051] In each of the sub-image data of the image data, the embodiments of the present disclosure provide a plurality of data combinations, each of which is a sequence of bits in the sub-image data. Each of the sub-image data can include the same number of data combinations, and each of the sub-image data can include X data combinations, X being a positive integer, for example, X can be 10, 12, or 15. In addition, each of the data combinations can have the same number of bits, and each of the data combinations can have Y bits, Y being a positive integer, for example, Y can be 450, 468, 486, 504, 520, or 540. In actual application, the number of data combinations included in the sub-image data can be determined first, and then the number of bits of each data combination can be determined based on the number of data combinations; or the number of bits of each data combination can be determined first, and then the number of data combinations included in the sub-image data can be determined based on the number of bits.

[0052] In some cases, there can be one or more empty data combinations in the sub-image data, and / or there can be one or more empty bit positions in the data combinations. Here, empty means that the bit value in the bit position is empty, so it can also be said that there can be no certain data combination or certain data combinations in the sub-image data, and / or there can be no certain bit position or certain bit positions in the data combination.

[0053] For example, it is pre-set that each sub-image data includes 15 data combinations, and each data combination has 540 bit positions. For the 966 / 960 channel in the CSPI protocol, since 966 / 960 multiplied by 8 bit positions is approximately 15 times 540 bit positions, each data combination exists, but some bit positions in the last data combination do not exist, or in other words, there are some empty bit positions in the last data combination. For the 726 / 720 channel in the CSPI protocol, since 726 / 720 multiplied by 8 bit positions is approximately 11 times 540 bit positions, the last four data combinations do not exist, or in other words, there are four empty data combinations, and in addition, some bit positions in the fifth last data combination do not exist, or in other words, there are some empty bit positions in the fifth last data combination.

[0054] In step 120, the address of the specific data in each data combination of each sub-image data is obtained, the specific data has M bit positions, and the bit values in the M bit positions are all 0 or all 1, and M is an integer greater than or equal to 2.

[0055] The specific data refers to data in which the bit values in the consecutive M bit positions are the same, and the value of M can be set according to actual conditions. For example, M can be 4, 5, 6, 7, 8, or 9. Exemplarily, when M is 9, the specific data includes 000000000 and 111111111; and when M is 5, the specific data includes 00000 and 11111.

[0056] The address of the specific data is used to indicate the specific position of the specific data in the data combination. For each data combination of each sub-image data, it can be queried whether the specific data exists in the data combination; when the specific data is queried, the address of the specific data is generated.

[0057] In some embodiments, each data combination includes a plurality of data blocks, and each data block corresponds to a plurality of data addresses. The address of the specific data includes a data block address and a data block address. The data block address is the address of the data block where the specific data is located in the data combination, and the data block address is the address of the data block where the specific data is located in the data block.

[0058] The data block address and the data block-in address can be represented by bit values. The number of bits of the data block address can be determined based on the number of data blocks in the data combination. The number of bits of the data block-in address can be determined based on the number of addresses in the data block. For example, assuming that each data combination includes 6 data blocks and each data block includes 28 addresses, since 6 different values are needed to distinguish the 6 data blocks and 28 different values are needed to distinguish the 28 addresses, and 3 bits are needed to represent the 6 different values and 5 bits are needed to represent the 28 different values, the data block address can include 3 bits and the data block-in address can include 5 bits. Based on this, FIG. 3 exemplarily shows a possible definition of the data block address, and FIG. 4 exemplarily shows a possible definition of the data block-in address. It should be understood that in FIG. 4, the "data block-in address" and the "address corresponding to the data block-in" are different definitions of the same address. The "data block-in address" is defined in binary and represented by a bit value. The "address corresponding to the data block-in" is defined in decimal and represented by a value.

[0059] Of course, the address of the specific data can also be represented in other ways. For example, the address of the specific data can be determined based on the position of the first bit, the last bit or any bit of the specific data in the data combination.

[0060] In the case where the address of the specific data is represented by the data block address and the data block-in address, for any data combination, it can be queried whether the specific data exists in each data block of the data combination. When the specific data is queried, the data block address and the data block-in address of the specific data are generated. Alternatively, the specific data can be sequentially or in parallel queried in each data block. After the specific data query process of all data blocks is completed, the data block address and the data block-in address of each specific data queried are generated. Or the specific data can be sequentially queried in each data block. When each specific data is queried, the data block address and the data block-in address of the specific data are generated.

[0061] In some embodiments, the above step 120 includes steps 122 to 128.

[0062] In step 122, it is determined whether the data of the M bits corresponding to the Sth address in the Kth data block in the data combination is the specific data. K is a positive integer less than or equal to P, and the initial value of K is 1. P is a positive integer. S is a positive integer less than or equal to Q, and the initial value of S is 1. Q is a positive integer.

[0063] Each data combination includes P data blocks, each data block includes Q addresses, and P and Q are positive integers, for example, P is 5, 6, 7 or 8, and Q is 10, 28 or 44. For any one data combination, starting from the first address in the first data block of the data combination (i.e., starting from K being 1 and S being 1), it is determined in sequence whether the data on the M bit positions corresponding to each address in each data block is the specific data, until the specific data query process corresponding to the last address in the last data block ends (i.e., until K+1 is greater than P and S+1 is greater than Q).

[0064] For the Kth data block of the data combination, when the Sth address in the Kth data block is queried, the data on the M bit positions corresponding to the Sth address can be read, and it is then determined whether the data on the M bit positions corresponding to the Sth address is the specific data. Alternatively, the M bit positions corresponding to the address in the data block refer to the M bit positions starting from the bit position corresponding to the address in the data block.

[0065] Since the specific data refers to data in which the bit values of the continuous M bit positions are all the same, when it is determined whether the data on the M bit positions is the specific data, it can be determined in sequence whether the bit value of the current bit position in the M bit positions is the same as the bit value of the next bit position, and if they are all the same, the data on the M bit positions is the specific data, and if there is a difference, the data on the M bit positions is not the specific data. Alternatively, the bit value of the first bit position in the M bit positions can be read first, and then it is determined in sequence whether the bit values of the subsequent bit positions in the M bit positions are the same as the bit value of the first bit position, and if they are all the same, the data on the M bit positions is the specific data, and if there is a difference, the data on the M bit positions is not the specific data.

[0066] Step 124, when the data on the M bit positions is the specific data, the data block address and the address in the data block of the specific data are generated.

[0067] For the M bit positions corresponding to the Sth address in the Kth data block, when the data on the M bit positions is the specific data, the data block address and the address in the data block of the specific data are generated in real time, wherein the data block address is used to indicate the Kth data block, and the address in the data block is used to indicate the Sth address in the Kth data block.

[0068] Step 126, S is set to S+1, and the step of determining whether the data on the M bit positions corresponding to the Sth address in the Kth data block of the data combination is the specific data is executed again.

[0069] After the judgment of step 122, whether the data on the M bit positions corresponding to the Sth address is the specific data or not, step 126 needs to be executed to continue judging whether the data on the M bit positions corresponding to the next address is the specific data or not, that is, let S be S+1, and execute again from the step of judging whether the data on the M bit positions corresponding to the Sth address in the Kth data block in the data combination is the specific data or not.

[0070] It should be understood that after the judgment of step 122, when the data on the M bit positions corresponding to the Sth address is the specific data, step 124 is executed first and then step 126 is executed; when the data on the M bit positions corresponding to the Sth address is not the specific data, step 126 is directly executed.

[0071] Step 128, when S+1 is greater than Q, let K be K+1 and let S be 1, and execute again from the step of judging whether the data on the M bit positions corresponding to the Sth address in the Kth data block in the data combination is the specific data or not, until K+1 is greater than P.

[0072] Wherein, each time when S is S+1 in step 126, it can be judged first whether S+1 is greater than Q or not, if S+1 is less than or equal to Q, the address in the current data block is not all queried, the specific data query process of the next address in the current data block is continued, that is, return to step 122 to execute again based on the new value of S; if S+1 is greater than Q, the address in the current data block is all queried, the specific data query process of the next data block is continued, that is, let K be K+1 and let S be 1, return to step 122 to execute again based on the new value of K and the new value of S.

[0073] Similarly, each time when K is K+1 in step 128, it can be judged first whether K+1 is greater than P or not, if K+1 is less than or equal to P, the data block included in the current data combination is not all queried, the specific data query process of the next data block in the current data combination is continued, that is, return to step 122 to execute again based on the new value of K and the new value of S; if K+1 is greater than P, the data block included in the current data combination is all queried, the specific data query process of the next data combination is continued, that is, execute again steps 122 to 128 with the next data combination.

[0074] Step 130, write the address and bit value of the first specific data in the data combination to one of the plurality of preset bit position combinations in the row configuration information of the sub-image data.

[0075] Each sub-image data corresponds to a line configuration information (Line Config), which is used to indicate the related parameters of a row of pixel units corresponding to the sub-image data in the displayed image. Embodiments of the present application add a plurality of preset bit combination in the line configuration information, and each preset bit combination corresponds to a data combination in the sub-image data.

[0076] In the preset bit combination corresponding to the data combination, the address and the bit value of the first specific data in the data combination are written into the line configuration information of the sub-image data.

[0077] In some embodiments, each preset bit combination includes a first bit combination, a second bit combination and a third bit combination arranged in sequence; in the case that the address of the specific data includes a data block address and an intra-data block address, the step 130 includes: writing the data block address of the first specific data in the data combination into the first bit combination of the preset bit combination; writing the bit value of the first specific data in the data combination into the second bit combination of the preset bit combination; and writing the intra-data block address of the first specific data in the data combination into the third bit combination of the preset bit combination.

[0078] In the preset bit combination corresponding to the data combination, the address and the bit value of the first specific data in the data combination are written into the line configuration information of the sub-image data.

[0079] In some embodiments, each sub-image data includes T data combinations arranged in sequence, and the row configuration information of each sub-image data includes T preset bit combinations arranged in sequence, where T is a positive integer. For example, T is 10, 12 or 15. Based on this, the step 130 includes: writing the address and bit value of the first specific data in the Rth data combination to the Rth preset bit combination of the row configuration information of the sub-image data, where R is a positive integer less than or equal to T. That is, the arrangement order of the plurality of data combinations in the corresponding sub-image data is consistent with the arrangement order of the plurality of preset bit combinations in the corresponding row configuration information.

[0080] In some embodiments, the data encoding method further includes: when the specific data does not exist in the Rth data combination, writing a first preset invalid data to the Rth preset bit combination of the row configuration information of the sub-image data.

[0081] In some embodiments, the data encoding method further includes: when the Rth data combination does not exist, filling a second preset invalid data to the Rth preset bit of the row configuration information of the sub-image data. For the description of the nonexistence of one or more data combinations in the sub-image data, please refer to the description of the step 110 above, which will not be repeated here.

[0082] In some embodiments, the data encoding method further includes: when the Rth data combination does not exist, filling a second preset invalid data to the Rth preset bit of the row configuration information of the sub-image data. For the description of the nonexistence of one or more data combinations in the sub-image data, please refer to the description of the step 110 above, which will not be repeated here.

[0083] For example, in the case that the preset bit combination includes a first bit combination, a second bit combination and a third bit combination arranged in sequence, the invalid data block address in the first preset invalid data and the second preset invalid data is filled into the first bit combination of the preset bit combination, the invalid data block address in the first preset invalid data and the second preset invalid data is filled into the third bit combination of the preset bit combination, and the second bit combination of the preset bit combination can be filled with 0 or 1 at will; thus, the preset bit combination filled with the first preset invalid data and the second preset invalid data can be any one of the following bit value conditions: 000000000, 000011101, 000011110, 000011111, 000100000, 000111101, 000111110, 000111111, 111000000, 111011101, 111011110, 111011111, 111100000, 111111101, 111111110, 111111111.

[0084] It should be understood that in the embodiments of the present application, the first preset invalid data and the second preset invalid data can be the same bit value condition or different bit value conditions. For example, the first preset invalid data and the second preset invalid data are both 111011111; or the first preset invalid data is 000111111 and the second preset invalid data is 111000000.

[0085] In some embodiments, the preset bit combination is a header bit combination, the row configuration information further includes a command (CMD) bit combination and a register (Reserve) bit combination; in the case that the sub-image data includes X data combinations, the row configuration information includes a 1T CMD bit combination, XT header bit combinations and a 4T Reserve bit combination.

[0086] For example, X is 15, and a possible definition of the row configuration information is shown in FIG. 6, the data (i.e., the encoded image data) transmitted from the encoding chip of the display device to the decoding chip is shown in FIG. 7, a row of data (i.e., the encoded sub-image data) is shown in FIG. 8, and the meanings of the instructions in FIGS. 6-8 are shown in FIG. 9; in addition, FIG. 10 shows the data transmitted from the encoding chip of the display device to the decoding chip in the related art, and based on the data encoding method provided by the embodiments of the present application, the row configuration information includes the original CMD bit combination, which is compatible with the data encoding method in the original CSPI protocol.

[0087] Step 140, write the address and bit value of the N+1th specific data in the data combination into the bit position where the Nth specific data in the data combination is located, N is a positive integer.

[0088] For any one data combination, in the case that there are two or more specific data in the data combination, write the address and bit value of the N+1th specific data in the data combination into the bit position where the Nth specific data in the data combination is located, N is a positive integer. That is, write the address and bit value of the second specific data in the data combination into the bit position where the first specific data in the data combination is located; write the address and bit value of the third specific data in the data combination into the bit position where the second specific data in the data combination is located; and so on, write the address and bit value of the current specific data in the data combination into the bit position where the last specific data in the data combination is located; until write the address and bit value of the last specific data in the data combination into the bit position where the second last specific data in the data combination is located.

[0089] In some embodiments, the bit position structure of the specific data in the data combination after being replaced (i.e. the bit position structure of the bit positions where the address and bit value are written after writing the address and bit value into the bit positions where the specific data is located) is the same as the bit position structure of the preset bit position combination of the row configuration information. By setting the same bit position structure, it is ensured that the uniform encoding specification is followed in the encoding process, and the encoding efficiency is improved. It should be understood that in this way, the number of bit positions that a specific data has is the same as the number of bit positions that a preset bit position combination has, i.e. both have M bit positions.

[0090] For example, in the case that the preset bit position combination includes a first bit position combination, a second bit position combination and a third bit position combination arranged in sequence, the bit position structure of the specific data after being replaced also includes three bit position combinations arranged in sequence, and when writing the address and bit value into the bit positions where the specific data is located, the data block address, the bit value, the address within the data block are written into the three bit position combinations in sequence. For other descriptions of the bit position structure and the number of bit positions of the preset bit position combination, please refer to the description of step 130 above, which will not be described here.

[0091] In some embodiments, the data encoding method further comprises: writing a third preset invalid data into the bit position where the last specific data in the data combination is located, the third preset invalid data being used to indicate the end of the encoding process of the data combination. That is, for any one data combination, when the specific data query process of the data combination ends, the last specific data in the data combination can be determined, and the third preset invalid data is written into the bit position where the last specific data is located to indicate the end of the encoding process for the data combination. Optionally, when the address of the specific data comprises a data block address and a data block internal address, the third preset invalid data comprises a preset invalid data block address and / or an invalid data block internal address. For the description of the invalid data block address and the invalid data block internal address, please refer to FIG. 3 and FIG. 4.

[0092] For example, after the bit position where the last specific data in the data combination is written into the third preset invalid data, the bit value can be any one of the following: 000000000, 000011101, 000011110, 000011111, 000100000, 000111101, 000111110, 000111111, 111000000, 111011101, 111011110, 111011111, 111100000, 111111101, 111111110, 111111111.

[0093] The data encoding method provided by the embodiments of the present application is described below with a specific example. FIG. 11 exemplarily shows a data combination, which has 540 bit positions, and the data combination is divided into 6 data blocks, so that each data block has 90 bit positions; for each data block, as shown in FIG. 12, the first bit position of each data block is marked as address 1, and then every two bit positions are marked as an address, so that 28 addresses can be marked for each data block.

[0094] In the data encoding process, the display device starts from the first address (address 1) in the first data block (1st Block (90bit)) and judges whether the data in the 9 bits (1st search 9bit) with the bit at address 1 as the starting bit is specific data (whether the bit values are all 0 or all 1); whether or not it is specific data, the data in the 9 bits (2nd search 9bit) with the bit at address 2 as the starting bit is continuously judged whether it is specific data; and so on, until the data in the 9 bits (28th search 9bit) with the bit at the last address in the last data block (6th Block (90bit)) as the starting bit is judged whether it is specific data.

[0095] In the above specific data query process, when the data in the 9 bits is determined to be specific data for the first time, the data block address, bit value and address in the data block of the specific data (the first specific data) are filled into the header bit combination of the line configuration information.

[0096] As shown in FIG. 11, the specific data is determined for the first time in the 9 bits (4th search 9bit) with the bit at the 4th address in the first data block as the starting bit, and the specific data 000000000 is the first specific data; the data block address of the first specific data is 001, which is written into the first bit combination (d0d1d2) of the header bit combination; the bit value of the first specific data is 0, which is written into the second bit combination (d3) of the header bit combination; the address in the data block of the first specific data is 00100, which is written into the third bit combination (d4d5d6d7d8) of the header bit combination; thus, the bit value on the header bit combination is 001000100.

[0097] In the above specific data query process, the address and bit value of the next specific data are written into the bit where the current specific data is located every time the next specific data is queried, and the bit structure after the specific data is replaced is the same as that of the header bit combination, so that the address and bit value of each specific data can be indicated by the bit where the last replaced specific data is located.

[0098] As shown in FIG. 11, the specific data is determined for the second time on the 9 bit (28th search 9bit) starting from the last address (data address 28) in the last data block (6th Block (90bit)), and the specific data 111111111 is the second specific data; the data block address of the second specific data is 110, the bit value is 1, and the address in the data block is 11100. The address and bit value of the second specific data are written to the bit where the first specific data is located; thus, the bit value in the bit where the replaced first specific data is located is 110111100.

[0099] After the above specific data query ends, the last specific data in the data combination can be determined, and the third preset invalid data is written to the bit where the last specific data is located to indicate that the encoding process for the data combination ends. The third preset invalid data includes a preset invalid data block address and / or an invalid data block address.

[0100] As shown in FIG. 11, the specific data is determined for the second time on the 9 bit (28th search 9bit) starting from the last address (data address 28) in the last data block (6th Block (90bit)), and the specific data 111111111 is the second specific data; the data block address of the second specific data is 110, the bit value is 1, and the address in the data block is 11100. The address and bit value of the second specific data are written to the bit where the first specific data is located; thus, the bit value in the bit where the replaced first specific data is located is 110111100.

[0101] In summary, the embodiment of the present application breaks the original situation of multiple logic 1s or multiple logic 0s appearing continuously in the image data by replacing the data with the same continuous multiple-bit value in the image data with the address and bit value of another data with the same continuous multiple-bit value during the encoding process, thereby achieving direct current balance and effectively avoiding errors caused by direct current offset during the decoding process.

[0102] Also, the embodiment of the present application does not add bit positions on the basis of original bit positions of image data by replacing data with the same continuous multi-bit value, but sets row configuration information for each sub-image data of the image data, writes the address and bit value of the first data with the same continuous multi-bit value in each data combination of the sub-image data of the image data to the corresponding preset bit position combination of the row configuration information of the sub-image data. Since the number of bit positions of the image data is much larger than the number of bit positions of the row configuration information, compared with the related art of inserting a large number of redundant bit positions in the image data, the embodiment of the present application only needs to configure a small number of additional bit positions, reduces the additional overhead of data transmission, and avoids excessive power consumption of the transmitting end and the receiving end. For example, in the 8b / 9b coding technology, 9 bits of bandwidth are needed for each transmission of 8 bits of data, and the additional overhead is 11.1%; and in the embodiment of the present application, 9 bits of additional row configuration information are needed for each transmission of 540 bits of data as the preset bit position combination, and the additional overhead is 1.6%.

[0103] In addition, through the technical solution of the embodiment of the present application, the address and bit value of each data with the same continuous multi-bit value in the original image data have corresponding indications after encoding, so that in the decoding process, based on the preset bit position combination of the row configuration information or based on the replaced data in the image data, the address and bit value of each data with the same continuous multi-bit value in the original image data can be obtained, and each data with the same continuous multi-bit value replaced in the image data can be restored, ensuring that the encoded image data can be correctly decoded. It can be seen that the embodiment of the present application not only realizes direct current balance and reduces additional overhead, but also guarantees the reliability of the encoding and decoding process.

[0104] Please refer to FIG. 13, which is a flowchart of a data decoding method provided by the embodiment of the present application. The data decoding method can include at least one of the following steps 210 to 230.

[0105] Step 210, receiving encoded image data, the image data including a plurality of sub-image data, each sub-image data being used for inputting to one row of pixel units of a display panel, and each sub-image data including a plurality of data combinations.

[0106] Step 220, restoring the first replacement data in at least one data combination to specific data according to the data written on at least one preset bit position combination of the row configuration information of the sub-image data, the specific data having M bit positions, and the bit values on the M bit positions being all 0 or all 1, M being an integer greater than or equal to 2.

[0107] At step 230, the (N+1)th specific data in the data combination is restored according to the Nth replacement data in the data combination, the Nth replacement data including the address of the (N+1)th replacement data and the restored bit value, N being a positive integer.

[0108] The replacement data refers to data obtained by replacing the specific data in the data combination during encoding, that is, after the address and bit value of the (N+1)th specific data in the data combination are written into the bit position of the Nth specific data in the data combination during encoding, the original bit position of the Nth specific data is replaced by the Nth replacement data.

[0109] It should be understood that the address of the Nth replacement data is the same as the address of the Nth specific data, and the restored bit value of the Nth replacement data is the same as the bit value of the Nth specific data. Since the address and bit value of the first specific data in each data combination are written into each preset bit position combination of the row configuration information of the sub-image data during encoding, during decoding, the address and restored bit value of the first replacement data in at least one data combination can be obtained according to the data written into at least one preset bit position combination of the row configuration information of the sub-image data, and the first replacement data is restored to the first specific data. In addition, since the address and bit value of the (N+1)th specific data in the data combination are written into the bit position of the Nth specific data in the data combination during encoding, during decoding, the address and restored bit value of the (N+1)th replacement data in the data combination can be obtained according to the Nth replacement data in the data combination, and the (N+1)th replacement data is restored to the (N+1)th specific data.

[0110] In some embodiments, the sub-image data includes T data combinations arranged in sequence, the row configuration information includes T preset bit position combinations arranged in sequence, T being a positive integer; and the step 220 includes: restoring the first replacement data in the Rth data combination of the sub-image data to specific data according to the data written into the Rth preset bit position combination of the row configuration information of the sub-image data, R being a positive integer less than or equal to T. That is, the address and restored bit value of the first replacement data in the Rth data combination of the sub-image data can be obtained according to the data written into the Rth preset bit position combination of the row configuration information of the sub-image data, and the first replacement data in the Rth data combination is restored to the first specific data.

[0111] In some embodiments, when there is no replacement data in the Rth data combination of the sub-image data, the data written into the Rth preset bit position combination of the row configuration information of the sub-image data is the first preset invalid data.

[0112] In some embodiments, when the Rth data combination does not exist in the sub-picture data, the data written on the Rth preset bit combination of the row configuration information of the sub-picture data is the second preset invalid data.

[0113] In some embodiments, the data written on the Rth preset bit combination of the row configuration information of the sub-picture data is the first preset invalid data; if the first preset invalid data is read from the Rth preset bit combination of the row configuration information of the sub-picture data, the decoding operation of the Rth data combination of the sub-picture data is ended.

[0114] In some embodiments, the data written on the Rth preset bit combination of the row configuration information of the sub-picture data is the second preset invalid data; if the second preset invalid data is read from the Rth preset bit combination of the row configuration information of the sub-picture data, the decoding operation of the Rth data combination of the sub-picture data is ended.

[0115] In some embodiments, the last replacement data in the data combination is the third preset invalid data; if the third preset invalid data is read from the data combination, the decoding operation of the data combination is ended. That is, during encoding, the third preset invalid data is written on the bit of the last specific data in the data combination, so that the last replacement data in the encoded data combination is the third preset invalid data, and during decoding, when the third preset invalid data is read from the encoded data combination, it is determined that the replacement data is the last replacement data, and the decoding process of the data combination is completed.

[0116] In some embodiments, the data combination includes a plurality of data blocks, each data block corresponding to a plurality of data addresses; the address of the specific data includes a data block address and a data block address within the data block, the data block address being the address of the data block where the specific data is located in the data combination, and the data block address within the data block being the address of the specific data within the data block. It should be understood that the address of the replacement data also includes a data block address and a data block address within the data block, the data block address being the address of the data block where the replacement data is located in the data combination, and the data block address within the data block being the address of the replacement data within the data block.

[0117] In some embodiments, the bit structure of the replacement data is the same as the bit structure of the preset bit combination of the row configuration information.

[0118] In some embodiments, the bit structure of each preset bit combination of the row configuration information comprises a first bit combination, a second bit combination and a third bit combination arranged in sequence; wherein the data written on the first bit combination of the preset bit combination is the data block address of the first replacement data in the encoded data combination, or in other words, the data written on the first bit combination is the data block address of the first specific data in the data combination before encoding; the data written on the second bit combination of the preset bit combination is the bit value of the first replacement data in the encoded data combination after restoration, or in other words, the data written on the second bit combination is the bit value of the first specific data in the data combination before encoding; the data written on the third bit combination of the preset bit combination is the intra-block address of the first replacement data in the encoded data combination, or in other words, the data written on the third bit combination is the intra-block address of the first specific data in the data combination before encoding.

[0119] In some embodiments, the bit structure of the replacement data comprises a first bit combination, a second bit combination and a third bit combination arranged in sequence; wherein the data written on the first bit combination of the Nth replacement data in the encoded data combination is the data block address of the (N+1)th replacement data in the encoded data combination, or in other words, the data written on the first bit combination is the data block address of the (N+1)th specific data in the data combination before encoding; the data written on the second bit combination of the Nth replacement data in the encoded data combination is the bit value of the (N+1)th replacement data in the encoded data combination after restoration, or in other words, the data written on the second bit combination is the bit value of the (N+1)th specific data in the data combination before encoding; the data written on the third bit combination of the Nth replacement data in the encoded data combination is the intra-block address of the (N+1)th replacement data in the encoded data combination, or in other words, the data written on the third bit combination is the intra-block address of the (N+1)th specific data in the data combination before encoding.

[0120] It should be understood that the explanations of terms, specific implementation manners and corresponding benefits in the data decoding method provided by the embodiments of the present application can refer to the descriptions in the data encoding method provided by the embodiments of the present application, which will not be described in detail here.

[0121] In order to better implement the data encoding method provided by the embodiments of the present application, the embodiments of the present application further provide an encoding chip based on the above-mentioned data encoding method, which comprises computer instructions, and the computer instructions can be used to execute the above-mentioned data encoding method, wherein the meanings of the terms are the same as those in the above-mentioned data encoding method, and the specific implementation details can refer to the descriptions in the method embodiments.

[0122] For example, the encoding chip is shown in FIG. 14, and the computer instructions in the encoding chip can be located in the modules shown in FIG. 14. In this case, the encoding chip can include a data acquisition module 1410, an information acquisition module 1420, and a data writing module 1430.

[0123] The data acquisition module 1410 is configured to acquire image data for input to the display panel. The image data includes a plurality of sub-image data. Each sub-image data is for input to one row of pixel units of the display panel, and each sub-image data includes a plurality of data combinations.

[0124] The information acquisition module 1420 is configured to acquire the address of a specific data in each data combination of each sub-image data. The specific data has M bits, and the bit values on the M bits are all 0 or all 1. M is an integer greater than or equal to 2.

[0125] The data writing module 1430 is configured to write the address and bit value of the first specific data in the data combination to one of a plurality of preset bit position combinations of the row configuration information of the sub-image data. The data writing module 1430 is further configured to write the address and bit value of the N+1th specific data in the data combination to the bit position where the Nth specific data in the data combination is located. N is a positive integer.

[0126] In some embodiments, the data combination includes a plurality of data blocks. The address of the specific data includes a data block address and a data block internal address. The data block address is the address of the data block where the specific data is located in the data combination. The data block internal address is the address of the specific data in the data block.

[0127] In some embodiments, the information acquisition module 1420 is further configured to: determine whether the data on the M bits corresponding to the Sth address in the Kth data block in the data combination is the specific data, K being a positive integer less than or equal to P and the initial value of K being 1, P being a positive integer, S being a positive integer less than or equal to Q and the initial value of S being 1, Q being a positive integer; generate the data block address and the data block internal address of the specific data when the data on the M bits is the specific data; set S to S+1, and perform again from the step of determining whether the data on the M bits corresponding to the Sth address in the Kth data block in the data combination is the specific data; set K to K+1 and set S to 1 when S+1 is greater than Q, and perform again from the step of determining whether the data on the M bits corresponding to the Sth address in the Kth data block in the data combination is the specific data until K+1 is greater than P.

[0128] In some embodiments, each preset bit combination includes, in sequence, a first bit combination, a second bit combination, and a third bit combination; and the data writing module 1430 is further configured to write the data block address of the first specific data in the data combination to the first bit combination of the preset bit combination; write the bit value of the first specific data in the data combination to the second bit combination of the preset bit combination; and write the in-data-block address of the first specific data in the data combination to the third bit combination of the preset bit combination.

[0129] In some embodiments, the sub-image data includes T data combinations arranged in sequence, and the row configuration information includes T preset bit combinations arranged in sequence, where T is a positive integer; and the data writing module 1430 is further configured to write the address and bit value of the first specific data in the Rth data combination to the Rth preset bit combination of the row configuration information of the sub-image data, where R is a positive integer less than or equal to T.

[0130] In some embodiments, when the specific data does not exist in the Rth data combination, the data writing module 1430 is further configured to write the first preset invalid data to the Rth preset bit combination of the row configuration information of the sub-image data.

[0131] In some embodiments, when the Rth data combination does not exist, the data writing module 1430 is further configured to write the second preset invalid data to the Rth preset bit combination of the row configuration information of the sub-image data.

[0132] In some embodiments, the data writing module 1430 is further configured to write the third preset invalid data to the bit position of the last specific data in the data combination.

[0133] It should be understood that, in actual implementation, each of the above modules can be implemented as an independent entity, or can be combined as the same or several entities.

[0134] To facilitate better implementation of the data decoding method provided by the embodiments of the present application, the embodiments of the present application further provide a decoding chip based on the above data decoding method. The decoding chip includes computer instructions, which can be used to execute the above data decoding method, where the meanings of the terms are the same as those in the above data decoding method, and the specific implementation details can be referred to the description in the method embodiments.

[0135] For example, the decoding chip is shown in FIG. 15, and the computer instructions in the decoding chip can be located in the modules shown in FIG. 15. At this time, the decoding chip can include a data receiving module 1510 and a data restoring module 1520.

[0136] The data receiving module 1510 is configured to receive encoded image data, the image data comprising a plurality of sub-image data, each of the sub-image data being used for inputting to a row of pixel units of a display panel, and each of the sub-image data comprising a plurality of data combinations.

[0137] The data restoring module 1520 is configured to restore a first replacement data in at least one data combination to specific data according to data written on at least one preset bit combination of the row configuration information of the sub-image data, the specific data having M bits, and the bit values of the M bits being all 0 or all 1, M being an integer greater than or equal to 2. The data restoring module 1520 is further configured to restore an (N+1)th replacement data in the data combination to specific data according to an Nth replacement data in the data combination, the Nth replacement data comprising an address of the (N+1)th replacement data and a restored bit value, N being a positive integer.

[0138] It should be understood that, in actual implementation, each of the above modules can be implemented as an independent entity, or can be combined as the same or several entities.

[0139] Those skilled in the art can understand that the above computer instructions can be stored in a computer readable storage medium and loaded and executed by a processor.

[0140] To this end, an embodiment of the present application provides a computer readable storage medium, which stores computer instructions capable of being loaded by a processor to execute steps in any one of the data encoding methods or steps in the data decoding method provided by the embodiments of the present application.

[0141] For example, the computer instructions can execute the following steps:

[0142] obtaining image data for inputting to a display panel, the image data comprising a plurality of sub-image data, each of the sub-image data being used for inputting to a row of pixel units of the display panel, and each of the sub-image data comprising a plurality of data combinations;

[0143] obtaining an address of specific data in each data combination of each sub-image data, the specific data having M bits, and the bit values of the M bits being all 0 or all 1, M being an integer greater than or equal to 2;

[0144] writing an address and a bit value of a first specific data in the data combination to one of a plurality of preset bit combinations of the row configuration information of the sub-image data;

[0145] writing an address and a bit value of an (N+1)th specific data in the data combination to a bit position where an Nth specific data in the data combination is located, N being a positive integer.

[0146] For example, the computer instructions can perform the following steps:

[0147] receiving encoded image data, the image data comprising a plurality of sub-image data, each of the sub-image data being used for inputting to a row of pixel units of a display panel, and each of the sub-image data comprising a plurality of data combinations;

[0148] restoring a first replacement data in at least one of the data combinations to specific data according to data written on at least one preset bit combination of row configuration information of the sub-image data, the specific data having M bits, and bit values on the M bits being all 0 or all 1, the M being an integer greater than or equal to 2;

[0149] restoring an (N+1)th replacement data in the data combination to the specific data according to an Nth replacement data in the data combination, the Nth replacement data comprising an address of the (N+1)th replacement data and a restored bit value, the N being a positive integer.

[0150] The computer readable storage medium can include a read only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0151] Due to the computer instructions stored in the computer readable storage medium, the steps in any of the data encoding methods or the steps in any of the data decoding methods provided by the embodiments of the present application can be performed, thus achieving the beneficial effects of any of the data encoding methods or the data decoding methods provided by the embodiments of the present application. Details are described above, and thus are not described here.

[0152] The embodiments of the present application also provide a display device, as shown in FIG. 16, which shows a structural schematic diagram of the display device related to the embodiments of the present application. Specifically:

[0153] The display device comprises a display panel, an encoding chip and a decoding chip. The encoding chip is used to perform the steps in the above data encoding method embodiments, and output encoded image data to the decoding chip. The decoding chip is used to perform the steps in the above data decoding method embodiments for the encoded image data, and output decoded image data to the display panel. The display panel is used to display images according to the decoded image data output by the decoding chip.

[0154] The specific implementation manners of the above operations and the corresponding beneficial effects can be referred to the detailed description of the data encoding method embodiments and the data decoding method embodiments above, and thus are not described here.

[0155] The data encoding method and chip, the data decoding method and chip, and the display device provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by using specific examples. The above description of the embodiments is only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges will be changed, and the above description of the embodiments should not be understood as a limitation on the present application.

Claims

1. A data encoding method, comprising: obtaining image data for inputting to a display panel; wherein the image data comprises a plurality of sub-image data, each of the sub-image data is for inputting to a row of pixel units of the display panel, and each of the sub-image data comprises a plurality of data combinations; obtaining an address of a specific data in each of the data combinations of each of the sub-image data; wherein the specific data has M bits, and the bit values of the M bits are all 0 or all 1, and the M is an integer greater than or equal to 2; writing the address and the bit value of the first specific data in the data combination into one of a plurality of preset bit position combinations of row configuration information of the sub-image data; and writing the address and the bit value of the N+1th specific data in the data combination into a bit position where the Nth specific data in the data combination is located; wherein the N is a positive integer.

2. The method of claim 1, wherein, the data combination comprises a plurality of data blocks, the address of the specific data comprises a data block address and a data block inner address, the data block address is an address of a data block where the specific data is located in the data combination, and the data block inner address is an address of the specific data in the data block; and the obtaining of the address of the specific data in each of the data combinations of each of the sub-image data comprises: judging whether data on the M bits corresponding to the Sth address in the Kth data block in the data combination is the specific data; wherein the K is a positive integer less than or equal to P, the initial value of the K is 1, the P is a positive integer, the S is a positive integer less than or equal to Q, the initial value of the S is 1, and the Q is a positive integer; generating the data block address and the data block inner address of the specific data when the data on the M bits is the specific data; setting S as S+1, and performing again from the step of judging whether data on the M bits corresponding to the Sth address in the Kth data block in the data combination is the specific data; and setting K as K+1 and setting S as 1 when S+1 is greater than the Q, and performing again from the step of judging whether data on the M bits corresponding to the Sth address in the Kth data block in the data combination is the specific data until K+1 is greater than the P.

3. The method of claim 1, wherein, the data combination comprises a plurality of data blocks, the address of the specific data comprises a data block address and a data block inner address, the data block address is an address of a data block where the specific data is located in the data combination, and the data block inner address is an address of the specific data in the data block; each of the preset bit position combinations comprises a first bit position combination, a second bit position combination and a third bit position combination arranged in sequence; and the writing of the address and the bit value of the first specific data in the data combination into one of a plurality of preset bit position combinations of row configuration information of the sub-image data comprises: writing the data block address of the first specific data in the data combination into the first preset bit combination of the preset bit combinations; writing the bit value of the first specific data in the data combination into the second preset bit combination of the preset bit combinations; and writing the data block address of the first specific data in the data combination into the third preset bit combination of the preset bit combinations.

4. The method of claim 1, wherein, the sub-image data comprises T data combinations arranged in sequence, and the row configuration information comprises T preset bit combinations arranged in sequence, T being a positive integer; and the writing of the address and bit value of the first specific data in the data combination into one of the preset bit combinations of the row configuration information of the sub-image data comprises: writing the address and bit value of the first specific data in the Rth data combination into the Rth preset bit combination of the row configuration information of the sub-image data; wherein R is a positive integer less than or equal to T.

5. The method of claim 4, wherein, The method further comprises: when the specific data does not exist in the Rth data combination, writing first preset invalid data into the Rth preset bit combination of the row configuration information of the sub-image data.

6. The method of claim 4, wherein, The method further comprises: when the Rth data combination does not exist, writing second preset invalid data into the Rth preset bit combination of the row configuration information of the sub-image data.

7. The method of claim 1, wherein, The method further comprises: writing third preset invalid data into the bit position of the last specific data in the data combination.

8. The method of claim 1, wherein, The number of bit positions of one of the preset bit combinations is equal to M.

9. The method of claim 1, wherein, M is 9.

10. A data decoding method, comprising: receiving encoded image data; wherein the image data comprises a plurality of sub-image data, each of the sub-image data being used to input to one row of pixel units of a display panel, and each of the sub-image data comprising a plurality of data combinations; restoring a first replacement data in at least one of the data combinations to a specific data according to data written into at least one preset bit combination of row configuration information of the sub-image data; wherein the specific data has M bit positions, and the bit values of the M bit positions are all 0 or all 1, M being an integer greater than or equal to 2; and restoring an N+1th replacement data in the data combinations to the specific data according to an Nth replacement data in the data combinations; wherein the Nth replacement data comprises an address and a restored bit value of the N+1th replacement data, N being a positive integer.

11. The method of claim 10, wherein, the sub-image data comprises T data combinations arranged in sequence, and the row configuration information comprises T preset bit combinations arranged in sequence, T being a positive integer; and and The data written on the at least one preset bit combination of the line configuration information of the sub-image data restores the first replacement data in the first data combination of the sub-image data to the specific data, including: The data written on the Rth preset bit combination of the line configuration information of the sub-image data restores the first replacement data in the Rth data combination of the sub-image data to the specific data; wherein, the R is a positive integer less than or equal to the T.

12. The method of claim 11, wherein, If the first preset invalid data is read from the Rth preset bit combination of the line configuration information of the sub-image data, the decoding operation on the Rth data combination of the sub-image data is ended.

13. The method of claim 11, wherein, If the second preset invalid data is read from the Rth preset bit combination of the line configuration information of the sub-image data, the decoding operation on the Rth data combination of the sub-image data is ended.

14. The method of claim 10, wherein, If the third preset invalid data is read from the data combination, the decoding operation on the data combination is ended.

15. The method of claim 10, wherein, The data combination includes a plurality of data blocks, the address of the replacement data includes a data block address and a data block internal address, the data block address is the address of the data block where the replacement data is located in the data combination, and the data block internal address is the address of the replacement data in the data block; and Each of the preset bit combinations of the line configuration information includes a first bit combination, a second bit combination and a third bit combination arranged in sequence; wherein, The data written on the first bit combination of the preset bit combination is the data block address of the first replacement data in the encoded data combination; The data written on the second bit combination of the preset bit combination is the bit value of the first replacement data in the encoded data combination after restoration; and The data written on the third bit combination of the preset bit combination is the data block internal address of the first replacement data in the encoded data combination.

16. An encoding chip, comprising computer instructions for performing: acquiring image data for input to a display panel; wherein The image data includes a plurality of sub-image data, each of the sub-image data is used to input to a row of pixel units of the display panel, and each of the sub-image data includes a plurality of data combinations; An address of specific data in each of the data combinations of each of the sub-image data is obtained; wherein, the specific data has M bits, and the bit values on the M bits are all 0 or all 1, and the M is an integer greater than or equal to 2; An address and a bit value of the first specific data in the data combination are written on one of a plurality of preset bit combinations of the line configuration information of the sub-image data; and An address and a bit value of the N+1th specific data in the data combination are written on a bit where the Nth specific data is located; wherein, the N is a positive integer.

17. The chip of claim 16, wherein, The data combination comprises a plurality of data blocks, the address of the specific data comprises a data block address and a data block internal address, the data block address is an address of the data block where the specific data is located in the data combination, and the data block internal address is an address of the specific data in the data block; and The computer instructions are further used to execute: determining whether data on M bit positions corresponding to an Sth address in a Kth data block in the data combination is the specific data; wherein K is a positive integer less than or equal to P, the initial value of K is 1, P is a positive integer, S is a positive integer less than or equal to Q, the initial value of S is 1, and Q is a positive integer; generating the data block address and the data block internal address of the specific data when the data on the M bit positions is the specific data; setting S to S+1 and performing again from the step of determining whether data on M bit positions corresponding to an Sth address in a Kth data block in the data combination is the specific data; and setting K to K+1 and setting S to 1 when S+1 is greater than Q, and performing again from the step of determining whether data on M bit positions corresponding to an Sth address in a Kth data block in the data combination is the specific data until K+1 is greater than P.

18. The chip of claim 16, wherein, The data combination comprises a plurality of data blocks, the address of the specific data comprises a data block address and a data block internal address, the data block address is an address of the data block where the specific data is located in the data combination, and the data block internal address is an address of the specific data in the data block; each of the preset bit position combinations comprises a first bit position combination, a second bit position combination and a third bit position combination arranged in sequence; and The computer instructions are further used to execute: writing the data block address of a first specific data in the data combination to the first bit position combination of the preset bit position combination; writing the bit value of the first specific data in the data combination to the second bit position combination of the preset bit position combination; and writing the data block internal address of the first specific data in the data combination to the third bit position combination of the preset bit position combination.

19. A decoding chip, comprising computer instructions for executing: receiving the encoded image data; wherein The image data comprises a plurality of sub-image data, each of the sub-image data is used to input to a row of pixel units of a display panel, and each of the sub-image data comprises a plurality of data combinations; replacing a first replacement data in at least one of the data combinations into specific data according to data written on at least one preset bit position combination of row configuration information of the sub-image data; wherein the specific data has M bit positions, and bit values on the M bit positions are all 0 or all 1, M is an integer greater than or equal to 2; and According to the Nth replacement data in the data combination, the N+1th replacement data in the data combination is restored to the specific data; wherein the Nth replacement data comprises an address of the N+1th replacement data and a restored bit value, and the N is a positive integer.

20. A display device comprising: The display panel, the encoding chip and the decoding chip are included, the encoding chip is used for executing the data encoding method as claimed in any one of claims 1 to 9 for image data, and the encoded image data is output to the decoding chip, the decoding chip is used for executing the data decoding method as claimed in any one of claims 10 to 15 for the encoded image data, and the decoded image data is output to the display panel, and the display panel is used for displaying an image according to the decoded image data output by the decoding chip.

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