Stacked transistor and manufacturing method therefor, semiconductor device, and electronic device

Abstract

The present invention provides a stacked transistor and a manufacturing method therefor, a semiconductor device, and an electronic device. The manufacturing method comprises: performing one etching on a semiconductor substrate to form active structures, wherein the active structures comprise a first active structure and a second active structure; on the basis of the first active structure, forming a first transistor of a stacked transistor, wherein the first transistor has a first gate structure, and the first gate structure is formed by using a replacement gate process; flipping a wafer and removing the semiconductor substrate; on the basis of the second active structure, forming a second transistor of the stacked transistor, wherein the second transistor has a second gate structure, and the second gate structure is formed by using the replacement gate process; and before replacing a dummy gate structure with the first gate structure and / or the second gate structure, performing depositing in gate isolation areas of the stacked transistor to form gate isolation structures, wherein the gate isolation structures are used for electrically isolating the gate structures of the stacked transistor from gate structures of transistors adjacent to the stacked transistor in a second direction.

Description

Stacked transistor, preparation method thereof, semiconductor device and electronic equipment

[0001] Cross-reference to related applications

[0002] The present disclosure is based on and claims priority from Chinese Patent Application No. 202410877439.6 filed on July 2, 2024, the content of which is hereby incorporated by reference in its entirety into the present disclosure. TECHNICAL FIELD

[0003] The present disclosure relates to the field of semiconductor, and in particular, to a stacked transistor, a preparation method thereof, a semiconductor device and an electronic equipment. BACKGROUND

[0004] At present, it is a hot issue in the industry to continue to promote the miniaturization of transistors as Moore's law continues to deepen. Stacked transistors, which integrate two or more layers of transistors in the vertical space, can further improve the integration density of transistors and become one of the important technologies to continue the miniaturization of integrated circuits.

[0005] In some schemes for preparing stacked transistors, the active regions of the upper and lower homologous transistors are formed by etching, and the stacked transistors are fabricated on the front and back surfaces of the wafer by developing. This can also be referred to as a "self-aligned flip transistor" scheme. However, in the "self-aligned flip transistor" scheme, a gate isolation trench needs to be formed by etching the metal gate structure after the metal gate structure is formed. After the gate isolation trench is formed, an insulating material is deposited in the gate isolation trench to form a gate isolation structure between adjacent transistor units using the insulating material. In this process, on the one hand, the etching deviation is likely to occur in the process of forming the gate isolation trench due to the precision of the etching process, thereby affecting the source-drain metal structure of the source-drain region, and on the other hand, it is more difficult to etch the gate structure of the metal material due to the limitation of the processing conditions. SUMMARY

[0006] The present disclosure provides a stacked transistor, a preparation method thereof, a semiconductor device and an electronic equipment.

[0007] The first aspect of the present disclosure provides a method for manufacturing a stacked transistor. The method comprises: etching a semiconductor substrate to form active structures in one step, the active structures comprising a first active structure and a second active structure, the first active structure and the second active structure being stacked in a first direction, the first active structure being farther away from the semiconductor substrate than the second active structure, the first direction being perpendicular to the semiconductor substrate; forming a first transistor of the stacked transistor based on the first active structure, the first transistor comprising a first gate structure, the first gate structure being formed by a gate replacement process, the gate replacement process comprising a step of replacing a dummy gate structure with a metal gate structure; peeling off the semiconductor substrate; forming a second transistor of the stacked transistor based on the second active structure, the second transistor comprising a second gate structure, the second gate structure being formed by the gate replacement process; the stacked transistor further comprising: a gate isolation structure, the gate isolation structure being deposited in a gate isolation region of the stacked transistor before the first gate structure and / or the second gate structure replaces the dummy gate structure; the gate isolation region being located on both sides of the stacked transistor in a second direction and at least overlapping a gate region of the stacked transistor in a third direction, the second direction being perpendicular to the first direction, the third direction being perpendicular to the first direction and the second direction; the gate isolation structure being configured to electrically isolate the gate structure of the stacked transistor and a gate structure of a transistor adjacent to the stacked transistor in the second direction.

[0008] The second aspect of the present disclosure provides a method for manufacturing a stacked transistor. The method comprises: etching a semiconductor substrate to form active structures in one step, the active structures comprising a first active structure and a second active structure, the first active structure and the second active structure being stacked in a first direction, the first active structure being farther away from the semiconductor substrate than the second active structure, the first direction being perpendicular to the semiconductor substrate; forming a first semiconductor structure based on the first active structure, the first semiconductor structure being configured to form a first transistor, the first transistor comprising a first gate structure, the first gate structure being formed by a gate replacement process, the gate replacement process comprising a step of replacing a dummy gate structure with a metal gate structure; peeling off the semiconductor substrate; forming the first transistor and a second transistor based on the second active structure and the first semiconductor structure, the second transistor comprising a second gate structure, the second gate structure being formed by the gate replacement process; the stacked transistor further comprising: a gate isolation structure, the gate isolation structure being deposited in a gate isolation region of the stacked transistor before the first gate structure and the second gate structure replaces the dummy gate structure; the gate isolation region being located on both sides of the stacked transistor in a second direction and at least overlapping a gate region of the stacked transistor in a third direction, the second direction being perpendicular to the first direction, the third direction being perpendicular to the first direction and the second direction; the gate isolation structure being configured to electrically isolate the gate structure of the stacked transistor and a gate structure of a transistor adjacent to the stacked transistor in the second direction.

[0009] The third aspect of the present disclosure provides a stacked transistor. The stacked transistor can be prepared by the preparation method of the first aspect or the preparation method of the second aspect. The stacked transistor comprises: a first transistor; a second transistor, the first transistor and the second transistor are arranged in a stack, a first active structure of the first transistor and a second active structure of the second transistor form an active structure; the first transistor comprises a first gate structure, and the second transistor comprises a second gate structure; a gate isolation structure is formed in a gate isolation region of the stacked transistor before the first gate structure and the second gate structure replace the dummy gate structure; the gate isolation region is located on both sides of the stacked transistor in a second direction, and at least overlaps with a gate region of the stacked transistor in a third direction, the second direction is perpendicular to the first direction, and the third direction is perpendicular to the first direction and the second direction; the gate isolation structure is used to electrically isolate the gate structure of the stacked transistor and the gate structure of a transistor adjacent to the stacked transistor in the second direction.

[0010] The fourth aspect of the present disclosure provides a semiconductor device. The semiconductor device comprises: the stacked transistor of the third aspect.

[0011] The fifth aspect of the present disclosure provides an electronic device, comprising: a circuit board and the semiconductor device of the fourth aspect, the semiconductor device is arranged on the circuit board.

[0012] Compared with the prior art, the present disclosure has the following beneficial effects:

[0013] In the embodiments of the present disclosure, by etching the active structure on the semiconductor substrate at one time, the active regions of the upper and lower transistors in the stacked transistor can be self-aligned. Then, the first transistor and the second transistor can be respectively prepared based on the first active structure in the active structure and the second active structure in the active structure. Moreover, before the first gate structure of the first transistor and the second gate structure of the second transistor are prepared, that is, before the metal gate replaces the dummy gate structure, the gate isolation structure located on both sides of the stacked transistor can be formed, so that the metal gate structure is formed after the gate isolation structure is formed. In this way, on the one hand, the problem of erroneous etching of the source-drain metal structure of the source-drain region when the gate isolation structure is formed after the metal gate structure is formed can be avoided, the cross-sectional area of the source-drain metal structure is increased, the resistance of the metal interconnection is reduced, and the overall unit performance is improved; on the other hand, the step of etching the metal material in the processing process can be avoided, the preparation difficulty is effectively reduced, and the process environment is friendly.

[0014] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, but not limiting the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0015] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, further serve to explain the principles of embodiments of the present disclosure.

[0016] FIG. 1 is an implementation flow diagram of a method for fabricating a stacked transistor according to embodiments of the present disclosure.

[0017] FIG. 2 is a top view of a stacked transistor according to embodiments of the present disclosure.

[0018] FIG. 3 is a top view of a stacked transistor according to embodiments of the present disclosure.

[0019] FIGS. 4-29 are structural diagrams of a fabrication process of a stacked transistor according to embodiments of the present disclosure.

[0020] FIG. 30 is an implementation flow diagram of a method for fabricating a stacked transistor according to embodiments of the present disclosure.

[0021] FIGS. 31-49 are structural diagrams of a fabrication process of a stacked transistor according to embodiments of the present disclosure.

[0022] FIG. 50 is a structural diagram of a stacked transistor according to embodiments of the present disclosure.

[0023] FIG. 51 is a structural diagram of a stacked transistor according to embodiments of the present disclosure.

[0024] Legend of Reference Signs Stacked transistor 10; first transistor 11; first dummy gate sidewall 111; first source-drain structure 112; first interlayer dielectric layer 113; first gate structure 114; first source-drain metal 115; first metal interconnection layer 116; second transistor 12; second dummy gate sidewall 121; second source-drain structure 122; second interlayer dielectric layer 123; second gate structure 124; second source-drain metal 125; second metal interconnection layer 126; semiconductor substrate 20; first active structure 21; second active structure 22; first recess 23; shallow trench isolation structure 24; first dummy gate structure 25; interlayer dielectric layer 26; recess 27; first gate isolation structure 28; insulating layer 29; carrier wafer 30; second dummy gate structure 31; second gate isolation structure 32; oxide layer 33; first hard mask structure 34; third dummy gate structure 35; second hard mask structure 36; second recess 37; gate isolation structure 38; third recess 39.

[0025] Embodiments

[0026] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The description herein relates to the drawings, in which the same numbers represent the same or similar elements, unless otherwise represented. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the embodiments of the present disclosure. Instead, they only illustrate apparatuses and methods consistent with some aspects of the embodiments of the present disclosure.

[0027] The terminology used in the present disclosure is solely for the purpose of describing particular embodiments and is not intended to limit the embodiments of the present disclosure. As used in the present disclosure, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "and / or," as used herein, refers to and encompasses any or all possible combinations of one or more of the associated listed items.

[0028] At the time of deepening Moore's Law, it is a hot issue in the current industry research and development to continue to promote the miniaturization of transistors. Stacked transistors can integrate two or more layers of transistors in the vertical space, which helps to further improve the transistor integration density and improve the circuit performance, and is considered as one of the important technologies to continue the size miniaturization of integrated circuits.

[0029] In an embodiment, there are two schemes for the preparation process of stacked transistors, the first one is a monolithic scheme, and the second one is a sequential scheme.

[0030] In the first scheme, N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) are fabricated on the same substrate without using wafer bonding technology. This determines that the transistors in the same layer must be of the same type, i.e., NFET or PFET. Moreover, the upper and lower layer transistors must be strictly in the same plane space without alignment deviation. The advantage of this scheme is better integration density. However, the following technical challenges exist in this scheme: (1) complex process, which requires a large amount of process technology development and optimization; (2) fixed polarity of each layer of transistors, which must rely on two layers of transistors to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, and poor design flexibility.

[0031] The second solution is to bond a wafer on top of the fabricated lower layer transistors and use the bonded wafer to fabricate the upper layer transistors, so as to vertically stack the two transistors. However, in the process of fabricating the upper layer transistors, the temperature needs to be strictly controlled to avoid affecting the lower layer transistors and the interconnection lines between the upper and lower layer transistors. The advantage of this solution is that due to wafer bonding, the device structures, channel crystal orientations and even channel materials of the upper and lower layer transistors can be different to obtain better and more matched device performance. However, the current technical challenges of this solution are as follows: (1) fabrication of high-quality top layer transistor active layer; (2) thinning and defect control of the top layer transistor bonding wafer; (3) alignment error of the upper and lower layer transistors, which requires high photolithography precision.

[0032] The common technical difficulties faced by the above two solutions include: (1) thermal stability of the bottom layer device when fabricating the top layer device; (2) performance of the top layer device under low thermal budget; (3) metal interconnection of the transistors between the top and bottom layers.

[0033] To solve the above technical problems, the embodiments of the present disclosure provide a flip-chip solution for implementing a self-aligned stacked transistor, which forms active regions of homologous transistors in upper and lower layers by etching, and realizes fabrication of stacked transistors on the front and back surfaces of a wafer by flipping, so as to overcome the disadvantages of the above two solutions. This can also be called a "self-aligned flip-chip transistor" solution.

[0034] However, in the "self-aligned flip-chip transistor" solution, a gate isolation trench needs to be formed by etching the metal gate structure after the metal gate structure is formed. After the gate isolation trench is formed, an insulating material is deposited in the gate isolation trench to realize formation of a gate isolation structure between adjacent transistor units by the insulating material. In this process, on the one hand, etching deviation is prone to occur in the process of forming the gate isolation trench due to the precision of the etching process, thereby affecting the source-drain metal structure of the source-drain region, and on the other hand, etching the metal material gate structure is more difficult in the process.

[0035] To solve the above technical problems, the embodiments of the present disclosure provide a preparation method of a stacked transistor to form a gate isolation structure before the metal gate structure is formed, so as to avoid the disadvantages of the process of forming the gate isolation structure after the metal gate structure is formed.

[0036] FIG. 1 is an implementation flowchart of a preparation method of a stacked transistor according to an embodiment of the present disclosure, referring to FIG. 1, the preparation method of the stacked transistor can include:

[0037] Step S101: etching on a semiconductor substrate to form active structures, the active structures including first active structures and second active structures, the first active structures and the second active structures being stacked in a first direction, the first active structures being farther away from the semiconductor substrate than the second active structures, the first direction being a direction perpendicular to the semiconductor substrate;

[0038] Step S102: based on the first active structures, forming a first transistor of the stacked transistor, the first transistor including a first gate structure, the first gate structure being formed by a gate replacement process, the gate replacement process including a step of replacing a dummy gate structure with a metal gate structure;

[0039] Step S103: developing and removing the semiconductor substrate;

[0040] Step S104: based on the second active structures, forming a second transistor of the stacked transistor, the second transistor including a second gate structure, the second gate structure being formed by a gate replacement process. The stacked transistor further includes a gate isolation structure, the gate isolation structure being deposited in a gate isolation region of the stacked transistor before the first gate structure and / or the second gate structure replaces the dummy gate structure. The gate isolation structure is used to electrically isolate the gate structure of the stacked transistor from a gate structure of a transistor adjacent to the stacked transistor in a second direction.

[0041] In an embodiment, the gate isolation structure can be formed by depositing an insulating material in the gate isolation region. In an embodiment, the insulating material can be a silicon nitride material. In an embodiment, the gate isolation region is located on both sides of the stacked transistor in the second direction, and at least coincides with a gate region of the stacked transistor in a third direction, the second direction being perpendicular to the first direction, and the third direction being perpendicular to the first direction and the second direction.

[0042] In an embodiment, the first direction can be a height direction of the active structures, the third direction can be an extension direction of the active structures, such as a width direction of the gate structure. The second direction can be a direction perpendicular to the extension direction of the active structures, such as a length direction of the gate structure. In the third direction, the gate structure and the source / drain structure of the stacked transistor are arranged alternately, so that the gate region and the source / drain region of the stacked transistor are arranged alternately. Then, the gate isolation region can be located at both ends of the gate structure in the second direction, and is used to electrically isolate two stacked transistor units adjacent in the second direction. Moreover, the gate isolation region can at least fall into the gate region of the stacked transistor. In an embodiment, the gate isolation region falls into the gate region, and a width of the gate isolation region in the third direction at least coincides with a width of the gate structure in the third direction.

[0043] It should be noted that the steps shown in FIG. 1 are not exclusive, and other steps can also be performed before, after or between any of the steps shown; the order of the steps shown in FIG. 1 can be adjusted according to actual needs.

[0044] In an embodiment, by etching the active structures on the semiconductor substrate at one time, the active regions of the upper and lower transistors in the stacked transistor can be self-aligned. Subsequently, the first transistor and the second transistor can be respectively prepared based on the first active structure in the active structures and the second active structure in the active structures. And before the first gate structure of the first transistor and the second gate structure of the second transistor are prepared, that is, before the metal gate replaces the dummy gate structure, the gate isolation structures located on both sides of the stacked transistor can be formed in the gate isolation region, so as to realize the formation of the metal gate structure after the gate isolation structure is formed. In this way, on the one hand, the problem of erroneous etching of the source-drain metal structure of the source-drain region when the gate isolation structure is formed after the metal gate structure is formed can be avoided, the cross-sectional area of the source-drain metal structure is increased, the resistance of the metal interconnection is reduced, and the overall unit performance is improved; on the other hand, the step of etching the metal material in the processing process can be avoided, the preparation difficulty is effectively reduced, and the process environment is friendly.

[0045] FIG. 2 is a top view of a stacked transistor according to an embodiment of the present disclosure, and FIG. 3 is a top view of a stacked transistor according to an embodiment of the present disclosure. Referring to FIGS. 2 and 3, only the fin structure, the gate structure, the source-drain structure and the gate isolation structure of the stacked transistor 10 are shown in the top views.

[0046] In an embodiment, the gate isolation structure can be arranged at both ends of the gate structure in the second direction, and only coincides with the gate region in the third direction (that is, falls within the gate region), as shown in FIG. 2. In this way, it can also be called a "isolation hole" scheme. In an embodiment, the gate isolation structure can be arranged at both ends of the gate structure in the second direction, and coincides with both the gate region and the source-drain region in the third direction (that is, falls within the gate region and the source-drain region), as shown in FIG. 3. In this way, it can also be called a "isolation line" scheme.

[0047] It should be noted that the selection of the "isolation hole" scheme or the "isolation line" scheme in the stacked transistor can be determined based on actual needs, and the embodiments of the present disclosure do not limit this.

[0048] FIGS. 4-29 are structural schematic diagrams of a preparation process of a stacked transistor according to an embodiment of the present disclosure. For ease of understanding, (a) in FIGS. 4-29 shows a cross-sectional view along the direction of dashed line A-A' in FIG. 2, (b) in FIGS. 4-29 shows a cross-sectional view along the direction of dashed line B-B' in FIG. 2, and (c) in FIGS. 4-29 shows a cross-sectional view along the direction of dashed line C-C' in FIG. 2. The first preparation method of the stacked transistor according to an embodiment of the present disclosure and the stacked transistor 10 prepared thereby will be described below with reference to FIGS. 1-29.

[0049] In step S101, referring to FIG. 5, the active structure is formed on the semiconductor substrate 20 by etching once.

[0050] In an embodiment, the active structure includes a first active structure 21 and a second active structure 22, the first active structure 21 and the second active structure 22 are stacked in a first direction, the first active structure 21 is farther away from the semiconductor substrate 20 than the second active structure 22, and the first direction is a direction perpendicular to the semiconductor substrate 20.

[0051] In an embodiment, the first active structure 21 is used to form an active region of a first transistor 11 (located at a lower layer) of the stacked transistor 10, and the second active structure 22 stacked with the first active structure 21 in the first direction is used to form an active region of a second transistor 12 (located at an upper layer) of the stacked transistor 10.

[0052] In an embodiment, a material layer deposition, epitaxial growth, photolithography, or the like can be performed on the semiconductor substrate 20, as shown in FIG. 4, to form the active structure on the semiconductor substrate 20 once. The active structure includes the first active structure 21 and the second active structure 22, and the second active structure 22 is closer to the semiconductor substrate 20 than the first active structure 21.

[0053] In an embodiment, the shape of the active structure can be different when the type of the stacked transistor 10 is different.

[0054] In an example, when the stacked transistor 10 is a fin field effect transistor, the active structure can constitute a fin structure. When the stacked transistor 10 is a gate-all-around nanosheet (GAA Nanosheet), the active structure can constitute a columnar structure; wherein the first active structure 21 and the second active structure 22 can be formed by alternately deposited silicon layers and silicon germanium layers. When the stacked transistor 10 is a planar field effect transistor, the active structure can constitute a block structure.

[0055] In an embodiment, a large etching depth can be used when forming the first active structure 21 and the second active structure 22 by photolithography. For example, the height of the fin-shaped structure (which can also be a column-shaped structure or a block-shaped structure) obtained by etching can be greater than 100 nm. It should be noted that the height of the fin-shaped structure can be set according to actual conditions, and the embodiments of the present disclosure do not limit this.

[0056] In some embodiments, the steps of the photolithography process can include: depositing a photoresist material, exposing and developing the photoresist material, removing a portion of the photoresist material, etching to remove the material layer corresponding to the portion of the photoresist material, and the like.

[0057] In some embodiments, the first transistor 11 and the second transistor 12 can be the same type of transistor. For example, the first transistor 11 and the second transistor 12 can both be fin field effect transistors.

[0058] In some embodiments, the first transistor 11 and the second transistor 12 can be different types of transistors. In an example, one transistor is a fin field effect transistor, and the other is a fully wrapped gate transistor; or, one transistor is a fin field effect transistor, and the other is a planar transistor; or, one transistor is a fully wrapped gate transistor, and the other is a planar transistor.

[0059] In an embodiment, the step of etching to form the active structure on the semiconductor substrate in step S101 can include: forming a first material layer, a second material layer, and a third material layer stacked along a first direction on the semiconductor substrate 20, and then etching the first material layer, the second material layer, and the third material layer from top to bottom in sequence to obtain the first active structure 21, the second active structure 22, and an isolation layer (not shown in the figure) between the first active structure 21 and the second active structure 22.

[0060] In an embodiment, the etched first material layer can form the second active structure 22; the etched second material layer can form the isolation layer; and the etched third material layer can form the first active structure 21. The isolation layer is used to electrically isolate the first active structure 21 and the second active structure 22. In an embodiment, the isolation layer can be formed of an oxidized material. In an embodiment, the isolation layer can be formed of a dielectric material.

[0061] It should be noted that in addition to the above embodiments, the embodiments of the present disclosure can also use other schemes to form the isolation layer between the first active structure 21 and the second active structure 22, and the embodiments of the present disclosure do not limit this. It should be noted that the materials used to form the first material layer, the second material layer, and the third material layer can be set according to actual needs, and the embodiments of the present disclosure do not limit this.

[0062] In an embodiment, the etching process can include any one of dry etching, wet etching, reactive ion etching and chemical oxide removal process, and the present disclosure is not limited thereto.

[0063] In an embodiment, the step of etching the semiconductor substrate once to form the active structure in step S101 can include: providing a wafer as shown in FIG. 4; etching the wafer to form an initial active structure with a preset depth; removing the initial active structure in the region on both sides of the stacked transistor 10 in the third direction by a fin cutting process to form the active structure as shown in FIG. 5. Ion implantation is performed in the middle part of the active structure to electrically isolate the first active structure 21 and the second active structure 22. Wherein, the region on both sides of the stacked transistor 10 in the third direction refers to the region on both sides of the stacked transistor in the C-C' direction in the cross-sectional view.

[0064] In an embodiment, the initial active structure in the region on both sides of the stacked transistor 10 can be removed by the fin cutting process, so that the active structures of the plurality of standard transistor units are disconnected with each other, and the isolation between adjacent transistor units is completed. In an example, the ions of ion implantation include P-type ions, N-type ions or oxygen ions. Wherein, the P-type ions include one or more of boron ions, gallium ions and indium ions; the N-type ions include one or more of phosphorus ions, arsenic ions and antimony ions.

[0065] In step S102, the first transistor 11 of the stacked transistor 10 is formed based on the first active structure 21 as shown in FIG. 14.

[0066] In an embodiment, the first transistor 11 in the stacked transistor 10 can be formed based on the exposed first active structure 21 by a semiconductor preparation process. Wherein, the first transistor 11 includes a first dummy gate side wall 111, a first source-drain structure 112, a first interlayer dielectric layer 113, a first gate structure 114 and a first source-drain metal 115.

[0067] In an embodiment, the first gate structure 114 can be formed by a gate replacement process.

[0068] In an embodiment, the gate replacement process includes the step of replacing the dummy gate structure with a metal gate, i.e., the step of forming the first transistor 11 including replacing the first dummy gate structure 25 with the first gate structure 114.

[0069] In some embodiments, the stacked transistor 10 further comprises a gate isolation structure, which can be formed in a gate isolation region of the stacked transistor before the first gate structure replaces the first dummy gate structure. The gate isolation region is located on both sides of the stacked transistor in the second direction, and at least overlaps with the gate region of the stacked transistor in the third direction, the second direction being perpendicular to the first direction, and the third direction being perpendicular to the first direction and the second direction. In an embodiment, the location of the gate isolation region can refer to the description in one or more of the above embodiments, which will not be described here for the sake of brevity of the description. In an embodiment, the gate isolation structure can be formed in the gate isolation region, and the gate isolation structure can constitute a "isolation hole" scheme or an "isolation line" scheme.

[0070] In the embodiments of the present disclosure, it is only necessary to remove the dummy gate structure in the gate isolation region before the metal structure replaces the dummy gate structure (the first gate structure replaces the first dummy gate structure), and to deposit an insulating material in the gate isolation region to form the gate isolation structure. The method and steps of forming other structures in the first transistor 11 can be set according to actual needs, and the embodiments of the present disclosure do not limit this.

[0071] In some embodiments, the gate isolation structure is used to electrically isolate the gate structure of the stacked transistor 10 and the gate structure of a transistor adjacent to the stacked transistor 10 in the second direction.

[0072] In some embodiments, the gate isolation structure comprises a first gate isolation structure 28 formed in the gate isolation region. Forming the first transistor 11 of the stacked transistor 10 based on the first active structure 21 in step S102 comprises: forming a shallow trench isolation structure 24 on the semiconductor substrate 20, the shallow trench isolation structure 24 wrapping the second active structure 22, and the first active structure 21 being exposed outside the shallow trench isolation structure 24; forming a first dummy gate structure 25 across the first active structure 21 and a first dummy gate sidewall 111 covering the sidewall of the first dummy gate structure 25 on the shallow trench isolation structure 24; etching the first dummy gate structure 25 in the gate isolation region to form the first gate isolation structure 28; and removing the first dummy gate structure 25 outside the gate isolation region by using a gate replacement process to form a first gate structure 114.

[0073] In an embodiment, referring to FIG. 6, after the first active structure 21 and the second active structure 22 are formed, an oxide material can be deposited on the semiconductor substrate 20 to form a shallow trench isolation (STI) structure 24. The shallow trench isolation structure 24 wraps the second active structure 22, and the first active structure 21 is exposed outside the shallow trench isolation structure 24. The oxide forming the shallow trench isolation structure 24 can be a silicon-based oxide (SiOx, x is the number of oxygen atoms), such as silicon dioxide (SiO2), etc.

[0074] In an embodiment, after the shallow trench isolation structure 24 is formed, a first dummy gate structure 25 spanning the first active structure 21 and a first dummy gate sidewall 111 covering the sidewall of the first dummy gate structure 25 can be formed on the shallow trench isolation structure 24, referring to FIGS. 7-8. Then, the first dummy gate structure 25 in the gate isolation region, that is, the part of the first dummy gate structure 25 at both ends in the second direction, is etched. After the first dummy gate structure 25 in the gate isolation region is removed, a groove 27 can be formed, referring to FIG. 9. The height of the groove bottom of the groove 27 is equal to the height of the lowest part of the first active structure 21. Then, an insulating material can be deposited at the position where the first dummy gate structure 25 is removed to form a first gate isolation structure 28, referring to FIG. 10. At this time, the first gate isolation structure 28 is opposite to the position where the first transistor 11 in the stacked transistor 10 is located, and can also be understood as the first gate isolation structure 28 being on both sides of the first transistor 11 in the second direction.

[0075] In an embodiment, the material forming the dummy gate structure can be polysilicon, amorphous silicon, etc., and the material forming the dummy gate sidewall can be silicon oxide, silicon nitride, etc. In an example, the first dummy gate sidewall 111 can have a single-layer structure and be made of the same material (such as porous silicon carbide oxide hydride (SiCOH)).

[0076] In an embodiment, after the first gate isolation structure 28 is formed, a gate replacement process can be used to remove the first dummy gate structure 25 outside the gate isolation region, that is, to remove the first dummy gate structure 25 still existing after the first gate isolation structure 28 is formed, and to deposit a gate material at the position where the first dummy gate structure 25 is removed, thereby forming a first gate structure 114 of the first transistor 11, referring to FIG. 13. The first gate structure 114 at least includes a first gate dielectric layer and a first gate electrode layer. The materials of the gate dielectric layer and the gate electrode layer can be set according to actual needs, and the embodiments of the present disclosure are not limited thereto.

[0077] In an example, the first gate dielectric layer can be composed of a silicon oxide layer and a high-K hafnium oxide layer, and the thickness of the silicon oxide layer and the hafnium oxide layer can be determined according to the polarity and performance of the first transistor 11. The first gate electrode layer can be composed of multiple layers of electrode materials, each layer of electrode material including but not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0078] In an example, the first gate dielectric layer can include a 0.6 nm silicon oxide layer and a 1.7 nm hafnium oxide layer.

[0079] In some embodiments, the method of forming the first transistor 11 further includes: before etching the first dummy gate structure 25 located in the gate isolation region to form the first gate isolation structure 28, forming the first source-drain structure 112 of the first transistor 11 between the first dummy gate sidewalls 111 of the two adjacent first dummy gate structures 25 based on the first active structure 21; or after etching the first dummy gate structure 25 located in the gate isolation region to form the first gate isolation structure 28, forming the first source-drain structure 112 of the first transistor 11 between the first dummy gate sidewalls 111 of the two adjacent first dummy gate structures 25 based on the first active structure 21.

[0080] In an embodiment, the first source-drain structure 112 of the first transistor 11 can be formed before the metal gate replaces the dummy gate structure, i.e., the first gate structure 114 replaces the first dummy gate structure 25. Then, the first source-drain structure 112 of the first transistor 11 can be formed between the first dummy gate sidewalls 111 of the two adjacent first dummy gate structures 25 based on the first active structure 21 before etching the first dummy gate structure 25 located in the gate isolation region to form the first gate isolation structure 28, or the first source-drain structure 112 of the first transistor 11 can be formed between the first dummy gate sidewalls 111 of the two adjacent first dummy gate structures 25 based on the first active structure 21 after etching the first dummy gate structure 25 located in the gate isolation region to form the first gate isolation structure 28. The present disclosure does not limit this.

[0081] In an example, FIGS. 23-25 show that the first source-drain structure 112 of the first transistor 11 can be formed between the first dummy gate sidewalls 111 of the two adjacent first dummy gate structures 25 based on the first active structure 21 before etching the first dummy gate structure 25 located in the gate isolation region to form the first gate isolation structure 28. FIGS. 10-12 show that the first source-drain structure 112 of the first transistor 11 can be formed between the first dummy gate sidewalls 111 of the two adjacent first dummy gate structures 25 based on the first active structure 21 after etching the first dummy gate structure 25 located in the gate isolation region to form the first gate isolation structure 28.

[0082] In one embodiment, the first source / drain structure 112 is formed after the formation of the first gate isolation structure 28. Then, the dielectric material can be filled in the source / drain region of the stacked transistor 10 during the formation of the first gate isolation structure 28 to ensure the normal fabrication of the stacked transistor 10.

[0083] In one example, the interlayer dielectric material is deposited in the source / drain region of the stacked transistor 10 to form the interlayer dielectric layer 26 before the formation of the first gate isolation structure 28, as shown in FIG. 8. The interlayer dielectric layer 26 is removed after the formation of the first gate isolation structure 28, as shown in FIG. 11.

[0084] In some embodiments, the first dummy gate structure 25 in the gate isolation region is etched simultaneously with the first dummy gate sidewall 111 and the interlayer dielectric layer 26 in the gate isolation region to form the first gate isolation structure 28. In this case, the first gate isolation structure 28 constitutes a "isolation line" scheme.

[0085] In one embodiment, the source / drain region of the stacked transistor 10 can be a region for forming the source / drain structure, and the gate region can be a region for forming the gate structure.

[0086] In some embodiments, the first active structure 21 in the source / drain region of the stacked transistor 10 can be etched to form a first source / drain recess, and a first source / drain structure 112 can be epitaxially grown in the first source / drain recess. After the formation of the first source / drain structure 112, an insulating material can be deposited on the first source / drain structure 112 to form a first interlayer dielectric layer 113, as shown in FIG. 12.

[0087] In one embodiment, the first source / drain recess can be formed on the first active structure 21 by using a fin recess process. In one embodiment, a strained material such as silicon germanium or silicon carbide can be formed in the first source / drain recess by selective epitaxial growth to fill the first source / drain recess, and then a first source / drain structure 112 can be formed on the strained material by a heavy doping process, as shown in FIG. 12.

[0088] In some embodiments, after the formation of the first gate structure 114, the first interlayer dielectric layer 113 can be etched to expose the first source / drain structure 112, and a metal material can be deposited on the first source / drain structure 112 to form a first source / drain metal 115, as shown in FIG. 14.

[0089] In an embodiment, after the first gate structure 114 and the first source-drain metal 115 are formed, a first metal interconnection layer 116 can be formed on the first gate structure 114 and the first source-drain metal 115 by using standard post-processes of semiconductor manufacturing (such as interconnection line medium deposition, metal line formation, lead pad formation, etc.), as shown in FIG. 14.

[0090] It should be noted that, for the convenience of description, the first source-drain structure mentioned in the embodiments of the present disclosure is a short form, which refers to the first source structure and / or the first drain structure. In addition, the second source-drain structure, the first source-drain metal, the second source-drain metal, etc. are similar to the first source-drain recess, and the "source-drain" therein is a short form of "source and / or drain".

[0091] It should be noted that the above one or more embodiments only show the preparation process of the transistor type being fin field effect transistor. Those skilled in the art should know that when the transistor type of the first transistor 11 and the second transistor 12 is of other types, the embodiments of the present disclosure also include standard preparation processes corresponding to other types of transistors. For the sake of brevity of the description, no further description is given here.

[0092] In step S103, the semiconductor substrate is inverted and removed.

[0093] In an embodiment, after the first transistor 11 is obtained, the first transistor 11 can be inverted so that the prepared first transistor 11 is located at the bottom, and the second active structure 22 for preparing the second transistor 12 can be located at the upper part, which facilitates the subsequent preparation of the second transistor 12.

[0094] Referring to FIG. 15, after the post-process of the first transistor 11 is completed, the first transistor 11 can be bonded with the carrier wafer 30. In an example, after the first metal interconnection layer 116 is deposited with an insulating material (such as silicon oxide), an insulating layer 29 can be formed, and the insulating layer 29 can be bonded with the carrier wafer 30. Then, the semiconductor substrate 20 can be inverted, and after the inversion, the first transistor 11 is located at the bottom of the stacked transistor 10.

[0095] In the embodiments of the present disclosure, the carrier wafer 30 after bonding can provide physical support for the inverted first transistor 11 after inversion, effectively preventing the first transistor 11 from being broken by external force during the preparation of the second transistor 12. In an embodiment, after inversion, the semiconductor substrate 20 can be removed by polishing treatment or chemical mechanical planarization treatment to expose the second active structure 22, as shown in FIG. 16.

[0096] In step S104, based on the second active structure 22, the second transistor 12 of the stacked transistor 10 is formed.

[0097] In an embodiment, after the first transistor 11 is formed, the second transistor 12 in the stacked transistor 10 can be formed based on the exposed second active structure 22 by using semiconductor manufacturing processes. The second transistor 12 includes a second dummy gate sidewall 121, a second source-drain structure 122, a second interlayer dielectric layer 123, a second gate structure 124, and a second source-drain metal 125. The second gate structure 124 can be formed by using a gate replacement process. In an embodiment, the gate replacement process includes a step of replacing the dummy gate structure with a metal gate, i.e., a step of replacing the second dummy gate structure 31 with the second gate structure 124 to form the second transistor 12.

[0098] In some embodiments, the stacked transistor 10 further includes a gate isolation structure, which can be formed by deposition in a gate isolation region of the stacked transistor 10 before the second gate structure 124 replaces the second dummy gate structure 31.

[0099] In an embodiment, in the embodiments of the present disclosure, only the dummy gate structure in the gate isolation region needs to be removed before the metal structure replaces the dummy gate structure (the second gate structure 124 replaces the second dummy gate structure 31), and the insulating material is deposited in the gate isolation region to form the gate isolation structure. The method and steps for forming other structures in the second transistor 12 can be set according to actual needs, and the embodiments of the present disclosure do not limit this.

[0100] In some embodiments, the gate isolation structure includes a second gate isolation structure 32 formed in the gate isolation region. The step S104 of forming the second transistor 12 of the stacked transistor 10 based on the second active structure 22 includes: thinning the shallow trench isolation structure 24 to expose the second active structure 22 wrapped by the shallow trench isolation structure 24; forming the second dummy gate structure 31 across the second active structure 22 and the second dummy gate sidewall 121 covering the sidewall of the second dummy gate structure 31; etching the second dummy gate structure 31 in the gate isolation region to form the second gate isolation structure 32; and removing the second dummy gate structure 31 outside the gate isolation region by using a gate replacement process to form the second gate structure 124.

[0101] In an embodiment, referring to FIG. 17, after step S103, an end of the second active structure 22 close to the first end of the semiconductor substrate 20 can be exposed. Then, the shallow trench isolation structure 24 wrapping the second active structure 22 can be thinned to a preset height to expose the second active structure 22. The preset height can be set according to actual needs, which is not limited in the embodiments of the present disclosure. In an embodiment, the shallow trench isolation structure 24 of the preset height is used to isolate the first gate structure 114 of the first transistor 11 and the second gate structure 124 of the second transistor 12; and the shallow trench isolation structure 24 of the preset height is also used to isolate the first source-drain structure 112 of the first transistor 11 and the second source-drain structure 122 of the second transistor 12.

[0102] In an embodiment, based on the exposed second active structure 22, a second dummy gate structure 31 spanning the second active structure 22 and a second dummy gate sidewall 121 covering the sidewall of the second dummy gate structure 31 can be formed. The second dummy gate structure 31 is arranged in the third direction, referring to FIG. 18. Then, the second dummy gate structure 31 in the gate isolation region, that is, a part of the second dummy gate structure 31 located at both ends in the second direction, can be etched. After the second dummy gate structure 31 in the gate isolation region is removed, an insulating material can be deposited at the position where the second dummy gate structure 31 is removed to form a second gate isolation structure 32, referring to FIG. 19. At this time, the second gate isolation structure 32 is opposite to the position where the second transistor 12 of the stacked transistor 10 is located, which can also be understood as that the second gate isolation structure 32 is located on both sides of the second transistor 12 in the second direction.

[0103] In an embodiment, after the second gate isolation structure 32 is formed, a gate replacement process can be used to remove the second dummy gate structure 31 located outside the gate isolation region, that is, to remove the second dummy gate structure 31 still existing after the second gate isolation structure 32 is formed, and to deposit a gate material at the position where the second dummy gate structure 31 is removed, so as to form the second gate structure 124 of the second transistor 12, referring to FIG. 21.

[0104] In an embodiment, the second gate structure 124 at least includes a second gate dielectric layer and a second gate electrode layer. The materials of the gate dielectric layer and the gate electrode layer can be set according to actual needs, which is not limited in the embodiments of the present disclosure. The second gate structure 124 can be the same as or different from the first gate structure 114, which is not limited in the embodiments of the present disclosure.

[0105] In some embodiments, the method of forming the second transistor 12 further comprises: before etching the second dummy gate structure 31 within the gate isolation region to form the second gate isolation structure 32, forming the second source-drain structure 122 of the second transistor 12 between the second dummy gate spacers 121 of two adjacent second dummy gate structures 31 based on the second active structure 22; or after etching the second dummy gate structure 31 within the gate isolation region to form the second gate isolation structure 32, forming the second source-drain structure 122 of the second transistor 12 between the second dummy gate spacers 121 of two adjacent second dummy gate structures 31 based on the second active structure 22, as shown in FIG. 20.

[0106] In an embodiment, the second source-drain structure of the second transistor 12 can be formed before the second gate structure replaces the second dummy gate structure 31, i.e. the second gate structure replaces the second dummy gate structure 31. Then, the second source-drain structure of the second transistor 12 can be formed between the second dummy gate spacers 121 of two adjacent second dummy gate structures 31 based on the second active structure 22 before etching the second dummy gate structure 31 within the gate isolation region to form the second gate isolation structure 32; or the second source-drain structure of the second transistor 12 can be formed between the second dummy gate spacers 121 of two adjacent second dummy gate structures 31 based on the second active structure 22 after etching the second dummy gate structure 31 within the gate isolation region to form the second gate isolation structure 32; the present disclosure does not limit this.

[0107] In an embodiment, the second source-drain structure 122 is formed after the second gate isolation structure 32 is formed. Then, the medium material can be filled in the source-drain region of the stacked transistor 10 during the formation of the second gate isolation structure 32 to ensure the normal preparation of the stacked transistor 10.

[0108] In some embodiments, the method of forming the second active structure 22, the second interlayer dielectric layer 123 and the second source-drain metal 125 can refer to one or more embodiments of forming the first transistor 11 described above, which will not be described herein for the sake of brevity of the description.

[0109] In some embodiments, after the second gate structure 124 and the second source-drain metal 125 are formed, the second metal interconnection layer 126 can be formed on the second gate structure 124 and the second source-drain metal 125 by using the standard post-process of semiconductor preparation (such as interconnection line medium deposition, metal line formation, lead pad formation, etc.), as shown in FIG. 22.

[0110] So far, the preparation process of the first stacked transistor 10 is completed.

[0111] In the embodiments of the present disclosure, by etching the active structures on the semiconductor substrate at one time, the active regions of the upper and lower transistors in the stacked transistor can be self-aligned. Then, the first transistor and the second transistor can be respectively prepared based on the first active structure and the second active structure in the active structures. Moreover, before the first gate structure of the first transistor and the second gate structure of the second transistor are prepared, that is, before the metal gate replaces the dummy gate structure, the gate isolation structures located on both sides of the stacked transistor can be formed, so that the metal gate structure is formed after the gate isolation structure is formed. In this way, on the one hand, the problem of erroneous etching of the source / drain metal structure of the source / drain region when the gate isolation structure is formed after the metal gate structure is formed can be avoided, the cross-sectional area of the source / drain metal structure is increased, the metal interconnection resistance is reduced, and the overall unit performance is improved; on the other hand, the step of etching the metal material in the process can be avoided, the preparation difficulty is effectively reduced, and the process environment is friendly.

[0112] In some possible embodiments, etching the first dummy gate structure 25 in the gate isolation region to form the first gate isolation structure 28 comprises: etching the first dummy gate structure 25 in the gate isolation region and the shallow trench isolation structure 24 in the gate isolation region until the semiconductor substrate 20 in the gate isolation region is exposed, to form a first recess; and depositing an insulating material in the first recess to form the first gate isolation structure 28.

[0113] In an embodiment, as shown in FIG. 26, after the shallow trench isolation structure 24 is formed on the semiconductor substrate 20, the first dummy gate structure 25 crossing the first active structure 21 and the first dummy gate sidewall 111 covering the sidewall of the first dummy gate structure 25 can be formed on the shallow trench isolation structure 24. Then, the first dummy gate structure 25 in the gate isolation region and the shallow trench isolation structure 24 in the gate isolation region can be etched until the semiconductor substrate 20 in the gate isolation region is exposed, so as to form a first recess 23, as shown in FIG. 27. The height of the bottom of the first recess 23 is lower than the height of the lowest part of the first active structure 21. Then, an insulating material can be deposited in the first recess 23 to form the first gate isolation structure 28, as shown in FIG. 28. At this time, the first gate isolation structure 28 is located on both sides of the first transistor 11 and the shallow trench isolation structure 24 in the second direction.

[0114] In some embodiments, when the first gate isolation structures 28 are located on both sides of the first transistors 11 and the shallow trench isolation structures 24 in the second direction, the second transistors 12 of the stacked transistors 10 are formed based on the second active structures 22, including: thinning the shallow trench isolation structures 24 located between the first gate isolation structures 28 to expose the second active structures 22 wrapped by the shallow trench isolation structures 24; based on the exposed second active structures 22, forming second dummy gate structures 31 across the second active structures 22 and second dummy gate sidewalls 121 covering the sidewalls of the second dummy gate structures 31; and removing the second dummy gate structures 31 located between the first gate isolation structures 28 by using a gate replacement process to form second gate structures.

[0115] In an embodiment, when the first gate isolation structures 28 are located on both sides of the first transistors 11 and the shallow trench isolation structures 24 in the second direction, the first gate isolation structures 28 are opposite to the first transistors 11 and the second transistors 12. At this time, the shallow trench isolation structures 24 wrapping the second active structures 22 located between the first gate isolation structures 28 can be thinned to expose the second active structures 22. Based on the exposed second active structures 22, the second dummy gate structures 31 across the second active structures 22 and the second dummy gate sidewalls 121 covering the sidewalls of the second dummy gate structures 31 can be formed between the first gate isolation structures 28. Then, the second dummy gate structures 31 located between the first gate isolation structures 28 can be removed by using a gate replacement process, and a gate material is deposited at the positions where the second dummy gate structures 31 are removed to form second gate structures. In this way, the stacked transistors 10 are obtained, as shown in FIG. 29.

[0116] FIG. 30 is an implementation flow diagram of a method for manufacturing a stacked transistor according to an embodiment of the present disclosure, and FIGS. 31-49 are structural diagrams of a manufacturing process of a stacked transistor according to an embodiment of the present disclosure. For ease of understanding, (a) in FIGS. 31-49 shows a cross-sectional view along the direction of dashed line A-A' in FIG. 2, (b) in FIGS. 31-49 shows a cross-sectional view along the direction of dashed line B-B' in FIG. 2, and (c) in FIGS. 31-49 shows a cross-sectional view along the direction of dashed line C-C' in FIG. 2. The second manufacturing method of the stacked transistor according to an embodiment of the present disclosure and the stacked transistor 10 manufactured by the method will be described below with reference to FIGS. 2-3 and 31-49.

[0117] In step S3001, referring to FIG. 31, the active structures are formed on the semiconductor substrate 20 by etching once.

[0118] In an embodiment, the method for forming the active structures in step S3001 can refer to the description in one or more embodiments of step S101. For the sake of brevity of the description, the details are not described herein.

[0119] In step S3002, a first semiconductor structure is formed based on the first active structure 21.

[0120] In an embodiment, the first semiconductor structure in the stacked transistor 10 can be formed based on the exposed first active structure 21 by using a semiconductor fabrication process. The first semiconductor structure is used to form the first transistor 11. In an embodiment, the first transistor 11 includes a first dummy gate sidewall 111, a first source-drain structure 112, a first interlayer dielectric layer 113, a first gate structure 114, and a first source-drain metal 115. In an embodiment, the first gate structure 114 can be formed by using a gate replacement process.

[0121] It is noted that in the second fabrication method of the stacked transistor 10, the dummy gate structure is a dummy gate structure shared by the upper and lower transistors.

[0122] In an embodiment, the gate replacement process includes a step of replacing the dummy gate structure with a metal gate, i.e., a step of forming a third dummy gate structure 35 shared by the first transistor 11 and the second transistor 12, and replacing the third dummy gate structure 35 with the first gate structure 114 and the second gate structure 124.

[0123] In an embodiment, the gate isolation structure 38 is formed in the gate isolation region of the stacked transistor 10 before the first gate structure 114 and the second gate structure 124 replace the dummy gate structure. That is, the gate isolation structure 38 can be formed during the formation of the first semiconductor structure before the wafer is flipped; or the gate isolation structure 38 can be formed during the formation of the first transistor 11 and the second transistor 12 after the wafer is flipped.

[0124] In an embodiment, the definition of the gate isolation region can refer to the description in one or more embodiments described above, and will not be described here for the sake of brevity of the description.

[0125] In some embodiments, when the gate isolation structure 38 is formed during the formation of the first semiconductor structure, the step of forming the first semiconductor structure based on the first active structure 21 in step S3002 includes: depositing a hard mask material on the semiconductor substrate 20 to form a first hard mask structure 34; forming a third dummy gate structure 35 spanning the active structure and a third dummy gate sidewall covering the sidewall of the third dummy gate structure 35 on the first hard mask structure 34; removing the first hard mask structure 34 on the semiconductor substrate 20 that is not covered by the third dummy gate structure 35 to form a second hard mask structure 36; etching the third dummy gate structure 35 in the gate isolation region until the second hard mask structure 36 to form a second recess 37, and depositing an insulating material in the second recess 37 to form the gate isolation structure.

[0126] In one embodiment, a hard mask material can be deposited on the semiconductor to form a first hard mask structure 34 for the first end portion of the second active structure 22, as shown in FIG. 32. In one embodiment, the first end portion is a portion of the second active structure 22 close to the semiconductor substrate 20. Subsequently, a third dummy gate structure 35 spanning the active structure and a third dummy gate sidewall covering the sidewall of the third dummy gate structure 35 can be formed on the first hard mask structure 34, as shown in FIG. 33. Then, the first hard mask structure 34 not covered by the third dummy gate structure 35 on the semiconductor substrate 20 is removed to form a second hard mask structure, as shown in FIG. 34. At this time, the hard mask structure within the source / drain region of the stack transistor 10 is removed, leaving only the hard mask structure within the gate region of the stack transistor 10. Subsequently, the third dummy gate structure 35 within the gate isolation region can be etched until the second hard mask structure 36 to form a second recess 37, the bottom of which is formed by the second hard mask structure 36, as shown in FIG. 37. Then, an insulating material is deposited in the second recess 37 to form a gate isolation structure, as shown in FIG. 38.

[0127] In some embodiments, after the second hard mask structure 36 is formed, the first source / drain structure 112 of the first transistor 11 can be formed based on the first active structure 21 within the source / drain region.

[0128] In one embodiment, as shown in FIGS. 35-36, a shallow trench isolation structure 24 can be formed by depositing in the source / drain region, which wraps the second active structure 22, and then the first source / drain structure 112 can be formed based on the exposed first active structure 21. Moreover, the first source / drain structure 112 can be wrapped by a first interlayer dielectric layer 113.

[0129] In some embodiments, after the first source / drain structure 112 is formed, a first metal interconnection layer 116 can be formed by using standard back-end-of-line (BEOL) processes of semiconductor manufacturing, such as interconnection line dielectric deposition, metal line formation, and lead pad formation, etc., as shown in FIG. 39.

[0130] In some embodiments, before the first semiconductor structure is formed based on the first active structure 21, the method further comprises: depositing an oxide material on the semiconductor substrate 20 and the active structure to form an oxide layer 33 covering the semiconductor substrate 20 and wrapping the active structure. In one embodiment, the oxide layer wrapping the active structure can effectively prevent the active structure from collapsing. In one example, as shown in FIG. 32, the oxide layer 33 is formed on the semiconductor substrate 20 and the active structure, and the first hard mask structure 34 is formed on the oxide layer 33.

[0131] In step S3003, the semiconductor substrate 20 is developed and removed.

[0132] In one embodiment, the method of removing the semiconductor substrate 20 in step S3003 can refer to the description in one or more embodiments corresponding to step S103, which will not be repeated here for the sake of brevity of the description.

[0133] In one example, as shown in FIG. 34, after the semiconductor substrate 20 is removed, the second hard mask structure 36 can be exposed.

[0134] In some embodiments, removing the semiconductor substrate 20 includes: removing the semiconductor substrate 20 to expose the oxide layer 33, as shown in FIG. 40; and then removing the oxide layer 33.

[0135] In step S3004, the first transistor 11 and the second transistor 12 are formed based on the second active structure 22 and the first semiconductor structure.

[0136] In one embodiment, after the first semiconductor structure is prepared, the second transistor 12 in the stacked transistor 10 can be formed based on the exposed second active structure 22 using a semiconductor preparation process; and the second transistor 12 in the stacked transistor 10 can be formed based on the first semiconductor structure using a semiconductor preparation process. The second transistor 12 includes a second dummy gate sidewall 121, a second source-drain structure 122, a second interlayer dielectric layer 123, a second gate structure 124, and a second source-drain metal 125. In one embodiment, the second gate structure 124 can be formed using a gate replacement process.

[0137] In some embodiments, forming the first transistor 11 and the second transistor 12 based on the second active structure 22 and the first semiconductor structure includes: using the second hard mask structure 36 as a hard mask, selectively etching the second active structure 22 until the height of the second active structure 22 is less than the height of the third dummy gate structure 35 to form a third recess 39; depositing a dummy gate material in the third recess 39 to form a fourth dummy gate structure; removing the third dummy gate structure 35 and the fourth dummy gate structure between the gate isolation structures; forming the first gate structure 114 of the first transistor 11 between the gate isolation structures; and forming the second gate structure of the second transistor 12 above the first gate structure 114 of the first transistor 11.

[0138] In one embodiment, after the second active structure 22 is exposed, the second active structure 22 can be selectively etched with the second hard mask structure 36 as a hard mask until the height of the second active structure 22 is less than the height of the third dummy gate structure 35. At this time, the third recess 39 can be formed in the gate region of the stacked transistor 10, and the bottom of the third recess 39 is formed by the second active structure 22, as shown in FIG. 41. Subsequently, the hard mask structure can be removed, and a dummy gate material can be deposited in the third recess 39 using an anisotropic process to form a fourth dummy gate structure (sharing the reference number 35 with the third dummy gate structure), as shown in FIG. 42. Since the fourth dummy gate structure is formed based on the anisotropic process, the fourth dummy gate structure can grow rapidly in the third recess 39, and the fourth dummy gate structure is self-aligned with the third dummy gate structure 35. Subsequently, the third dummy gate structure 35 and the fourth dummy gate structure between the gate isolation structures can be removed. The first gate structure 114 of the first transistor 11 is formed between the gate isolation structures; and the second gate structure 124 of the second transistor 12 is formed on the first gate structure 114 of the first transistor 11, as shown in FIG. 43.

[0139] In one embodiment, after the first gate structure 114 is formed, the first semiconductor structure can be prepared to form the first transistor 11, and after the second gate structure 124 is formed, the second transistor 12 can be formed. In some embodiments, the second source / drain structure 122 of the second transistor 12 can be formed before the second gate structure 124 is formed. In one embodiment, the process of forming the second source / drain structure 122 can refer to the description in one or more embodiments described above, and will not be described herein for the sake of brevity. In some embodiments, the second metal interconnection layer 126 can be formed after the second gate structure 124 is formed, as shown in FIG. 43.

[0140] So far, the preparation process of the second stacked transistor 10 is completed.

[0141] In some possible implementations, when the gate isolation structure 38 is not formed during the formation of the first semiconductor structure, the first semiconductor structure is formed based on the first active structure 21, including: depositing a hard mask material on the semiconductor substrate 20 to form a first hard mask structure 34, the first hard mask structure 34 wrapping a first end portion of the second active structure 22, the first end portion being a portion of the second active structure 22 close to the semiconductor substrate 20; forming a third dummy gate structure 35 spanning the active structure and a third dummy gate sidewall covering the sidewall of the third dummy gate structure 35 on the first hard mask structure 34; removing the first hard mask structure 34 on the semiconductor substrate 20 that is not covered by the third dummy gate structure 35 to form a second hard mask structure 36.

[0142] In an embodiment, after the first hard mask structure 34 is formed, a third dummy gate structure 35 spanning the active structure and a third dummy gate spacer covering the sidewall of the third dummy gate structure 35 can be formed on the first hard mask structure 34. Then, the first hard mask structure 34 not covered by the third dummy gate structure 35 can be removed to form a second hard mask structure 36.

[0143] In some embodiments, the first source / drain structure 112, the first source / drain metal 115 and the first metal interconnection layer 116 can also be formed in the source / drain region of the stacked transistor 10, as shown in FIG. 44.

[0144] In the embodiments of the present disclosure, compared with the scheme of forming the gate isolation structure in the process of forming the first semiconductor structure, the scheme of not forming the gate isolation structure has fewer steps in the process of forming the first semiconductor structure.

[0145] In some embodiments, when the gate isolation structure 38 is not formed in the process of forming the first semiconductor structure, based on the second active structure 22 and the first semiconductor structure, the first transistor 11 and the second transistor 12 are formed, including: taking the second hard mask structure 36 as a hard mask, selectively etching the second active structure 22 until the height of the second active structure 22 is less than the height of the third dummy gate structure 35 to form a third recess 39; depositing a dummy gate material in the third recess 39 to form a fourth dummy gate structure, the fourth dummy gate structure being self-aligned with the third dummy gate structure 35, as shown in FIG. 45. Then, an interlayer dielectric layer can be formed in the source / drain region, as shown in FIG. 46. Then, the third dummy gate structure 35 located in the gate isolation region and the fourth dummy gate structure located in the gate isolation region can be etched to form a fourth recess, as shown in FIG. 47, and an insulating material is deposited in the fourth recess to form the gate isolation structure 38, as shown in FIG. 48. Then, the third dummy gate structure 35 and the fourth dummy gate structure between the gate isolation structures are removed; the first gate structure 114 of the first transistor 11 is formed between the gate isolation structures; the second gate structure 124 of the second transistor 12 is formed on the first gate structure 114 of the first transistor 11, as shown in FIG. 49.

[0146] In one embodiment, after the second active structure 22 is exposed, the second active structure 22 can be selectively etched with the second hard mask structure 36 as a hard mask until the height of the second active structure 22 is less than the height of the third dummy gate structure 35. At this time, the third recess 39 can be formed in the gate region of the stacked transistor 10, and the bottom of the third recess 39 is formed by the second active structure 22. Subsequently, the hard mask structure can be removed, and the dummy gate material can be deposited in the third recess 39 by using an anisotropic process to form a fourth dummy gate structure. Since the fourth dummy gate structure is formed based on the anisotropic process, the fourth dummy gate structure can be rapidly grown in the third recess 39, and the fourth dummy gate structure is self-aligned with the third dummy gate structure 35. Subsequently, the third dummy gate structure 35 in the gate isolation region and the fourth dummy gate structure in the gate isolation region can be etched to form a fourth recess, and an insulating material can be deposited in the fourth recess to form the gate isolation structure 38.

[0147] In one embodiment, after the first gate structure 114 is formed, the first semiconductor structure can be prepared to form the first transistor 11, and after the second gate structure is formed, the second transistor 12 can be formed.

[0148] In the embodiments of the present disclosure, by etching the active structures on the semiconductor substrate at one time, the active regions of the upper and lower transistors in the stacked transistor can be self-aligned. Subsequently, the first transistor and the second transistor can be prepared based on the first active structure in the active structures and the second active structure in the active structures, respectively. Moreover, before the first gate structure of the first transistor and the second gate structure of the second transistor are prepared, that is, before the metal gate replaces the dummy gate structure, the gate isolation structures on both sides of the stacked transistor can be formed, so that the metal gate structure is formed after the gate isolation structure is formed. In this way, on the one hand, the problem of erroneous etching of the source / drain metal structure of the source / drain region when the gate isolation structure is formed after the metal gate structure is formed can be avoided, the cross-sectional area of the source / drain metal structure is increased, the metal interconnection resistance is reduced, and the overall cell performance is improved. On the other hand, the step of etching the metal material in the process can be avoided, the preparation difficulty is effectively reduced, and the process environment is friendly.

[0149] In embodiments of the present disclosure, a stacked transistor is provided, which can be prepared by the method in one or more embodiments of FIG. 2 to FIG. 49. FIG. 50 is a structural schematic diagram of a stacked transistor according to an embodiment of the present disclosure; FIG. 51 is a structural schematic diagram of a stacked transistor according to an embodiment of the present disclosure. Referring to FIG. 29, FIG. 49 to FIG. 51, the stacked transistor 10 includes a first transistor 11 and a second transistor 12, the first transistor 11 and the second transistor 12 are stacked, and a first active structure 21 of the first transistor 11 and a second active structure 22 of the second transistor 12 form an active structure; the first transistor 11 includes a first gate structure 114, and the second transistor 12 includes a second gate structure.

[0150] In an embodiment, the stacked transistor 10 further includes a gate isolation structure, which is deposited in a gate isolation region of the stacked transistor 10 before the first gate structure 114 and the second gate structure are replaced by the dummy gate structure; the gate isolation region is located on both sides of the stacked transistor 10 in a second direction, and at least coincides with a gate region of the stacked transistor 10 in a third direction, the second direction is perpendicular to the first direction, and the third direction is perpendicular to the first direction and the second direction; the gate isolation structure is used to electrically isolate the gate structure of the stacked transistor 10 and the gate structure of a transistor adjacent to the stacked transistor 10 in the second direction.

[0151] In some embodiments, the first transistor 11 or the second transistor 12 can be any one of a fin field effect transistor, a fully wrapped gate field effect transistor, and a planar field effect transistor.

[0152] In an example, referring to FIG. 49, the first transistor 11 and the second transistor 12 are fin field effect transistors; referring to FIG. 50, the first transistor 11 and the second transistor 12 are fully wrapped gate field effect transistors; referring to FIG. 51, the first transistor 11 and the second transistor 12 are planar field effect transistors.

[0153] In an embodiment, the structure of the gate isolation structure in embodiments of the present disclosure can refer to the description in one or more embodiments described above, and for the sake of brevity of the description, it will not be repeated here.

[0154] In an embodiment, the gate isolation structure of the stacked transistor in the embodiment of the present disclosure is formed by deposition in the gate isolation region of the stacked transistor before the first gate structure and the second gate structure replace the dummy gate structure. In this way, on the one hand, the problem of erroneous etching of the source-drain metal structure of the source-drain region when the gate isolation structure is formed after the metal gate structure is formed can be avoided, the cross-sectional area of the source-drain metal structure can be increased, the resistance of the metal interconnection can be reduced, and the overall unit performance can be improved. On the other hand, the step of etching the metal material can be avoided in the processing process, the preparation difficulty can be effectively reduced, and the process environment is friendly.

[0155] It should be noted that the present embodiment provides a plurality of preparation methods for forming a gate isolation structure, and a gate isolation structure formed based on the preparation method, thereby facilitating the cost and performance requirements in different application scenarios, and effectively improving the flexibility of application. At the same time, in one or more embodiments of the above preparation of the stacked transistor, the stacked transistor also has self-alignment, which on the one hand solves the long-standing problems of process complexity and alignment difficulty existing in the existing mainstream technical solutions of the stacked transistor, and promotes the industrialization of the transistor stacking technology. On the other hand, through the self-aligned "back-to-back" active structure and gate structure, the upper and lower transistors can have independent signal and power supply networks, and are connected through the stacked transistor interconnection, which greatly releases the metal wiring resources.

[0156] Finally, the scheme of the upper and lower transistors through flip-chip is compatible with the existing mainstream device architecture, and can realize the front and back stacking of planar field effect transistors, fin field effect transistors, full-surround gate field effect transistors, and even vertical field effect transistors. Without special process development for specific device architecture, the flexibility is strong, and the extendability is strong from the perspective of semiconductor process node iteration. The flip-chip transistor is very advanced in concept, has important industrial value, and has strong practicality and wide development prospects.

[0157] The embodiment of the present disclosure provides a semiconductor device, which comprises the stacked transistor of the above embodiment. The definition of the stacked transistor can be referred to the stacked transistor shown in FIG. 29, FIG. 49 to FIG. 51, which will not be repeated here.

[0158] The embodiment of the present disclosure provides an electronic device, which comprises a circuit board and a semiconductor device as described in the above embodiment, and the semiconductor device is arranged on the circuit board. The semiconductor device comprises the stacked transistor described above. The definition of the stacked transistor can be referred to the structure shown in FIG. 29, FIG. 49 to FIG. 51, which will not be repeated here.

[0159] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0160] The above merely provides the implementation manner of the present disclosure in an embodiment, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for fabricating a stacked transistor, comprising: forming active structures on a semiconductor substrate in one etching process, the active structures comprising a first active structure and a second active structure, the first active structure and the second active structure being stacked in a first direction, the first active structure being farther away from the semiconductor substrate than the second active structure, the first direction being a direction perpendicular to the semiconductor substrate; forming a first transistor of the stacked transistor based on the first active structure, the first transistor comprising a first gate structure, the first gate structure being formed by a gate replacement process, the gate replacement process comprising a step of replacing a dummy gate structure with a metal gate structure; stripping and removing the semiconductor substrate; forming a second transistor of the stacked transistor based on the second active structure, the second transistor comprising a second gate structure, the second gate structure being formed by a gate replacement process; the stacked transistor further comprising: a gate isolation structure, the gate isolation structure being formed in a gate isolation region of the stacked transistor before the first gate structure and / or the second gate structure replaces a dummy gate structure, the gate isolation region being located on both sides of the stacked transistor in a second direction and at least coinciding with a gate region of the stacked transistor in a third direction, the second direction being perpendicular to the first direction, the third direction being perpendicular to the first direction and the second direction, the gate isolation structure being configured to electrically isolate the gate structure of the stacked transistor and a gate structure of a transistor adjacent to the stacked transistor in the second direction.

2. The production method according to claim 1, wherein, the gate isolation structure comprises a first gate isolation structure; the forming a transistor of the stacked transistor based on the first active structure comprises: forming a shallow trench isolation structure on the semiconductor substrate, the shallow trench isolation structure wrapping the second active structure, the first active structure being exposed outside the shallow trench isolation structure; forming a first dummy gate structure across the first active structure and a first dummy gate sidewall covering sidewalls of the first dummy gate structure on the shallow trench isolation structure; etching the first dummy gate structure in a gate isolation region to form the first gate isolation structure; removing the first dummy gate structure outside the gate isolation region by a gate replacement process to form the first gate structure, the first gate isolation structure being located on both sides of the first transistor.

3. The method of making according to claim 2, wherein, the method further comprises: before etching the first dummy gate structure in a gate isolation region to form the first gate isolation structure, forming a first source / drain structure of the first transistor between first dummy gate sidewalls of two adjacent first dummy gate structures based on the first active structure; or, after etching the first dummy gate structure in a gate isolation region to form the first gate isolation structure, forming a first source / drain structure of the first transistor between first dummy gate sidewalls of two adjacent first dummy gate structures based on the first active structure.

4. The production method according to claim 2, wherein etching the first dummy gate structure within the gate isolation region to form a first gate isolation structure; etching the first dummy gate structure within the gate isolation region and the shallow trench isolation structure within the gate isolation region until the semiconductor substrate within the gate isolation region is exposed to form a first recess; depositing an insulating material within the first recess to form the first gate isolation structure, the first gate isolation structure being on both sides of the first transistor and the shallow trench isolation structure.

5. The production method according to claim 2, wherein The gate isolation structure further comprises a second gate isolation structure, the second gate isolation structure being on both sides of the second transistor in a second direction; forming a second transistor of the stacked transistors based on the second active structure, comprising: thinning the shallow trench isolation structure to expose the second active structure wrapped by the shallow trench isolation structure; forming a second dummy gate structure across the second active structure and a second dummy gate spacer covering sidewalls of the second dummy gate structure; etching the second dummy gate structure within the gate isolation region to form the second gate isolation structure; removing the second dummy gate structure outside the gate isolation region using a gate replacement process to form the second gate structure.

6. The production method according to claim 4, wherein forming a second transistor of the stacked transistors based on the second active structure, comprising: thinning the shallow trench isolation structure between the first gate isolation structures to expose the second active structure wrapped by the shallow trench isolation structure; forming a second dummy gate structure across the second active structure and a second dummy gate spacer covering sidewalls of the second dummy gate structure based on the exposed second active structure, the second dummy gate structure being between the first gate isolation structures; removing the second dummy gate structure between the first gate isolation structures using a gate replacement process to form the second gate structure.

7. The production method according to claim 5, wherein The method further comprises: before etching the second dummy gate structure within the gate isolation region to form the second gate isolation structure, forming a second source-drain structure of the second transistor based on the second active structure between the second dummy gate spacers of two adjacent second dummy gate structures; or, after etching the second dummy gate structure within the gate isolation region to form the second gate isolation structure, forming a second source-drain structure of the second transistor based on the second active structure between the second dummy gate spacers of two adjacent second dummy gate structures.

8. A method for manufacturing a stacked transistor, comprising: forming active structures on a semiconductor substrate in one etching process, the active structures comprising a first active structure and a second active structure, the first active structure and the second active structure being stacked in a first direction, the first active structure being farther away from the semiconductor substrate than the second active structure, the first direction being a direction perpendicular to the semiconductor substrate; forming a first semiconductor structure based on the first active structure, the first semiconductor structure being used to form a first transistor, the first transistor including a first gate structure, the first gate structure being formed using a gate replacement process, the gate replacement process including a step of replacing a dummy gate structure with a metal gate; reversing the semiconductor substrate and removing the semiconductor substrate; forming the first transistor and a second transistor based on the second active structure and the first semiconductor structure, the second transistor including a second gate structure, the second gate structure being formed using a gate replacement process; the stacked transistor further includes: a gate isolation structure, the gate isolation structure being formed within a gate isolation region of the stacked transistor before the first gate structure and the second gate structure replace the dummy gate structure; the gate isolation region being located on both sides of the stacked transistor in a second direction, and at least coinciding with a gate region of the stacked transistor in a third direction, the second direction being perpendicular to the first direction, and the third direction being perpendicular to the first direction and the second direction; the gate isolation structure being used to electrically isolate the gate structure of the stacked transistor and a gate structure of a transistor adjacent to the stacked transistor in the second direction.

9. The production method according to claim 8, wherein when the gate isolation structure is formed during the forming of the first semiconductor structure, the forming a first semiconductor structure based on the first active structure includes: depositing a hard mask material on the semiconductor substrate to form a first hard mask structure, the first hard mask structure wrapping a first end portion of the second active structure, the first end portion being a portion of the second active structure close to the semiconductor substrate; forming a third dummy gate structure across the active structure and a third dummy gate sidewall covering sidewalls of the third dummy gate structure on the first hard mask structure; removing the first hard mask structure on the semiconductor substrate that is not covered by the third dummy gate structure to form a second hard mask structure; etching the third dummy gate structure within the gate isolation region until the second hard mask structure to form a second recess, and depositing an insulating material within the second recess to form the gate isolation structure.

10. The production method according to claim 9, wherein the forming the first transistor and a second transistor based on the second active structure and the first semiconductor structure includes: selectively etching the second active structure until a height of the second active structure is less than a height of the third dummy gate structure using the second hard mask structure as a hard mask to form a third recess; depositing a dummy gate material within the third recess to form a fourth dummy gate structure, the fourth dummy gate structure being self-aligned with the third dummy gate structure; removing the third dummy gate structure and the fourth dummy gate structure between the gate isolation structures; forming a first gate structure of the first transistor between the gate isolation structures; forming a second gate structure of the second transistor on the first gate structure of the first transistor.

11. The production method according to claim 8, wherein when the gate isolation structure is not formed during forming the first semiconductor structure, the forming the first semiconductor structure based on the first active structure comprises: depositing a hard mask material on the semiconductor substrate to form a first hard mask structure, the first hard mask structure wrapping a first end portion of the second active structure, the first end portion being a portion of the second active structure close to the semiconductor substrate; forming a third dummy gate structure across the active structure and a third dummy gate sidewall covering sidewalls of the third dummy gate structure on the first hard mask structure; removing the first hard mask structure on the semiconductor substrate not covered by the third dummy gate structure to form a second hard mask structure.

12. The method of manufacturing according to claim 11, wherein, when the gate isolation structure is not formed during forming the first semiconductor structure, the forming the first transistor and the second transistor based on the second active structure and the first semiconductor structure comprises: selectively etching the second active structure with the second hard mask structure as a hard mask until a height of the second active structure is less than a height of the third dummy gate structure to form a third recess; depositing a dummy gate material in the third recess to form a fourth dummy gate structure, the fourth dummy gate structure self-aligned with the third dummy gate structure; etching the third dummy gate structure located in the gate isolation region and the fourth dummy gate structure located in the gate isolation region to form a fourth recess and depositing an insulating material in the fourth recess to form the gate isolation structure; removing the third dummy gate structure and the fourth dummy gate structure between the gate isolation structures; forming a first gate structure of the first transistor between the gate isolation structures; forming a second gate structure of the second transistor on the first gate structure of the first transistor.

13. The method of making according to claim 8, wherein, before the peeling and removing the semiconductor substrate, the method further comprises: forming a first source-drain structure of the first transistor based on the first active structure; after the peeling and removing the semiconductor substrate, the method further comprises: forming a second source-drain structure of the second transistor based on the second active structure.

14. The production method according to claim 8, wherein, before the forming the first semiconductor structure based on the first active structure, the method further comprises: depositing an oxide material on the semiconductor substrate and the active structure to form an oxide layer covering the semiconductor substrate and wrapping the active structure, the oxide layer for preventing the active structure from collapsing; the peeling and removing the semiconductor substrate comprises: peeling and removing the semiconductor substrate to expose the oxide layer; removing the oxide layer.

15. A stacked transistor, prepared using the preparation method of any one of claims 1 to 7 or 8 to 14, comprising: a first transistor; a second transistor, the first transistor and the second transistor being stacked, a first active structure of the first transistor and a second active structure of the second transistor constituting an active structure; the first transistor comprising a first gate structure, the second transistor comprising a second gate structure. a gate isolation structure, which is formed in a gate isolation region of the stack transistor before the first gate structure and the second gate structure replace the dummy gate structure; the gate isolation region is located on both sides of the stack transistor in a second direction, and at least coincides with the gate region of the stack transistor in a third direction, the second direction is perpendicular to the first direction, and the third direction is perpendicular to the first direction and the second direction; the gate isolation structure is used to electrically isolate the gate structure of the stack transistor and the gate structure of a transistor adjacent to the stack transistor in the second direction.

16. The stacked transistor of claim 15, wherein, The first transistor or the second transistor can be any one of: Fin field effect transistors, fully wrapped gate field effect transistors, and planar field effect transistors.

17. A semiconductor device comprising: The stack transistor as claimed in claim 15 or claim 16.

18. An electronic device, comprising: The circuit board and the semiconductor device as claimed in claim 17, wherein the semiconductor device is disposed on the circuit board.

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