Semiconductor device

Abstract

The present invention provides a transistor capable of carrying large currents or having a small footprint. Provided is a semiconductor device including the following. A pair of first spacer layers are spaced apart and located above a first insulating layer. A first semiconductor layer is located above the pair of first spacer layers and has a region that does not overlap the pair of first spacer layers. A pair of first conductive layers are spaced apart and have a portion located above the first semiconductor layer. A third insulating layer has a portion located on the pair of first conductive layers, a portion in contact with a lateral surface of the pair of first conductive layers, and a portion in contact with the first insulating layer. A second insulating layer has a portion in contact with an upper surface, a lower surface, and a lateral surface in the region of the first semiconductor layer that does not overlap the pair of first spacer layers. A second conductive layer has a portion surrounding the upper surface, the lower surface, and the lateral surface of the first semiconductor layer, with the second insulating layer interposed therebetween.

Description

Semiconductor Devices

[0001] 1. Field of the Invention One embodiment of the present invention relates to a transistor, a semiconductor device, and a method for manufacturing a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of technical fields of one embodiment of the present invention include semiconductor devices, signal processing devices, arithmetic devices, memory devices, input devices, input / output devices, sensors, imaging devices, display devices, light-emitting devices, power storage devices, electronic devices, and driving methods or manufacturing methods thereof. Note that in this specification and the like, a semiconductor device refers to a device that utilizes semiconductor characteristics, such as a circuit including a transistor, a device having such a circuit, and the like. It also refers to any device that can function by utilizing semiconductor characteristics.

[0003] One aspect of the invention disclosed in this specification relates to an object or a method, or to a method (process), a machine, a manufacture, or a composition of matter.

[0004] In recent years, development of semiconductor devices such as large-scale integration (LSI) chips, central processing units (CPUs), graphics processing units (GPUs), and memories (storage devices) has been progressing. Furthermore, development of AI chips as semiconductor devices has been progressing. AI chips include GPUs, field programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs). These semiconductor devices are used in various electronic devices such as computers and personal digital assistants. Furthermore, memories with various storage methods have been developed depending on the application, such as temporary storage during arithmetic processing and long-term storage of data. Typical memory storage methods include, for example, dynamic random access memory (DRAM), static random access memory (SRAM), and flash memory.

[0005] Furthermore, a technique for constructing a transistor using a semiconductor thin film formed on an insulating surface has been attracting attention. Such transistors are widely used in electronic devices such as integrated circuits and display devices. While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also been attracting attention as other materials.

[0006] Furthermore, it is known that a transistor including an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the property of a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time.

[0007] JP 2012-257187 A JP 2011-151383 A

[0008] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0009] An object of one embodiment of the present invention is to provide a transistor capable of passing a large current. Another object is to provide a transistor with favorable electrical characteristics. Another object is to provide a transistor that can be miniaturized. Another object is to provide a transistor that occupies a small area. Another object is to provide a transistor with high reliability. Another object of one embodiment of the present invention is to provide a semiconductor device in which transistors can be arranged at high density. Another object is to provide a semiconductor device with low power consumption.

[0010] An object of one embodiment of the present invention is to provide a semiconductor device having a novel structure, and to overcome at least one of the problems of the prior art.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0012] One aspect of the present invention is a semiconductor device including a first semiconductor layer, a pair of first spacer layers, a pair of first conductive layers, a second conductive layer, a first insulating layer, a second insulating layer, and a third insulating layer. The pair of first spacer layers are spaced apart and located above the first insulating layer. The first semiconductor layer is located above the pair of first spacer layers. The first semiconductor layer has a first region that does not overlap with the pair of first spacer layers. The pair of first conductive layers have portions that are spaced apart and located above the first semiconductor layer. Each of the pair of first conductive layers has portions that contact at least two side surfaces of the first semiconductor layer. The third insulating layer has portions that are located on the pair of first conductive layers, portions that contact the side surfaces of the pair of first conductive layers, and a portion that contacts the first insulating layer. The second insulating layer has portions that contact the top surface, bottom surface, and side surfaces of the first semiconductor layer in the first region of the first semiconductor layer. The second conductive layer has a portion that surrounds the top surface, bottom surface, and side surfaces of the first semiconductor layer via the second insulating layer.

[0013] Another aspect of the present invention is a semiconductor device including first and second semiconductor layers, a pair of first and second spacer layers, a pair of first conductive layers, a second conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, and a pair of third conductive layers. The pair of first spacer layers are spaced apart and located above the first insulating layers. The first semiconductor layer is located above the pair of first spacer layers. The first semiconductor layer has a first region that does not overlap with the pair of first spacer layers. The pair of second spacer layers are spaced apart and located above the first semiconductor layer. The second semiconductor layer is located above the pair of second spacer layers. The second semiconductor layer has a second region that does not overlap with the pair of second spacer layers. The pair of first conductive layers are spaced apart and have portions located above the first and second semiconductor layers. The pair of first conductive layers each have a portion in contact with at least two side surfaces of the first semiconductor layer and a portion in contact with at least two side surfaces of the second semiconductor layer. The third insulating layer has a portion located on the pair of first conductive layers, a portion in contact with the side surfaces of the pair of first conductive layers, and a portion in contact with the first insulating layer. The second insulating layer has portions in contact with the upper surface, lower surface, and side surfaces of the first semiconductor layer in a first region of the first semiconductor layer, and portions in contact with the upper surface, lower surface, and side surfaces of the second semiconductor layer in a second region of the second semiconductor layer. The second conductive layer has portions surrounding the upper surface, lower surface, and side surfaces of the first semiconductor layer via the second insulating layer, and portions surrounding the upper surface, lower surface, and side surfaces of the second semiconductor layer via the second insulating layer.

[0014] In the above, it is preferable that the first semiconductor layer has a portion in contact with the pair of first spacer layers.

[0015] In the above, it is preferable that the second semiconductor layer has a portion in contact with the pair of second spacer layers.

[0016] In the above, it is preferable that the first semiconductor layer be made of indium oxide, and the first spacer layer be made of a metal oxide containing indium, gallium, and zinc.

[0017] In the above, it is preferable that the second semiconductor layer is made of indium oxide, and the second spacer layer is made of a metal oxide containing indium, gallium, and zinc.

[0018] In the above-described semiconductor device, the semiconductor device preferably includes a pair of third conductive layers, the pair of third conductive layers being in contact with an upper surface of the first semiconductor layer and having portions located between the first semiconductor layer and the pair of first conductive layers.

[0019] In the above, the pair of third conductive layers preferably have a portion in contact with an upper surface of the second semiconductor layer and located between the second semiconductor layer and the pair of first conductive layers.

[0020] According to one embodiment of the present invention, a transistor capable of passing a large current can be provided. Alternatively, a transistor with favorable electrical characteristics can be provided. Alternatively, a transistor that can be miniaturized can be provided. Alternatively, a transistor that occupies a small area can be provided. Alternatively, a transistor with high reliability can be provided. One embodiment of the present invention can provide a semiconductor device in which transistors can be arranged at high density. Furthermore, a semiconductor device with low power consumption can be provided.

[0021] Advantageous Effects of Invention According to one aspect of the present invention, it is possible to provide a semiconductor device having a novel configuration, and to improve at least one of the problems of the prior art.

[0022] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0023] FIGS. 1A, 1B, 1C, and 1D are structural examples of semiconductor devices. FIGS. 2A, 2B, 2C, and 2D are structural examples of semiconductor devices. FIGS. 3A, 3B, 3C, and 3D are structural examples of semiconductor devices. FIGS. 4A, 4B, 4C, and 4D are structural examples of semiconductor devices. FIGS. 5A and 5B are structural examples of semiconductor devices. FIGS. 6A, 6B, 6C, and 6D are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 7A, 7B, 7C, and 7D are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 8A, 8B, and 8C are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 9A and 9B are diagrams illustrating the carrier concentration dependence of Hall mobility. FIG. 9C is a cross-sectional view illustrating an indium oxide film. FIGS. 10A and 10B are structural examples of semiconductor devices. FIG. 11A is an equivalent circuit diagram of a logic circuit. FIG. 11B is a diagram illustrating a circuit symbol for a logic circuit. FIG. 11C is a timing chart explaining the operation of a logic circuit. FIGS. 12A and 12D are equivalent circuit diagrams of logic circuits. FIGS. 12B, 12C, 12E, and 12F are diagrams showing circuit symbols for logic circuits. FIGS. 13A and 13B are diagrams showing an example of electronic components. FIGS. 14A, 14B, and 14C are diagrams showing an example of a mainframe computer. FIG. 14D is a diagram showing an example of space equipment. FIG. 14E is a diagram showing an example of a storage system applicable to a data center.

[0024] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0025] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0026] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0027] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or stacking order). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0028] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0029] In this specification and the like, a transistor using an oxide semiconductor for a semiconductor layer and a transistor having an oxide semiconductor for a channel formation region may be referred to as an OS (oxide semiconductor) transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0030] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and drain through the channel formation region. In this specification and the like, the channel formation region refers to a region of a semiconductor layer that overlaps (or faces) a gate electrode via a gate insulating film and is located between a region in contact with the source electrode and a region in contact with the drain electrode.

[0031] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0032] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the line connecting the source region and the drain region at the shortest distance. In other words, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in an on-state. The channel width direction refers to a direction perpendicular to the channel length direction. Depending on the structure or shape of the transistor, the channel length direction and the channel width direction may not be defined as a single direction.

[0033] In this specification and the like, unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the voltage Vgs between the gate and the source of an n-channel transistor is lower than the threshold voltage Vth (higher than Vth for a p-channel transistor). Note that when "Vgs" is used to refer to a voltage, it refers to the potential difference between the source and the gate when the source is used as the reference.

[0034] In this specification and the like, unless otherwise specified, the on-state current refers to the drain current when a transistor is in an on state (also referred to as a "conducting state"). Unless otherwise specified, the on state refers to a state in which Vgs is equal to or higher than Vth for an n-channel transistor, and a state in which Vgs is equal to or lower than the threshold voltage for a p-channel transistor.

[0035] In this specification, "connection" includes "electrical connection." Furthermore, in this specification, "electrical connection" includes connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0036] In this specification and the like, a plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (for example, a substrate) on which the component is formed.

[0037] In the following, expressions indicating directions such as "up" and "down" will basically be used in accordance with the directions in the drawings. However, for purposes such as facilitating explanation, the directions indicated by "up" or "down" in the specification may not match those in the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided (such as a forming surface, a support surface, an adhesive surface, or a flat surface) is located above the laminate in the drawings, the forming surface side may be expressed as "down" and the direction opposite to the forming surface as "up."

[0038] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0039] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0040] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0041] Embodiment 1 In this embodiment, a structure example of a semiconductor device according to one embodiment of the present invention and an example of a manufacturing method thereof will be described. As a specific example of the semiconductor device, a transistor will be described below.

[0042] One embodiment of the present invention is a transistor including a semiconductor layer. The transistor has a gate insulating film that covers a part of the upper surface, lower surface, and side surface of the semiconductor layer. The transistor has a gate electrode that surrounds the part of the upper surface, lower surface, and side surface of the semiconductor layer through the gate insulating film. A region of the semiconductor layer surrounded by the gate electrode through the gate insulating film functions as a channel formation region. With this structure, a gate electric field is applied to the semiconductor layer from above, below, and side surfaces, and thus the source-drain current (also referred to as on-current) can be increased when the transistor is in an on state. Furthermore, the source-drain current (also referred to as off-current) can be reduced when the transistor is in an off state.

[0043] The semiconductor layer is preferably not a single layer but a plurality of layers, two or more layers. The plurality of semiconductor layers are preferably stacked with a gap therebetween in the vertical direction. In this case, a gate insulating film is provided to cover a portion of the upper surface, lower surface, and side surface of each of the plurality of semiconductor layers. A gate electrode is provided to surround a portion of the upper surface, lower surface, and side surface of each of the plurality of semiconductor layers via the gate insulating film. The gate electrode has a portion located between the semiconductor layers stacked with a gap therebetween in the vertical direction. Regions of the plurality of semiconductor layers surrounded by the gate electrode via the gate insulating film function as channel formation regions. A gate electric field is applied to each of the plurality of channel formation regions from the upper surface, lower surface, and side surface, and therefore the plurality of channel formation regions function as channel formation regions of one transistor, thereby increasing the effective channel width. This further increases the on-current compared to a single semiconductor layer. Furthermore, since the plurality of semiconductor layers are arranged vertically, a transistor with a small occupation area can be manufactured.

[0044] A spacer layer is provided below the semiconductor layer. The spacer layer has a function of securing a space below the semiconductor layer for providing a gate insulating film and a gate electrode. When two or more semiconductor layers are stacked, a pair of spacer layers is provided between two semiconductor layers adjacent to each other vertically, and the spacer layers can secure the space between the channel formation regions of the two semiconductor layers.

[0045] When the semiconductor layer is a single layer, a pair of spacer layers is provided between the semiconductor layer and the insulating base layer provided below the semiconductor layer. When two or more semiconductor layers are stacked, a pair of spacer layers is provided between the lowermost semiconductor layer and the insulating base layer. The spacer layers can ensure the space between the channel formation region of the semiconductor layer and the insulating base layer.

[0046] In addition, when the semiconductor layer is a single layer, a pair of first electrodes is preferably provided above the semiconductor layer. When two or more semiconductor layers are stacked, a pair of first electrodes is preferably provided above the uppermost semiconductor layer. One of the pair of first electrodes can function as a source electrode, and the other can function as a drain electrode. Each of the pair of first electrodes preferably has a portion in contact with at least two side surfaces of the semiconductor layer.

[0047] In addition, when the semiconductor layer is a single layer, a pair of second electrodes is preferably provided between the semiconductor layer and the pair of first electrodes. When two or more semiconductor layers are stacked, a pair of second electrodes is preferably provided between the uppermost semiconductor layer and the pair of first electrodes. The pair of second electrodes is preferably in contact with the semiconductor layer. One of the pair of second electrodes can function as part of a source electrode, and the other can function as part of a drain electrode.

[0048] When the semiconductor layer is a single layer, each of the pair of first electrodes preferably contacts at least two side surfaces of the semiconductor layer and is in contact with the second electrode. When the semiconductor layer is a single layer and no second electrode is provided, each of the pair of first electrodes preferably contacts at least two side surfaces of the semiconductor layer and is in contact with the top surface of the semiconductor layer. When two or more semiconductor layers are stacked, each of the pair of first electrodes preferably contacts at least two side surfaces of each of the two or more semiconductor layers and is in contact with the second electrode. When two or more semiconductor layers are stacked and no second electrode is provided, each of the pair of first electrodes preferably contacts at least two side surfaces of each of the two or more semiconductor layers and is in contact with the top surface of the uppermost semiconductor layer. This can increase the contact area between the semiconductor layer and the source electrode or drain electrode, allowing a large current to flow when the transistor is on.

[0049] The spacer layer is preferably made of a semiconductor or a conductor. The side surfaces of the spacer layer are in contact with the pair of first electrodes. The top surface of the spacer layer is in contact with the semiconductor layer. Therefore, by using the spacer layer as a semiconductor or a conductor, it is possible to reduce the electrical resistance between the semiconductor layer having the portions that function as the channel formation regions and the pair of first electrodes.

[0050] The spacer layer preferably has an etching selectivity with respect to the semiconductor layer. The spacer layer preferably has an etching selectivity with respect to at least the channel formation region of the semiconductor layer. Furthermore, the spacer layer preferably has an etching selectivity with respect to the pair of first electrodes, the pair of second electrodes, and the base insulating layer.

[0051] A more specific example will be described below with reference to the drawings.

[0052] [Configuration Example] Fig. 1A shows a schematic top view of a transistor 100. Figs. 1B, 1C, and 1D show schematic cross-sectional views taken along the cutting lines A1-A2, B1-B2, and B3-B4 in Fig. 1A, respectively. Figs. 2A, 2C, and 2D show schematic perspective views taken along the cutting lines A1-A2, B1-B2, and B3-B4 in Fig. 1A, respectively. Figs. 1B and 2A include a cross section of the transistor 100 in the channel length direction. Figs. 1C and 2C include a cross section of the transistor 100 in the channel width direction. Figs. 1D and 2D include a cross section of the source electrode or drain electrode of the transistor 100 in the channel width direction.

[0053] The transistor 100 includes at least a semiconductor layer 13, an insulating layer 18, a conductive layer 19 (conductive layers 19a and 19b), a pair of conductive layers 14 (conductive layer 14a and conductive layer 14b), a pair of conductive layers 15 (conductive layer 15a and conductive layer 15b), and a pair of spacer layers 12 (spacer layer 12a and spacer layer 12b). A part of the insulating layer 18 functions as a gate insulating film. A part of the conductive layer 19 functions as a gate electrode. The pair of conductive layers 14 (conductive layer 14a and conductive layer 14b) each function as a part of a source electrode or a drain electrode. The pair of conductive layers 15 (conductive layer 15a and conductive layer 15b) each function as a part of a source electrode or a drain electrode.

[0054] In this embodiment, when describing matters common to components distinguished by alphabets attached to their reference symbols (conductive layer 14a, conductive layer 14b, etc.) and components distinguished by numbers attached to their reference symbols (semiconductor layer 13-1, semiconductor layer 13-2, etc.), the description may be made using reference symbols with the alphabets or numbers omitted (conductive layer 14, semiconductor layer 13, etc.).

[0055] The transistor 100 is provided over an insulating layer 11 provided over a substrate (not shown). The insulating layer 11 functions as a base insulating layer.

[0056] The spacer layer 12a and the spacer layer 12b are provided separately on the insulating layer 11. The semiconductor layer 13 is provided on the spacer layer 12a and the spacer layer 12b so as to overlap with each other. The semiconductor layer 13 also has a region that does not overlap with the spacer layer 12a and the spacer layer 12b.

[0057] The conductive layers 14a and 14b are provided separately on and in contact with the semiconductor layer 13. The conductive layer 15a has a portion provided on the conductive layer 14a, and the conductive layer 15b has a portion provided on the conductive layer 14b. The semiconductor layer 13 has regions that do not overlap with the conductive layers 14a and 14b and the conductive layers 15a and 15b.

[0058] 1B and 1D, the conductive layer 15a and the conductive layer 15b are each provided in contact with three side surfaces of the semiconductor layer 13. With this structure, the contact area between the semiconductor layer 13 and the conductive layer 15a and the conductive layer 15b functioning as a source electrode or a drain electrode can be increased, and a large current can flow when the transistor is in an on state.

[0059] As shown in Figures 1B and 1C, the insulating layer 18 has at least a portion that contacts the upper surface, lower surface, and a pair of opposing side surfaces of the semiconductor layer 13 in an area that does not overlap with any of the spacer layer 12, the conductive layer 14, and the conductive layer 15.

[0060] As shown in FIGS. 1B and 1C , the conductive layer 19 is provided to surround, via the insulating layer 18, the upper surface, the lower surface, and a pair of opposing side surfaces of a region of the semiconductor layer 13 that does not overlap with any of the spacer layer 12, the conductive layer 14, and the conductive layer 15. The region of the semiconductor layer 13 that is surrounded by the conductive layer 19 via the insulating layer 18 functions as a channel formation region. FIG. 2B is a perspective view of the conductive layer 19, the semiconductor layer 13, and the spacer layer 12 of the transistor 100. As shown in FIG. 2B , the conductive layer 19 applies an electric field to the channel formation region of the semiconductor layer 13 from the upper surface, the lower surface, and a pair of opposing side surfaces. This allows the on-current of the transistor to be increased and the off-current to be reduced. Alternatively, the transistor can be miniaturized while maintaining a high on-current. Alternatively, the area occupied by the transistor can be reduced while maintaining a high on-current. Alternatively, transistors can be arranged at a high density while maintaining a high on-current.

[0061] 1B, it is preferable that the length L2 of the conductive layer 19 facing the lower surface of the semiconductor layer 13 via the insulating layer 18 is longer than the distance L1 between the conductive layers 15a and 15b provided at a distance from each other. This makes it possible to reduce the offset region of the transistor and further increase the on-current.

[0062] The insulating layer 16 is provided to cover the semiconductor layer 13, the conductive layer 14, and the conductive layer 15. The insulating layer 16 has a region in contact with the side surfaces of the conductive layer 15a and the conductive layer 15b, and a region in contact with the insulating layer 11. The insulating layer 16 is preferably a film having at least one or both of an oxygen barrier property and a hydrogen barrier property. A highly reliable transistor can be obtained by using a structure in which the insulating layer 16 and the insulating layer 11 surround the semiconductor layer 13.

[0063] The insulating layer 17 is provided to cover the insulating layer 16. A slit is provided in the insulating layer 17, and an insulating layer 18 and a conductive layer 19 are provided inside the slit. The slit is provided to include a region overlapping with a region between the pair of conductive layers 15, and has a portion that is approximately parallel to the channel width direction of the transistor. The insulating layer 18 is provided along the inside of the slit, and the conductive layer 19 is provided to fill the slit.

[0064] Here, an oxide semiconductor is preferably used for the semiconductor layer 13. Furthermore, a conductive oxide is preferably used for part or all of the conductive layer 14 in contact with the semiconductor layer 13. Furthermore, a conductive oxide is preferably used for part or all of the conductive layer 15 in contact with the semiconductor layer 13. With such a structure, the conductive layer 14 or the conductive layer 15 can form a good connection with the semiconductor layer 13.

[0065] The spacer layer 12 is preferably made of a semiconductor or a conductor. Alternatively, an oxide semiconductor is preferably used. Alternatively, a conductive oxide is preferably used. Alternatively, a conductive material is preferably used. By using such a material, the spacer layer 12 itself can function as a source or a drain.

[0066] It is also preferable that there is a large difference in etching rate between the semiconductor layer 13 and the spacer layer 12. The etching rate of the spacer layer 12 is preferably faster than the etching rate of the semiconductor layer 13. Therefore, it is preferable that the semiconductor layer 13 and the spacer layer 12 use materials that differ in at least one of film formation conditions, constituent elements, composition, and crystallinity. It is also preferable that the etching rate of the spacer layer 12 is faster than the etching rates of the conductive layer 14, the conductive layer 15, the insulating layer 16, the insulating layer 17, and the insulating layer 11.

[0067] As an example of a combination of the semiconductor layer 13 and the spacer layer 12, it is preferable to use indium oxide for the semiconductor layer 13 and In-Ga-Zn oxide (also called IGZO) for the spacer layer 12.

[0068] The indium oxide used for the semiconductor layer 13 is preferably formed by atomic layer deposition (ALD), and the IGZO used for the spacer layer 12 is preferably formed by ALD.

[0069] As another example of a combination of the semiconductor layer 13 and the spacer layer 12, it is preferable to use an IGZO film formed by sputtering for the semiconductor layer 13 and an IGZO film formed by ALD for the spacer layer 12.

[0070] As another example of a combination of the semiconductor layer 13 and the spacer layer 12, it is preferable to use IGZO for the semiconductor layer 13 and zinc oxide for the spacer layer 12. Note that the IGZO used for the semiconductor layer 13 is preferably formed by a sputtering method, and the zinc oxide used for the spacer layer 12 is preferably formed by an ALD method.

[0071] <Regarding Modifications> Modifications of the semiconductor device described using Figures 1A to 2D will be described using Figures 3A to 5B. Hereinafter, differences from the semiconductor device described using Figures 1A to 2D will be mainly described, and overlapping parts will be referred to and descriptions thereof may be omitted.

[0072] 3A to 3D show a configuration example in which the conductive layer 14 (conductive layer 14a, conductive layer 14b) shown in FIG. 1B and the like is not provided. In this case, the conductive layer 15a contacts a part of the top surface of the semiconductor layer 13, and the conductive layer 15b contacts another part of the top surface of the semiconductor layer 13. With this configuration, the process of etching the conductive layer 15 to separate it into the conductive layer 15a and the conductive layer 15b becomes easier, and productivity and yield can be improved.

[0073] 4A to 4D show a configuration example in which the conductive layer 14 (conductive layer 14a, conductive layer 14b) shown in FIG. 1B and the like is not provided, and an insulating layer 41 is provided between the insulating layer 11 and the spacer layer 12. The omission of the conductive layer 14 facilitates the process of etching the conductive layer 15 to separate it into the conductive layer 15a and the conductive layer 15b, thereby improving productivity and yield. Furthermore, it is preferable to use an insulating film having a function of capturing or fixing hydrogen as the insulating layer 41. The insulating layer 16 covers the semiconductor layer 13, contacts the side surfaces of the conductive layer 15a and the conductive layer 15b, and is provided so as to be in contact with the insulating layer 11. The insulating layer 11 and the insulating layer 16 are preferably films having at least one or both of an oxygen barrier property and a hydrogen barrier property. A highly reliable transistor can be provided by using the insulating layer 16 and the insulating layer 11 to surround the semiconductor layer 13 and the insulating layer 41.

[0074] Although the transistor 100 has been described above as having a single semiconductor layer 13, the number of semiconductor layers 13 is not limited to this. The fewer the number of semiconductor layers 13, the more simplified the transistor manufacturing process can be, and the higher the yield can be. The more the number of semiconductor layers 13, the more the on-state current of the transistor 100 can be.

[0075] Fig. 5A shows an example of the configuration of a transistor in which the semiconductor layer 13 in Fig. 2A, which shows the A1-A2 cross section of the transistor 100 shown in Fig. 1A, is made into two layers. Fig. 5B shows an example of the configuration of a transistor in which the semiconductor layer 13 in Fig. 2A is made into five layers.

[0076] In the configuration shown in FIG. 5A , the transistor includes two semiconductor layers 13 (semiconductor layer 13-1 and semiconductor layer 13-2), two spacer layers 12 (spacer layer 12-1a and spacer layer 12-2a, and spacer layers 12-1b and 12-2b), conductive layer 14 (conductive layer 14a and conductive layer 14b), conductive layer 15 (conductive layer 15a and conductive layer 15b), insulating layer 18, and conductive layer 19 (conductive layer 19a and conductive layer 19b). The spacer layer 12-1a and spacer layer 12-1b are provided on the insulating layer 11 at a distance from each other. The semiconductor layer 13-1 is provided overlapping the spacer layer 12-1a and spacer layer 12-1b. The spacer layer 12-2a and spacer layer 12-2b are provided on the semiconductor layer 13-1 at a distance from each other. The semiconductor layer 13-2 is provided on and overlaps the spacer layer 12-2a and the spacer layer 12-2b.

[0077] The conductive layers 14a and 14b are spaced apart and in contact with the upper surface of the semiconductor layer 13-2. The conductive layer 15a has a portion provided on the conductive layer 14a, and the conductive layer 15b has a portion provided on the conductive layer 14b. The conductive layers 15a and 15b are each provided in contact with three side surfaces of the semiconductor layer 13 (semiconductor layers 13-1 and 13-2). The side surface of the conductive layer 14 facing the insulating layer 18 and the side surface of the conductive layer 15 facing the insulating layer 18 are aligned or approximately aligned in a plan view.

[0078] The insulating layer 18 has portions in contact with the upper surface, lower surface, and a pair of opposing side surfaces of a region of the semiconductor layer 13-1 that does not overlap with any of the spacer layers 12-1 a, 12-1 b, 12-2 a, and 12-2 b. The insulating layer 18 also has portions in contact with at least the upper surface, lower surface, and a pair of opposing side surfaces of a region of the semiconductor layer 13-2 that does not overlap with any of the spacer layers 12-2 a, 12-2 b, conductive layers 14 a, 14 b, 15 a, and 15 b.

[0079] The conductive layer 19 is provided so as to surround the upper surfaces, lower surfaces, and a pair of opposing side surfaces of the above-mentioned regions of the semiconductor layer 13-2 and the semiconductor layer 13-1 via the insulating layer 18. The regions of the semiconductor layer 13-2 and the semiconductor layer 13-1 surrounded by the conductive layer 19 via the insulating layer 18 function as channel formation regions.

[0080] <Variation 4> The configuration shown in FIG. 5B includes five semiconductor layers 13 (semiconductor layers 13-1 to 13-5), five spacer layers 12 (spacer layers 12-1a to 12-5a, and spacer layers 12-1b to 12-5b), conductive layers 14 (conductive layers 14a and 14b), conductive layers 15 (conductive layers 15a and 15b), insulating layer 18, and conductive layers 19 (conductive layers 19a and 19b).

[0081] The conductive layer 14a and the conductive layer 14b are provided separately in contact with the top surface of the semiconductor layer 13-5. The conductive layer 15a has a portion provided on the conductive layer 14a, and the conductive layer 15b has a portion provided on the conductive layer 14b. The conductive layer 15a and the conductive layer 15b are each provided in contact with three side surfaces of the semiconductor layer 13 (semiconductor layers 13-1 to 13-5).

[0082] The insulating layer 18 has portions that contact at least the upper and lower surfaces and a pair of opposing side surfaces of the semiconductor layers 13-1 to 13-5 in regions that do not overlap with the spacer layers 12-1a to 12-5b.

[0083] The conductive layer 19 is provided to surround the top surface, the bottom surface, and a pair of side surfaces facing each other of the semiconductor layers 13-1 to 13-5 with the insulating layer 18 interposed therebetween. Regions of the semiconductor layers 13-1 to 13-5 surrounded by the conductive layer 19 with the insulating layer 18 interposed therebetween function as channel formation regions.

[0084] Although FIG. 5A shows an example in which the semiconductor layer 13 has a two-layer structure and FIG. 5B shows an example in which the semiconductor layer 13 has a five-layer structure, the semiconductor layer may have three, four, six or more layers.

[0085] The above is a description of an example of the configuration of the semiconductor device.

[0086] [Regarding Components] <Substrate> The substrate on which a transistor is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Examples of semiconductor substrates include those having an insulating region within the aforementioned semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides may also be used. Further, there are substrates in which a conductive layer or a semiconductor layer is provided on an insulating substrate, substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or an insulating layer is provided on a conductive substrate. Alternatively, any of these substrates may be provided with elements. The elements provided on the substrate include capacitor elements, resistor elements, switch elements (including transistors), light-emitting elements, memory elements, and the like.

[0087] <Semiconductor Layer> The semiconductor layer 13 preferably includes an oxide semiconductor. The oxide semiconductor is preferably a metal oxide.

[0088] The semiconductor layer 13 is preferably made of indium oxide.

[0089] Furthermore, the metal oxide that can be used for the semiconductor layer 13 preferably contains at least In or Zn. Furthermore, the metal oxide preferably contains two or three elements selected from In, element M, and Zn. The element M is a metal element or semimetal element having a high bond energy with oxygen, for example, a metal element or semimetal element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The element M contained in the metal oxide is preferably one or more of the above elements, particularly preferably one or more selected from Al, Ga, Y, and Sn, with Ga being more preferred. Hereinafter, a metal oxide containing In, the element M, and Zn may be referred to as an In-M-Zn oxide.

[0090] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such an In-M-Zn oxide include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, and compositions in the vicinity thereof. Note that the term "nearby compositions" includes a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current, field-effect mobility, and the like of a transistor can be increased.

[0091] Furthermore, the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of the element M. For example, the atomic ratio of the metal elements in such an In-M-Zn oxide may be In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or a composition close to these. By increasing the atomic ratio of M in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0092] The semiconductor layer 13 may be made of, for example, In—Zn oxide, In—Ga oxide, In—Sn oxide, In—Ti oxide, In—Ga—Al oxide, In—Ga—Sn oxide, In—Ga—Zn oxide, In—Sn—Zn oxide, In—Al—Zn oxide, In—Ti—Zn oxide, In—Ga—Sn—Zn oxide, In—Ga—Al—Zn oxide, or In—W oxide. Ga—Zn oxide may also be used. A material containing Zn is preferred because it is easy to increase crystallinity.

[0093] Note that the metal oxide may contain one or more metal elements with higher period numbers in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element with a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements with higher period numbers include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu. Note that La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.

[0094] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0095] The metal oxide can be preferably formed by sputtering or ALD. In particular, it is preferable to form the metal oxide film by ALD, which has excellent coverage. When forming the metal oxide by sputtering, the composition of the metal oxide film may differ from the composition of the target. In particular, the zinc content in the metal oxide film may decrease to about 50% of that of the target.

[0096] In this specification, the content of a metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide. For example, if a metal oxide contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide is A, then Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ ) In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the metal oxide (atomic number ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0097] For example, in the case of a metal oxide containing In, a transistor with a high on-state current can be realized by increasing the In content.

[0098] By using a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 13, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of threshold voltage fluctuation in a PBTS (Positive Bias Temperature Stress) test can be obtained. Furthermore, when a metal oxide containing Ga is used, it is preferable to make the Ga content lower than the In content. This makes it possible to realize a transistor with high mobility and high reliability.

[0099] On the other hand, by increasing the Ga content, a transistor with high reliability against light can be obtained. That is, a transistor with a small amount of variation in threshold voltage in a Negative Bias Temperature Illumination Stress (NBTIS) test can be obtained. Specifically, a metal oxide in which the atomic ratio of Ga is equal to or greater than the atomic ratio of In has a larger band gap, and the amount of variation in threshold voltage of the transistor in the NBTIS test can be reduced.

[0100] Furthermore, by increasing the zinc content, the metal oxide becomes highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0101] The semiconductor layer 13 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 13 may have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. A stacked structure in which two or more oxide semiconductor layers with different compositions are stacked may also be used. Furthermore, by using the ALD method, it is possible to form a metal oxide layer whose composition varies continuously in the thickness direction. This not only broadens the range of design options compared to using a film with a fixed composition, but also prevents the generation of interface states between two layers with different compositions, thereby improving electrical characteristics and reliability. Furthermore, a metal oxide layer having a stacked structure may be formed using both the sputtering method and the ALD method.

[0102] When the semiconductor layer 13 has a two-layer structure, it is preferable to use a high-mobility material (highly conductive material) for one of the layers. This allows for a transistor with a high on-state current. Therefore, low power consumption and high performance can be achieved at the same time. Alternatively, a high-mobility material may be used on the side in contact with the source electrode and drain electrode. This reduces the contact resistance between the semiconductor layer 13 and the source electrode or drain electrode, thereby reducing parasitic resistance and enabling a transistor with a high on-state current.

[0103] Furthermore, when the semiconductor layer 13 has a three-layer structure, it is preferable to use a material for the second layer that has a higher mobility than the first and third layers, so that the second layer mainly serves as a current path, thereby suppressing interface scattering between the gate insulating layer and the semiconductor layer 13 and realizing a transistor with a high on-current and high reliability.

[0104] The difference in mobility and conductivity can be expressed, for example, by the content of indium. Additionally, whether or not an element other than indium that contributes to improving conductivity is included, and the content of that element, also affect mobility and conductivity. Examples of high-mobility materials include In:Ga:Zn = 4:3:2, In:Ga:Zn = 4:2:3, In:Zn = 1:1, In:Zn = 2:1, In:Zn = 4:1, In:Sn:Zn = 40:X:10 (where X is a real number between 0.1 and 5, typically X = 1), and materials with compositions close to these. On the other hand, materials with lower mobility or conductivity compared to the above-mentioned materials include In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:4, In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2, and materials with compositions close to these.

[0105] It is preferable to use a crystalline metal oxide layer for the semiconductor layer 13. For example, a metal oxide layer having a single crystal structure, a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, a nanocrystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 13, the density of defect states in the semiconductor layer 13 can be reduced, and a highly reliable semiconductor device can be realized.

[0106] The higher the crystallinity of the metal oxide layer used in the semiconductor layer 13, the more the defect level density in the semiconductor layer 13 can be reduced.

[0107] It is preferable to use indium oxide for the semiconductor layer 13. In particular, it is preferable to use a single-crystal indium oxide film. Note that it is preferable to use a crystalline film for the semiconductor layer 13, and it is particularly preferable to use indium oxide having a single-crystal structure. However, indium oxide having a polycrystalline structure or a microcrystalline structure can also be used. By using indium oxide having a single-crystal structure, carrier scattering at crystal grain boundaries can be suppressed, and a transistor with high field-effect mobility can be realized. Furthermore, a highly reliable transistor can be realized. When indium oxide having a polycrystalline structure is used, it is preferable that crystal grain boundaries are not observed at least in the channel formation region (the region overlapping with the conductive layer 19). As a result, even indium oxide having a polycrystalline structure can achieve the same effects as indium oxide having a single-crystal structure.

[0108] The thickness of the semiconductor layer 13 is preferably 1 nm or more and 50 nm or less, more preferably 2.5 nm or more and 30 nm or less, more preferably 2.5 nm or more and 20 nm or less, more preferably 5 nm or more and 20 nm or less, and even more preferably 5 nm or more and 10 nm or less. By setting the thickness of the semiconductor layer 13 within the above range, the crystallinity of the semiconductor layer 13 can be improved.

[0109] Among oxide semiconductors with high crystallinity, indium oxide is a film through which one or both of hydrogen and oxygen move more easily than, for example, an IGZO (In—Ga—Zn—O-based oxide) film. Therefore, indium oxide can be said to be a film through which one or both of hydrogen and oxygen are more easily supplied and discharged than, for example, an IGZO film. This means that excess oxygen or excess hydrogen, which can become carriers or fixed charges, is less likely to accumulate in the semiconductor layer 13, thereby making it possible to provide a transistor with good electrical characteristics and reliability.

[0110] The semiconductor layer 13 preferably has a reduced concentration of elements that reduce crystallinity. For example, the concentration of elements such as boron and aluminum is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.

[0111] Furthermore, when indium oxide is used for the semiconductor layer 13, the amount of variation in threshold voltage in the PBTS test may increase because unintentionally mixed gallium has the property of easily bonding with excess oxygen atoms. Therefore, when indium oxide is used for the semiconductor layer 13, the gallium concentration in the semiconductor layer 13 is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.

[0112] An OS transistor has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has significantly lower source-drain leakage current in an off state (hereinafter also referred to as off-state current), and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0113] The semiconductor device according to one embodiment of the present invention can be applied to, for example, a processor, a memory device, or various ICs. The transistor according to one embodiment of the present invention is capable of passing a large current and has an extremely low off-state current, and therefore, high-speed operation of a circuit and low power consumption can be achieved at the same time.

[0114] OS transistors have smaller variations in electrical characteristics due to radiation exposure than Si transistors, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0115] The semiconductor material that can be used for the semiconductor layer 13 is not limited to oxide semiconductors. For example, semiconductors made of simple elements or compound semiconductors can be used. Examples of semiconductors made of simple elements include silicon (including single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon) and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. These semiconductor materials may contain impurities as dopants.

[0116] Alternatively, the semiconductor layer 13 may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a high on-state current can be provided.

[0117] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0118] The crystallinity of the semiconductor material used for the semiconductor layer 13 is not particularly limited, and any of an amorphous semiconductor, a single-crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0119] <Gate insulating film> As transistors become more miniaturized and highly integrated, thinner gate insulating layers can cause problems such as leakage current. Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. Meanwhile, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is preferable to select materials according to the function of the insulating layer.

[0120] The insulating layer 18 functions as a gate insulating film of a transistor. When an oxide semiconductor is used for the semiconductor layer 13, it is preferable to use an oxide insulating film for at least a film of the insulating layer 18 that is in contact with the semiconductor layer 13. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide can be used. Alternatively, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide can also be used for the insulating layer 18. Furthermore, the insulating layer 18 may have a stacked structure, for example, a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0121] The insulating layer 18 is preferably formed by stacking insulating films having a high dielectric constant (high-k), and is preferably formed by stacking an insulating film having a high dielectric constant (high-k) and an insulating film having a high dielectric strength. For example, hafnium oxide, zirconium oxide, and aluminum oxide can be used as the insulating layer 18. Alternatively, an insulating film (also referred to as ZAZ) in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order can be used. Alternatively, an insulating film (also referred to as ZAZA) in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in this order can be used. Alternatively, an insulating film (also referred to as hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide) can be stacked in this order. By stacking insulating films having a relatively high dielectric strength, such as aluminum oxide, the dielectric strength can be improved, and electrostatic breakdown can be suppressed. Examples of insulating films with a high dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. The above-mentioned ZAZ and ZAZA are also examples of insulating films with a high dielectric constant. Silicon oxide or silicon oxynitride can be used as an insulating film with high dielectric strength. Silicon oxide or silicon oxynitride can also be said to be insulating films that suppress leakage current.

[0122] Furthermore, a ferroelectric insulating film may be used as the insulating layer 18. Examples of the ferroelectric insulating film include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide.

[0123] When the insulating layer 18 has a two-layer structure, it is preferable to use an insulating film having a function of capturing or fixing hydrogen as the film located on the semiconductor layer 13 side, and an insulating film having a barrier property against hydrogen as the film located on the conductive layer 19 side that functions as a gate electrode. This makes it possible to suppress diffusion of hydrogen from the conductive layer 19 side to the semiconductor layer 13, thereby realizing a highly reliable transistor.

[0124] When the insulating layer 18 has a three-layer structure, it is preferable to use an insulating film with high dielectric strength or an insulating film that suppresses leakage current as the film located on the semiconductor layer 13 side, an insulating film with barrier properties against hydrogen, an insulating film with barrier properties against oxygen, or an insulating film that has a function of suppressing the permeation of impurities such as water and hydrogen and oxygen as the film located on the conductive layer 19 side, and an insulating film that has a function of capturing or fixing hydrogen as the film located between them. The film located on the conductive layer 19 side can prevent oxygen from diffusing toward the conductive layer 19 side and suppress oxidation of the conductive layer 19.

[0125] When the insulating layer 18 has a four-layer structure, it is preferable to use an insulating film having a barrier property against oxygen as the film located closest to the semiconductor layer 13, an insulating film having high dielectric strength or an insulating film that suppresses leakage current as the film next closest to the semiconductor layer 13, an insulating film having a function of capturing or fixing hydrogen as the film closest to the semiconductor layer 13, and an insulating film having a barrier property against hydrogen, an insulating film having a barrier property against oxygen, or an insulating film having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen as the film located closest to the conductive layer 19. That is, in addition to the above-described three-layer structure, a structure can be obtained in which an additional film is located on the semiconductor layer 13 side. By using an insulating film having a barrier property against oxygen as the film in contact with the semiconductor layer 13, oxygen desorption from the semiconductor layer 13 can be suppressed. In this case, it is preferable to use an aluminum oxide film as the film in contact with the semiconductor layer 13. Aluminum oxide not only has a barrier property against oxygen but also has the function of capturing or fixing hydrogen, thereby preventing hydrogen from diffusing into the semiconductor layer 13.

[0126] When the insulating layer 18 has a stacked structure, each insulating film is preferably a thin film. For example, the total thickness of the insulating layer 18 is 1 nm to 20 nm, preferably 2 nm to 10 nm, to reduce the subthreshold swing (also referred to as the S value) of the transistor. The thickness of each insulating film is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, still more preferably 0.5 nm to 5 nm, still more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm.

[0127] As a specific example, it is preferable to use a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 13 side, and to set the thicknesses of these films to 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer 13 side.

[0128] As another specific example, it is preferable to use a four-layer structure in which a hafnium oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 13 side, and to set the thicknesses of these films to 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer 13 side.

[0129] As another specific example, it is preferable to use a two-layer structure in which a silicon oxide film and a hafnium oxide film are stacked in this order from the semiconductor layer 13 side, and to set the thicknesses of these films to 1 nm and 1.5 nm from the semiconductor layer 13 side.

[0130] In this specification and the like, the barrier property refers to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that makes the permeability of the corresponding substance low, or a function that suppresses the permeation of the corresponding substance). Note that when hydrogen is described as a corresponding substance, it can refer to, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0131] Examples of insulating films that have a function of suppressing the permeation of oxygen and impurities such as water and hydrogen include metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Also usable are nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0132] Examples of insulating film materials capable of capturing or adhering hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium (hafnium zirconium oxide). Metal oxides with an amorphous structure have dangling bonds in some oxygen atoms, which enhance their ability to capture or adhering hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure may be achieved by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Metal oxides may have crystalline regions and / or grain boundaries in some regions.

[0133] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0134] Examples of materials for the insulating film having a barrier property against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, hafnium aluminate, hafnium zirconium oxide, silicon nitride, silicon nitride oxide, and gallium oxide films.

[0135] Examples of materials for insulating films having a barrier property against oxygen include oxides containing either or both of aluminum and hafnium, magnesium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing either or both of aluminum and hafnium include aluminum oxide, hafnium oxide, hafnium aluminate, and hafnium silicate.

[0136] <Conductive Layer> The conductive layer 14 and the conductive layer 15 are in contact with the semiconductor layer 13. When an oxide semiconductor is used as the semiconductor layer 13, if an easily oxidized metal such as aluminum is used in the portions of the conductive layer 14 and the conductive layer 15 in contact with the semiconductor layer 13, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 14 and the conductive layer 15 and the semiconductor layer 13, preventing electrical conduction therebetween. Therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material for at least the portions of the conductive layer 14 and the conductive layer 15 in contact with the semiconductor layer 13.

[0137] For the conductive layer 14 and the conductive layer 15 in contact with the semiconductor layer 13, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. These are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when oxidized.

[0138] Alternatively, conductive oxides such as indium oxide, In—Sn oxide, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, and In—Sn—Si oxide can be used. Conductive oxides containing indium are particularly preferred due to their high conductivity. Alternatively, oxide materials such as In—Ga—Zn oxide that can be used for the semiconductor layer 13 can also be used as a conductive layer by increasing the carrier concentration.

[0139] For example, the conductive layer 14 and the conductive layer 15 can each be a single-layer structure of the above-mentioned conductive oxide film, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on a tungsten film, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on the above-mentioned conductive oxide film, a two-layer structure in which the above-mentioned conductive oxide film is stacked on a ruthenium film or a ruthenium oxide film, a two-layer structure in which a conductive oxide film is stacked on a tungsten film, or a three-layer structure in which a titanium nitride film, a tungsten film, and a titanium nitride film are stacked in this order.

[0140] The conductive layers 14, 15, and 19 are preferably made of a low-resistance conductive material. For the conductive layers 14, 15, and 19, it is preferable to use a metal element selected from the group consisting of aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing such a metal element. Nitrides of the above metals or alloys, or oxides of the above metals or alloys, may also be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferably used. Semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may also be used.

[0141] Furthermore, a stacked structure of the conductive oxide or conductive nitride and the metal can be used for the conductive layer 14 and the conductive layer 15. For example, a stacked structure of tantalum nitride and tungsten is preferable.

[0142] The conductive layer 19 may be made of the nitride or oxide that can be used for the conductive layers 14 and 15. For example, a laminated structure of titanium nitride and tungsten is preferable.

[0143] <Insulating Layer> The insulating layer 17 can be used as an interlayer insulating film. For example, it is preferably formed by a film formation method such as a sputtering method or a plasma CVD method. In particular, when a sputtering method is used, hydrogen gas is not used as a film formation gas, and therefore a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the semiconductor layer 13 can be suppressed, and the electrical characteristics of the transistor 100 can be stabilized.

[0144] The insulating layer 17 preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer insulating film, the parasitic capacitance generated between wirings can be reduced. For example, it is preferable to have one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies. Silicon oxide and silicon oxynitride are preferable because they are thermally stable.

[0145] Since the insulating layer 17 functions as an interlayer insulating layer, it is preferable to use a film formation method that allows film formation at a high film formation rate compared to other insulating layers. For example, the insulating layer 17 may be formed using TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC ２ H ５ ) ４ Alternatively, a silicon oxide film formed by plasma CVD using a silicon dioxide film containing SiO 2 may be used. This can improve productivity.

[0146] The insulating layer 11, which functions as a base insulating layer, also functions as an interlayer insulating layer. The insulating layer 11 can be made of the same insulating material as can be used for the insulating layer 17.

[0147] Here, a transistor using a metal oxide film can have stable electrical characteristics by being surrounded by an insulating film that has a function of suppressing the permeation of impurities such as water and hydrogen and oxygen. The insulating layer 11, the insulating layer 16, and the insulating layer 41 of the semiconductor device preferably use an insulating film that has a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, an insulating film that has a function of capturing or fixing hydrogen, an insulating film that has a barrier property against hydrogen, or an insulating film that has a barrier property against oxygen. The use of these insulating layers can suppress the diffusion of hydrogen into the semiconductor layer 13. Furthermore, oxidation of the conductive layer 14 or the conductive layer 15 can be suppressed.

[0148] <Spacer Layer> The spacer layer 12 can be made of an insulating material, a semiconductor material, or a conductive material. The spacer layer 12 can be made of a material that has an etching rate selectivity at least similar to that of the semiconductor layer 13. The spacer layer 12 can be made of a material that differs from the semiconductor layer 13 in at least one of the constituent elements, composition, crystallinity, and density.

[0149] It is particularly preferable to use, as the spacer layer 12, a material that can be used for the semiconductor layer 13 or a material that can be used for the conductive layer 14. Note that, as the spacer layer 12, a material that can be used for the conductive layer 14 and the conductive layer 15, a material that can be used for the insulating layer 16, or a material that can be used for the insulating layer 17 can also be applied.

[0150] This concludes the description of the components.

[0151] [Manufacturing Method Example] An example of a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described below, taking the transistor 100 illustrated in FIGS. 1A to 1D as an example of the above-described structure example.

[0152] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an ALD method, etc. CVD methods include a plasma enhanced chemical vapor deposition (PECVD) method and a thermal CVD method. One type of thermal CVD method is a metal organic chemical vapor deposition (MOCVD) method.

[0153] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0154] The thin film constituting the semiconductor device can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Alternatively, the island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0155] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0156] 6A to 7D are schematic perspective views corresponding to the steps in an example of a fabrication method described below, and FIGS. 8A to 8C are schematic perspective views including a horizontal cross section of FIG. 7A.

[0157] First, an insulating layer 11 is formed on a substrate (not shown).

[0158] The substrate may be a substrate having heat resistance sufficient to withstand at least the subsequent heat treatment.

[0159] The insulating layer 11 may be an inorganic insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The insulating layer 11 may be formed by a method such as sputtering, CVD, vacuum deposition, PLD, or ALD. If the surface on which the insulating layer 11 is to be formed is not flat, a planarization treatment may be performed after the insulating layer 11 is formed so that the upper surface of the insulating layer 11 becomes flat.

[0160] Next, a film that will become the spacer layer 12 is deposited on the insulating layer 11. This film can be formed by a deposition method such as a sputtering method or an ALD method. For example, when IGZO or zinc oxide is used for the film that will become the spacer layer 12, the film can be formed by a sputtering method or an ALD method. When a metal oxide film is used for the film that will become the spacer layer 12, the description of the method for forming the film that will become the semiconductor layer 13 described in this specification can be referenced.

[0161] The thickness of the film that will become the spacer layer 12 is determined by the thicknesses of the insulating layer 18 and conductive layer 19 (thickness in the region that overlaps with the semiconductor layer 13) that will be formed later. The thickness of the film that will become the spacer layer 12 is at least twice the thickness of the insulating layer 18. For example, the thickness of the film that will become the spacer layer 12 is more than twice but not more than 10 times the thickness of the insulating layer 18, preferably 2.5 to 10 times, and more preferably 3 to 10 times.

[0162] Subsequently, a film that will become the semiconductor layer 13 is formed on the film that will become the spacer layer 12 .

[0163] Although the description here is of a case where one semiconductor layer 13 is provided, a configuration having two or more semiconductor layers 13 may be used. In this case, films that will become the spacer layers 12 and films that will become the semiconductor layers 13 are alternately stacked.

[0164] A metal oxide (oxide semiconductor) film having semiconductor properties can be used as the semiconductor layer 13. The metal oxide film may be formed by a sputtering method, an ALD method, or the like, as appropriate. For example, IGZO, indium oxide, or the like can be used. Note that the description of Embodiment 2 can be referred to for the indium oxide used for the semiconductor layer 13.

[0165] The metal oxide film preferably has crystallinity. In particular, the metal oxide film according to one embodiment of the present invention preferably has a metal oxide having a single crystal structure, a polycrystalline structure, or a CAAC structure.

[0166] It is preferable to perform a treatment to enhance the crystallinity of the metal oxide film during or after the formation of the metal oxide film. Examples of treatments to enhance the crystallinity of the metal oxide film include heat treatment, plasma treatment, microwave (typically 2.45 GHz) treatment, microwave-excited plasma treatment (also simply referred to as microwave plasma treatment), and light (e.g., ultraviolet light) irradiation treatment. A plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave-excited plasma treatment may be performed simultaneously. Alternatively, microwave-excited plasma treatment may be performed after heat treatment.

[0167] The treatment for enhancing the crystallinity of the metal oxide film may be performed after the metal oxide film is formed. Specifically, the treatment may be performed directly on the formed metal oxide film, or may be performed through another film, such as an insulating film, formed on the metal oxide film. For example, a microwave-excited plasma treatment may be performed after the metal oxide film is formed. Alternatively, an insulating film (e.g., a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc.) may be formed after the metal oxide film is formed, and then a heat treatment or a microwave-excited plasma treatment may be performed on the metal oxide film through the insulating film. Note that the treatment for enhancing the crystallinity of the metal oxide film described above can also serve as a treatment for removing impurities contained in the metal oxide film. For example, carbon, hydrogen, nitrogen, and the like contained in the metal oxide film can be preferably removed. Alternatively, the treatment for enhancing the crystallinity of the metal oxide film may be performed in an oxygen gas atmosphere to reduce oxygen vacancies in the metal oxide film.

[0168] When performing a treatment to increase the crystallinity of a metal oxide film, it is preferable to set the temperature of the heat treatment (or the temperature of the substrate) to room temperature (e.g., 25°C) or higher, 100°C or higher and 700°C or lower, 100°C or higher and 600°C or lower, or 300°C or higher and 450°C or lower.

[0169] By increasing the crystallinity of the metal oxide film, a highly reliable transistor can be realized.

[0170] As an example of a means for enhancing the crystallinity of a metal oxide film, it is preferable to use indium oxide for the film that will become the semiconductor layer 13 and IGZO for the film that will become the spacer layer 12. By using IGZO for the film that will become the spacer layer 12, it is possible to obtain a crystallized indium oxide layer formed in contact with the film that will become the spacer layer 12. More preferably, by using IGZO for the spacer layer 12, whose c-axis is oriented perpendicular or approximately perpendicular to the surface on which the film is to be formed, the

[111] direction of the crystals of the indium oxide film of the semiconductor layer 13 formed directly thereon can be made parallel or approximately parallel to the c-axis of the spacer layer 12.

[0171] The metal oxide film can be formed by, for example, a sputtering method using a metal oxide target.

[0172] The metal oxide film is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film is preferably a high-purity film with as few impurities as possible, such as hydrogen and water, as reduced as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film.

[0173] Furthermore, when forming a metal oxide film, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). Note that the higher the ratio of oxygen gas to the total deposition gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow ratio), the higher the crystallinity of the metal oxide film can be, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film can be, and a transistor with a higher on-state current can be obtained.

[0174] When forming a metal oxide film, the higher the substrate temperature, the higher the crystallinity and density of the metal oxide film, whereas the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film.

[0175] The metal oxide film may be formed under the conditions of a substrate temperature of from room temperature to 250° C., preferably from room temperature to 200° C., and more preferably from room temperature to 140° C. For example, a substrate temperature of from room temperature to less than 140° C. is preferred because productivity is increased.

[0176] When the ALD method is used, it is preferable to use a film formation method such as thermal ALD (Atomic Layer Deposition) or PEALD (Plasma Enhanced ALD). The thermal ALD method is preferable because it exhibits extremely high step coverage. The PEALD method is also preferable because it exhibits high step coverage and allows low-temperature film formation.

[0177] For example, when a metal oxide is used for the semiconductor film, the film can be formed by an ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0178] For example, when forming an indium oxide film, a precursor containing indium can be used.

[0179] For example, when forming an In—Ga—Zn oxide film, three precursors, i.e., a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, i.e., a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0180] Examples of precursors that can be used that contain indium include triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethylindium.

[0181] Furthermore, examples of precursors that can be used that contain gallium include trimethylgallium, triethylgallium, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride.

[0182] Furthermore, as a precursor containing zinc, dimethyl zinc, diethyl zinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc. can be used.

[0183] The oxidizing agent is, for example, ozone (O ３ ), oxygen (O ２ ), water (H ２ O), nitrogen dioxide (NO ２ ), nitrous oxide (N ２ O), hydrogen peroxide (H ２ O ２ ) or the like can be used, and two or more of these may be used.

[0184] In order to reduce the hydrogen and nitrogen concentrations in the film, O is used as an oxidizing agent. ２ or O ３ It is preferable to use O ３ It is more preferable to use

[0185] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the time for which the source gases are flowed, the order in which the source gases are flowed, etc. By adjusting these, it is also possible to form a film whose composition changes continuously. It is also possible to form two or more films with different compositions continuously.

[0186] After the metal oxide film is formed, heat treatment is preferably performed. The heat treatment is preferably performed at 250° C. or higher and 650° C. or lower, preferably 400° C. or higher and 600° C. or lower. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas to compensate for the desorbed oxygen.

[0187] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a highly purified gas for the heat treatment, it is possible to prevent moisture and the like from being incorporated into the metal oxide film as much as possible.

[0188] In the following drawings, the semiconductor layer is shown as a single layer, but it may also have a laminated structure. For example, it may have a two-layer structure formed by the ALD method, a three-layer structure formed by the ALD method, a two-layer structure in which the first layer is formed by the ALD method and the second layer is formed by the sputtering method, or a three-layer structure in which the first layer is formed by the ALD method, the second layer is formed by the sputtering method, and the third layer is formed by the ALD method or the sputtering method. Forming the first layer by the ALD method is preferable because it can suppress mixing, but it is also possible to form the first layer by the sputtering method and the second layer by the ALD method. The semiconductor layer may also have a laminated structure of four or more layers.

[0189] Subsequently, a film that will become the conductive layer 14 is formed on the film that will become the semiconductor layer 13. The film that will become the conductive layer 14 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0190] Next, a resist mask is formed on the film that will become the conductive layer 14, and portions of the film that will become the spacer layer 12, the film that will become the semiconductor layer 13, and the film that will become the conductive layer 14 that are not covered by the resist mask are etched. As a result, an island-shaped film 61 that will become the spacer layer 12, and island-shaped films 62 that will become the semiconductor layer 13 and the conductive layer 14 are formed on the insulating layer 11 ( FIG. 6A ).

[0191] The island-shaped film 62 that becomes the conductive layer 14 can be used as a metal hard mask when etching the semiconductor layer 13. Here, the case where the conductive layer 14 is left has been described, but the island-shaped film 62 can be removed after the island-shaped film 61 that becomes the spacer layer 12, the semiconductor layer 13, and the island-shaped film 62 are formed, thereby fabricating the semiconductor device shown in FIGS.

[0192] It is preferable to use anisotropic dry etching for the etching. While Fig. 6A shows an example in which the side surfaces of each layer are perpendicular to the upper surface of the insulating layer 11, the side surfaces of each layer may have a tapered shape depending on the etching conditions. In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of the structure is inclined with respect to the substrate surface or the surface on which the structure is to be formed.

[0193] Next, a film that will become the conductive layer 15 is formed to cover the island-shaped film 61, the semiconductor layer 13, and the island-shaped film 62. A resist mask is formed on the film that will become the conductive layer 15. Portions of the film that will become the conductive layer 15 that are not covered by the resist mask are etched to form an island-shaped film 63 that will become the conductive layer 15 ( FIG. 6B ).

[0194] Subsequently, the insulating layer 16 is formed on the island-shaped film 63 that will become the conductive layer 15. The insulating layer 16 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method. The insulating layer 16 is preferably an insulating layer that has a function of capturing or fixing hydrogen. In addition, the insulating layer 16 is preferably an insulating layer that has a barrier property against hydrogen.

[0195] Subsequently, an insulating layer 17 is formed on the insulating layer 16 by a film formation method such as a sputtering method, an ALD method, or a CVD method. After the insulating layer 17 is formed, the insulating layer 17 is planarized by a planarization process. For example, a CMP (Chemical Mechanical Polishing) method can be used as the planarization process ( FIG. 6C ).

[0196] Next, a resist mask is formed on the insulating layer 17. The insulating layer 17, insulating layer 16, island-shaped film 63, and island-shaped film 62 that are not covered by the resist mask are etched to form trenches 64. At this time, conductive layers 15a and 15b are formed from the island-shaped film 63, and conductive layers 14a and 14b are formed from the island-shaped film 62. The conductive layers 15a and 15b are separated by the trench 64. The conductive layers 14a and 14b are separated by the trench 64. A portion of the semiconductor layer 13 and a portion of the spacer layer 12 are exposed in the trench 64. Here, anisotropic dry etching is preferably used to form the trench 64 ( FIG. 6D ).

[0197] Next, the island-shaped film 61 in the trench 64 is etched. At this time, the spacer layer 12a and the spacer layer 12b are formed from the island-shaped film 61. The spacer layer 12a and the spacer layer 12b are separated by the trench 64 (FIGS. 7A and 7B). It is preferable to use isotropic etching for etching the island-shaped film 61. Wet etching can be used as the isotropic etching. Note that FIG. 7B is a perspective schematic view of FIG. 7A cut in the channel length direction.

[0198] For example, when a film having higher crystallinity than the spacer layer 12 is used for the semiconductor layer 13, wet etching is preferably used to obtain a large etching rate selectivity. For wet etching, for example, hydrofluoric acid, phosphoric acid, oxalic acid, nitric acid, acetic acid, hydrochloric acid, or an aqueous solution of tetramethylammonium hydroxide (TMAH), or a mixed solution or mixed aqueous solution containing two or more of these, can be used. The chemical solution used for wet etching may be alkaline or acidic.

[0199] By separating the island-shaped film 61 between the spacer layer 12a and the spacer layer 12b, a space can be formed between the semiconductor layer 13 and the insulating layer 11. The height of the space is equal to or approximately equal to the film thickness of the spacer layer 12. It is preferable that the width of the space be wider than the width of the trench 64 in the channel length direction. FIGS. 8A to 8C are perspective schematic views including the horizontal cross section C shown in FIG. 7A. Depending on how the spacer layer 12 is isotropically etched, the shapes of the spacer layer 12a and the spacer layer 12b may vary. As long as the spacer layer 12a and the spacer layer 12b can be separated, any of the shapes shown in FIGS. 8A to 8C may be used. The top surfaces of the spacer layer 12a and the spacer layer 12b in FIG. 8A are rectangular. The top surfaces of the spacer layer 12a and the spacer layer 12b in FIG. 8B are arc-shaped, convex toward the opposing spacer layer. The top surfaces of the spacer layers 12a and 12b in FIG. 8C have a concave arc shape facing the opposing spacer layer.

[0200] The length of the semiconductor layer 13 in the channel length direction in a plan view within the trench 64 is preferably longer than the length of the semiconductor layer 13 in the channel width direction. For example, the length of the semiconductor layer 13 in the channel length direction in a plan view within the trench 64 is preferably at least twice as long as the length of the semiconductor layer 13 in the channel width direction.

[0201] Next, a film that will become the insulating layer 18 is formed. The film that will become the insulating layer 18 is preferably formed using an ALD method, which has better step coverage than other film formation methods. Then, a film that will become the conductive layer 19 is formed. After the films that will become the insulating layer 18 and the conductive layer 19 are formed, CMP is performed to remove the films that will become the insulating layer 18 and the conductive layer 19 from the insulating layer 17 ( FIGS. 7C and 7D ). Note that FIG. 7D is a schematic perspective view of FIG. 7C cut in the channel length direction. The conductive layer 19 may have, for example, a two-layer structure of conductive layers 19a and 19b. The conductive layer 19a is preferably formed by a method that has better step coverage than the conductive layer 19b. As shown in FIG. 7D , by separating the semiconductor layer 13 and the insulating layer 11 using the spacer layers 12a and 12b, at least the insulating layer 18 and the conductive layer 19a are formed in the space between the semiconductor layer 13 and the insulating layer 11.

[0202] Through the above steps, the transistor 100 can be manufactured.

[0203] The above is a description of an example of the manufacturing method.

[0204] This embodiment can be implemented by appropriately combining at least a part of it with other embodiments described in this specification. In addition, when multiple configuration examples are shown in one embodiment in this specification, the configuration examples can be appropriately combined.

[0205] Embodiment 2 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

[0206] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0207] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0208] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 9A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 9B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0209] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 9B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 9A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 9A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 9A.

[0210] 9A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0211] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0212] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0213] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0214] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 9A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0215] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0216] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0217] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0218] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0219] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0220] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0221] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0222] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0223] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0224] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 9C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0225] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor exhibiting extremely high reliability can be realized.

[0226] 9C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with the oxygen contained in the membrane and is released as water molecules.

[0227] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0228] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0229]

[0230] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0231] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0232] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0233] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0234] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0235] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0236] Embodiment 3 In this embodiment, an example of a CMOS circuit configuration using a Si transistor and an OS transistor according to one embodiment of the present invention will be described.

[0237] 10A and 10B illustrate a Si transistor 1100 and an OS transistor 1200 provided thereover. Note that the OS transistor 1200 can be the transistor 100 described in Embodiment 1.

[0238] The Si transistor 1100 will be described. The Si transistor 1100 is a Fin-type transistor. Fig. 10A shows a schematic cross-sectional view in the channel length direction, and Fig. 10B shows a schematic cross-sectional view in the channel width direction.

[0239] The Si transistor 1100 is provided on a substrate 1011 and has a conductive layer 1018a that functions as a gate electrode, an insulating layer 1017 that functions as a gate insulating film, a semiconductor region 1013 that functions as a channel formation region, and a low-resistance region 1014 that functions as a source region or a drain region.

[0240] The substrate 1011 may be, for example, a silicon substrate or an SOI (Silicon On Insulator) substrate.

[0241] Next, the semiconductor device shown in FIGS. 10A and 10B will be described. An element isolation layer 1012, an insulating layer 1015, and dummy gate electrodes 1018b and 1018c are provided on a substrate 1011. The insulating layer 1015 functions as a sidewall. Furthermore, insulating layers 1016, 1019, 1020, 1021, 1023, 1025, 1026, 1027, 1029, and 1030 are provided, and these insulating layers function as interlayer insulating films. Furthermore, the insulating layers 1019, 1021, 1025, 1027, and 1030 function as barrier films. The conductive layers 1022, 1024, and 1028 function as plugs, electrodes, or wirings.

[0242] An OS transistor 1200 is provided over the insulating layer 11 .

[0243] The conductive layer 1032 functions as a plug provided in the insulating layer 17. The insulating layer 1031 is provided so as to cover the side surface of the conductive layer 1032 provided in the insulating layer 17. The insulating layer 1031 is preferably an insulating layer having at least one of an oxygen barrier property and a hydrogen barrier property.

[0244] Insulating layers 1033, 1034, 1035, and 1036 are provided above the OS transistor 1200 and function as interlayer insulating films. The insulating layers 1033 and 1035 function as barrier films. The conductive layer 1037 functions as an electrode or a wiring.

[0245] 10A, one of the source and drain of the Si transistor 1100 (here, the low-resistance region 1014) is connected to one of the source and drain of the OS transistor 1200 through a conductive layer. Also, as shown in FIG. 10B, the gate of the Si transistor 1100 is connected to the gate of the OS transistor 1200 through a conductive layer.

[0246] Si transistors have higher field-effect mobility and faster operation speed than OS transistors. Furthermore, OS transistors have significantly lower off-state current than Si transistors. In particular, OS transistors that use indium oxide for the semiconductor layer in which a channel is formed have significantly lower off-state current and higher field-effect mobility comparable to that of Si transistors. A CMOS circuit with low power consumption and high-speed operation can be realized by using an OS transistor and a Si transistor in combination.

[0247] In this embodiment, examples of logic circuits including a NOT circuit, a NOR circuit, and a NAND circuit will be described as examples of circuits including Si transistors and OS transistors.

[0248] [NOT Circuit] Fig. 11A is a circuit diagram showing an example of the configuration of a NOT circuit (NOT). A NOT circuit is also called an inversion circuit, an inverter circuit, etc. Fig. 11B shows the circuit symbol of a NOT circuit. Fig. 11C is a timing chart explaining the operation of the NOT circuit.

[0249] The NOT circuit shown in FIG. 11A includes a transistor Tr11 and a transistor Tr12. The transistor Tr11 is a Si transistor functioning as a p-type transistor, and the transistor Tr12 is an OS transistor functioning as an n-type transistor. A potential H (e.g., a high power supply potential VDD) is supplied to one of the source and the drain of the transistor Tr11. The other of the source and the drain of the transistor Tr11 is connected to one of the source and the drain of the transistor Tr12 and to a terminal Y. A potential L (e.g., a low power supply potential VSS) is supplied to the other of the source and the drain of the transistor Tr12. The gates of the transistors Tr11 and Tr12 are connected to a terminal A.

[0250] 11A, the terminal A functions as an input terminal, and the terminal Y functions as an output terminal. When a potential H is input to the terminal A of the NOT circuit, the terminal Y outputs a potential L, and when a potential L is input to the terminal A, the terminal Y outputs a potential H (see FIG. 11C).

[0251] As shown in FIG. 11C , the NOT circuit has a function of correcting an input signal distorted by wiring resistance, parasitic capacitance, noise, etc., to a signal that is distorted or has reduced distortion, and outputting the corrected signal (also referred to as a "waveform shaping function"). The NOT circuit also has a function of amplifying the voltage amplitude of the input signal and outputting the signal. The output of the NOT circuit is supplied to a load such as a capacitance element Cx and a transistor Trx. Since power is supplied to the output of the NOT circuit via transistor Tr11 or transistor Tr12, the ability to drive a load connected to the output can be improved. The NOT circuit has a function of improving the ability to drive a load (also referred to as a "driving force improvement function").

[0252] [NOR Circuit] Fig. 12A is a circuit diagram showing an example of the configuration of a two-input, one-output NOR circuit (NOR). Fig. 12B shows a circuit symbol for the NOR circuit. The NOR circuit shown in Fig. 12A includes transistors Tr21, Tr22, Tr23, and Tr24. Si transistors functioning as p-channel transistors are used as the transistors Tr21 and Tr22, and OS transistors functioning as n-channel transistors are used as the transistors Tr23 and Tr24.

[0253] 12A , a potential H is supplied to one of the source or drain of transistor Tr21. The other of the source or drain of transistor Tr21 is connected to one of the source or drain of transistor Tr22. The other of the source or drain of transistor Tr22 is connected to one of the source or drain of transistor Tr23, one of the source or drain of transistor Tr24, and terminal Y. A potential L is supplied to the other of the source or drain of transistor Tr23 and the other of the source or drain of transistor Tr24.

[0254] The gate of the transistor Tr21 is connected to the gate of the transistor Tr23 and the terminal A. The gate of the transistor Tr22 is connected to the gate of the transistor Tr24 and the terminal B.

[0255] 12A and 12B has a function of outputting a potential H from a terminal Y when a potential L is input to both a terminal A and a terminal B. In addition, the NOR circuit has a function of outputting a potential L from a terminal Y when a potential H is input to one or both of the terminals A and B.

[0256] Furthermore, as shown in FIG. 12C, an OR circuit can be realized by connecting the input of a NOT circuit to the output of a NOR circuit.

[0257] [NAND Circuit] Fig. 12D is a circuit diagram showing a configuration example of a two-input, one-output NAND circuit (NAND). Fig. 12E shows a circuit symbol of the NAND circuit. The NAND circuit shown in Fig. 12D includes transistors Tr31, Tr32, Tr33, and Tr34. Si transistors functioning as p-channel transistors are used as the transistors Tr31 and Tr32, and OS transistors functioning as n-channel transistors are used as the transistors Tr33 and Tr34.

[0258] 12D , a potential H is supplied to one of the source or drain of transistor Tr31 and one of the source or drain of transistor Tr32. The other of the source or drain of transistor Tr31 and the other of the source or drain of transistor Tr32 are connected to one of the source or drain of transistor Tr33 and terminal Y. The other of the source or drain of transistor Tr33 is connected to one of the source or drain of transistor Tr34. A potential L is supplied to the other of the source or drain of transistor Tr34.

[0259] The gate of the transistor Tr31 is connected to the gate of the transistor Tr34 and the terminal B. The gate of the transistor Tr32 is connected to the gate of the transistor Tr33 and the terminal A.

[0260] 12D and 12E has a function of outputting a potential L from a terminal Y when a potential H is input to both a terminal A and a terminal B. In addition, the NAND circuit has a function of outputting a potential H from a terminal Y when a potential L is input to one or both of the terminals A and B.

[0261] Furthermore, as shown in FIG. 12F, an AND circuit can be realized by combining a NAND circuit with a NOT circuit.

[0262] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0263] In this embodiment, an application example of a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device according to one embodiment of the present invention is suitable for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers because it can provide a transistor with high on-state current and a small area.

[0264] [Electronic Component] FIG. 13A shows a perspective view of a substrate (mounting substrate 989) on which an electronic component 980 is mounted. The electronic component 980 shown in FIG. 13A has a semiconductor device 981 inside a mold 984. FIG. 13A omits some details in order to show the interior of the electronic component 980. The electronic component 980 has lands 985 on the outside of the mold 984. The lands 985 are electrically connected to electrode pads 986, and the electrode pads 986 are electrically connected to the semiconductor device 981 via wires 987. The electronic component 980 is mounted on, for example, a printed circuit board 988. A plurality of such electronic components are combined and electrically connected on the printed circuit board 988 to complete the mounting substrate 989.

[0265] The semiconductor device 981 also includes a drive circuit layer 982 and a memory layer 983. The memory layer 983 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 982 and the memory layer 983 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 982 and the memory layer 983, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0266] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0267] Furthermore, it is preferable that the memory cell arrays included in the memory layer 983 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked configuration, it is possible to improve one or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 983, it is more difficult to form a monolithic stacked configuration than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked configuration.

[0268] The semiconductor device 981 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0269] 13B shows a perspective view of an electronic component 990. The electronic component 990 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 990 has an interposer 991 provided on a package substrate 992 (printed circuit board), and a semiconductor device 994 and a plurality of semiconductor devices 981 provided on the interposer 991.

[0270] The electronic component 990 shows an example in which the semiconductor device 981 is used as a high bandwidth memory (HBM). The semiconductor device 994 can be used in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0271] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 992. For example, a silicon interposer or a resin interposer can be used as the interposer 991.

[0272] The interposer 991 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 991 also functions to connect the integrated circuits provided on the interposer 991 to electrodes provided on the package substrate 992. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 991, and the integrated circuits and the package substrate 992 are connected using the through electrodes. In addition, in a silicon interposer, TSVs can also be used as through electrodes.

[0273] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0274] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0275] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 990, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array.

[0276] A heat sink (heat dissipation plate) may be provided over the electronic component 990. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 991. For example, in the electronic component 990 shown in this embodiment, it is preferable to align the height of the semiconductor device 981 and the height of the semiconductor device 994.

[0277] Electrodes 993 may be provided on the bottom of the package substrate 992 in order to mount the electronic component 990 on another substrate. FIG. 13B shows an example in which the electrodes 993 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 992, BGA (Ball Grid Array) mounting can be achieved. The electrodes 993 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 992, PGA (Pin Grid Array) mounting can be achieved.

[0278] The electronic component 990 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0279] 14A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 shown in Fig. 14A has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0280] The computer 5620 can have the configuration shown in the perspective view of Fig. 14B, for example. In Fig. 14B, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0281] A PC card 5621 shown in Figure 14C is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622. The board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Figure 14C illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, but for these semiconductor devices, the following descriptions of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 can be referred to.

[0282] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630 , and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630 .

[0283] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 can be connected to the board 5622 by inserting the terminal into a socket (not shown) provided on the board 5622.

[0284] Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. The semiconductor device 5627 may be, for example, the electronic component 990.

[0285] The semiconductor device 5628 can be, for example, a memory device. The semiconductor device 5628 can be, for example, the electronic component 990.

[0286] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0287] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

[0288] A semiconductor device according to one embodiment of the present invention includes an OS transistor. Compared to a Si transistor, an OS transistor exhibits smaller variations in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and is therefore highly reliable and suitable for use in environments where radiation may be incident. For example, an OS transistor can be suitably used in outer space. Specifically, an OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Note that outer space refers to an altitude of 100 km or higher, for example. However, the outer space described in this specification can include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0289] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0290] Fig. 14D shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 14D also shows a planet 6804 in space.

[0291] 14D , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0292] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the control device 6807 is preferably a semiconductor device including an OS transistor which is one embodiment of the present invention.

[0293] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0294] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0295] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to accommodate the installation of storage and servers for storing a huge amount of data, a stable power source for storing the data, or cooling equipment required for storing the data.

[0296] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0297] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0298] Fig. 14E shows a storage system applicable to a data center. The storage system 7010 shown in Fig. 14E has a plurality of servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has a plurality of storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0299] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0300] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0301] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0302] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0303] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0304] 11: insulating layer, 12: spacer layer, 12a: spacer layer, 12b: spacer layer, 13: semiconductor layer, 14: conductive layer, 14a: conductive layer, 14b: conductive layer, 15: conductive layer, 15a: conductive layer, 15b: conductive layer, 16: insulating layer, 17: insulating layer, 18: insulating layer, 19: conductive layer, 19a: conductive layer, 19b: conductive layer, 41: insulating layer, 61: island-shaped film, 62: island-shaped film, 63: island-shaped film, 64: trench, 100: transistor, 980: electronic component, 981: semiconductor device, 982: drive circuit layer, 983: memory layer, 984: mold, 985: land, 986: electrode pad, 987: wire, 988: printed circuit board, 989: mounting board, 990: electronic component, 991: interposer, 992: package substrate, 993: electrode, 994: semiconductor device, 1011: substrate, 1012: element isolation layer, 1013: semiconductor region, 1014: low resistance region, 1015: insulating layer, 1016: insulating layer, 1017: insulating layer, 1018a: conductive layer, 1018b: dummy gate electrode, 1018c: dummy gate electrode, 1019: insulating layer, 1020: insulating layer, 1021: insulating layer, 1022: conductive layer, 1023: insulating layer, 1024: conductive layer, 1025: insulating layer, 1026: insulating layer, 1027: insulating layer, 1028: conductive layer, 1029: insulating layer, 1030: insulating layer, 1031: insulating layer, 1032: conductive layer, 1033: insulating layer, 1034: insulating layer, 1035: insulating layer, 1036: insulating layer, 1037: conductive layer, 1100: Si transistor, 1200: OS transistor, Cx: capacitor, Tr11: transistor, Tr12: transistor, Tr21: transistor, Tr22: transistor, Tr23: transistor, Tr24: transistor, Tr31: transistor, Tr32: transistor, Tr33: transistor Tr34: transistor, Trx: transistor, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7001: host,7001sb: server, 7002: storage control circuit, 7003: storage, 7003md: storage device, 7010: storage system,

Claims

a first semiconductor layer, a pair of first spacer layers, a pair of first conductive layers, a second conductive layer, a first insulating layer, a second insulating layer, and a third insulating layer; the pair of first spacer layers are spaced apart and positioned above the first insulating layer; the first semiconductor layer is located above the pair of first spacer layers and has a first region that does not overlap with the pair of first spacer layers; the pair of first conductive layers are spaced apart and have portions located above the first semiconductor layer; each of the pair of first conductive layers has a portion in contact with at least two side surfaces of the first semiconductor layer; the third insulating layer has a portion located on the pair of first conductive layers, a portion in contact with side surfaces of the pair of first conductive layers, and a portion in contact with the first insulating layer; the second insulating layer has portions in contact with an upper surface, a lower surface, and a side surface of the first semiconductor layer in the first region of the first semiconductor layer; the second conductive layer has a portion surrounding an upper surface, a lower surface, and a side surface of the first semiconductor layer via the second insulating layer; Semiconductor device. 　 In claim 1, a pair of third conductive layers; The pair of third conductive layers are on and in contact with the first semiconductor layer and have portions located between the first semiconductor layer and the pair of first conductive layers. 　 a first semiconductor layer, a second semiconductor layer, a pair of first spacer layers, a pair of second spacer layers, a pair of first conductive layers, a second conductive layer, a first insulating layer, a second insulating layer, and a third insulating layer; the pair of first spacer layers are spaced apart and positioned above the first insulating layer; the first semiconductor layer is located above the pair of first spacer layers and has a first region that does not overlap with the pair of first spacer layers; the pair of second spacer layers are spaced apart and positioned above the first semiconductor layer; the second semiconductor layer is located above the pair of second spacer layers and has a second region that does not overlap with the pair of second spacer layers; the pair of first conductive layers are spaced apart and have portions located above the second semiconductor layer; each of the pair of first conductive layers has a portion in contact with at least two side surfaces of the first semiconductor layer and a portion in contact with at least two side surfaces of the second semiconductor layer; the third insulating layer has a portion located on the pair of first conductive layers, a portion in contact with side surfaces of the pair of first conductive layers, and a portion in contact with the first insulating layer; the second insulating layer has, in the first region of the first semiconductor layer, a portion in contact with an upper surface, a lower surface, and a side surface of the first semiconductor layer, and a portion in contact with an upper surface, a lower surface, and a side surface of the second semiconductor layer in the second region of the second semiconductor layer; the second conductive layer has a portion surrounding an upper surface, a lower surface, and a side surface of the first semiconductor layer and a portion surrounding an upper surface, a lower surface, and a side surface of the second semiconductor layer, with the second insulating layer interposed therebetween; Semiconductor device.

4. The semiconductor device according to claim 3, wherein the second semiconductor layer has a portion in contact with the pair of second spacer layers.

4. The semiconductor device according to claim 3, wherein the second semiconductor layer is made of indium oxide, and the pair of second spacer layers are made of a metal oxide containing indium, gallium, and zinc. 　 In claim 3, a pair of third conductive layers; The pair of third conductive layers are on and in contact with the second semiconductor layer and have portions located between the second semiconductor layer and the pair of first conductive layers.

4. The semiconductor device according to claim 1, wherein the first semiconductor layer has a portion in contact with the pair of first spacer layers.

4. The semiconductor device according to claim 1, wherein the first semiconductor layer is made of indium oxide, and the pair of first spacer layers is made of a metal oxide containing indium, gallium, and zinc.

Images