Image sensor, light detection device, and control method for image sensor

Abstract

The present invention improves the image quality of an image sensor that reads out voltage that corresponds to charge.　According to the present invention, a photoelectric conversion film generates charge by photoelectric conversion. A charge accumulator accumulates the charge. An amplification transistor successively outputs a reset level that corresponds to the voltage of the charge accumulator at initialization and a signal level that corresponds to the voltage of the charge accumulator after a prescribed accumulation period has passed. A connection transistor controls a conversion gain for conversion of charge to voltage to any of a plurality of values. A vertical drive unit causes the reset level to be outputted while causing the conversion gain to to be controlled to each of the plurality of values when the charge accumulator has been initialized and causes the signal level to be outputted while causing the conversion gain to be controlled to each of the plurality of values when the accumulation period has passed.

Description

Image sensor, photodetection device, and method for controlling image sensor

[0001] The present technology relates to an image sensor, and more particularly to an image sensor that reads out a voltage according to an amount of charge, a photodetector, and a method for controlling the image sensor.

[0002] Conventionally, image sensors have been configured to photoelectrically convert photons into signal charges (electrons and holes), store them, and then read out a voltage signal corresponding to the amount of stored charge as an image signal. This configuration is also used in visible light image sensors using silicon, as well as infrared image sensors using compound semiconductors such as indium gallium arsenide (InGaAs), quantum dots, or organic photoelectric conversion elements.

[0003] In these image sensors, a larger capacitance for accumulating signal charges is better for achieving a wide dynamic range. On the other hand, a smaller capacitance (i.e., a higher conversion gain) is better for achieving high sensitivity. For example, an infrared image sensor has been proposed that reads out a signal level while controlling the conversion gain to high gain and low gain, and then reads out a reset level while maintaining the high gain (see, for example, Patent Document 1).

[0004] International Publication No. 2022 / 201874

[0005] The above-mentioned conventional technology achieves a wide dynamic range and high sensitivity by reading out signal levels at both high and low gains. However, the above-mentioned conventional technology does not read out the reset level at low gain. Therefore, when calculating the difference between the low-gain signal level and the high-gain reset level, there is a risk of noise occurring due to poor correlation between them, resulting in a deterioration in image quality. Furthermore, with the above-mentioned conventional technology, when pixels are miniaturized, the size of the capacitance within the pixel becomes smaller, which narrows the dynamic range and may result in a deterioration in image quality.

[0006] This technology was developed in light of these circumstances, and aims to improve image quality in image sensors that read out voltages according to the amount of charge.

[0007] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is an image sensor and a control method thereof, including: a photoelectric conversion film that generates charges by photoelectric conversion; a charge accumulation unit that accumulates the charges; an amplification transistor that sequentially outputs a reset level corresponding to an initialized voltage of the charge accumulation unit and a signal level corresponding to the voltage of the charge accumulation unit after a predetermined accumulation period has elapsed; a connection transistor that controls a conversion gain when the charges are converted into the voltage to one of a plurality of values; and a vertical drive unit that, when the charge accumulation unit is initialized, controls the conversion gain to one of the plurality of values ​​and outputs the reset level, and when the accumulation period has elapsed, controls the conversion gain to one of the plurality of values ​​and outputs the signal level, thereby achieving an effect of realizing a wide dynamic range and high sensitivity.

[0008] In addition, in this first aspect, the photoelectric conversion element may further include a reset transistor that initializes the charge storage unit, the charge storage unit including first and second charge storage regions, the photoelectric conversion film being connected to the first charge storage region, and the connection transistor controlling the conversion gain by opening and closing a path between the first and second charge storage regions, thereby providing the effect of controlling the conversion gain in two stages.

[0009] In addition, in the first aspect, the device may further include a reset transistor that initializes the charge accumulation unit and a transfer transistor that transfers the charge from the photoelectric conversion film to the charge accumulation unit, thereby enabling exposure by a global shutter method.

[0010] In addition, in this first aspect, the photoelectric conversion element may further include a reset transistor that initializes the charge storage unit, the charge storage unit including first, second, and third charge storage regions, the photoelectric conversion film being connected to the first charge storage region, and the connection transistor including a first connection transistor that opens and closes one of two paths between the first, second, and third charge storage regions and a second connection transistor that opens and closes the other of the two paths, thereby providing the effect of controlling the conversion gain in three stages.

[0011] In addition, in this first aspect, the device may further include a reset transistor that initializes the charge storage unit and a charge drain transistor that drains a portion of the charge from the charge storage unit every time a predetermined period has elapsed over the storage period, thereby providing the effect of expanding the dynamic range regardless of the size of the charge storage unit.

[0012] In addition, in this first aspect, the semiconductor memory device may further include a charge drain transistor that initializes the charge storage unit before the start of the accumulation period and drains a portion of the charge from the charge storage unit every time a predetermined period has elapsed within the accumulation period, thereby reducing the number of reset transistors.

[0013] In addition, in this first aspect, the image reading device may further include an analog-to-digital converter that converts the reset level and the signal level into digital signals in order, and the digital signals may include low-gain reset data corresponding to the reset level when the conversion gain is lower than a predetermined value, high-gain reset data corresponding to the reset level when the conversion gain is higher than the predetermined value, low-gain signal data corresponding to the signal level when the conversion gain is lower than the predetermined value, and high-gain signal data corresponding to the signal level when the conversion gain is higher than the predetermined value. This brings about the effect of reading out data for four frames.

[0014] In addition, in this first aspect, the accumulation period may include a plurality of accumulation periods, the low-gain signal data may include first low-gain signal data and second low-gain signal data having different accumulation periods, and the high-gain signal data may include first high-gain signal data and second high-gain signal data having different accumulation periods. This brings about an effect of enabling moving object determination.

[0015] In addition, in the first aspect, the digital signal processing device may further include a difference calculation unit that calculates a difference between the low-gain reset data and the low-gain signal data as low-gain Correlated Double Sampling (CDS) data, and calculates a difference between the high-gain reset data and the high-gain signal data as high-gain CDS data, thereby reducing the amount of output data.

[0016] In addition, in the first aspect, a synthesis processing unit may be further provided that synthesizes the low-gain CDS data and the high-gain CDS data, thereby providing the effect of reducing the amount of output data.

[0017] According to a second aspect of the present technology, there is provided an image sensor including a charge storage unit including a plurality of charge storage regions for storing electric charges, a connection transistor for opening and closing paths between the plurality of charge storage regions, and a charge drain transistor for periodically draining a portion of the electric charges from the charge storage unit over an accumulation period, thereby achieving an effect of expanding the dynamic range regardless of the size of the charge storage unit.

[0018] In addition, in the second aspect, the display device may further comprise a vertical drive section that drives the connection transistor and the charge discharging transistor over the accumulation period, thereby providing the effect of periodically driving the transistors.

[0019] In this second aspect, the vertical drive unit may periodically drive the connection transistor and the charge drain transistor, and may change at least one of the period for driving the connection transistor and the period for driving the charge drain transistor at a predetermined timing within the accumulation period, thereby achieving the effect of maintaining a constant output even under a light source whose brightness periodically fluctuates.

[0020] In this second aspect, the vertical drive section may drive the charge discharging transistor at a predetermined cycle throughout the accumulation period, and drive the connection transistor at a cycle different from the predetermined cycle, thereby achieving the effect of finely adjusting the amount of discharged charge.

[0021] In this second aspect, the photoelectric conversion unit, the charge accumulation unit, the connection transistor, and the charge discharge transistor may be arranged in first and second pixels having different sensitivities, respectively, and the vertical drive unit may drive the charge discharge transistor arranged in the first pixel at a predetermined cycle over an accumulation period, and drive the charge discharge transistor arranged in the second pixel at a cycle different from the predetermined cycle, thereby providing an effect of controlling the cycle according to sensitivity.

[0022] In addition, in this second aspect, the charge accumulation unit may further include first, second, and third charge accumulation regions, the photoelectric conversion unit may be connected to the first charge accumulation region, and the connection transistor may include a first connection transistor that opens and closes one of two paths between the first, second, and third charge accumulation regions and a second connection transistor that opens and closes the other of the two paths, thereby providing an effect of enabling control of the conversion gain.

[0023] In the second aspect, the vertical drive section may drive the first connection transistor at a predetermined cycle over an accumulation period, and drive the second connection transistor at a cycle different from the predetermined cycle, thereby providing an effect of controlling the conversion gain.

[0024] In the second aspect, the vertical drive section may drive the first connection transistor at a predetermined cycle while controlling the second connection transistor to be in an on state throughout the accumulation period, thereby providing an effect of changing the ratio between the storage capacitance and the discharge capacitance.

[0025] According to a third aspect of the present technology, there is provided a photodetector device including: a photoelectric conversion film that generates charges by photoelectric conversion; a charge accumulation unit that accumulates the charges; an amplifying transistor that sequentially outputs a reset level corresponding to an initialized voltage of the charge accumulation unit and a signal level corresponding to the voltage of the charge accumulation unit after a predetermined accumulation period has elapsed; a connection transistor that controls a conversion gain when converting the charges to the voltage to one of a plurality of values; a vertical drive unit that, when the charge accumulation unit is initialized, controls the conversion gain to each of the plurality of values ​​and outputs the reset level, and, when the accumulation period has elapsed, controls the conversion gain to each of the plurality of values ​​and outputs the signal level; an analog-to-digital converter that sequentially converts the reset level and the signal level into digital signals; and a signal processing circuit that processes frames in which the digital signals are arranged, thereby improving the image quality of the frames.

[0026] 1 is a block diagram showing an example of a configuration of a photodetector according to a first embodiment of the present technology. FIG. 2 is a circuit diagram showing an example of a configuration of a pixel according to the first embodiment of the present technology. FIG. 3 is a block diagram showing an example of a configuration of a column processing unit according to the first embodiment of the present technology. FIG. 4 is a block diagram showing an example of a configuration of a DSP (Digital Signal Processing) circuit according to the first embodiment of the present technology. FIG. 5 is a timing chart showing an example of a readout operation of an image sensor at the start of exposure according to the first embodiment of the present technology. FIG. 6 is a timing chart showing an example of a readout operation of an image sensor at the end of exposure according to the first embodiment of the present technology. FIG. 7 is an example of a potential diagram within a pixel according to the first embodiment of the present technology. FIG. 8 is a flowchart showing an example of an operation of an image sensor according to the first embodiment of the present technology. FIG. 9 is a circuit diagram showing an example of a configuration of a pixel according to a first modified example of the first embodiment of the present technology. FIG. 10 is a timing chart showing an example of a readout operation of an image sensor after the start of exposure according to the first modified example of the first embodiment of the present technology. FIG. 11 is a timing chart showing an example of a readout operation of an image sensor after the end of exposure according to the first modified example of the first embodiment of the present technology. FIG. 12 is a block diagram showing an example of a configuration of a column processing unit according to a second modified example of the first embodiment of the present technology. 10 is a timing chart showing an example of a readout operation of an image sensor in a second modified example of the first embodiment of the present technology. FIG. 11 is a block diagram showing an example of a configuration of a column processing unit in a third modified example of the first embodiment of the present technology. FIG. 12 is a timing chart showing an example of a readout operation of an image sensor in a third modified example of the first embodiment of the present technology. FIG. 13 is a timing chart showing an example of a readout operation of reset data and signal data in a fourth modified example of the first embodiment of the present technology. FIG. 14 is a timing chart showing an example of a readout operation of signal data in a fourth modified example of the first embodiment of the present technology. FIG. 15 is a block diagram showing an example of a configuration of a data calculation unit in a fourth modified example of the first embodiment of the present technology. FIG. 16 is a circuit diagram showing an example of a configuration of a pixel in a second embodiment of the present technology.10 is a timing chart showing an example of a readout operation of an image sensor at the start of exposure in a second embodiment of the present technology. FIG. 11 is a timing chart showing an example of a readout operation of an image sensor at the end of exposure in a second embodiment of the present technology. FIG. 12 is a circuit diagram showing an example of a configuration of a pixel in a modified example of the second embodiment of the present technology. FIG. 13 is a timing chart showing an example of a readout operation of an image sensor at the start of exposure in a modified example of the second embodiment of the present technology. FIG. 14 is a circuit diagram showing an example of a configuration of a pixel in a third embodiment of the present technology. FIG. 15 is a timing chart showing an example of an operation of an image sensor during an accumulation period in a third embodiment of the present technology. FIG. 16 is a timing chart showing an example of a readout operation of an image sensor at the end of exposure in a third embodiment of the present technology. FIG. 17 is a block diagram showing an example of a configuration of a DSP circuit in a third embodiment of the present technology. FIG. 18 is a timing chart showing an example of an operation of an image sensor during an accumulation period in a first modified example of the third embodiment of the present technology. FIG. 19 is a block diagram showing an example of a configuration of a photodetector in a second modified example of the third embodiment of the present technology. FIG. 19 is a timing chart showing an example of an operation of an image sensor during an accumulation period in a second modified example of the third embodiment of the present technology. FIG. 10 is a circuit diagram showing a configuration example of a pixel in a fourth embodiment of the present technology. FIG. 11 is a timing chart showing an example of operation of an image sensor during an accumulation period in the fourth embodiment of the present technology. FIG. 12 is a timing chart showing an example of readout operation of an image sensor at the end of exposure in the fourth embodiment of the present technology. FIG. 13 is a block diagram showing a configuration example of a DSP circuit in the fourth embodiment of the present technology. FIG. 14 is a timing chart showing an example of operation of an image sensor during an accumulation period in a modified example of the fourth embodiment of the present technology. FIG. 15 is a timing chart showing an example of readout operation of an image sensor at the end of exposure in a modified example of the fourth embodiment of the present technology. FIG. 16 is a circuit diagram showing a configuration example of a pixel in a fifth embodiment of the present technology. FIG. 17 is a timing chart showing an example of operation of an image sensor at the start of exposure and during an accumulation period in a modified example of the fifth embodiment of the present technology.Fig. 10 is a timing chart showing an example of a readout operation of an image sensor at the end of exposure in a modified example of the fifth embodiment of the present technology. Fig. 11 is a circuit diagram showing an example of a configuration of a pixel in a sixth embodiment of the present technology. Fig. 12 is a timing chart showing an example of an operation of an image sensor at the start of exposure and during an accumulation period in a modified example of the sixth embodiment of the present technology. Fig. 13 is a timing chart showing an example of a readout operation of an image sensor at the end of exposure in a modified example of the sixth embodiment of the present technology. Fig. 14 is a block diagram showing an example of a schematic configuration of a vehicle control system. Fig. 15 is an explanatory diagram showing an example of installation positions of an outside-vehicle information detection unit and an imaging unit.

[0027] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order. 1. First embodiment (an example in which a reset level and a signal level are output while controlling the conversion gain in two stages) 2. Second embodiment (an example in which a reset level and a signal level are output while controlling the conversion gain in three stages) 3. Third embodiment (an example in which a part of the charge is periodically discharged within the accumulation period) 4. Fourth embodiment (an example in which a part of the charge is periodically discharged within the accumulation period and the conversion gain is controlled) 5. Fifth embodiment (an example in which a part of the charge is periodically discharged within the accumulation period and the reset level and signal level are output while controlling the conversion gain in two stages) 6. Sixth embodiment (an example in which a part of the charge is periodically discharged within the accumulation period in a pixel with reduced transistors and the reset level and signal level are output while controlling the conversion gain in two stages) 7. Application example to a moving body

[0028] 1 is a block diagram showing an example of the configuration of a photodetection device 100 according to an embodiment of the present technology. The photodetection device 100 is a device that detects light and captures image data, and includes an image sensor 200 and a DSP circuit 400.

[0029] The image sensor 200 includes a vertical drive unit 210, a system control unit 220, a pixel array unit 230, a column processing unit 300, and a horizontal drive unit 290. A plurality of pixels 240 are arranged in a two-dimensional lattice pattern in the pixel array unit 230. For example, an infrared image sensor that receives infrared rays via an optical filter or the like is used as the image sensor 200.

[0030] The vertical drive section 210 sequentially selects and drives rows in the pixel array section 230 to output analog signals as pixel signals.

[0031] The system control unit 220 controls the operation timing of the vertical drive unit 210, the column processing unit 300, and the horizontal drive unit 290 in synchronization with a vertical synchronization signal VS. The system control unit 220 also generates a horizontal synchronization signal HS, which has a higher frequency than the vertical synchronization signal VS, in synchronization with the vertical synchronization signal VS and supplies the horizontal synchronization signal HS to the vertical drive unit 210. The vertical drive unit 210 selects a row in synchronization with the horizontal synchronization signal HS.

[0032] The column processing unit 300 performs various signal processing such as AD (Analog to Digital) conversion processing on pixel signals for each column in the pixel array unit 230. The column processing unit 300 supplies the processed digital signals to the DSP circuit 400.

[0033] The horizontal driving section 290 controls the column processing section 300 to output digital signals for each column in sequence.

[0034] The DSP circuit 400 performs various signal processing such as CDS processing on the digital signals from the column processing section 300. The DSP circuit 400 outputs image data in the form of frames, in which the processed signals are arranged.

[0035] The photodetector 100 may further include a recording unit for recording frames, an interface for outputting frames to the outside, and the like.

[0036] 2 is a circuit diagram showing an example of the configuration of a pixel 240 according to the first embodiment of the present technology. The pixel 240 includes a connection transistor 241, a photoelectric conversion film 243, a reset transistor 244, an amplification transistor 245, a selection transistor 246, and charge accumulation regions 251 and 252. For example, an nMOS (n-channel Metal Oxide Semiconductor) transistor is used as each transistor in the pixel 240. In addition, a vertical signal line 229 is wired for each column in the pixel array unit 230.

[0037] The charge storage region 251 is a capacitance node that stores signal charges from the photoelectric conversion film 243 and generates a voltage according to the amount of stored charge. For example, the input capacitance of the transistor, the wiring capacitance, the diffusion capacitance, and the parasitic capacitance within the film are used as this capacitance.

[0038] The charge storage region 252 is a capacitance node that stores charge that overflows from the charge storage region 251. For example, the input capacitance or wiring capacitance of a transistor is used as this capacitance. The capacitance formed by the charge storage regions 251 and 252 is hereinafter referred to as a "charge storage portion."

[0039] The charge storage regions 251 and 252 are examples of the first and second charge storage regions set forth in the claims.

[0040] The connection transistor 241 controls the conversion gain when converting charge into voltage by opening and closing a path between the charge accumulation regions 251 and 252 in accordance with a drive signal FX from the vertical drive unit 210. The threshold value of this connection transistor 241 is lower than that of the reset transistor 244. Alternatively, the off-voltage, which is the voltage applied to the gate of the connection transistor 241 when it is off, is lower than the off-voltage of the reset transistor 244. As a result, when the charge accumulation region 251 becomes saturated during the accumulation period, the overflowing charge is accumulated in the charge accumulation region 252 via the connection transistor 241 in the off state.

[0041] When the connection transistor 241 is in the on state, the conversion gain is controlled to a high gain higher than a predetermined value, and when the connection transistor 241 is in the off state, the conversion gain is controlled to a low gain lower than the predetermined value.

[0042] If the capacitance value of the charge accumulation section (i.e., charge accumulation regions 251 and 252) is C and the elementary charge is q, the conversion gain is q / C. If the capacitance value of the charge accumulation region 251 is C_FD and the capacitance value of the charge accumulation region 252 is C_FC, the high gain HG and the low gain LG are respectively expressed by the following equations: HG=q / C_FD (Equation 1) LG=q / (C_FD+C_FC) (Equation 2)

[0043] The photoelectric conversion film 243 generates signal charges through photoelectric conversion. This photoelectric conversion film 243 is composed of a compound semiconductor such as indium gallium arsenide (InGaAs), quantum dots, organic photoelectric conversion elements, etc. One end of the photoelectric conversion film 243 is connected to a power supply line L1 that supplies a power supply voltage VTOP, and the other end is connected to the charge accumulation region 251.

[0044] The reset transistor 244 initializes the potential of the charge accumulation section (charge accumulation regions 251 and 252) in accordance with a reset signal RST from the vertical drive section 210. For example, the potential of the charge accumulation section is initialized to a reset power supply voltage VDDRST supplied via a power supply line L2. Note that although the reset transistor 244 is connected to the charge accumulation region 251, it may also be connected to the charge accumulation region 252.

[0045] The amplifier transistor 245 forms a source follower circuit with its drain connected to the power supply voltage VDD, and outputs a signal at a level corresponding to the voltage of the charge storage region 251 .

[0046] Hereinafter, the voltage of the charge accumulation region 251 when initialized and the level corresponding to that voltage (the output level of the amplification transistor 245 and the potential of the vertical signal line 229) will be referred to as the "reset level." Furthermore, the voltage of the charge accumulation region 251 after a predetermined accumulation period has elapsed and the level corresponding to that voltage will be referred to as the "signal level."

[0047] The selection transistor 246 outputs the signal from the amplification transistor 245 to the vertical signal line 229 as a pixel signal in accordance with a selection signal SEL from the vertical drive unit 210 .

[0048] The vertical driver 210 sequentially selects and exposes rows using a rolling shutter method. At the start of an accumulation period, the vertical driver 210 initializes the charge storage unit and controls the conversion gain to a low gain or a high gain while outputting a reset level. After the accumulation period has elapsed, the vertical driver 210 controls the conversion gain to a high gain or a low gain while outputting a signal level.

[0049] 3 is a block diagram showing an example of the configuration of the column processing unit 300 according to the first embodiment of the present technology. The column processing unit 300 includes a readout circuit 310 and a data output unit 340. The readout circuit 310 includes an ADC 311 for each column.

[0050] The ADC 311 converts pixel signals from the pixels 240 in the corresponding column into digital signals and supplies the digital signals to the data output unit 340. As the ADC 311, for example, a single-slope ADC is used.

[0051] Here, as described above, the vertical drive unit 210 controls the conversion gain to low gain and high gain at the start of the accumulation period and outputs the reset level. Hereinafter, the digital signal obtained by AD converting the reset level at low gain will be referred to as "LG reset data." Also, the digital signal obtained by AD converting the reset level at high gain will be referred to as "HG reset data."

[0052] Furthermore, the vertical drive unit 210 outputs a signal level while controlling the conversion gain to either high gain or low gain at the end of the accumulation period. Hereinafter, the digital signal obtained by AD converting the signal level at high gain will be referred to as "HG signal data." Also, the digital signal obtained by AD converting the signal level at low gain will be referred to as "LG signal data."

[0053] The data output section 340 outputs, for each pixel, the LG reset data, the HG reset data, the HG signal data, and the LG signal data in that order to the DSP circuit 400. The data in which these four data are arranged for each pixel corresponds to four frames of data.

[0054] 4 is a block diagram showing an example configuration of a DSP circuit 400 according to the first embodiment of the present technology. The DSP circuit 400 includes a holding memory 410 and a data calculation unit 420. The holding memory 410 includes data buffers 411, 412, 413, and 414. The data calculation unit 420 includes a difference calculation unit 421 and a synthesis processing unit 422.

[0055] The data buffer 411 holds LG reset data. The data buffer 412 holds HG reset data. The data buffer 413 holds HG signal data. The data buffer 414 holds LG signal data. These data buffers hold data, for example, in frame units or line units.

[0056] The difference calculation unit 421 performs CDS processing to calculate the difference between reset data and signal data. This difference calculation unit 421 calculates the difference between HG reset data and HG signal data for each pixel and outputs the result as HG CDS data to the synthesis processing unit 422. The difference calculation unit 421 also calculates the difference between LG reset data and LG signal data for each pixel and outputs the result as LG CDS data to the synthesis processing unit 422.

[0057] The synthesis processing unit 422 synthesizes the HG·CDS data and the LG·CDS data. This synthesis processing unit 422 obtains a determination result for each pixel as to whether or not the illuminance is higher than a predetermined value. For example, an analog circuit (not shown) in the image sensor 200 compares the signal level with a threshold for each column and supplies the comparison result to the synthesis processing unit 422 as the illuminance determination result. Alternatively, the DSP circuit 400 itself determines for each frame whether or not the pixel data in that frame exceeds the threshold, stores the result, and uses the determination result for the next frame.

[0058] For example, the synthesis processor 422 selects LG / CDS data as pixel data when the illuminance is higher than a predetermined value, and selects HG / CDS data as pixel data when the illuminance is lower than the predetermined value. The synthesis processor 422 then outputs image data in which the pixel data are arranged as a synthesis frame. This synthesis process makes it possible to achieve a wide dynamic range and high sensitivity.

[0059] [Example of Image Sensor Operation] Fig. 5 is a timing chart showing an example of a readout operation of the image sensor at the start of exposure according to the first embodiment of the present technology. In the figure, the vertical axis represents the row address, and the horizontal axis represents time. The same applies to the subsequent timing charts.

[0060] The vertical drive unit 210 sequentially selects rows using a rolling shutter method to start exposure, and outputs a reset level while switching the conversion gain from low gain to high gain for each row. The thick dotted lines from timing T1 to T3 in the figure indicate the timing for reading out the LG reset data for each row, and the dashed dotted lines indicate the timing for reading out the HG reset data for each row.

[0061] The readout period for the reset level of row n is defined as the period from timing T11 when the horizontal synchronization signal HS falls to timing T14 when the horizontal synchronization signal HS falls again. Here, n is an integer between 1 and N, where N is the total number of rows. During the readout period, the vertical drive unit 210 sets the drive signal FX for row n to high level at timing T11, and supplies a high-level reset signal RST to row n during the period from timing T11 to timing T12. This initializes the charge storage unit, and exposure of row n begins. In the figure, RST_[n], FX_[n], and SEL_[n] indicate signals to row n. This also applies to the subsequent timing charts.

[0062] Then, the vertical drive unit 210 sets the drive signal FX to low level at timing T13, thereby switching the conversion gain from low gain to high gain. The vertical drive unit 210 also supplies a high-level selection signal SEL to row n during the period from timing T11 to timing T14.

[0063] The ADC 311 for each column reads out the LG reset data in the period from timing T12 to T13, and reads out the HG reset data in the period from timing T13 to T14.

[0064] FIG. 6 is a timing chart showing an example of a readout operation of the image sensor at the end of exposure according to the first embodiment of the present technology.

[0065] At the end of exposure for each row, the vertical drive unit 210 outputs a signal level while switching the conversion gain from high to low. In the figure, the thick diagonal lines from timing T2 to T5 indicate the timing for reading out the HG signal data for each row, and the thin diagonal lines indicate the timing for reading out the LG signal data for each row. Timings T3 to T5 correspond to the accumulation period (i.e., the exposure period) for the signal charge of the final row. Timings T0 to T4 correspond to the frame period.

[0066] The period from timing T21 when the horizontal synchronization signal HS falls to timing T24 when the horizontal synchronization signal HS next falls is defined as the readout period for the signal levels of row n. During this readout period, the vertical drive unit 210 sets the drive signal FX to a high level at timing T22. This switches the conversion gain from high to low.

[0067] The vertical drive unit 210 then supplies a high-level reset signal RST to the nth row during the period from timing T23 to timing T24. The vertical drive unit 210 also supplies a high-level selection signal SEL to the nth row during the period from timing T21 to timing T24.

[0068] The ADC 311 for each column reads out the HG signal data in the period from timing T21 to T22, and reads out the LG signal data in the period from timing T22 to T23.

[0069] Thereafter, the controls shown in FIGS. 5 and 6 are repeatedly executed for each frame period.

[0070] Here, as a first comparative example, a configuration is considered in which the reset level and signal level are read out sequentially while controlling to either high gain or low gain on a row-by-row or frame-by-frame basis depending on the illuminance, as shown in FIG. 3 of Patent Document 1.

[0071] In this first comparative example, because the conversion gain is switched row by row or frame by frame, an appropriate conversion gain may not be set on a pixel by pixel basis. For example, if a high-illuminance pixel exists in a low-illuminance row set to high gain, the dynamic range may be narrowed. Also, if a low-illuminance pixel exists in a high-illuminance row set to low gain, the sensitivity may be insufficient.

[0072] Next, as shown in FIG. 4 of Patent Document 1, a configuration is assumed as a second comparative example in which the signal level is read out while controlling the gain to high and low at the end of exposure, and the reset level is read out while maintaining the high gain.

[0073] In this second comparative example, the DSP circuit 400 calculates the difference between the LG signal data and the HG reset data, and there is a risk that noise will occur due to the poor correlation between them, resulting in a deterioration in the quality of the image data.

[0074] In contrast, in the first embodiment, when the vertical drive unit 210 initializes the charge accumulation unit (in other words, when exposure starts), as described above, the vertical drive unit 210 controls the conversion gain for each pixel from low gain to high gain and outputs a reset level. Then, when the accumulation period has elapsed (in other words, when exposure has ended), the vertical drive unit 210 controls the conversion gain for each pixel from high gain to low gain and outputs a signal level. This pixel-by-pixel conversion gain switching can achieve a wider dynamic range and higher sensitivity than the first comparative example, in which the conversion gain is switched row by row or frame by frame.

[0075] Furthermore, the DSP circuit 400 can calculate the difference between the LG signal data and the LG reset data, and the difference between the HG signal data and the HG reset data, thereby reducing noise more than in the second comparative example in which the difference between the LG signal data and the HG reset data is calculated.

[0076] 7 is an example of a potential diagram within a pixel in the first embodiment of the present technology. In the figure, "a" shows a potential diagram when LG reset data is read, and "b" shows a potential diagram when HG reset data is read. In the figure, "c" shows a potential diagram when HG signal data is read, and "d" shows a potential diagram when LG signal data is read. The downward direction of "a," "b," "c," and "d" in the figure indicates a direction in which the potential increases.

[0077] As illustrated in FIG. 10A, the vertical drive unit 210 initializes the charge storage regions 251 and 252 and sets the drive signal FX to high level, thereby generating a reset level with low gain and reading out the LG reset data.

[0078] After reading out the LG reset data, the vertical drive unit 210 sets the drive signal FX to low level, as shown in b in the figure, thereby generating a reset level with high gain and reading out the HG reset data.

[0079] During the accumulation period, signal charge is accumulated in the charge accumulation region 251, but when the signal amount is large and exceeds the threshold of the connection transistor 241, the charge overflows via the connection transistor 241 and is accumulated in the charge accumulation region 252. In the figure, c and d show examples in which no overflow occurs.

[0080] Then, as shown in Fig. 1C, at the end of the accumulation period, signal charges corresponding to the amount of exposure are accumulated. The dark gray areas in Fig. 1C indicate signal charges. At this time, the drive signal FX remains at a low level, so a high-gain signal level is generated and the HG signal data is read out.

[0081] After reading out the HG signal data, the vertical drive section 210 sets the drive signal FX to high level, as shown by d in the figure, thereby generating a signal level with low gain and reading out the LG signal data.

[0082] 8 is a flowchart showing an example of the operation of the image sensor 200 according to the first embodiment of the present technology. This operation is started, for example, when a predetermined application for capturing a frame is executed.

[0083] The image sensor 200 selects a row and starts exposure by initializing the selected row (step S901).The image sensor 200 then reads out the LG reset data of the row (step S902) and the HG reset data (step S903).

[0084] Then, the image sensor 200 determines whether exposure of any row has been completed (step S904). If exposure of any row has been completed (step S904: Yes), the image sensor 200 reads out the HG signal data of the row for which exposure has been completed (step S905), and reads out the LG signal data (step S906).

[0085] Then, the image sensor 200 determines whether or not the readout of the reset levels of all rows has been completed (step S907). If the exposure of the first row has not yet been completed (step S904: No), or if the readout of the reset levels of any row has not been completed (step S907: No), the image sensor 200 repeats step S901 and subsequent steps.

[0086] If the readout of the reset levels of all rows has been completed (step S907: Yes), the image sensor 200 determines whether the readout of the signal levels of all rows has been completed (step S908).If the readout of the signal levels of any row has not been completed (step S908: No), the image sensor 200 repeatedly executes step S904 and subsequent steps.

[0087] When the reading of the signal levels of all rows is completed (step S908: Yes), the image sensor 200 ends the operation for capturing one frame. When capturing multiple frames consecutively, steps S901 to S908 are repeatedly executed in synchronization with the vertical synchronization signal VS.

[0088] As described above, according to the first embodiment of the present technology, when the charge storage unit is initialized, the vertical drive unit 210 controls the conversion gain from low gain to high gain and outputs a reset level. Then, when the storage period has elapsed, the vertical drive unit 210 controls the conversion gain from high gain to low gain and outputs a signal level. Through this control, the DSP circuit 400 can combine the LG CDS data and the HG CDS data to achieve a wide dynamic range and high sensitivity.

[0089] [First Modification] In the first embodiment described above, the image sensor 200 performs exposure using the rolling shutter method, but this control can cause rolling shutter distortion. The image sensor 200 in this first modification of the first embodiment differs from the first embodiment in that it performs exposure using the global shutter method.

[0090] 9 is a circuit diagram showing a configuration example of a pixel 240 in a first modified example of the first embodiment of the present technology. The pixel 240 in this first modified example of the first embodiment differs from the first embodiment in that it further includes a transfer transistor 247. In addition, in the first modified example of the first embodiment, the reset transistor 244 is connected to the charge accumulation region 252.

[0091] The transfer transistor 247 transfers signal charges from the photoelectric conversion film 243 to the charge accumulation region 251 in accordance with a transfer signal TX from the vertical drive section 210. As the transfer transistor 247, for example, an nMOS transistor is used.

[0092] It should be noted that the pixel 240 is not limited to the circuit configuration exemplified in the figure, as long as the circuit is capable of completely transferring the electric charges from the photoelectric conversion film 243 during readout.

[0093] 10 is a timing chart showing an example of a readout operation of an image sensor after the start of exposure in a first modified example of the first embodiment of the present technology. In a frame period from timing T0 to T7, a period from timing T11 to T12 is set as an initialization period for all rows. During this period, the vertical drive unit 210 supplies a high-level transfer signal TX, a reset signal RST, and a drive signal FX to all rows from the first row to the Nth row. This causes exposure to start simultaneously for all rows. TX_[1:N], RST_[1:N], and FX_[1:N] in the figure represent signals from the first row to the Nth row. This also applies to subsequent timing charts.

[0094] The vertical drive unit 210 then selects the rows in sequence, switches the conversion gain from low gain to high gain, and outputs the reset level. The thick dotted lines from timing T2 to T3 in the figure indicate the timing for reading out the LG reset data for each row, and the dashed-dotted lines indicate the timing for reading out the HG reset data for each row. The pixel drive method for reading out data in the first modification of the first embodiment is the same as that in the first embodiment, except that the transfer signal TX is controlled to a low level.

[0095] 11 is a timing chart showing an example of a readout operation of the image sensor after exposure in the first modified example of the first embodiment of the present technology. During the period from timing T41 to T42, the vertical drive unit 210 supplies a high-level transfer signal TX to all rows from the first row to the Nth row. This causes signal charges to be transferred in all rows, completing exposure of all rows. The period from timing T1 to T4 corresponds to the accumulation period for all rows.

[0096] The vertical drive unit 210 then selects the rows in sequence, switches the conversion gain from high gain to low gain, and outputs the signal level. The thick diagonal lines from timing T5 to T6 in the figure indicate the timing for reading out the HG signal data for each row, and the thin diagonal lines indicate the timing for reading out the LG signal data for each row. The method for driving pixels during readout in the first modification of the first embodiment is the same as that of the first embodiment, except that the transfer signal TX is controlled to a low level.

[0097] 10 and 11 , the transfer transistors 247 of all pixels simultaneously transfer signal charges from the photoelectric conversion film 243 to the charge accumulation section, allowing the image sensor 200 to perform exposure using a global shutter system. This makes it possible to suppress rolling shutter distortion and improve image quality. Furthermore, as in the first embodiment, the image sensor 200 reads out reset levels and signal levels at high gain and low gain, respectively, thereby achieving a wide dynamic range and high sensitivity.

[0098] Thus, according to the first variant of the first embodiment of the present technology, the transfer transistors 247 of all pixels simultaneously transfer signal charges from the photoelectric conversion film 243 to the charge storage section, thereby realizing exposure using a global shutter method.

[0099] [Second Modification] In the first embodiment described above, the image sensor 200 outputs four frames of data to the DSP circuit 400 for each frame period. However, this configuration increases the number of terminals and power consumption of the data output unit 340 compared to when one frame of data is output. The image sensor 200 in this second modification of the first embodiment differs from the first embodiment in that the amount of output data is reduced by calculating the difference between the reset data and the signal data.

[0100] 12 is a block diagram showing a configuration example of the column processing unit 300 in the second modified example of the first embodiment of the present technology. The column processing unit 300 in the second modified example of the first embodiment differs from the first embodiment in that it further includes a retention memory 320 and a data calculation unit 330.

[0101] The holding memory 320 includes data buffers 321 to 324, and holds LG reset data, HG reset data, HG signal data, and LG signal data for each pixel.

[0102] The data calculation unit 330 includes a difference calculation unit 331. The difference calculation unit 331 calculates the difference between the HG reset data and the HG signal data for each pixel, and supplies the difference to the data output unit 340 as HG·CDS data. The difference calculation unit 331 also calculates the difference between the LG reset data and the LG signal data for each pixel, and supplies the difference to the data output unit 340 as LG·CDS data. The data output unit 340 supplies these data to the DSP circuit 400. The DSP circuit 400 executes synthesis processing, but does not need to perform difference calculation.

[0103] As illustrated in the figure, the difference calculation unit 331 calculates the difference between the HG reset data and the HG signal data, and the difference between the LG reset data and the LG signal data, so the data output unit 340 only needs to output two frames' worth of data per frame period. This reduces the amount of output data. Reducing the amount of output data also reduces the output data rate of the image sensor 200. Furthermore, this reduces the processing load on the DSP circuit 400, which is advantageous for reducing power consumption and increasing speed (such as improving the frame rate).

[0104] 13 is a timing chart showing an example of a readout operation of the image sensor 200 according to the second modified example of the first embodiment of the present technology. In the drawing, "a" shows an example of a readout operation of the readout circuit 310, and "b" shows an example of an output operation of the data output unit 340.

[0105] As shown in the diagram, the readout circuit 310 reads out the LG reset data and the HG reset data for each row during the period from timing T1 to T3, and then reads out the HG signal data and the LG signal data for each row during the period from timing T2 to T5.

[0106] As shown in Fig. 1B, the data output unit 340 outputs the HG CDS data and LG CDS data for each row obtained by the difference calculation during the period from timing T2 to T5. The fine dotted diagonal lines in Fig. 1B indicate the output timing of the HG CDS data for each row, and the coarse dotted diagonal lines indicate the output timing of the LG CDS data for each row.

[0107] The first modification can be applied to the second modification of the first embodiment.

[0108] Thus, according to the second modification of the first embodiment of the present technology, the image sensor 200 calculates the difference between the HG reset data and the HG signal data, and the difference between the LG reset data and the LG signal data, thereby reducing the amount of output data.

[0109] [Third Modification] In the second modification of the first embodiment described above, the image sensor 200 outputs two frames of data per frame period to the DSP circuit 400, but it is preferable to further reduce the amount of output data. The image sensor 200 in this third modification of the first embodiment differs from the second modification of the first embodiment in that the amount of output data is further reduced by combining the HG·CDS data and the LG·CDS data.

[0110] 14 is a block diagram showing a configuration example of the column processing unit 300 in the third modified example of the first embodiment of the present technology. The column processing unit 300 in the third modified example of the first embodiment differs from the first embodiment in that a synthesis processing unit 332 is further provided in the data calculation unit 330.

[0111] The synthesis processing unit 332 synthesizes the HG·CDS data and the LG·CDS data to generate a synthesized frame. The data output unit 340 outputs the synthesized frame to the DSP circuit 400. The DSP circuit 400 does not need to perform difference calculations or synthesis processing, and instead performs various other processes.

[0112] 15 is a timing chart showing an example of a read operation of the image sensor 200 according to the third modified example of the first embodiment of the present technology. In the drawing, "a" shows an example of a read operation of the read circuit 310, and "b" shows an example of an output operation of the data output unit 340.

[0113] As shown in the diagram, the readout circuit 310 reads out the LG reset data and the HG reset data for each row during the period from timing T1 to T3, and then reads out the HG signal data and the LG signal data for each row during the period from timing T2 to T5.

[0114] As shown in FIG. 10B, the data output section 340 outputs the composite frame obtained by the difference calculation and the composition process during the period from timing T2 to T5.

[0115] The first modification can be applied to the third modification of the first embodiment.

[0116] As described above, according to the third modification of the first embodiment of the present technology, the image sensor 200 combines the HG·CDS data and the LG·CDS data, so that the amount of output data can be further reduced.

[0117] [Fourth Modification] In the first embodiment described above, the photodetector 100 captures one frame per frame period, but it can also capture two frames. The photodetector 100 in this fourth modification of the first embodiment differs from the first embodiment in that it captures two frames with different accumulation periods.

[0118] 16 is a timing chart showing an example of a read operation of reset data and signal data according to the fourth modification of the first embodiment of the present technology. After timing T1, the vertical drive unit 210 sequentially selects rows to start exposure, and outputs a reset level while controlling the conversion gain to a low gain.

[0119] During the readout period for n rows from timing T11 to T12, the vertical drive unit 210 supplies a reset signal RST pulse to the n rows and sets the drive signal FX and selection signal SEL to high level. The ADC 311 reads out the LG reset data for the n rows. The thin dotted diagonal lines in the figure indicate the readout timing of the LG reset data for each row.

[0120] After timing T2, the vertical driver 210 sequentially selects rows and outputs a reset level while controlling the conversion gain to a high gain.

[0121] During the readout period for n rows from timing T21 to T22, the vertical drive unit 210 sets the drive signal FX to low level and the selection signal SEL to high level. The ADC 311 reads out the HG reset data for n rows. The thick dotted diagonal lines in the figure indicate the readout timing of the HG reset data for each row.

[0122] After timing T3, the vertical driving section 210 outputs a signal level with the conversion gain remaining high for each row.

[0123] During the readout period for n rows from timing T31 to T32, the vertical drive unit 210 sets the selection signal SEL to high level while keeping the drive signal FX at low level. The ADC 311 reads out the HG signal data for the n rows. This first HG signal data is called "HG Ｓ In the figure, the thick diagonal lines starting from timing T3 indicate the HG of each row. Ｓ The timing for reading signal data is shown.

[0124] In addition, HG Ｓ The signal data is an example of first high-gain signal data as defined in the claims.

[0125] FIG. 17 is a timing chart showing an example of a signal data read operation in the fourth modified example of the first embodiment of the present technology.

[0126] After timing T4, the vertical driver 210 outputs a signal level with the conversion gain remaining high for each row.

[0127] During the readout period for n rows from timing T41 to T42, the vertical drive unit 210 sets the selection signal SEL to high level while keeping the drive signal FX at low level. The ADC 311 reads out the HG signal data for the n rows. This HG signal data has a longer accumulation time than the HG signal data read out initially, and this data is referred to as "HG Ｌ In the figure, the thick diagonal lines starting from timing T4 indicate the HG of each row. Ｌ The timing for reading signal data is shown.

[0128] In addition, HG Ｌ The signal data is an example of second high-gain signal data as defined in the claims.

[0129] After timing T5, the vertical driver 210 sequentially selects rows and outputs a signal level while controlling the conversion gain to a low gain.

[0130] During the readout period for n rows from timing T51 to T52, the vertical drive unit 210 sets the drive signal FX to a high level and sets the selection signal SEL to a high level. The ADC 311 reads out the LG signal data for the n rows. This first LG signal data is referred to as "LG Ｓ In the figure, the thin diagonal lines starting from timing T5 indicate the LG of each row. Ｓ The timing for reading signal data is shown.

[0131] In addition, LG Ｓ The signal data is an example of first low gain signal data as defined in the claims.

[0132] Then, from timing T6 onwards, the vertical driving section 210 outputs a signal level with the conversion gain remaining at low gain for each row.

[0133] During the readout period for n rows from timing T61 to T62, the vertical drive unit 210 sets the selection signal SEL to high level while the drive signal FX remains at high level. The ADC 311 reads out the LG signal data for the n rows. This LG signal data has a longer accumulation time than the LG signal data read out initially, and this data is referred to as "LG Ｌ In the figure, the thick diagonal lines starting from timing T6 indicate the LG Ｌ The timing for reading signal data is shown.

[0134] In addition, LG Ｌ The signal data is an example of second low gain signal data as defined in the claims.

[0135] In addition, the accumulation period EX1 from timing T2 to T3 is Ｓ The accumulation period EX2 from timing T2 to T4 corresponds to the signal data. Ｌ The accumulation period EX1' from timing T1 to T4 corresponds to the signal data. Ｓ The accumulation period EX2' from timing T1 to T6 corresponds to the signal data. Ｌ This is the accumulation period corresponding to the signal data.

[0136] The vertical driving section 210 receives two LG signal data sets with different accumulation periods (i.e., LG Ｓ Signal Data and LG Ｌ However, it is also possible to generate three or more LG signal data with different accumulation periods. The same applies to HG signal data.

[0137] 18 is an example of a potential diagram in a pixel in a fourth modified example of the first embodiment of the present technology. In the figure, a shows a potential diagram when LG reset data is read, and b shows a potential diagram when HG reset data is read. In the figure, c shows a potential diagram when HG Ｓ The potential diagram when reading out signal data is shown. In the figure, d represents the potential of HG. Ｌ The potential diagram when reading signal data is shown. In the figure, e represents LG Ｓ A potential diagram when reading signal data is shown, where f in the figure is LG Ｌ 1 shows a potential diagram for reading signal data, in which the downward direction from a to f indicates a direction in which the potential increases.

[0138] As illustrated in a and b in the figure, the potential diagrams when reading out the LG reset data and the HG reset data in the fourth modified example of the first embodiment are similar to those in the first embodiment.

[0139] As shown in the example of c in the figure, at the end of the accumulation period EX1, signal charges corresponding to the exposure amount are accumulated. At this time, since the drive signal FX remains at a low level, a signal level is generated with a high gain, and HG Ｓ The signal data is read out.

[0140] Then, as shown in d in the figure, at the end of the accumulation period EX2, signal charges corresponding to the amount of exposure are accumulated. At this time, since the drive signal FX remains at a low level, a signal level is generated with a high gain, and HG Ｌ The signal data is read out. The gray area that increases at point d in the figure indicates the amount of signal accumulated during the period from point c to point d in the figure.

[0141] Then, as illustrated in e in the figure, the vertical drive unit 210 sets the drive signal FX to a high level at the end of the accumulation period EX1'. This generates a signal level with a low gain, and LG Ｓ The signal data is read out.

[0142] Then, as shown by f in the figure, at the end of the accumulation period EX2', signal charges corresponding to the amount of exposure are accumulated. At this time, since the drive signal FX remains at a high level, a signal level is generated at a low gain, and LG Ｌ The signal data is read out. The gray area that increases at f in the figure indicates the amount of signal accumulated during the period from e to f in the figure.

[0143] 19 is a block diagram showing an example configuration of the data calculation unit 420 in the DSP circuit 400 according to the fourth modified example of the first embodiment of the present technology. The data calculation unit 420 according to the fourth modified example of the first embodiment further includes a moving object determination unit 423 in addition to a difference calculation unit 421 and a synthesis processing unit 422.

[0144] In addition, the holding memory 410 (not shown) in the front stage of the data calculation unit 420 stores LG reset data, HG reset data, and HG reset data for each pixel. Ｓ Signal data, HG Ｌ Signal data, LG Ｓ Signal Data and LG Ｌ The signal data is retained.

[0145] The difference calculation unit 421 calculates HG reset data and HG Ｌ The difference calculation unit 421 calculates the difference between the signal data and supplies it as HG long accumulation data to the synthesis processing unit 422. Ｓ The difference calculation unit 421 calculates the difference between the signal data and supplies it as HG short-term accumulated data to the synthesis processing unit 422 and the moving object determination unit 423. Ｓ Signal data and HG Ｌ The difference between the signal data is calculated and supplied to the moving object determination unit 423 as HG short-term accumulated data.

[0146] The difference calculation unit 421 calculates the LG reset data and the LG Ｌ The difference calculation unit 421 calculates the difference between the signal data and supplies it as LG long accumulated data to the synthesis processing unit 422. Ｓ The difference calculation unit 421 calculates the difference between the signal data and supplies it as LG short-term accumulated data to the synthesis processing unit 422 and the moving object determination unit 423. Ｓ Signal Data and LG Ｌ The difference between the signal data is calculated and supplied to the moving object determining unit 423 as LG short-term accumulated data.

[0147] The synthesis processing unit 422 synthesizes the HG long accumulation data and the LG long accumulation data, and outputs the data as a long accumulation frame. A low illuminance signal can be obtained with high precision using this long accumulation frame. Furthermore, the synthesis processing unit 422 synthesizes the HG short accumulation data and the LG short accumulation data, and outputs the data as a short accumulation frame. Using this short accumulation frame, a signal at high illuminance can be obtained without saturating. By synthesizing these frames, the dynamic range can be expanded.

[0148] The moving object determination unit 423 determines the presence or absence of a moving object by using a pair of HG short-term accumulation data and a pair of LG short-term accumulation data. This moving object determination unit 423 outputs determination data indicating the determination result to the outside.

[0149] It should be noted that the first, second, and third modified examples can each be applied to the fourth modified example of the first embodiment. When the second modified example is applied, a difference calculation unit is provided on the image sensor 200 side. When the third modified example is applied, a difference calculation unit and a synthesis processing unit are provided on the image sensor 200 side. When the second or third modified example is applied, a moving object determination unit can also be provided on the image sensor 200 side.

[0150] As described above, according to the fourth modified example of the first embodiment of the present technology, the vertical drive unit 210 generates LG reset data and HG reset data, two pieces of HG signal data with different accumulation periods, and two pieces of LG signal data with different accumulation periods. This enables the subsequent DSP circuit 400 to generate long accumulation frames and short accumulation frames and determine the presence or absence of a moving object.

[0151] 2. Second Embodiment In the first embodiment described above, the vertical drive unit 210 controls the conversion gain in two stages, high gain and low gain, but it can also control it in three or more stages. The image sensor 200 in this second embodiment differs from the first embodiment in that it controls the conversion gain in three stages.

[0152] 20 is a circuit diagram showing a configuration example of a pixel 240 according to a second embodiment of the present technology. The pixel 240 according to the second embodiment differs from the pixel 240 according to the first embodiment in that it further includes a connection transistor 242 and a charge storage region 253. As the connection transistor 242, for example, an nMOS transistor is used.

[0153] The connection transistor 241 opens and closes the path between the charge accumulation regions 252 and 253 in accordance with a drive signal FX1 from the vertical drive unit 210. The connection transistor 242 opens and closes the path between the charge accumulation regions 251 and 253 in accordance with a drive signal FX2 from the vertical drive unit 210.

[0154] The charge storage region 253 is an example of a third charge storage region as defined in the claims, and the connection transistors 241 and 242 are an example of first and second connection transistors as defined in the claims.

[0155] The threshold value of the connection transistor 242 is lower than that of the reset transistor 244 and higher than that of the connection transistor 241. Alternatively, the off-voltage of the connection transistor 242 is lower than that of the reset transistor 244 and higher than that of the connection transistor 241. As a result, when the charge accumulation region 251 is saturated within the accumulation period, the overflowing charge is accumulated in the charge accumulation region 253 via the off-state connection transistor 242. Furthermore, when the charge accumulation region 253 is saturated, the overflowing charge is accumulated in the charge accumulation region 252 via the off-state connection transistor 241.

[0156] The conversion gain can be controlled in three stages by turning on and off the connection transistors 241 and 242. The highest conversion gain is called high gain, the lowest conversion gain is called low gain, and the intermediate conversion gain is called "middle gain." The digital signals obtained by AD converting the reset level and signal level at the middle gain are called "MG reset data" and "MG signal data."

[0157] When the connection transistors 241 and 242 are both on, the conversion gain is controlled to a low gain. When the connection transistor 241 is off and the connection transistor 242 is on, the conversion gain is controlled to a medium gain. When the connection transistors 241 and 242 are both on, the conversion gain is controlled to a low gain.

[0158] If the capacitance value of the charge storage region 251 is C_FD1, the capacitance value of the charge storage region 253 is C_FD2, and the capacitance value of the charge storage region 252 is C_FC, the high gain HG, the middle gain MG, and the low gain LG are respectively expressed by the following equations: HG=q / C_FD1 (Equation 3), MG=q / (C_FD1+C_FD2) (Equation 4), and LG=q / (C_FD1+C_FD2+C_FC) (Equation 5).

[0159] 21 is a timing chart showing an example of a readout operation of an image sensor at the start of exposure according to the second embodiment of the present technology. FX1_[n] and FX2_[n] in the figure represent signals to row n. The same applies to the subsequent timing charts.

[0160] The vertical drive unit 210 sequentially selects rows using a rolling shutter system to start exposure, and outputs a reset level while switching the conversion gain for each row in the order of low gain, middle gain, and high gain. The thick dotted lines from timing T1 to T3 in the figure indicate the timing for reading out the LG reset data for each row, and the thin dotted lines indicate the timing for reading out the MG reset data. The dashed-dotted lines indicate the timing for reading out the HG reset data for each row.

[0161] The period from timing T11 to T15 is defined as a readout period for the reset level of row n. During this readout period, the vertical drive unit 210 sets the drive signals FX1 and FX2 for row n to high level at timing T11, and supplies a high-level reset signal RST to row n during the period from timing T11 to timing T12. This initializes the charge storage unit, and exposure of row n begins.

[0162] Then, the vertical drive unit 210 sets the drive signal FX1 to low level at timing T13. This switches the conversion gain from low gain to middle gain. Then, the vertical drive unit 210 sets the drive signal FX2 to low level at timing T14. This switches the conversion gain from middle gain to low gain. The vertical drive unit 210 also supplies a high-level selection signal SEL to row n during the period from timing T11 to T15.

[0163] The ADC 311 for each column reads out the LG reset data in the period from timing T12 to T13, and reads out the MG reset data in the period from timing T13 to T14. Then, each ADC 311 reads out the HG reset data in the period from timing T14 to T15.

[0164] It is also possible to add a connecting transistor and a charge storage region to control the conversion gain in four or more stages.

[0165] FIG. 22 is a timing chart showing an example of a readout operation of the image sensor at the end of exposure according to the second embodiment of the present technology.

[0166] At the end of exposure for each row, the vertical drive unit 210 outputs a signal level while switching the conversion gain in the order of high gain, middle gain, and low gain. In the figure, the thick diagonal lines from timing T2 to T5 indicate the timing of reading out the HG signal data for each row, the two-dot chain lines indicate the timing of reading out the MG signal data for each row, and the thin diagonal lines indicate the timing of reading out the LG signal data for each row.

[0167] The period from timing T21 to T25 is the readout period for the signal level of row n. During this readout period, the vertical drive unit 210 sets the drive signal FX2 to high level at timing T22. This switches the conversion gain from high gain to middle gain. Then, the vertical drive unit 210 sets the drive signal FX1 to high level at timing T23. This switches the conversion gain from middle gain to low gain.

[0168] Then, the vertical drive section 210 supplies a high-level reset signal RST to the nth row during the period from timing T24 to timing T25.

[0169] The ADC 311 for each column reads out the HG signal data in the period from timing T21 to T22, and reads out the MG signal data in the period from timing T22 to T23. Each ADC 311 reads out the LG signal data in the period from timing T23 to T24.

[0170] It should be noted that the second, third, and fourth modifications of the first embodiment can be applied to the second embodiment. In the second embodiment, the image sensor 200 needs to output six frames of data per frame period, but by applying the second or third modification, the amount of output data can be reduced.

[0171] As described above, according to the second embodiment of the present technology, the connection transistor 242 and the charge storage region 253 are added, and therefore the conversion gain can be switched between three stages by turning on and off the connection transistors 241 and 242 .

[0172] In the second embodiment described above, the vertical drive unit 210 controls the conversion gain in three stages, but the value of the middle gain can also be made variable. The image sensor 200 in this modification of the second embodiment differs from the second embodiment in that the value of the middle gain can be changed by driving.

[0173] 23 is a circuit diagram showing a configuration example of a pixel 240 in a modified example of the second embodiment of the present technology. In the modified example of the second embodiment, a connection transistor 241 opens and closes a path between charge storage regions 251 and 252. A connection transistor 242 opens and closes a path between charge storage regions 251 and 253. A reset transistor 244 is connected to the charge storage region 253.

[0174] The vertical drive section 210 can switch between the drive of FIGS. 21 and 22 and the drive of FIGS. 24 and 25 in which the drive signals FX1 and FX2 are interchanged.

[0175] 24 is a timing chart showing an example of a read operation of the image sensor at the start of exposure in a modified example of the second embodiment of the present technology. Differences from the second embodiment will be described. The vertical drive unit 210 sets the drive signal FX2 to a low level at timing T13, and sets the drive signal FX1 to a low level at timing T14.

[0176] 25 is a timing chart showing an example of a readout operation of the image sensor at the end of exposure in a modified example of the second embodiment of the present technology. Differences from the second embodiment will be described. The vertical drive unit 210 sets the drive signal FX1 to a high level at timing T22, and sets the drive signal FX2 to a high level at timing T23.

[0177] In the driving illustrated in FIGS. 24 and 25, the middle gain MG is changed to a value expressed by the following formula: MG=q / (C_FD1+C_FC) (Formula 6)

[0178] As described above, the vertical drive section 210 can change the value of the middle gain by switching the drive.

[0179] It should be noted that the second, third, and fourth modifications of the first embodiment can be applied to the modification of the second embodiment.

[0180] As described above, according to the modification of the second embodiment of the present technology, the circuit configuration of the pixel 240 is changed, and therefore the value of the middle gain can be changed by switching the drive.

[0181] 3. Third Embodiment In the first embodiment described above, the vertical drive unit 210 outputs a reset level and a signal level while controlling the conversion gain between a low gain and a high gain. However, when pixels are miniaturized, the size of the charge storage unit becomes smaller, which may narrow the dynamic range. The image sensor 200 in this third embodiment differs from the first embodiment in that it suppresses the reduction in dynamic range when pixels are miniaturized by periodically discharging charge within the storage period.

[0182] 26 is a circuit diagram showing a configuration example of a pixel 240 according to a third embodiment of the present technology. The pixel 240 according to the third embodiment differs from the pixel 240 according to the first embodiment in that it further includes a charge discharging transistor 248. As the charge discharging transistor 248, for example, an nMOS transistor is used.

[0183] The charge drain transistor 248 drains a portion of the charge in the charge storage section every time a predetermined period elapses within the accumulation period in accordance with a drain signal OF from the vertical drive section 210. The charge drain transistor 248 opens and closes a path between the charge storage region 252 and the power supply voltage VDD in accordance with the drain signal OF.

[0184] There is no particular limitation on the difference in threshold voltage between the charge discharging transistor 248 and the connection transistor 241. In the third embodiment, a transfer transistor 247 can be inserted between the photoelectric conversion film 243 and the charge accumulation region 251, as illustrated in FIG.

[0185] In the third embodiment, a silicon photodiode may be used instead of the photoelectric conversion film 243. The photoelectric conversion film 243 is an example of a photoelectric conversion section described in the claims.

[0186] 27 is a timing chart showing an example of the operation of the image sensor 200 during the accumulation period according to the third embodiment of the present technology. OF_[n] in the figure indicates a signal to the nth row. The same applies to the subsequent timing charts.

[0187] During the period from timing T1 to T3, the vertical driver 210 sequentially selects rows using a rolling shutter method to start exposure. Then, during the period from timing T2 to T5, the vertical driver 210 sequentially selects rows to finish exposure. During the accumulation period from the start to the end of exposure, the vertical driver 210 periodically discharges a portion of the charge. In the figure, the gray areas indicate the accumulation periods for each row.

[0188] During the accumulation period for n rows, the vertical drive unit 210 supplies a pulse of the drive signal FX and a pulse of the discharge signal OF to the n rows every time a certain period elapses. For example, the vertical drive unit 210 supplies a high-level drive signal FX for a pulse period starting from timing T11 when the horizontal synchronization signal HS falls, and then supplies a high-level discharge signal OF for a pulse period starting from timing T12 immediately thereafter.

[0189] The timing T13 is the timing when a period Δt1 has elapsed since timing T11. The vertical drive unit 210 supplies a high-level drive signal FX for a pulse period from timing T13, and then supplies a high-level discharge signal OF for a pulse period from timing T14 immediately thereafter. Δt1 is set to, for example, twice the period of the horizontal synchronization signal HS. Similar control is repeated thereafter. By the control illustrated in the figure, a portion of the signal charge is periodically discharged during the accumulation period.

[0190] FIG. 28 is a timing chart showing an example of a readout operation of the image sensor 200 at the end of exposure according to the third embodiment of the present technology.

[0191] The vertical drive unit 210 sequentially outputs a reset level and a signal level at the end of exposure for each row. In the figure, thick diagonal lines indicate the timing for reading out the signal data for each row, and thin diagonal lines indicate the timing for reading out the reset data for each row.

[0192] The period from timing T21 to T24 is defined as the readout period for row n. During this readout period, the vertical drive unit 210 supplies a high-level drive signal FX for a pulse period from timing T21, and then supplies a high-level discharge signal OF for a pulse period from timing T22 immediately thereafter.

[0193] The vertical drive section 210 then supplies a high-level drive signal FX and a high-level discharge signal OF over a pulse period from timing T23, and also sets the selection signal SEL to a high level during the period from timing T21 to T24.

[0194] The FD potential, which is the potential of the charge storage portion, changes from the signal level to the reset level at timing T23. The ADC 311 of each column reads out signal data during the period from timing T22 to T23, and reads out reset data during the period from timing T23 to T24.

[0195] When there is a sufficient amount of photocurrent, the incident photocharge and the charge discharged through the charge accumulation region 252 are balanced, and the FD potential during the accumulation period is in a balanced state. This potential is determined by the capacitance ratio of C_FD and C_FC and the cycle Δt (for example, Δt1) for discharging the signal charge. If the FD potential immediately before the connection transistor 241 turns on is V1 and the FD potential when the connection transistor 241 is in the on state is V2, the following equation is established: C_FD·(V1-V2)=I ｐｈ ・Δt ...Equation 7 C_FD・V1=(C_FD+C_FC)・V2 ...Equation 8 In the above equation, I ｐｈ denotes the photocurrent flowing within Δt.

[0196] From equations 7 and 8, the following equation is obtained: V2 = I ｐｈ ・Δt / C_FC ... Formula 10

[0197] As shown in Equation 9 and Equation 10, the FD potential is proportional to the amount of photocurrent and also depends on the capacitance ratio and Δt. Therefore, by having the vertical drive unit 210 control the drive timing of the transistors according to the amount of light, the image sensor 200 can measure the amount of photocurrent without saturating the charge storage unit, even under strong light conditions. This indicates that the dynamic range can be expanded even if the size of the charge storage unit is small, and is an advantageous characteristic, particularly as pixels become smaller in the future.

[0198] The third embodiment is also useful when used with a sensor that has a large amount of background signal other than the accumulated signal, such as an infrared image sensor. Furthermore, the vertical drive unit 210 can adjust the effective accumulation capacitance by changing the drive timing of the transistors. For example, the image sensor 200 can optimize the dynamic range by adjusting the drive timing according to the illuminance of the subject and optimizing the accumulation capacitance.

[0199] Furthermore, when photographing a highly luminous subject, the accumulation period is often shortened to avoid signal saturation, resulting in a long dead period during which no image is captured, but in the third embodiment, the charge is periodically discharged, so the accumulation period can be lengthened, thereby eliminating the dead period and enabling the photographing of highly luminous subjects.

[0200] 29 is a block diagram showing an example configuration of a DSP circuit 400 according to the third embodiment of the present technology. The DSP circuit 400 according to the third embodiment differs from the first embodiment in that the data buffers 413 and 414 and the synthesis processing unit 422 are eliminated.

[0201] The data buffers 411 and 412 hold reset data and signal data for each pixel.

[0202] The difference calculation unit 421 calculates the difference between the reset data and the signal data for each pixel, and outputs a frame in which these are arranged.

[0203] It should be noted that the second modified example of the first embodiment, in which the difference calculation is performed on the image sensor 200 side, can be applied to the third embodiment.

[0204] As described above, according to the third embodiment of the present technology, the charge drain transistor 248 periodically drains a portion of the signal charge during the accumulation period, thereby expanding the dynamic range regardless of the size of the charge accumulation section.

[0205] [First Modification] In the third embodiment described above, the cycle for driving the charge discharging transistor 248 and the cycle for driving the connection transistor 241 are the same, but this control is not limited to this. The image sensor in the first modification of the third embodiment differs from the first embodiment in that the method for driving the transistors is changed.

[0206] 30 is a timing chart showing an example of the operation of the image sensor 200 during the accumulation period in the first modified example of the third embodiment of the present technology. During the accumulation period for n rows, from timing T11 to T21, the cycle in which the vertical drive unit 210 drives the charge discharging transistor 248 using the discharge signal OF is Δt1. The cycle in which the vertical drive unit 210 drives the connection transistor 241 using the drive signal FX is also Δt1.

[0207] On the other hand, from timing T21 onwards during the accumulation period for row n, the vertical drive unit 210 drives the charge discharging transistor 248 at a different period from the period in which it drives the connection transistor 241. For example, the period in which it drives the charge discharging transistor 248 with the discharge signal OF is Δt1, and the period in which it drives the connection transistor 241 with the drive signal FX is Δt2. Δt2 is set to the period of the horizontal synchronization signal HS, for example.

[0208] The period of the discharge signal OF after timing T21 can be set to Δt3, which is different from Δt1 and Δt2.

[0209] As shown in the figure, the vertical drive unit 210 changes at least one of the cycles at which the charge discharge transistor 248 is driven and the cycle at which the connection transistor 241 is driven at a predetermined timing within the accumulation period. This control makes it possible to adjust the output of the image sensor 200 to be constant even under a light source whose brightness periodically fluctuates (such as an electric lamp that causes flicker). Because a flicker-free signal can be obtained, this is also useful when capturing images of subjects that flash at high brightness, such as LEDs (Light Emitting Diodes).

[0210] Furthermore, by setting the cycle for driving the charge discharging transistor 248 and the cycle for driving the connection transistor 241 to be different, the amount of charge to be discharged can be adjusted more finely than in the third embodiment.

[0211] The read operation in the first modification of the third embodiment is similar to that in the third embodiment.

[0212] As described above, according to the first modified example of the third embodiment of the present technology, the vertical drive unit 210 changes the cycle midway through the accumulation period, so that the output can be kept constant even under a light source whose brightness periodically fluctuates (such as an electric lamp that causes a flicker phenomenon). Furthermore, because the cycle for driving the charge discharging transistor 248 differs from the cycle for driving the connection transistor 241, the amount of charge to be discharged can be adjusted more finely.

[0213] In the third embodiment described above, the vertical drive unit 210 drives the transistors of all pixels at the same cycle, but when a plurality of pixels with different sensitivities are arranged, it is preferable to change the cycle according to the sensitivity. The image sensor 200 in this second variation of the third embodiment differs from the third embodiment in that the cycle is changed according to the sensitivity.

[0214] 31 is a block diagram showing a configuration example of a photodetector 100 according to a second modified example of the third embodiment of the present technology. In the second modified example of the third embodiment, in the pixel array unit 230, R pixels that are pixels 240 that receive red light, G pixels that are pixels 240 that receive green light, and B pixels that are pixels 240 that receive blue light are arranged in, for example, a Bayer array.

[0215] 32 is a timing chart showing an example of operation of the image sensor 200 during an accumulation period in a second modified example of the third embodiment of the present technology. In the figure, "a" shows operation during an accumulation period for n rows in which G pixels and B pixels are arranged, and "b" shows operation during an accumulation period for n+1 rows in which R pixels and B pixels are arranged.

[0216] Because the nth row and the n+1th row have different sensitivities, the cycle for driving the transistors is changed depending on the sensitivity. The higher the sensitivity, the shorter the cycle is set. For example, the vertical drive unit 210 drives the charge discharging transistors 248 and connection transistors 241 in the nth row with a cycle Δt1, and drives the charge discharging transistors 248 and connection transistors 241 in the n+1th row with a cycle Δt2.

[0217] As described above, according to the second modified example of the third embodiment of the present technology, the period at which the vertical drive unit 210 drives the transistors is changed depending on the color of the pixel (in other words, the sensitivity), so that the dynamic range can be expanded even in a Bayer array or the like.

[0218] 4. Fourth Embodiment In the third embodiment described above, the image sensor 200 reads out the signal level at a constant conversion gain, but it is also possible to read out the signal level by switching the conversion gain. The image sensor 200 in this fourth embodiment differs from the third embodiment in that it reads out the signal level by switching the conversion gain.

[0219] 33 is a circuit diagram showing a configuration example of a pixel 240 according to a fourth embodiment of the present technology. The pixel 240 according to the fourth embodiment differs from the pixel 240 according to the first embodiment in that it further includes a connection transistor 242 and a charge storage region 253.

[0220] The connection transistor 241 opens and closes the path between the charge accumulation regions 252 and 253 in accordance with a drive signal FX1 from the vertical drive unit 210. The connection transistor 242 opens and closes the path between the charge accumulation regions 251 and 253 in accordance with a drive signal FX2 from the vertical drive unit 210.

[0221] 34 is a timing chart showing an example of the operation of the image sensor 200 during the accumulation period according to the fourth embodiment of the present technology. The vertical drive unit 210 sets a cycle for driving the connection transistor 241 with the drive signal FX1 to a different value from a cycle for driving the connection transistor 242 with the drive signal FX2.

[0222] For example, during the accumulation period for row n, the vertical drive section 210 supplies a high-level drive signal FX1 for a pulse period from timing T11, and then supplies a high-level discharge signal OF and drive signal FX2 for a pulse period from timing T12 immediately thereafter.

[0223] The timing Δt1 after timing T11 is defined as T13. The vertical drive unit 210 supplies a high-level drive signal FX1 for a pulse period from timing T13, and then supplies a high-level discharge signal OF for a pulse period from timing T14 immediately thereafter.

[0224] The timing T15 is the time when Δt2 has elapsed since timing T11. The vertical drive unit 210 supplies a high-level drive signal FX1 for a pulse period from timing T15, and then supplies a high-level discharge signal OF and drive signal FX2 for a pulse period from timing T16 immediately thereafter. Similar control is then repeatedly executed.

[0225] By the control shown in the figure, the cycle Δt2 for driving the connection transistor 242 is twice the cycle Δt1 for driving the connection transistor 241 and the charge discharging transistor 248 .

[0226] FIG. 35 is a timing chart showing an example of a readout operation of the image sensor at the end of exposure according to the fourth embodiment of the present technology.

[0227] At the end of exposure for each row, the vertical drive unit 210 switches the conversion gain from high gain to low gain to output a signal level, and then outputs a reset level while maintaining the low gain. In the figure, the thick diagonal lines indicate the timing for reading out the HG signal data for each row, the two-dot chain lines indicate the timing for reading out the LG signal data for each row, and the thin diagonal lines indicate the timing for reading out the LG reset data for each row.

[0228] The period from timing T21 to T24 is defined as the readout period for row n. During this readout period, the vertical drive unit 210 supplies a high-level drive signal FX2 over a pulse period from timing T21, and supplies high-level drive signals FX1 and FX2 over a pulse period from timing T22.

[0229] The vertical drive unit 210 then supplies a high-level discharge signal OF and drive signals FX1 and FX2 over a pulse period from timing T23. The vertical drive unit 210 also sets the selection signal SEL to a high level during the period from timing T21 to T24.

[0230] As described above, the cycles of the drive signals FX1 and FX2 are different, and therefore the potential of the charge accumulation region 251 and the potential of the charge accumulation region 252 are different values. In the above control, the potential of the charge accumulation region 251 becomes the signal level for low gain, and the potential of the charge accumulation region 252 becomes the signal level for high gain.

[0231] The ADC 311 of each column reads out HG signal data in the period from timing T21 to T22, reads out LG signal data in the period from timing T22 to T23, and reads out LG reset data in the period from timing T23 to T24.

[0232] 36 is a block diagram showing an example configuration of a DSP circuit 400 according to the fourth embodiment of the present technology. The DSP circuit 400 according to the fourth embodiment differs from the third embodiment in that it further includes a data buffer 413 and a synthesis processing unit 422.

[0233] The data buffers 411, 412, and 413 hold LG reset data, HG signal data, and LG signal data for each pixel.

[0234] The difference calculation unit 421 calculates the difference between the LG reset data and the HG signal data for each pixel, and outputs the result as HG·CDS data to the synthesis processing unit 422. The difference calculation unit 421 also calculates the difference between the LG reset data and the LG signal data for each pixel, and outputs the result as LG·CDS data to the synthesis processing unit 422.

[0235] The synthesis processing unit 422 synthesizes the HG·CDS data and the LG·CDS data to generate a frame, thereby achieving a wide dynamic range and high sensitivity.

[0236] The fourth embodiment can be applied to the second modified example of the first embodiment, in which the difference calculation is performed on the image sensor 200 side. Also, the fourth embodiment can be applied to the third modified example of the first embodiment, in which the difference calculation and the combination process are performed on the image sensor 200 side.

[0237] As described above, according to the fourth embodiment of the present technology, the connection transistor 242 and the charge accumulation region 253 are added, and therefore the vertical drive section 210 can switch the conversion gain.

[0238] In the fourth embodiment described above, the connection transistors 241 and 242 are driven at different cycles during the accumulation period, but this driving method is not limiting. The image sensor 200 in this modification of the fourth embodiment differs from the fourth embodiment in that the connection transistor 241 is controlled to be always on during the accumulation period.

[0239] 37 is a timing chart showing an example of the operation of the image sensor during the accumulation period in a modification of the fourth embodiment of the present technology. In this modification of the fourth embodiment, the vertical drive unit 210 drives the charge discharging transistor 248 and the connection transistor 242 in the same manner as in the fourth embodiment. That is, the vertical drive unit 210 drives the charge discharging transistor 248 with a cycle Δt1 using a discharge signal OF over the accumulation period, and drives the connection transistor 242 with a cycle Δt2 using a drive signal FX2.

[0240] On the other hand, the vertical drive section 210 controls the connection transistor 241 to be always in an on state by the drive signal FX1 at a high level throughout the accumulation period.

[0241] FIG. 38 is a timing chart showing an example of a readout operation of the image sensor 200 at the end of exposure in the modified example of the fourth embodiment of the present technology.

[0242] The vertical drive unit 210 sequentially outputs a signal level and a reset level at the end of exposure for each row. In the figure, thick diagonal lines indicate the timing for reading out the signal data for each row, and thin diagonal lines indicate the timing for reading out the reset data for each row.

[0243] The period from timing T21 to T23 is the readout period for row n. During this readout period, the vertical drive unit 210 supplies a high-level drive signal FX2 from timing T21 throughout the pulse period while keeping the drive signal FX1 at a high level. Then, the vertical drive unit 210 supplies a high-level discharge signal OF and drive signal FX2 from timing T22 throughout the pulse period.

[0244] Furthermore, the vertical drive unit 210 sets the selection signal SEL to high level during the period from timing T21 to T23.

[0245] The ADC 311 of each column reads out signal data during the period from timing T21 to T22, and reads out reset data during the period from timing T22 to T23.

[0246] It should be noted that the DSP circuit 400 in the modification of the fourth embodiment does not include the synthesis processing unit 422, as in the third embodiment.

[0247] 37 and 38 , the vertical drive unit 210 keeps the connection transistor 241 always on throughout the accumulation period, thereby changing the ratio of the accumulation capacitance to the discharge capacitance to a value different from that of the fourth embodiment. For example, the value of (accumulation capacitance) / (discharge capacitance) in the modification of the fourth embodiment is smaller than that in the fourth embodiment. The driving of the modification of the fourth embodiment is used when it is better to reduce the (accumulation capacitance) / (discharge capacitance), such as when the amount of light is very large.

[0248] It should be noted that the second modification of the first embodiment, in which the difference calculation is performed on the image sensor 200 side, can be applied to the modification of the fourth embodiment.

[0249] In this way, according to the modified example of the fourth embodiment of the present technology, the connection transistor 241 is controlled to be always on by the high-level drive signal FX1 throughout the accumulation period, so that the ratio between the storage capacitance and the discharge capacitance can be changed to a value different from that of the fourth embodiment.

[0250] 5. Fifth Embodiment In the above-described fourth embodiment, the vertical drive unit 210 outputs a signal level while controlling the conversion gain to a high gain or a low gain, and outputs a reset level while maintaining the low gain. However, as in the first embodiment, it is preferable that the vertical drive unit 210 outputs a signal level and a reset level while controlling the conversion gain to a high gain or a low gain. The image sensor 200 in this fifth embodiment differs from the fourth embodiment in that it outputs a signal level and a reset level while controlling the conversion gain to a high gain or a low gain.

[0251] 39 is a circuit diagram showing a configuration example of a pixel 240 according to a fifth embodiment of the present technology. The pixel 240 according to the fifth embodiment differs from the pixel 240 according to the fourth embodiment in that a reset transistor 244 is further included.

[0252] 40 is a timing chart showing an example of the operation of the image sensor at the start of exposure and during the accumulation period in a modified example of the fourth embodiment of the present technology. In the fifth embodiment, the vertical drive unit 210 outputs a reset level while switching the conversion gain from low gain to high gain for each row. Furthermore, during the accumulation period, the vertical drive unit 210 periodically drives the charge discharging transistor 248 and the connection transistor 241. In the figure, the thick dotted lines from timing T1 to T3 indicate the timing of reading out the LG reset data for each row, and the dashed dotted lines indicate the timing of reading out the HG reset data for each row.

[0253] The period from timing T11 to T14 is set as a readout period for the reset level of row n. During this readout period, the vertical drive unit 210 sets the drive signal FX2 for row n to high level at timing T11, and supplies high-level reset signal RST, discharge signal OF, and drive signal FX1 to row n during the period from timing T11 to timing T12.

[0254] Then, the vertical drive unit 210 sets the drive signal FX2 to low level at timing T13, thereby switching the conversion gain from low gain to high gain. The vertical drive unit 210 also supplies a high-level selection signal SEL to row n during the period from timing T11 to T14.

[0255] The ADC 311 for each column reads out the LG reset data in the period from timing T12 to T13, and reads out the HG reset data in the period from timing T13 to T14.

[0256] The driving method during the accumulation period after timing T15 is the same as in Embodiment 3. That is, the vertical driving section 210 periodically drives the charge discharging transistor 248 and the connection transistor 241 with the discharge signal OF and the drive signal FX1.

[0257] FIG. 41 is a timing chart showing an example of a readout operation of the image sensor at the end of exposure in the modified example of the fifth embodiment of the present technology.

[0258] At the end of exposure for each row, the vertical drive unit 210 outputs a signal level while switching the conversion gain from high gain to low gain.

[0259] The period from timing T21 to T25 is the readout period for the signal level of row n. During this readout period, the vertical drive unit 210 supplies a high-level reset signal RST to row n over the pulse period from timing T22 to T23, and sets the drive signal FX2 to high level at timing T23. This switches the conversion gain from high to low.

[0260] The vertical drive unit 210 then supplies a high-level reset signal RST, a high-level discharge signal OF, and a high-level drive signal FX1 to the nth row during the period from timing T24 to timing T25, and sets the drive signal FX2 to a low level at timing T25. The vertical drive unit 210 also supplies a high-level selection signal SEL to the nth row during the period from timing T21 to timing T25.

[0261] The ADC 311 for each column reads out the HG signal data in the period from timing T21 to T22, and reads out the LG signal data in the period from timing T23 to T24.

[0262] The DSP circuit 400 in the fifth embodiment is the same as that in the first embodiment. The DSP circuit 400 can calculate the difference between the HG reset data and the HG signal data, and therefore can reduce noise and improve image quality compared to the fourth embodiment in which the difference between the LG reset data and the HG signal data is calculated.

[0263] Furthermore, by applying the driving method of the first embodiment as described above, it is possible to achieve high sensitivity while widening the dynamic range regardless of the size of the charge storage section.

[0264] The fifth embodiment can be applied to the second modified example of the first embodiment, in which the difference calculation is performed on the image sensor 200 side. Also, the fifth embodiment can be applied to the third modified example of the first embodiment, in which the difference calculation and the combining process are performed on the image sensor 200 side.

[0265] As described above, according to the fifth embodiment of the present technology, the vertical drive unit 210 outputs the reset level while switching the conversion gain from high level to low level, and therefore the DSP circuit 400 can calculate the difference between the HG reset data and the HG signal data, thereby improving the image quality compared to the fourth embodiment.

[0266] 6. Sixth Embodiment In the fifth embodiment described above, the reset transistor 244 is disposed for each pixel, but it is possible to eliminate this reset transistor 244. The image sensor 200 in this sixth embodiment differs from the fourth embodiment in that the circuit configuration is changed to eliminate the reset transistor 244 while achieving driving similar to that of the fifth embodiment.

[0267] 42 is a circuit diagram showing a configuration example of a pixel 240 according to a sixth embodiment of the present technology. The pixel 240 according to the sixth embodiment differs from the fifth embodiment in that the reset transistor 244 is omitted. In addition, in the sixth embodiment, the gate of the amplification transistor 245 is connected to the charge accumulation region 253.

[0268] 43 is a timing chart showing an example of the operation of the image sensor at the start of exposure and during the accumulation period in a modified example of the sixth embodiment of the present technology. The driving method in the sixth embodiment is the same as that in the fifth embodiment illustrated in FIG. 40, except that the reset signal RST is not supplied.

[0269] In the sixth embodiment, the charge drain transistor 248 periodically drains a portion of the charge from the charge storage unit during the accumulation period and also initializes the charge storage unit at the start of exposure. In other words, the charge drain transistor 248 also plays the role of a reduced version of the reset transistor 244.

[0270] FIG. 44 is a timing chart showing an example of a readout operation of the image sensor at the end of exposure in the modified example of the sixth embodiment of the present technology.

[0271] The period from timing T21 to T24 is defined as a readout period for the signal level of row n. During this readout period, the vertical drive unit 210 supplies a high-level discharge signal OF and drive signal FX1 to row n over the pulse period from timing T22 to T23, and sets drive signal FX2 to high level at timing T23. This switches the conversion gain from high gain to low gain. Then, the vertical drive unit 210 sets drive signal FX2 to low level at timing T24. Furthermore, the vertical drive unit 210 supplies a high-level selection signal SEL to row n during the period from timing T21 to timing T24.

[0272] The ADC 311 for each column reads out the HG signal data in the period from timing T21 to T22, and reads out the LG signal data in the period from timing T23 to T24.

[0273] In the driving method shown in the figure, the image sensor 200 first reads out the potential of the charge accumulation region 252 corresponding to the current that has overflowed the charge accumulation region 251, and then sets the drive signal FX2 to a high level to read out the charge accumulated in the charge accumulation region 251. This driving method is useful when it is desired to measure the amount of overflow current more accurately.

[0274] The DSP circuit 400 in the sixth embodiment is similar to that in the fifth embodiment.

[0275] As described above, the charge drain transistor 248 initializes the charge storage section at the start of exposure and periodically drains part of the charge from the charge storage section during the storage period. This driving allows a pixel without the reset transistor 244 to output a reset level and a signal level by switching the conversion gain in two stages.

[0276] The sixth embodiment can be applied to the second modified example of the first embodiment, in which the difference calculation is performed on the image sensor 200 side. Also, the sixth embodiment can be applied to the third modified example of the first embodiment, in which the difference calculation and the combining process are performed on the image sensor 200 side.

[0277] Thus, according to the sixth embodiment of the present technology, the charge discharge transistor 248 initializes the charge storage unit at the start of exposure and periodically discharges a portion of the charge from the charge storage unit within the accumulation period, thereby making it possible to eliminate the reset transistor 244.

[0278] 7. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0279] FIG. 45 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0280] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 45, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0281] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0282] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0283] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0284] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0285] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0286] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0287] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0288] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0289] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 45, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0290] FIG. 46 is a diagram showing an example of the installation position of the imaging unit 12031.

[0291] In FIG. 46, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0292] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0293] 46 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0294] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0295] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the closest three-dimensional object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0296] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0297] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0298] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the image capturing unit 12031 of the above-described configuration. Specifically, the image sensor 200 in FIG. 1 can be applied to the image capturing unit 12031. By applying the technology according to the present disclosure to the image capturing unit 12031, it is possible to obtain a captured image that is easier to see, thereby reducing driver fatigue.

[0299] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist thereof.

[0300] The effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0301] The present technology may also be configured as follows: (1) An image sensor comprising: a photoelectric conversion film that generates charges by photoelectric conversion; a charge accumulation unit that accumulates the charges; an amplifying transistor that sequentially outputs a reset level corresponding to an initialized voltage of the charge accumulation unit and a signal level corresponding to the voltage of the charge accumulation unit after a predetermined accumulation period has elapsed; a connection transistor that controls a conversion gain when the charges are converted to the voltage to one of a plurality of values; and a vertical drive unit that, when the charge accumulation unit is initialized, outputs the reset level while controlling the conversion gain to each of the plurality of values, and when the accumulation period has elapsed, outputs the signal level while controlling the conversion gain to each of the plurality of values. (2) The image sensor according to (1), further comprising: a reset transistor that initializes the charge accumulation unit, wherein the charge accumulation unit includes first and second charge accumulation regions, the photoelectric conversion film is connected to the first charge accumulation region, and the connection transistor controls the conversion gain by opening and closing a path between the first and second charge accumulation regions. (3) The image sensor according to (1), further comprising: a reset transistor that initializes the charge accumulation unit; and a transfer transistor that transfers the charge from the photoelectric conversion film to the charge accumulation unit. (4) The image sensor according to (1), further comprising: a reset transistor that initializes the charge accumulation unit, wherein the charge accumulation unit includes first, second, and third charge accumulation regions, the photoelectric conversion film is connected to the first charge accumulation region, and the connection transistor includes a first connection transistor that opens and closes one of two paths between the first, second, and third charge accumulation regions and a second connection transistor that opens and closes the other of the two paths. (5) The image sensor according to (4), further comprising: a reset transistor that initializes the charge accumulation unit; and a charge discharge transistor that discharges a portion of the charge from the charge accumulation unit every time a predetermined period has elapsed over the accumulation period.(6) The image sensor according to (4), further comprising a charge draining transistor that initializes the charge storage unit before the accumulation period starts and drains a portion of the charge from the charge storage unit every time a predetermined period has elapsed within the accumulation period. (7) The image sensor according to (1), further comprising an analog-to-digital converter that converts the reset level and the signal level into digital signals in sequence, the digital signals including low-gain reset data corresponding to the reset level when the conversion gain is lower than a predetermined value, high-gain reset data corresponding to the reset level when the conversion gain is higher than the predetermined value, low-gain signal data corresponding to the signal level when the conversion gain is lower than the predetermined value, and high-gain signal data corresponding to the signal level when the conversion gain is higher than the predetermined value. (8) The image sensor according to (7), further comprising: (9) The image sensor according to (7) or (8), further comprising a difference calculation unit that calculates a difference between the low-gain reset data and the low-gain signal data as low-gain CDS (Correlated Double Sampling) data and calculates a difference between the high-gain reset data and the high-gain signal data as high-gain CDS data. (10) The image sensor according to (9), further comprising a synthesis processing unit that synthesizes the low-gain CDS data and the high-gain CDS data. (11) An image sensor comprising: a photoelectric conversion unit that generates charges by photoelectric conversion; a charge accumulation unit including a plurality of charge accumulation regions that accumulate the charges; a connection transistor that opens and closes paths between the plurality of charge accumulation regions; and a charge exhaust transistor that periodically exhausts a portion of the charges from the charge accumulation unit over the accumulation period. (12) The image sensor according to (11), further comprising a vertical drive unit that drives the connection transistor and the charge exhaust transistor over the accumulation period.(13) The image sensor according to (12), wherein the vertical drive unit periodically drives the connection transistor and the charge discharging transistor, and changes at least one of the period for driving the connection transistor and the period for driving the charge discharging transistor at a predetermined timing within the accumulation period. (14) The image sensor according to (12) or (13), wherein the vertical drive unit drives the charge discharging transistor at a predetermined period throughout the accumulation period, and drives the connection transistor at a period different from the predetermined period. (15) The image sensor described in (12), wherein the photoelectric conversion unit, the charge accumulation unit, the connection transistor, and the charge discharge transistor are respectively arranged in first and second pixels having different sensitivities, and the vertical drive unit drives the charge discharge transistor arranged in the first pixel at a predetermined cycle over an accumulation period, and drives the charge discharge transistor arranged in the second pixel at a cycle different from the predetermined cycle. (16) The image sensor described in (12), wherein the charge accumulation unit further includes first, second, and third charge accumulation regions, the photoelectric conversion unit is connected to the first charge accumulation region, and the connection transistor includes a first connection transistor that opens and closes one of two paths between the first, second, and third charge accumulation regions, and a second connection transistor that opens and closes the other of the two paths. (17) The image sensor described in (16), wherein the vertical drive unit drives the first connection transistor at a predetermined cycle over an accumulation period, and drives the second connection transistor at a cycle different from the predetermined cycle. (18) The image sensor according to (16), wherein the vertical drive section drives the first connection transistor at a predetermined cycle while controlling the second connection transistor to be in an on state over an accumulation period.(19) A photodetector comprising: a photoelectric conversion film that generates charges by photoelectric conversion; a charge storage unit that stores the charges; an amplifying transistor that sequentially outputs a reset level corresponding to the initialized voltage of the charge storage unit and a signal level corresponding to the voltage of the charge storage unit after a predetermined storage period has elapsed; a connection transistor that controls a conversion gain when the charges are converted into the voltage to one of a plurality of values; a vertical drive unit that, when the charge storage unit is initialized, outputs the reset level while controlling the conversion gain to each of the plurality of values, and, when the storage period has elapsed, outputs the signal level while controlling the conversion gain to each of the plurality of values; an analog-to-digital conversion unit that sequentially converts the reset level and the signal level into digital signals; and a signal processing circuit that processes frames in which the digital signals are arranged. (20) A control method for an image sensor, comprising: a control procedure for controlling a conversion gain to one of a plurality of values ​​when converting electric charges into the voltage; and a vertical drive procedure for, when a charge accumulation section that accumulates electric charges generated by a photoelectric conversion film is initialized, controlling the conversion gain to each of the plurality of values ​​while outputting a reset level corresponding to the voltage of the charge accumulation section, and, when the accumulation period has elapsed, controlling the conversion gain to each of the plurality of values ​​while outputting a signal level corresponding to the voltage of the charge accumulation section.

[0302] 100 Photodetector 200 Image sensor 210 Vertical drive unit 220 System control unit 230 Pixel array unit 240 Pixel 241, 242 Connection transistor 243 Photoelectric conversion film 244 Reset transistor 245 Amplification transistor 246 Selection transistor 247 Transfer transistor 248 Charge discharge transistor 251, 252, 253 Charge storage region 290 Horizontal drive unit 300 Column processing unit 310 Readout circuit 311 ADC 320, 410 Retention memory 321 to 324, 411 to 414 Data buffer 330, 420 Data calculation unit 331, 421 Difference calculation unit 332, 422 Synthesis processing unit 340 Data output unit 400 DSP circuit 423 Moving object determination unit 12031 Imaging unit

Claims

1. An image sensor comprising: a photoelectric conversion film that generates electric charges by photoelectric conversion; a charge storage section that stores the electric charges; an amplifying transistor that sequentially outputs a reset level corresponding to the initialized voltage of the charge storage section and a signal level corresponding to the voltage of the charge storage section when a predetermined storage period has elapsed; a connection transistor that controls a conversion gain when the electric charges are converted into the voltage to one of a plurality of values; and a vertical drive section that, when the charge storage section is initialized, outputs the reset level while controlling the conversion gain to each of the plurality of values, and, when the storage period has elapsed, outputs the signal level while controlling the conversion gain to each of the plurality of values.

2. The image sensor according to claim 1, further comprising a reset transistor that initializes the charge storage section, wherein the charge storage section includes first and second charge storage regions, the photoelectric conversion film is connected to the first charge storage region, and the connection transistor controls the conversion gain by opening and closing a path between the first and second charge storage regions.

3. The image sensor according to claim 1, further comprising: a reset transistor that initializes the charge storage section; and a transfer transistor that transfers the charges from the photoelectric conversion film to the charge storage section.

4. The image sensor according to claim 1, further comprising a reset transistor that initializes the charge storage section, wherein the charge storage section includes first, second, and third charge storage regions, the photoelectric conversion film is connected to the first charge storage region, and the connection transistor includes a first connection transistor that opens and closes one of two paths between the first, second, and third charge storage regions, and a second connection transistor that opens and closes the other of the two paths.

5. The image sensor according to claim 4, further comprising: a reset transistor that initializes the charge storage section; and a charge discharge transistor that discharges a portion of the charge from the charge storage section every time a predetermined period has elapsed over the accumulation period.

6. The image sensor according to claim 4, further comprising a charge drain transistor that initializes the charge storage section before the start of the accumulation period and drains a portion of the charge from the charge storage section every time a predetermined period has elapsed within the accumulation period.

7. The image sensor according to claim 1, further comprising an analog-to-digital converter that converts the reset level and the signal level into digital signals in order, wherein the digital signals include low-gain reset data corresponding to the reset level when the conversion gain is lower than a predetermined value, high-gain reset data corresponding to the reset level when the conversion gain is higher than the predetermined value, low-gain signal data corresponding to the signal level when the conversion gain is lower than the predetermined value, and high-gain signal data corresponding to the signal level when the conversion gain is higher than the predetermined value.

8. The image sensor according to claim 7, wherein the accumulation period includes a plurality of accumulation periods, the low gain signal data includes first low gain signal data and second low gain signal data having different accumulation periods, and the high gain signal data includes first high gain signal data and second high gain signal data having different accumulation periods.

9. The image sensor according to claim 7, further comprising a difference calculation unit that calculates the difference between the low-gain reset data and the low-gain signal data as low-gain CDS (Correlated Double Sampling) data, and calculates the difference between the high-gain reset data and the high-gain signal data as high-gain CDS data.

10. The image sensor according to claim 9, further comprising a synthesis processing unit for synthesizing the low-gain CDS data and the high-gain CDS data.

11. An image sensor comprising: a photoelectric conversion unit that generates charges by photoelectric conversion; a charge accumulation unit including a plurality of charge accumulation regions that accumulate the charges; a connection transistor that opens and closes paths between the plurality of charge accumulation regions; and a charge discharge transistor that periodically discharges a portion of the charges from the charge accumulation unit over the accumulation period.

12. The image sensor of claim 11, further comprising a vertical drive section that drives the connection transistor and the charge drain transistor during the integration period.

13. The image sensor according to claim 12, wherein the vertical drive section periodically drives the connection transistor and the charge discharging transistor, and changes at least one of the period for driving the connection transistor and the period for driving the charge discharging transistor at a predetermined timing within the accumulation period.

14. The image sensor according to claim 12, wherein the vertical drive section drives the charge discharging transistor at a predetermined cycle throughout the accumulation period, and drives the connection transistor at a cycle different from the predetermined cycle.

15. The image sensor according to claim 12, wherein the photoelectric conversion section, the charge accumulation section, the connection transistor and the charge discharge transistor are arranged in first and second pixels having different sensitivities, respectively, and the vertical drive section drives the charge discharge transistor arranged in the first pixel at a predetermined cycle over an accumulation period, and drives the charge discharge transistor arranged in the second pixel at a cycle different from the predetermined cycle.

16. The image sensor according to claim 12, wherein the charge accumulation section further includes first, second, and third charge accumulation regions, the photoelectric conversion section is connected to the first charge accumulation region, and the connection transistor includes a first connection transistor that opens and closes one of two paths between the first, second, and third charge accumulation regions, and a second connection transistor that opens and closes the other of the two paths.

17. The image sensor according to claim 16, wherein the vertical drive section drives the first connection transistor at a predetermined cycle over an accumulation period, and drives the second connection transistor at a cycle different from the predetermined cycle.

18. The image sensor according to claim 16, wherein the vertical drive section drives the first connection transistor at a predetermined cycle while controlling the second connection transistor to be in an on state throughout an accumulation period.

19. A photodetector comprising: a photoelectric conversion film that generates charges by photoelectric conversion; a charge storage section that stores the charges; an amplifying transistor that sequentially outputs a reset level corresponding to the initialized voltage of the charge storage section and a signal level corresponding to the voltage of the charge storage section after a predetermined storage period has elapsed; a connection transistor that controls a conversion gain when converting the charges to the voltage to one of a plurality of values; a vertical drive section that, when the charge storage section is initialized, outputs the reset level while controlling the conversion gain to each of the plurality of values, and, when the storage period has elapsed, outputs the signal level while controlling the conversion gain to each of the plurality of values; an analog-to-digital conversion section that sequentially converts the reset level and the signal level into digital signals; and a signal processing circuit that processes frames in which the digital signals are arranged.

20. A control method for an image sensor comprising: a control procedure for controlling a conversion gain to one of a plurality of values ​​when converting electric charges into the voltage; and a vertical drive procedure for, when a charge accumulation section that accumulates electric charges generated by a photoelectric conversion film is initialized, controlling the conversion gain to each of the plurality of values ​​while outputting a reset level corresponding to the voltage of the charge accumulation section, and, when the accumulation period has elapsed, controlling the conversion gain to each of the plurality of values ​​while outputting a signal level corresponding to the voltage of the charge accumulation section.

Images