Display device and electronic device comprising same

Abstract

This display device comprises: a plurality of pixel circuit blocks, each pixel circuit block including at least one pixel driving circuit including a plurality of transistors; a light-emitting element electrically connected to the pixel driving circuit and including an anode electrode and a cathode electrode; a first power voltage wiring; a second power voltage wiring; a switching circuit including a first switching element connected to the first power voltage wiring and turned on by a first voltage level and a second switching element connected to the second power voltage wiring and turned on by a second voltage level different from the first voltage level, the switching circuit being electrically connected one-to-one with the pixel circuit blocks; and a data wiring electrically connected to the switching circuit and providing the first voltage level or the second voltage level to the switching circuit.

Description

Display device and electronic device including same

[0001] The present invention relates to a display device. More specifically, the present invention relates to a display device that provides visual information.

[0002] As information technology advances, the importance of display devices, which serve as a link between users and information, is growing. Consequently, the use of display devices such as liquid crystal displays (LCDs), organic light-emitting displays (OLEDs), and plasma displays is increasing.

[0003] A display device includes a light-emitting element and a pixel driving circuit for driving the light-emitting element. The light-emitting element is driven by the pixel driving circuit to emit light.

[0004] One object of the present invention is to provide a display device with reduced power consumption.

[0005] Another object of the present invention is to provide an electronic device including the display device.

[0006] However, the purpose of the present invention is not limited to these purposes, and may be expanded in various ways without departing from the spirit and scope of the present invention.

[0007] A display device according to one embodiment may include a plurality of pixel circuit blocks each including at least one pixel driving circuit including a plurality of transistors, a light-emitting element electrically connected to the pixel driving circuit and including an anode electrode and a cathode electrode, a first power voltage line receiving a high-level power voltage, a second power voltage line receiving a low-level power voltage, a switching circuit including a first switching element electrically connected one-to-one with the plurality of pixel circuit blocks, the first switching element being connected to the first power voltage line and turned on by a data voltage of a first voltage level, and the second switching element being connected to the second power voltage line and turned on by a data voltage of a second voltage level different from the first voltage level, and a data line electrically connected to the switching circuit and providing the data voltage of the first voltage level or the data voltage of the second voltage level to the switching circuit.

[0008] In one embodiment, the switching circuit selectively provides the high level power supply voltage or the low level power supply voltage to any one of the plurality of pixel circuit blocks electrically connected to the switching circuit.

[0009] In one embodiment, the first switching element can be turned off by a data voltage of the second voltage level, and the second switching element can be turned off by a data voltage of the first voltage level.

[0010] In one embodiment, when the first switching element is turned on, the second switching element can be turned off, and when the first switching element is turned off, the second switching element can be turned on.

[0011] In one embodiment, when the first switching element is a PMOS transistor, the second switching element may be an NMOS transistor, and when the first switching element is an NMOS transistor, the second switching element may be a PMOS transistor.

[0012] In one embodiment, a power line to which a common voltage is applied is connected to the cathode electrode, and the power voltage may be a driving voltage having a voltage level higher than the voltage level of the common voltage.

[0013] In one embodiment, the plurality of transistors include a switching transistor including a gate electrode, a source electrode, and a drain electrode controlled by a light emission control signal, and the display device may further include an output power connection wiring that connects the source electrode of the switching transistor and the switching circuit, and selectively receives the high-level power voltage or the low-level power voltage through the switching circuit.

[0014] In one embodiment, the display device may further include an output power connection wiring that connects the anode electrode and the switching circuit and selectively receives the high-level power voltage or the low-level power voltage through the switching circuit.

[0015] In one embodiment, the display device may further include an output power connection wiring that connects the cathode electrode and the switching circuit and selectively receives the high-level power voltage or the low-level power voltage.

[0016] In one embodiment, the display device further includes a separator disposed on the pixel driving circuit portion and surrounding the pixel circuit blocks on a plane, wherein the cathode electrode can be disconnected by the separator.

[0017] In one embodiment, the side surface of the separator may have a reverse tapered slope.

[0018] In one embodiment, the pixel driving circuit unit may further include an inorganic insulating layer disposed on a substrate, a first organic insulating layer disposed on the inorganic insulating layer, a second organic insulating layer disposed on the first organic insulating layer and having a first sub-opening defined therein that exposes at least a portion of the output power connection wiring, and a pixel defining film disposed on the second organic insulating layer and having a second sub-opening defined therein that is spatially connected to the first sub-opening.

[0019] In one embodiment, the display device may further include a connection pattern disposed on the pixel defining film, contacting the cathode electrode in an area overlapping an edge of the separator, and contacting the output power connection wiring through the first and second sub-openings.

[0020] In one embodiment, the light-emitting element further includes a light-emitting layer disposed between the anode electrode and the cathode electrode and overlapping the light-emitting region, and the connection pattern may have a shape surrounding the light-emitting region on a plane.

[0021] In one embodiment, the connection pattern may be spaced apart from the light-emitting region on a plane.

[0022] In one embodiment, the output power connection wiring includes a first conductive layer, a second conductive layer, and a third conductive layer sequentially laminated, and a side surface of each of the first and third conductive layers may protrude outward from a side surface of the second conductive layer.

[0023] In one embodiment, the cathode electrode is disconnected by the output power connection wiring, and the cathode electrode can be in contact with a side surface of the second conductive layer and a side surface of the third conductive layer.

[0024] In one embodiment, the pixel driving circuit unit further includes an inorganic insulating layer disposed on a substrate, a first organic insulating layer disposed on the inorganic insulating layer, a second organic insulating layer disposed on the first organic insulating layer and having a first sub-opening defined therein that exposes at least a portion of the output power connection wiring, and a pixel defining film disposed on the second organic insulating layer and having a second sub-opening defined therein that is spatially connected to the first sub-opening, wherein the pixel defining film may include an engraved pattern that surrounds the pixel circuit blocks on a plane.

[0025] In one embodiment, the cathode electrode may be disconnected by the engraved pattern.

[0026] A display device according to one embodiment comprises a plurality of pixel circuit blocks, each pixel circuit block including at least one pixel driving circuit unit that generates a driving current and includes a driving transistor that is a PMOS transistor, a light-emitting element electrically connected to the pixel driving circuit unit and including an anode electrode and a cathode electrode, a first power voltage line that receives a high-level power voltage, a second power voltage line that receives a low-level power voltage, a switching circuit unit that is electrically connected one-to-one with the pixel circuit blocks, and includes a first switching element that is connected to the first power voltage line and is turned on by a data voltage of a first voltage level and turned off by a second voltage level different from the first voltage level, and a second switching element that is connected to the second power voltage line and is turned off by a data voltage of the first voltage level and turned on by a data voltage of the second voltage level, an output power connection line that connects a node between the cathode electrode and the first and second switching elements and selectively receives the high-level power voltage or the low-level power voltage, and It may include a data wire that is electrically connected to the switching circuit and provides a data voltage of the first voltage level or a data voltage of the second voltage level to the switching circuit.

[0027] In one embodiment, the switching circuitry can selectively provide the high-level power supply voltage or the low-level power supply voltage to any one of the pixel circuit blocks electrically connected to the switching circuitry.

[0028] In one embodiment, when the first switching element is turned on, the second switching element can be turned off, and when the first switching element is turned off, the second switching element can be turned on.

[0029] In one embodiment, the display device further includes a separator disposed on the pixel driving circuit portion and surrounding the pixel circuit blocks on a plane, wherein the cathode electrode can be disconnected by the separator.

[0030] In one embodiment, the pixel driving circuit unit may further include an inorganic insulating layer disposed on a substrate, a first organic insulating layer disposed on the inorganic insulating layer, a second organic insulating layer disposed on the first organic insulating layer and having a first sub-opening defined therein that exposes at least a portion of the output power connection wiring, and a pixel defining film disposed on the second organic insulating layer and having a second sub-opening defined therein that is spatially connected to the first sub-opening.

[0031] In one embodiment, the display device may further include a connection pattern disposed on the pixel defining film, contacting the cathode electrode in an area overlapping an edge of the separator, and contacting the output power connection wiring through the first and second sub-openings.

[0032] In one embodiment, the output power connection wiring includes a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially laminated, and a side surface of each of the first and third conductive layers protrudes outward from a side surface of the second conductive layer, and the cathode electrode is disconnected by the output power connection wiring, and the cathode electrode can be in contact with a side surface of the second conductive layer and a side surface of the third conductive layer.

[0033] In one embodiment, the pixel driving circuit unit further includes an inorganic insulating layer disposed on a substrate, a first organic insulating layer disposed on the inorganic insulating layer, a second organic insulating layer disposed on the first organic insulating layer and having a first sub-opening defined therein that exposes at least a portion of the output power connection wiring, and a pixel defining film disposed on the second organic insulating layer and having a second sub-opening spatially connected to the first sub-opening, wherein the pixel defining film includes an engraved pattern that surrounds the pixel circuit blocks on a plane, and the cathode electrode can be disconnected by the engraved pattern.

[0034] An electronic device according to one embodiment includes a display device and a processor for controlling the display device, wherein the display device may include a plurality of pixel circuit blocks each including at least one pixel driving circuit including a plurality of transistors, a light-emitting element electrically connected to the pixel driving circuit and including an anode electrode and a cathode electrode, a first power voltage line receiving a high-level power voltage, a second power voltage line receiving a low-level power voltage, a switching circuit including a first switching element electrically connected one-to-one with the pixel circuit blocks, the first switching element being connected to the first power voltage line and turned on by a data voltage of a first voltage level, and a second switching element being connected to the second power voltage line and turned on by a data voltage of a second voltage level different from the first voltage level, and a data line electrically connected to the switching circuit and providing the data voltage of the first voltage level or the data voltage of the second voltage level to the switching circuit.

[0035] A display device according to one embodiment may include a plurality of pixel circuit blocks, each including at least one pixel driving circuit unit that generates a driving current and includes a driving transistor that is an NMOS transistor, and a switching circuit unit that is electrically connected one-to-one with the pixel circuit blocks to selectively provide a high-level power supply voltage or a low-level power supply voltage. In this case, a high-level power supply voltage may be applied to pixel circuit blocks arranged in a high-brightness area of ​​a display area, and a low-level power supply voltage may be applied to pixel circuit blocks arranged in a low-brightness area of ​​the display area. Accordingly, power consumption of the display device may be reduced.

[0036] In another embodiment, the display device may include a plurality of pixel circuit blocks, each of which includes at least one pixel driving circuit unit that generates a driving current and includes a driving transistor that is a PMOS transistor, and a switching circuit unit that is electrically connected one-to-one with the pixel circuit blocks to selectively provide a high-level power supply voltage or a low-level power supply voltage. In this case, a low-level power supply voltage may be applied to pixel circuit blocks arranged in a high-brightness area of ​​the display area, and a high-level power supply voltage may be applied to pixel circuit blocks arranged in a low-brightness area of ​​the display area. Accordingly, power consumption of the display device may be reduced.

[0037] However, the effects of the present invention are not limited to the above effects, and may be expanded in various ways without departing from the spirit and scope of the present invention.

[0038] FIG. 1A is a plan view showing a display device according to one embodiment.

[0039] FIG. 1b is a plan view showing a display device according to one embodiment.

[0040] FIG. 2a is a circuit diagram showing an example of a circuit structure of a pixel and switching circuit unit included in the display device of FIG. 1a and FIG. 1b according to one embodiment.

[0041] FIG. 2b is a circuit diagram showing an example of a circuit structure of a pixel and switching circuit unit included in the display device of FIG. 1a and FIG. 1b according to one embodiment.

[0042] FIG. 3 is a plan view schematically illustrating a portion of the display area of ​​FIGS. 1A and 1B according to one embodiment.

[0043] FIG. 4 is a plan view schematically illustrating a portion of the display area of ​​FIGS. 1A and 1B according to one embodiment.

[0044] FIG. 5 is a circuit diagram showing an example of a circuit structure of a pixel and switching circuit unit included in the display device of FIG. 1a and FIG. 1b according to one embodiment.

[0045] FIG. 6 is a circuit diagram showing an example of a circuit structure of a pixel and switching circuit unit included in the display device of FIG. 1a and FIG. 1b according to one embodiment.

[0046] FIG. 7 is a plan view schematically illustrating a portion of the display area of ​​FIGS. 1A and 1B according to one embodiment.

[0047] FIG. 8 is an enlarged plan view of a pixel circuit block, light-emitting elements connected to the pixel circuit block, and a switching circuit unit of FIG. 7 according to one embodiment.

[0048] FIG. 9 is a cross-sectional view showing an example of a cross-section taken along line II' of FIG. 8 according to one embodiment.

[0049] FIG. 10 is a cross-sectional view showing an example of a cross-section taken along line II' of FIG. 8 according to one embodiment.

[0050] FIG. 11 is an enlarged plan view of a pixel circuit block, light-emitting elements connected to the pixel circuit block, and a switching circuit unit of FIG. 7 according to one embodiment.

[0051] FIG. 12 is a cross-sectional view taken along line II-II' of FIG. 11 according to one embodiment.

[0052] FIG. 13 is an enlarged plan view of a pixel circuit block, light-emitting elements connected to the pixel circuit block, and a switching circuit unit of FIG. 7 according to one embodiment.

[0053] FIG. 14 is a cross-sectional view showing an example of a cross-section taken along line III-III' of FIG. 13 according to one embodiment.

[0054] FIG. 15 is a cross-sectional view showing an example of a cross-section taken along line III-III' of FIG. 13 according to one embodiment.

[0055] FIG. 16 is a plan view schematically illustrating a portion of the display area of ​​FIGS. 1A and 1B according to one embodiment.

[0056] FIG. 17 is an enlarged plan view of a pixel circuit block, light-emitting elements connected to the pixel circuit block, and a switching circuit unit of FIG. 16 according to one embodiment.

[0057] FIG. 18 is a plan view schematically illustrating a portion of the display area of ​​FIGS. 1A and 1B according to one embodiment.

[0058] FIG. 19 is an enlarged plan view of a pixel circuit block, light-emitting elements connected to the pixel circuit block, and a switching circuit unit of FIG. 18 according to one embodiment.

[0059] FIG. 20 is a block diagram illustrating an electronic device according to one embodiment.

[0060] FIG. 21 is a graphic image showing an electronic device according to various embodiments.

[0061] The present invention is susceptible to various modifications and takes various forms. Specific embodiments are illustrated in the drawings and described in detail herein. However, this is not intended to limit the invention to specific disclosed forms, but rather to encompass all modifications, equivalents, and alternatives falling within the spirit and technical scope of the present invention.

[0062] While terms like "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms may be used to distinguish one component from another. For example, without departing from the scope of the present invention, a first component could be referred to as a "second component," and similarly, a second component could also be referred to as a "first component."

[0063] When a component is referred to as being "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but there may also be other components intervening. Other expressions describing the relationship between components, such as "between" and "directly between," or "adjacent to" and "directly adjacent to," should be interpreted similarly.

[0064] The terminology used herein is for the purpose of describing specific embodiments only and is not intended to limit the present invention. The singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, it should be understood that the terms "comprises" or "has" indicate the presence of a described feature, number, step, operation, component, part, or combination thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0065] Terms such as "below," "below," "underneath," "below," "above," "above," "above," and "above" are used to describe the relationships between components depicted in the drawings. These terms are relative concepts and are explained based on the directions indicated in the drawings.

[0066] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by those of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning within the context of the relevant technology, and shall not be construed in an idealized or overly formal sense unless explicitly defined herein.

[0067] Hereinafter, a display device according to one embodiment will be described in more detail with reference to the attached drawings. Identical components in the drawings will be designated by the same reference numerals, and redundant descriptions of identical components will be omitted.

[0068] FIG. 1a is a plan view showing a display device according to one embodiment, and FIG. 1b is a plan view showing a display device according to one embodiment.

[0069] In one embodiment, referring to FIGS. 1A and 1B, the display device (DD, DDa) may be a device activated in response to an electrical signal. For example, the display device (DD) of FIG. 1A may be a small display device used in small electronic devices such as smartphones, mobile phones, smart watches, game consoles, and cameras.

[0070] In another embodiment, the display device (DDa) of FIG. 1b may be a medium- to large-sized display device used in medium- to large-sized electronic devices such as laptops, tablet PCs, televisions, computer monitors, vehicle monitors, and external billboards. FIG. 1a illustrates the display device (DD) as an example of the small-sized display device, and FIG. 1b illustrates the display device (DDa) as an example of the medium- to large-sized display device.

[0071] In one embodiment, the display device (DD, DDa) may include a display area (DA) and a peripheral area (NDA). The display area (DA) may be an area that generates light or displays an image by controlling the transmittance of light provided from an external light source. The peripheral area (NDA) may be located around the display area (DA). For example, the peripheral area (NDA) may surround at least a portion of the display area (DA). In one embodiment, the peripheral area (NDA) may be an area that does not display an image. However, the present invention is not necessarily limited thereto, and an image may be displayed in at least a portion of the peripheral area (NDA). For example, a light-emitting element that emits light may be arranged in at least a portion of the peripheral area (NDA).

[0072] In one embodiment, the display device (DD, DDa) may include a substrate (SUB), a plurality of pixels (PX), a gate wiring (GL), a data wiring (DL), a data driver (DDV), and a gate driver (GDV).

[0073] In one embodiment, the substrate (SUB) may form the base of the display device (DD, DDa). In one embodiment, examples of materials that may be used as the substrate (SUB) include glass, quartz, silicon, polymers, etc. These may be used alone or in combination. In addition, the substrate (SUB) may have a single-layer structure or a multi-layer structure in which multiple layers comprising different materials are laminated.

[0074] In one embodiment, pixels (PX) may be arranged in a display area (DA) on a substrate (SUB). The pixels (PX) may be electrically connected to gate lines (GL) and data lines (DL). For example, the pixels (PX) may be arranged in a matrix form along a first direction (DR1) and a second direction (DR2). Each of the pixels (PX) may include a pixel driving circuit and a light-emitting element. The light-emitting element may emit light. For example, the light-emitting element may be an organic light-emitting diode or an inorganic light-emitting diode.

[0075] In one embodiment, the gate wiring (GL) and the data wiring (DL) may intersect each other. For example, the gate wiring (GL) may extend in a first direction (DR1) and be arranged along a second direction (DR2). The data wiring (DL) may extend in a second direction (DR2) and be arranged along the first direction (DR1). However, the present invention is not necessarily limited thereto.

[0076] In one embodiment, a data driver (DDV) may be disposed in a peripheral area (NDA) on a substrate (SUB). The data driver (DDV) may generate a data voltage. The data driver (DDV) may output the data voltage to a data line (DL). The data voltage may be applied to pixels (PX) through the data line (DL).

[0077] In one embodiment, the data driver (DDV) may be mounted on the substrate (SUB). However, the present invention is not necessarily limited thereto, and the data driver (DDV) may also be disposed on a flexible film coupled to the substrate (SUB). That is, the data driver (DDV) may be disposed on the flexible film in a chip-on-film (COF) manner.

[0078] In one embodiment, the display device (DDa) of FIG. 1B may include a plurality of data driving units (DDV). For example, the data driving units (DDV) may be arranged on both sides of the display area (DA) in the second direction (DR2). For example, the data driving units (DDV) may be arranged along the long side of the substrate (SUB). However, the present invention is not necessarily limited thereto.

[0079] In one embodiment, the gate driver (GDV) may be disposed in a peripheral area (NDA) on the substrate (SUB). The gate driver (GDV) may generate a gate signal. The gate driver (GDV) may output the gate signal to a gate line (GL). The gate signal may be applied to pixels (PX) through the gate line (GL). In one embodiment, the gate driver (GDV) may be disposed on both sides of the display area (DA) in the first direction (DR1). However, the present invention is not necessarily limited thereto.

[0080] In one embodiment, a light emitting driver unit that generates a light emitting control signal may be further disposed in the peripheral area (NDA). The light emitting control signal may be applied to the pixels (PX) through a light emitting control line.

[0081] In one embodiment, the number and arrangement relationship of the data driving units (DDV) illustrated in FIGS. 1A and 1B may vary depending on the embodiments, and the number and arrangement relationship of the gate driving units (GDV) may vary depending on the embodiments.

[0082] In one embodiment, although the display device (DD) in FIG. 1A is illustrated as having a substantially rectangular planar shape having a short side extending in the first direction (DR1) and a long side extending in the second direction (DR2), the present invention is not necessarily limited thereto. Furthermore, although the display device (DDa) in FIG. 1B is illustrated as having a rectangular planar shape having a long side extending in the first direction (DR1) and a short side extending in the second direction (DR2), the present invention is not necessarily limited thereto. That is, the planar shapes of the display devices (DD, DDa) may be variously changed depending on the embodiments.

[0083] In one embodiment, the descriptions referring to the drawings below can be equally applied to the display device (DD) of FIG. 1a and the display device (DDa) of FIG. 1b. Therefore, for convenience of explanation, the term "display device (DD)" will be used hereafter.

[0084] FIG. 2A is a circuit diagram showing an example of the circuit structure of a pixel and switching circuit included in the display device of FIGS. 1A and 1B according to one embodiment. FIG. 2B is a circuit diagram showing an example of the circuit structure of a pixel and switching circuit included in the display device of FIGS. 1A and 1B according to one embodiment.

[0085] In one embodiment, referring to FIGS. 2A and 2B, a pixel (PX) may include a pixel driving circuit (PC) and a light-emitting element (LED) electrically connected to the pixel driving circuit (PC). The pixel driving circuit (PC) may generate a driving current (ID), and the light-emitting element (LED) may generate light based on the driving current (ID).

[0086] In one embodiment, the pixel driving circuit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a first capacitor (C1), and a second capacitor (C2).

[0087] In one embodiment, the first transistor (T1), the second transistor (T2), the third transistor (T3), and the fourth transistor (T4) may be NMOS transistors, and the fifth transistor (T5) and the sixth transistor (T6) may be PMOS transistors. However, embodiments of the present invention are not necessarily limited thereto. For example, the first transistor (T1) may be an NMOS transistor. Some of the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), and the sixth transistor (T6) may be NMOS transistors, and others may be PMOS transistors. In another embodiment, the first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), and the sixth transistor (T6) may all be NMOS transistors.

[0088] Here, the first transistor (T1) may be referred to as a driving transistor, and the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), and the sixth transistor (T6) may each be referred to as switching transistors.

[0089] In one embodiment, when the pixel driving circuit (PC) includes an NMOS transistor and a PMOS transistor, the active pattern of the NMOS transistor may include an oxide semiconductor, and the active pattern of the PMOS transistor may include a silicon semiconductor. However, the present invention is not necessarily limited thereto, and the active pattern of the NMOS transistor may include a silicon semiconductor, and the active pattern of the PMOS transistor may include an oxide semiconductor.

[0090] In one embodiment, the pixel driving circuit (PC) can be electrically connected to a first gate wire (GWL), a second gate wire (GRL), a third gate wire (GIL), a first data wire (DL_P), a first emission control wire (EL1), a second emission control wire (EL2), a first voltage wire (VL1), a second voltage wire (VL2), and a third voltage wire (VL3). The first gate wire (GWL) can transmit a first gate signal (GW). The second gate wire (GRL) can transmit a second gate signal (GR). The third gate wire (GIL) can transmit a third gate signal (GI). The first data wire (DL_P) can transmit a first data voltage (DATA1). The first emission control wire (EL1) can transmit a first emission control signal (EM1). The second emission control wire (EL2) can transmit a second emission control signal (EM2). The first voltage line (VL1) can transmit the first power voltage (ELVSS). The second voltage line (VL2) can transmit the reference voltage (VREF). The third voltage line (VL3) can transmit the initialization voltage (VINT).

[0091] In one embodiment, the first transistor (T1) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor (T1) may be connected to a first node (N1). The first electrode of the first transistor (T1) may be connected to a second node (N2). The second electrode of the first transistor (T1) may be connected to a second electrode (e.g., a drain electrode) of a fifth transistor (T5). The first transistor (T1) may provide a driving current (ID) to a light-emitting element (LED). In one embodiment, the first electrode of the first transistor (T1) may be a source electrode, and the second electrode of the first transistor (T1) may be a drain electrode.

[0092] The first transistor (T1) may further include a back gate electrode. The back gate electrode of the first transistor (T1) may be connected to a node between the second capacitor (C2) and the second node (N2).

[0093] In one embodiment, the second transistor (T2) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the second transistor (T2) may be connected to a first gate line (GWL). The first electrode of the second transistor (T2) may be connected to a first node (N1). The second electrode of the second transistor (T2) may be connected to a first data line (DL_P). In one embodiment, the first electrode of the second transistor (T2) may be a source electrode, and the second electrode of the second transistor (T2) may be a drain electrode. In another embodiment, the first electrode of the second transistor (T2) may be a drain electrode, and the second electrode of the second transistor (T2) may be a source electrode.

[0094] In one embodiment, the gate electrode of the second transistor (T2) can receive a first gate signal (GW) through a first gate wire (GWL). The second transistor (T2) can be turned on or off in response to the first gate signal (GW). For example, when the first gate signal (GW) has an activation level, the second transistor (T2) can be turned on. In this case, the second transistor (T2) can provide the first data voltage (DATA1) to the first node (N1) through the first data wire (DL_P). Conversely, when the first gate signal (GW) has a deactivation level, the second transistor (T2) can be turned off. In this case, the second transistor (T2) can block the supply of the first data voltage (DATA1).

[0095] In one embodiment, the third transistor (T3) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the third transistor (T3) may be connected to a second gate line (GRL). The first electrode of the third transistor (T3) may be connected to a first node (N1). The second electrode of the third transistor (T3) may be connected to a second voltage line (VL2). In one embodiment, the first electrode of the third transistor (T3) may be a source electrode, and the second electrode of the third transistor (T3) may be a drain electrode. In another embodiment, the first electrode of the third transistor (T3) may be a drain electrode, and the second electrode of the third transistor (T3) may be a source electrode.

[0096] In one embodiment, the gate electrode of the third transistor (T3) can receive a second gate signal (GR) through a second gate line (GRL). The third transistor (T3) can be turned on or off in response to the second gate signal (GR). For example, when the second gate signal (GR) has an activation level, the third transistor (T3) can be turned on. In this case, the third transistor (T3) can provide the reference voltage (VREF) to the first node (N1) through the second voltage line (VL2). Conversely, when the second gate signal (GR) has an inactivation level, the third transistor (T3) can be turned off. In this case, the third transistor (T3) can block the supply of the reference voltage (VREF).

[0097] In one embodiment, the fourth transistor (T4) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the fourth transistor (T4) may be connected to a third gate wire (GIL). The first electrode of the fourth transistor (T4) may be connected to an anode electrode of a light emitting element (LED). The second electrode of the fourth transistor (T4) may be connected to a third voltage wire (VL3). In one embodiment, the first electrode of the fourth transistor (T4) may be a source electrode, and the second electrode of the fourth transistor (T4) may be a drain electrode. In another embodiment, the first electrode of the fourth transistor (T4) may be a drain electrode, and the second electrode of the fourth transistor (T4) may be a source electrode.

[0098] The gate electrode of the fourth transistor (T4) can receive a third gate signal (GI) through a third gate line (GIL). The fourth transistor (T4) can be turned on or off in response to the third gate signal (GI). For example, when the third gate signal (GI) has an activation level, the fourth transistor (T4) can be turned on. In this case, the fourth transistor (T4) can provide an initialization voltage (VINT) to a second electrode (e.g., a drain electrode) of the sixth transistor (T6) through a third voltage line (VL3). Conversely, when the third gate signal (GI) has an inactivation level, the fourth transistor (T4) can block the supply of the initialization voltage (VINT).

[0099] In one embodiment, the fifth transistor (T5) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the fifth transistor (T5) may be connected to the first light emission control line (EL1). The first electrode of the fifth transistor (T5) may be connected to the third node (N3). The second electrode of the fifth transistor (T5) may be connected to the second electrode (e.g., a drain electrode) of the first transistor (T1). In one embodiment, the first electrode of the fifth transistor (T5) may be a source electrode, and the second electrode of the fifth transistor (T5) may be a drain electrode. In another embodiment, the first electrode of the fifth transistor (T5) may be a drain electrode, and the second electrode of the fifth transistor (T5) may be a source electrode.

[0100] In one embodiment, the sixth transistor (T6) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the sixth transistor (T6) may be connected to the second light-emitting control line (EL2). The first electrode of the sixth transistor (T6) may be connected to the second node (N2). The second electrode of the sixth transistor (T6) may be connected to the anode electrode of the light-emitting element (LED). In one embodiment, the first electrode of the sixth transistor (T6) may be a source electrode, and the second electrode of the sixth transistor (T6) may be a drain electrode. In another embodiment, the first electrode of the sixth transistor (T6) may be a drain electrode, and the second electrode of the sixth transistor (T6) may be a source electrode.

[0101] In one embodiment, the gate electrode of the fifth transistor (T5) can receive a first light emission control signal (EM1) through the first light emission control wire (EL1). The fifth transistor (T5) can be turned on or turned off in response to the first light emission control signal (EM1). Similarly, the gate electrode of the sixth transistor (T6) can receive a second light emission control signal (EM2) through the second light emission control wire (EL2). The sixth transistor (T6) can be turned on or turned off in response to the second light emission control signal (EM2).

[0102] For example, in one embodiment, when both the first light emission control signal (EM1) and the second light emission control signal (EM2) have an activation level, both the fifth transistor (T5) and the sixth transistor (T6) can be turned on. In this case, the fifth transistor (T5) and the sixth transistor (T6) can provide the driving current (ID) generated by the first transistor (T1) to the anode electrode of the light emitting element (LED). Conversely, when both the first light emission control signal (EM1) and the second light emission control signal (EM2) have an inactivation level, both the fifth transistor (T5) and the sixth transistor (T6) can be turned off. In this case, the fifth transistor (T5) and the sixth transistor (T6) can block the supply of the driving current (ID) generated by the first transistor (T1).

[0103] In one embodiment, the first capacitor (C1) may include a first electrode and a second electrode. The first electrode of the first capacitor (C1) may be connected to a first node (N1). The second electrode of the first capacitor (C1) may be connected to a second node (N2). The first capacitor (C1) may be charged and discharged according to a first data voltage (DATA1) transmitted to the first node (N1).

[0104] In one embodiment, the second capacitor (C2) may include a first electrode and a second electrode. The first electrode of the second capacitor (C2) may be connected to a third node (N3). The second electrode of the second capacitor (C2) may be connected to a back gate electrode of the first transistor (T1) and the second node (N2).

[0105] The light emitting element (LED) may include an anode electrode and a cathode electrode. The anode electrode of the light emitting element (LED) may be connected to the second electrode of the sixth transistor (T6). The cathode electrode of the light emitting element (LED) may be connected to a first voltage line (VL1). The cathode electrode of the light emitting element (LED) may receive a first power supply voltage (ELVSS) through the first voltage line (VL1).

[0106] In one embodiment, the display device (DD) may further include a switching circuit (SPC) disposed in the display area (DA) and electrically connected to the pixel driving circuit (PC) of FIG. 2A (or the pixel circuit block (PCB) of FIG. 2B). The switching circuit (SPC) may selectively provide a high-level second power voltage (ELVDD_H) or a low-level second power voltage (ELVDD_L) to the pixel driving circuit (PC) of FIG. 2A (or the pixel circuit block (PCB) of FIG. 2B).

[0107] In one embodiment, the switching circuit (SPC) may be electrically connected to the pixel driving circuit (PC) of FIG. 2A (or the pixel circuit block (PCB) of FIG. 2B) via an output power connection wiring (PV_CL). Specifically, the output power connection wiring (PV_CL) may connect a third node (N3) of the pixel driving circuit (PC) of FIG. 2A (or the pixel circuit block (PCB) of FIG. 2B) and a fourth node (N4) of the switching circuit (SPC). Accordingly, the output power connection wiring (PV_CL) may selectively receive a high-level second power voltage (ELVDD_H) or a low-level second power voltage (ELVDD_L).

[0108] For example, in one embodiment, the high-level second power voltage (ELVDD_H) and the low-level second power voltage (ELVDD_L) may each be driving voltages having a voltage level higher than the first power voltage (ELVSS). In this case, the first power voltage (ELVSS) may be referred to as a common voltage.

[0109] In one embodiment, the switching circuit (SPC) may include a first switching element (M1), a second switching element (M2), a third switching element (M3), and a third capacitor (C_S).

[0110] In one embodiment, the first switching element (M1) may be a PMOS transistor, and the second switching element (M2) may be an NMOS transistor. However, the present invention is not necessarily limited thereto, and in another embodiment, the first switching element (M1) may be an NMOS transistor, and the second switching element (M2) may be a PMOS transistor.

[0111] In one embodiment, the third switching element (M3) may be an NMOS transistor. However, the present invention is not necessarily limited thereto, and the third switching element (M3) may also be a PMOS transistor.

[0112] In one embodiment, a switching circuit unit (SPC) may be electrically connected to a first power voltage line (PVL_H), a second power voltage line (PVL_L), a gate line (GL), and a second data line (DL_S). The first power voltage line (PVL_H) may transmit a high-level second power voltage (ELVDD_H). The second power voltage line (PVL_L) may transmit a low-level second power voltage (ELVDD_L). The gate line (GL) may transmit a gate signal (GS). The second data line (DL_S) may transmit a second data voltage (DATA2).

[0113] In one embodiment, the first switching element (M1) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first switching element (M1) may be connected to a fifth node (N5). The first electrode of the first switching element (M1) may be connected to a first power voltage line (PVL_H). The second electrode of the first switching element (M1) may be connected to a fourth node (N4). In one embodiment, the first electrode of the first switching element (M1) may be a source electrode, and the second electrode of the first switching element (M1) may be a drain electrode. In another embodiment, the first electrode of the first switching element (M1) may be a drain electrode, and the second electrode of the first switching element (M1) may be a source electrode.

[0114] In one embodiment, the second switching element (M2) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the second switching element (M2) may be connected to a fifth node (N5). The first electrode of the second switching element (M2) may be connected to a fourth node (N4). The second electrode of the second switching element (M2) may be connected to a second power voltage line (PVL_L). In one embodiment, the first electrode of the second switching element (M2) may be a source electrode, and the second electrode of the second switching element (M2) may be a drain electrode. In another embodiment, the first electrode of the second switching element (M2) may be a drain electrode, and the second electrode of the second switching element (M2) may be a source electrode.

[0115] In one embodiment, the third switching element (M3) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the third switching element (M3) may be connected to a gate line (GL). The first electrode of the third switching element (M3) may be connected to a fifth node (N5). The second electrode of the third switching element (M3) may be connected to a second data line (DL_S). In one embodiment, the first electrode of the third switching element (M3) may be a source electrode, and the second electrode of the third switching element (M3) may be a drain electrode. In another embodiment, the first electrode of the third switching element (M3) may be a drain electrode, and the second electrode of the third switching element (M3) may be a source electrode.

[0116] In one embodiment, the third capacitor (C_S) may include a first electrode and a second electrode. The first electrode of the third capacitor (C_S) may be connected to a second power voltage line (PVL_L). Accordingly, the first electrode of the third capacitor (C_S) may receive a low-level second power voltage (ELVDD_L). The second electrode of the third capacitor (C_S) may be connected to a fifth node (N5).

[0117] In one embodiment, the gate electrode of the third switching element (M3) can receive a gate signal (GS) through a gate wiring (GL). The third switching element (M3) can be turned on or off in response to the gate signal (GS).

[0118] In one embodiment, the gate signal (GS) may be identical to the first gate signal (GW). In this case, the gate wiring (GL) transmitting the gate signal (GS) and the first gate wiring (GWL) transmitting the first gate signal (GW) may be a single gate wiring. In another embodiment, the gate wiring (GL) transmitting the gate signal (GS) may be independent of the first gate wiring (GWL) transmitting the first gate signal (GW). However, the present invention is not necessarily limited thereto, and the gate signal (GS) may be identical to the second gate signal (GR) or the third gate signal (GI).

[0119] For example, in one embodiment, when the gate signal (GS) has an activation level, the third switching element (M3) can be turned on. In this case, the third switching element (M3) can provide a second data voltage (DATA2) of a first voltage level or a second data voltage (DATA2) of a second voltage level different from the first voltage level to the gate electrode of the first switching element (M1) and the gate electrode of the second switching element (M2) through the second data line (DL_S).

[0120] For example, in one embodiment, when the first switching element (M1) is a PMOS transistor and the second switching element (M2) is an NMOS transistor, the first voltage level may be a low level and the second voltage level may be a high level.

[0121] In one embodiment, when the third switching element (M3) provides the second data voltage (DATA2) of the first voltage level to the gate electrode of the first switching element (M1) and the gate electrode of the second switching element (M2), the first switching element (M1) may be turned on and the second switching element (M2) may be turned off. In this case, the first switching element (M1) may provide the second power voltage (ELVDD_H) of the high level to the output power connection line (PV_CL). Accordingly, the output power connection line (PV_CL) may transmit the second power voltage (ELVDD_H) of the high level to the pixel driving circuit unit (PC) of FIG. 2A (or the pixel circuit block (PCB) of FIG. 2B).

[0122] In one embodiment, when the third switching element (M3) provides the second data voltage (DATA2) of the second voltage level to the gate electrode of the first switching element (M1) and the gate electrode of the second switching element (M2), the first switching element (M1) may be turned off and the second switching element (M2) may be turned on. In this case, the second switching element (M2) may provide the second power voltage (ELVDD_L) of the low level to the output power connection line (PV_CL). Accordingly, the output power connection line (PV_CL) may transmit the second power voltage (ELVDD_L) of the low level to the pixel driving circuit unit (PC) of FIG. 2A (or the pixel circuit block (PCB) of FIG. 2B).

[0123] In one embodiment, as illustrated in FIG. 2A, a switching circuit (SPC) may be electrically connected to a pixel driving circuit (PC). That is, the switching circuit (SPC) may be electrically connected one-to-one with the pixel driving circuit (PC).

[0124] In another embodiment, a switching circuit unit (SPC) may be electrically connected to at least one pixel driving circuit unit. That is, the switching circuit unit (SPC) may be electrically connected to at least one pixel driving circuit unit in a one-to-many manner. For example, as illustrated in FIG. 2B, a switching circuit unit (SPC) may be electrically connected to one pixel circuit block (PCB) including first to fourth pixel driving circuit units (PC1, PC2, PC3, PC4) having the same circuit structure through an output power connection line (PV_CL). At this time, the pixels (PX1, PX2, PX3, PX4) may include light emitting elements (LEDs) electrically connected to the pixel driving circuit units (PC1, PC2, PC3, PC4) and the pixel driving circuit units (PC1, PC2, PC3, PC4), respectively.

[0125] In one embodiment, the number of pixel driving circuit units of the pixel circuit block (PCB) illustrated in FIG. 2B is an example, and the pixel circuit block (PCB) may include at least one pixel driving circuit unit including a plurality of transistors.

[0126] In addition, although FIGS. 2A and 2B illustrate that the pixel driving circuit (PC, PC1, PC2, PC3, PC4) of each pixel (PX, PX1, PX2, PX3, PX4) includes six transistors and two capacitors, the present invention is not necessarily limited thereto. For example, the pixel driving circuit (PC, PC1, PC2, PC3, PC4) of each pixel (PX, PX1, PX2, PX3, PX4) may include two transistors and one capacitor. In this case, the driving transistor that generates the driving current may be an NMOS transistor.

[0127] FIGS. 3 and 4 are plan views schematically illustrating a portion of the display area of ​​FIGS. 1A and 1B according to one embodiment.

[0128] In one embodiment, referring to FIGS. 3 and 4, the display device (DD) may include first to third pixel driving circuits (PCa, PCb, PCc), first to third light-emitting elements (LEDa, LEDb, LEDc), and a switching circuit (SPC) respectively arranged in the display area (DA).

[0129] In one embodiment, the pixel driving circuits (PCa, PCb, PCc) may correspond to the pixel driving circuits (PC, PC1, PC2, PC3, PC4) illustrated in FIGS. 2A and 2B, respectively. That is, the pixel driving circuits (PCa, PCb, PCc) may have the same circuit structure and include the same components as the pixel driving circuits (PC, PC1, PC2, PC3, PC4) illustrated in FIGS. 2A and 2B, respectively.

[0130] For example, in one embodiment, the pixel driving circuits (PCa, PCb, PCc) may be sequentially arranged along the first direction (DR1) in a rectangular shape. However, the present invention is not necessarily limited thereto, and the shape and arrangement of the pixel driving circuits (PCa, PCb, PCc) may be varied in various ways depending on the embodiments.

[0131] In one embodiment, the light emitting elements (LEDa, LEDb, LEDc) may correspond to the light emitting elements (LEDs) illustrated in FIGS. 2a and 2b, respectively.

[0132] In one embodiment, the display area (DA) may include first to third light-emitting areas (EAa, EAb, EAc), respectively. A first light-emitting element (LEDa) may be arranged in the first light-emitting area (EAa), a second light-emitting element (LEDb) may be arranged in the second light-emitting area (EAb), and a third light-emitting element (LEDc) may be arranged in the third light-emitting area (EAc).

[0133] In one embodiment, the light-emitting elements (LEDa, LEDb, LEDc) can emit light of different colors. For example, the first light-emitting element (LEDa) can emit red light, the second light-emitting element (LEDb) can emit green light, and the third light-emitting element (LEDc) can emit blue light. Accordingly, the first light-emitting area (EAa) can emit red light, the second light-emitting area (EAb) can emit green light, and the third light-emitting area (EAc) can emit blue light. However, the present invention is not necessarily limited thereto.

[0134] For example, in one embodiment, the light-emitting areas (EAa, EAb, EAc) may be arranged in an S-stripe type. However, the present invention is not necessarily limited thereto, and the arrangement of the light-emitting areas (EAa, EAb, EAc) may be varied in various ways depending on the embodiments.

[0135] In one embodiment, the light-emitting elements (LEDa, LEDb, LEDc) may be respectively connected to pixel driving circuits (PCa, PCb, PCc). For example, a first light-emitting element (LEDa) may be connected to a first pixel driving circuit (PCa), a second light-emitting element (LEDb) may be connected to a second pixel driving circuit (PCb), and a third light-emitting element (LEDc) may be connected to a third pixel driving circuit (PCc). Accordingly, the first pixel driving circuit (PCa) and the first light-emitting element (LEDa) may form one pixel, the second pixel driving circuit (PCb) and the second light-emitting element (LEDb) may form one pixel, and the third pixel driving circuit (PCc) and the third light-emitting element (LEDc) may form one pixel.

[0136] In one embodiment, a switching circuit (SPC) may be electrically connected one-to-one with a pixel circuit block (PCB). One switching circuit (SPC) may be arranged around one pixel circuit block (PCB).

[0137] For example, in one embodiment, pixel circuit blocks (PCBs) can be repeatedly arranged along a first direction (DR1) and a second direction (DR2).

[0138] In one embodiment, the switching circuit (SPC) may correspond to the switching circuit (SPC) illustrated in FIGS. 2A and 2B. That is, the switching circuit (SPC) may have the same circuit structure and include the same components as the switching circuit (SPC) illustrated in FIGS. 2A and 2B.

[0139] In one embodiment, a switching circuit (SPC) may be electrically connected to a first power supply voltage line (PVL_H) for transmitting a high-level second power supply voltage (e.g., ELVDD_H in FIGS. 2A and 2B), a second power supply voltage line (PVL_L) for transmitting a low-level second power supply voltage (e.g., ELVDD_L in FIGS. 2A and 2B), a gate line (GL) for transmitting a gate signal (e.g., GS in FIGS. 2A and 2B), and a second data line (DL_S) for transmitting a second data voltage (e.g., DATA2 in FIGS. 2A and 2B).

[0140] Additionally, in one embodiment, the switching circuit (SPC) may be electrically connected to the pixel driving circuits (PCa, PCb, PCc) (i.e., pixel circuit blocks (PCB)) via an output power connection line (PV_CL) that selectively provides the second power voltage of the high level or the second power voltage of the low level.

[0141] For example, in one embodiment, the first power voltage line (PVL_H), the second power voltage line (PVL_L), and the second data line (DL_S) may each extend in the second direction (DR2). The second power voltage line (PVL_L) may be located between the first power voltage line (PVL_H) and the second data line (DL_S) on a plane. In addition, the output power connection line (PV_CL) may include a first portion extending in the second direction (DR2) in an area where the switching circuit unit (SPC) is disposed, and a second portion extending in the first direction (DR1) in an area where the first to third pixel driving circuit units (PCa, PCb, PCc) are disposed. The output power connection line (PV_CL) may be located on the left side of the first power voltage line (PVL_H).

[0142] For example, in one embodiment, the output power connection wiring (PV_CL) may be connected to the switching circuit (SPC) through a first contact hole (CNT1_S), the first power voltage wiring (PVL_H) may be connected to the switching circuit (SPC) through a second contact hole (CNT2_S), the second power voltage wiring (PVL_L) may be connected to the switching circuit (SPC) through a third contact hole (CNT3_S), and the second data wiring (DL_S) may be connected to the switching circuit (SPC) through a fourth contact hole (CNT4_S). In addition, the output power connection wiring (PV_CL) may be connected to each of the pixel driving circuits (PCa, PCb, PCc) through a contact hole (CNT_P).

[0143] FIG. 5 is a circuit diagram showing an example of a circuit structure of a pixel and switching circuit unit included in the display device of FIG. 1a and FIG. 1b according to one embodiment.

[0144] In the following, descriptions that overlap with the descriptions of the pixel and switching circuits described with reference to FIGS. 2a and 2b are omitted or simplified.

[0145] In one embodiment, referring to FIG. 5, a first pixel (PX1') may include a first pixel driving circuit unit (PC1') and a light emitting element (LED) electrically connected to the first pixel driving circuit unit (PC1'), and a second pixel (PX2') may include a second pixel driving circuit unit (PC2') and a light emitting element (LED) electrically connected to the second pixel driving circuit unit (PC2').

[0146] In one embodiment, the first pixel driving circuit unit (PC1') and the second pixel driving circuit unit (PC2') may have substantially the same circuit structure.

[0147] In one embodiment, the first pixel driving circuit unit (PC1') and the second pixel driving circuit unit (PC2') may each include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a first capacitor (C1), and a second capacitor (C2).

[0148] In one embodiment, the first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), and the sixth transistor (T6) may all be NMOS transistors. However, the present invention is not necessarily limited thereto. For example, in another embodiment, the first transistor (T1) may be an NMOS transistor. Some of the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), and the sixth transistor (T6) may be NMOS transistors, and others may be PMOS transistors.

[0149] In one embodiment, the first pixel driving circuit unit (PC1') and the second pixel driving circuit unit (PC2') may be electrically connected to a first gate wire (GWL), a second gate wire (GCL), a third gate wire (GRL), a first data wire (DL_P), a first light emission control wire (EL1), a second light emission control wire (EL2), a first voltage wire (VL1), a second voltage wire (VL2), and a third voltage wire (VL3), respectively. The first gate wire (GWL) may transmit a first gate signal (GW). The second gate wire (GCL) may transmit a second gate signal (GC). The third gate wire (GRL) may transmit a third gate signal (GR). The first data wire (DL_P) may transmit a first data voltage (DATA1). The first light emission control wire (EL1) may transmit a first light emission control signal (EM1). The second light emission control wire (EL2) can transmit the second light emission control signal (EM2). The first voltage wire (VL1) can transmit the first power voltage (ELVSS). The second voltage wire (VL2) can transmit the reference voltage (VREF). The third voltage wire (VL3) can transmit the initialization voltage (VINT).

[0150] In one embodiment, the first transistor (T1) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor (T1) may be connected to a first node (N1). The first electrode of the first transistor (T1) may be connected to a second node (N2). The second electrode of the first transistor (T1) may be connected to a first electrode (e.g., a source electrode) of a fifth transistor (T5).

[0151] In one embodiment, the second transistor (T2) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the second transistor (T2) may be connected to a first gate line (GWL) to receive a first gate signal (GW). The first electrode of the second transistor (T2) may be connected to a first node (N1). The second electrode of the second transistor (T2) may be connected to a first data line (DL_P) to receive a first data voltage (DATA1).

[0152] In one embodiment, the third transistor (T3) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the third transistor (T3) may be connected to a second gate line (GCL) to receive a second gate signal (GC). The first electrode of the third transistor (T3) may be connected to a third node (N3). The second electrode of the third transistor (T3) may be connected to a third voltage line (VL3) to receive an initialization voltage (VCINT).

[0153] In one embodiment, the fourth transistor (T4) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the fourth transistor (T4) may be connected to a third gate line (GRL) to receive a third gate signal (GR). The first electrode of the fourth transistor (T4) may be connected to a first electrode (e.g., a source electrode) of the second transistor (T2). The second electrode of the fourth transistor (T4) may be connected to a second voltage line (VL2) to receive a reference voltage (VREF).

[0154] In one embodiment, the fifth transistor (T5) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the fifth transistor (T5) may be connected to the first light emission control line (EL1) and may receive the first light emission control signal (EM1). The first electrode of the fifth transistor (T5) may be connected to the second electrode (e.g., the drain electrode) of the first transistor (T1). The second electrode of the fifth transistor (T5) may be connected to the third node (N3).

[0155] In one embodiment, the sixth transistor (T6) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the sixth transistor (T6) may be connected to a second light emission control line (EL2) to receive a second light emission control signal (EM2). The first electrode of the sixth transistor (T6) may be connected to a second node (N2). The second electrode of the sixth transistor (T6) may be connected to a first voltage line (VL1) to receive a first power voltage (ELVSS).

[0156] In one embodiment, the first capacitor (C1) may include a first electrode and a second electrode. The first electrode of the first capacitor (C1) may be connected to a first node (N1). The second electrode of the first capacitor (C1) may be connected to a second electrode of a second capacitor (C2).

[0157] In one embodiment, the second capacitor (C2) may include a first electrode and a second electrode. The first electrode of the second capacitor (C2) may be connected to the first voltage line (VL1). The second electrode of the second capacitor (C2) may be connected to the second electrode of the first capacitor (C1).

[0158] In one embodiment, the light emitting element (LED) may include an anode electrode and a cathode electrode. The cathode electrode of the light emitting element (LED) may be connected to a third node (N3). The anode electrode of the light emitting element (LED) may be connected to an output power connection wire (PV_CL).

[0159] In one embodiment, the first electrode of each of the first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), and the sixth transistor (T6) may be a source electrode, and the second electrode of each may be a drain electrode. However, the present invention is not necessarily limited thereto.

[0160] In one embodiment, the display device (DD) may further include a switching circuit (SPC) disposed in the display area (DA) and electrically connected to a pixel circuit block (PCB') including pixel driving circuits (PC1', PC2'). The switching circuit (SPC) may selectively provide a high-level second power voltage (ELVDD_H) or a low-level second power voltage (ELVDD_L) to the pixel circuit block (PCB').

[0161] In one embodiment, the switching circuit (SPC) can be electrically connected to the pixel driving circuits (PC1', PC2') via an output power connection line (PV_CL). Specifically, the output power connection line (PV_CL) can connect anode electrodes of light-emitting elements (LEDs) of the pixel driving circuits (PC1', PC2') to a fourth node (N4) of the switching circuit (SPC). Accordingly, the output power connection line (PV_CL) can selectively receive a high-level second power voltage (ELVDD_H) or a low-level second power voltage (ELVDD_L).

[0162] In one embodiment, the switching circuit (SPC) may include a first switching element (M1), a second switching element (M2), a third switching element (M3), and a third capacitor (C_S). The circuit structure of the switching circuit (SPC) may be substantially the same as the circuit structure of the switching circuit (SPC) illustrated in FIGS. 2A and 2B.

[0163] The number of pixel driving circuits of the pixel circuit block (PCB') connected to the switching circuit unit (SPC) illustrated in FIG. 5 is an example of one embodiment, and the pixel circuit block (PCB') may include at least one pixel driving circuit unit including a plurality of transistors.

[0164] In one embodiment, although FIG. 5 illustrates that the pixel driving circuits (PC1', PC2') of each pixel (PX1', PX2') include six transistors and two capacitors, the present invention is not necessarily limited thereto. For example, in one embodiment, the pixel driving circuits (PC1', PC2') of each pixel (PX1', PX2') may include two transistors and one capacitor. In this case, the driving transistor that generates the driving current may be an NMOS transistor.

[0165] In one embodiment, referring again to FIGS. 2A, 2B, 3, 4, and 5, the display device (DD) may include a plurality of pixel circuit blocks, each including at least one pixel driving circuit including a plurality of transistors, and a switching circuit (SPC) electrically connected one-to-one to the pixel circuit blocks to selectively provide a high-level second power voltage (ELVDD_H) or a low-level second power voltage (ELVDD_L). The plurality of transistors may generate a driving current (ID) and include a driving transistor that is an NMOS transistor. For example, a high-level second power voltage (ELVDD_H) may be applied to the pixel circuit blocks disposed in a high-brightness area of ​​the display area (DA), and a low-level second power voltage (ELVDD_L) may be applied to the pixel circuit blocks disposed in a low-brightness area of ​​the display area (DA). Accordingly, power consumption of the display device (DD) may be reduced.

[0166] FIG. 6 is a circuit diagram showing an example of a circuit structure of a pixel and switching circuit unit included in the display device of FIG. 1a and FIG. 1b according to one embodiment.

[0167] In the following, descriptions that overlap with the descriptions of the pixel and switching circuits described with reference to FIGS. 2a and 2b are omitted or simplified.

[0168] In one embodiment, referring to FIG. 6, a first pixel (PX1'') may include a first pixel driving circuit unit (PC1'') and a light emitting element (LED) electrically connected to the first pixel driving circuit unit (PC1''), and a second pixel (PX2'') may include a second pixel driving circuit unit (PC2'') and a light emitting element (LED) electrically connected to the second pixel driving circuit unit (PC2'').

[0169] In one embodiment, the first pixel driving circuit unit (PC1'') and the second pixel driving circuit unit (PC2'') may have substantially the same circuit structure.

[0170] In one embodiment, the first pixel driving circuit unit (PC1'') and the second pixel driving circuit unit (PC2'') may each include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), a first capacitor (C1), and a second capacitor (C2).

[0171] In one embodiment, the first transistor (T1), the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) may be PMOS transistors, and the third transistor (T3) and the fourth transistor (T4) may be NMOS transistors. However, the present invention is not necessarily limited thereto, and in another embodiment, the first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) may all be PMOS transistors.

[0172] In one embodiment, the first pixel driving circuit unit (PC1'') and the second pixel driving circuit unit (PC2'') may be electrically connected to a first gate wire (GWL), a second gate wire (GCL), a third gate wire (GIL), a fourth gate wire (GBL), a first data wire (DL_P), a light emission control wire (EL), a first voltage wire (VL1), a second voltage wire (VL2), and a third voltage wire (VL3), respectively. The first gate wire (GWL) may transmit a first gate signal (GW). The second gate wire (GCL) may transmit a second gate signal (GC). The third gate wire (GIL) may transmit a third gate signal (GI). The fourth gate wire (GBL) may transmit a fourth gate signal (GB). The first data wire (DL_P) may transmit a first data voltage (DATA1). The light emission control wire (EL) may transmit a light emission control signal (EM). The first voltage line (VL1) can transmit the second power voltage (ELVDD). The second voltage line (VL2) can transmit the first initialization voltage (VINT). The third voltage line (VL3) can transmit the second initialization voltage (AINT).

[0173] In one embodiment, the first transistor (T1) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor (T1) may be connected to a first node (N1). The first electrode of the first transistor (T1) may be connected to a second node (N2). The second electrode of the first transistor (T1) may be connected to a third node (N3). The first transistor (T1) may be referred to as a driving transistor.

[0174] In one embodiment, the second transistor (T2) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the second transistor (T2) may be connected to a first gate line (GWL) to receive a first gate signal (GW). The first electrode of the second transistor (T2) may be connected to a first data line (DL_P) to receive a first data voltage (DATA1). The second electrode of the second transistor (T2) may be connected to a second node (N2).

[0175] In one embodiment, the third transistor (T3) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the third transistor (T3) may be connected to a second gate wiring (GCL) and may receive a second gate signal (GC). The first electrode of the third transistor (T3) may be connected to a third node (N3). The second electrode of the third transistor (T3) may be connected to a first node (N1).

[0176] In one embodiment, the fourth transistor (T4) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the fourth transistor (T4) may be connected to a third gate line (GIL) to receive a third gate signal (GI). The first electrode of the fourth transistor (T4) may be connected to a second electrode of the third transistor (T3). The second electrode of the fourth transistor (T4) may be connected to a second voltage line (VL2) to receive a first initialization voltage (VINT).

[0177] In one embodiment, the fifth transistor (T5) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the fifth transistor (T5) may be connected to a light emission control line (EL) to receive a light emission control signal (EM). The first electrode of the fifth transistor (T5) may be connected to a first voltage line (VL1) to receive a second power voltage (ELVDD). The second electrode of the fifth transistor (T5) may be connected to a second node (N2).

[0178] In one embodiment, the sixth transistor (T6) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the sixth transistor (T6) may be connected to an emission control line (EL) to receive an emission control signal (EM). The first electrode of the sixth transistor (T6) may be connected to a third node (N3). The second electrode of the sixth transistor (T6) may be connected to a second electrode of the seventh transistor (T7).

[0179] In one embodiment, as illustrated in FIG. 6, a single light emission control line (EL) may be connected to the gate electrode of the fifth transistor (T5) and the gate electrode of the sixth transistor (T6). In another embodiment, the light emission control line connected to the gate electrode of the fifth transistor (T5) and the light emission control line connected to the gate electrode of the sixth transistor (T6) may be independent of each other.

[0180] In one embodiment, the seventh transistor (T7) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the seventh transistor (T7) may be connected to a fourth gate line (GBL) to receive a fourth gate signal (GB). The first electrode of the seventh transistor (T7) may be connected to a third voltage line (VL3) to receive a second initialization voltage (AINT). The second electrode of the seventh transistor (T7) may be connected to an anode electrode of a light-emitting element (LED).

[0181] In one embodiment, the first capacitor (C1) may include a first electrode and a second electrode. The first electrode of the first capacitor (C1) may be connected to a first voltage line (VL1) and may receive a second power supply voltage (ELVDD). The second electrode of the first capacitor (C1) may be connected to a first node (N1).

[0182] In one embodiment, the second capacitor (C2) may include a first electrode and a second electrode. The first electrode of the second capacitor (C2) may be connected to the gate electrode of the second transistor (T2). The second electrode of the second capacitor (C2) may be connected to the first node (N1).

[0183] In one embodiment, the light emitting element (LED) may include an anode electrode and a cathode electrode. The anode electrode of the light emitting element (LED) may be connected to the second electrode of the seventh transistor (T7). The cathode electrode of the light emitting element (LED) may be connected to an output power connection wire (PV_CL).

[0184] In one embodiment, the first electrode of each of the first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) may be a source electrode, and the second electrode of each may be a drain electrode. However, the present invention is not necessarily limited thereto.

[0185] In one embodiment, the display device (DD) may further include a switching circuit (SPC) disposed in the display area (DA) and electrically connected to a pixel circuit block (PCB'') including first and second pixel driving circuits (PC1'', PC2''), respectively. The switching circuit (SPC) may selectively provide a first power supply voltage (ELVSS_H) of a high level or a first power supply voltage (ELVSS_L) of a low level to the pixel circuit block (PCB'').

[0186] In one embodiment, the switching circuit (SPC) can be electrically connected to the pixel driving circuits (PC1'', PC2'') via an output power connection line (PV_CL). Specifically, the output power connection line (PV_CL) can connect the cathode electrodes of the light-emitting elements (LEDs) of the pixel driving circuits (PC1'', PC2'') to the fourth node (N4) of the switching circuit (SPC). Accordingly, the output power connection line (PV_CL) can selectively receive a high-level first power voltage (ELVSS_H) or a low-level first power voltage (ELVSS_L).

[0187] In one embodiment, the switching circuit (SPC) may include a first switching element (M1), a second switching element (M2), a third switching element (M3), and a third capacitor (C_S). The circuit structure of the switching circuit (SPC) may be substantially the same as the circuit structure of the switching circuit (SPC) illustrated in FIGS. 2A and 2B.

[0188] For example, in one embodiment, the first power supply voltage (ELVSS_H) at a high level and the first power supply voltage (ELVSS_L) at a low level may each be a common voltage having a lower voltage level than the second power supply voltage (ELVDD). In this case, the second power supply voltage (ELVDD) may be referred to as a driving voltage.

[0189] For example, in one embodiment, when the gate signal (GS) has an activation level, the third switching element (M3) can be turned on. In this case, the third switching element (M3) can provide a second data voltage (DATA2) of a first voltage level or a second data voltage (DATA2) of a second voltage level different from the first voltage level to the gate electrode of the first switching element (M1) and the gate electrode of the second switching element (M2) through the second data line (DL_S).

[0190] For example, in one embodiment, when the first switching element (M1) is a PMOS transistor and the second switching element (M2) is an NMOS transistor, the first voltage level may be a low level and the second voltage level may be a high level.

[0191] In one embodiment, when the third switching element (M3) provides the second data voltage (DATA2) of the first voltage level to the gate electrode of the first switching element (M1) and the gate electrode of the second switching element (M2), the first switching element (M1) can be turned on and the second switching element (M2) can be turned off. In this case, the first switching element (M1) can provide the first power voltage (ELVSS_H) of the high level to the output power connection wiring (PV_CL). Accordingly, the output power connection wiring (PV_CL) can transmit the first power voltage (ELVSS_H) of the high level to the pixel circuit block (PCB'') including the pixel driving circuits (PC1'', PC2'').

[0192] In one embodiment, when the third switching element (M3) provides the second data voltage (DATA2) of the second voltage level to the gate electrode of the first switching element (M1) and the gate electrode of the second switching element (M2), the first switching element (M1) may be turned off and the second switching element (M2) may be turned on. In this case, the second switching element (M2) may provide the first power voltage (ELVSS_L) of the low level to the output power connection line (PV_CL). Accordingly, the output power connection line (PV_CL) may transmit the first power voltage (ELVSS_L) of the low level to the pixel circuit block (PCB'') including the pixel driving circuits (PC1'', PC2'').

[0193] In one embodiment, the number of pixel driving circuits of a pixel circuit block (PCB'') connected to a switching circuit unit (SPC) illustrated in FIG. 6 is an example, and the pixel circuit block (PCB'') may include at least one pixel driving circuit unit including a plurality of transistors.

[0194] In one embodiment, FIG. 6 illustrates that the pixel driving circuits (PC1'', PC2'') of each pixel (PX1'', PX2'') include seven transistors and two capacitors, but the present invention is not necessarily limited thereto.

[0195] For example, in one embodiment, the pixel driving circuitry (PC1'', PC2'') of each pixel (PX1'', PX2'') may include at least one transistor and at least one capacitor. In this case, the driving transistor that generates the driving current may be a PMOS transistor.

[0196] Fig. 7 is a plan view schematically illustrating a portion of the display area of ​​Figs. 1a and 1b according to one embodiment. Fig. 8 is an enlarged plan view of one pixel circuit block, light-emitting elements connected to one pixel circuit block, and one switching circuit unit of Fig. 7 according to one embodiment.

[0197] In the following, descriptions that overlap with those described with reference to FIGS. 3 and 4 are omitted or simplified.

[0198] In one embodiment, referring to FIGS. 7 and 8, the display device (DD) may include pixel driving circuits (PCa, PCb, PCc), light-emitting elements (LEDa, LEDb, LEDc), a switching circuit (SPC), a plurality of connection patterns (CNP), and a separator (SPR) arranged in a display area (DA).

[0199] In one embodiment, the pixel driving circuits (PCa, PCb, PCc) may each correspond to the pixel driving circuits (PC1'', PC2'') illustrated in FIG. 6. That is, the pixel driving circuits (PCa, PCb, PCc) may each have the same circuit structure as the pixel driving circuits (PC1'', PC2'') illustrated in FIG. 6 and may include the same components.

[0200] In one embodiment, the light emitting elements (LEDa, LEDb, LEDc) may each correspond to the light emitting elements (LED) illustrated in FIG. 6. The display area (DA) may include light emitting areas (EAa, EAb, EAc). A first light emitting element (LEDa) may be arranged in a first light emitting area (EAa), a second light emitting element (LEDb) may be arranged in a second light emitting area (EAb), and a third light emitting element (LEDc) may be arranged in a third light emitting area (EAc).

[0201] In one embodiment, the light emitting elements (LEDa, LEDb, LEDc) may each include a first electrode (e.g., the first electrode E1 of FIGS. 9 and 10), a light emitting layer (e.g., the light emitting layer EML of FIGS. 9 and 10) disposed on the first electrode, an intermediate layer (e.g., the intermediate layer ML of FIGS. 9 and 10) disposed on the light emitting layer, and a second electrode layer disposed on the intermediate layer. In one embodiment, the first electrode may be an anode electrode, and the second electrode layer may be a cathode electrode.

[0202] In one embodiment, in the display area (DA), a first unit light emitting area (UEA1) including light emitting areas (EAa, EAb, EAc) and a second unit light emitting area (UEA2) including light emitting areas (EAa, EAb, EAc) can be defined.

[0203] For example, in one embodiment, the first unit light emitting area (UEA1) and the second unit light emitting area (UEA2) can be distinguished based on the arrangement relationship between the light emitting elements (LEDa, LEDb, LEDc) (or the arrangement relationship between the light emitting areas (EAa, EAb, EAc)). That is, the arrangement relationship between the light emitting elements (LEDa, LEDb, LEDc) (or the light emitting areas (EAa, EAb, EAc)) in each first unit light emitting area (UEA1) can be substantially the same, and the arrangement relationship between the light emitting elements (LEDa, LEDb, LEDc) (or the light emitting areas (EAa, EAb, EAc)) in each second unit light emitting area (UEA2) can be substantially the same.

[0204] For example, in one embodiment, the first unit light-emitting area (UEA1) and the second unit light-emitting area (UEA2) may be arranged alternately along the first direction (DR1) and the second direction (DR2). However, the present invention is not necessarily limited thereto, and the number of different unit light-emitting areas or the arrangement relationship between the unit light-emitting areas may vary depending on the embodiments.

[0205] In one embodiment, the pixel circuit block (PCB'') may include a plurality of pixel driving circuit units. For example, the pixel circuit block (PCB'') may include four first pixel driving circuit units (PCa), four second pixel driving circuit units (PCb), and four third pixel driving circuit units (PCc). However, the present invention is not limited thereto, and the number of pixel driving circuit units included in the pixel circuit block (PCB'') may vary.

[0206] In one embodiment, the switching circuit (SPC) may correspond to the switching circuit (SPC) illustrated in FIG. 6. That is, the switching circuit (SPC) may have the same circuit structure as the switching circuit (SPC) illustrated in FIG. 6 and may include the same components.

[0207] In one embodiment, a switching circuit (SPC) may be electrically connected to a first power voltage line (PVL_H) that transmits a high-level first power voltage (e.g., ELVSS_H in FIG. 6), a second power voltage line (PVL_L) that transmits a low-level second power voltage (e.g., ELVSS_L in FIG. 6), a gate line (GL) that transmits a gate signal (e.g., GS in FIG. 6), and a second data line (DL_S) that transmits a second data voltage (e.g., DATA2 in FIG. 6).

[0208] In one embodiment, the switching circuitry (SPC) can be electrically connected to the pixel driving circuitry (PCa, PCb, PCc) (i.e., the pixel circuit block (PCB'')) through an output power connection line (PV_CL) that selectively provides the first power voltage of the high level or the first power voltage of the low level.

[0209] In one embodiment, the separator (SPR) may include an organic insulating material. The separator (SPR) may include a photosensitive resin (e.g., photoresist). However, the present invention is not necessarily limited thereto.

[0210] In one embodiment, the separator (SPR) may have a mesh structure surrounding the pixel circuit blocks (PCB'') and the switching circuit unit (SPC) on a plane. Specifically, the separator (SPR) may be disposed between adjacent pixel circuit blocks (PCB''), and between the switching circuit unit (SPC) and the pixel circuit block (PCB'') adjacent to the switching circuit unit (SPC) in the first direction (DR1).

[0211] In one embodiment, the second electrode layer of the light emitting elements (LEDa, LEDb, LEDc) may be separated (or disconnected) by a separator (SPR). Accordingly, the second electrode layer may be separated (or disconnected) into a plurality of unit electrodes (E2_U) spaced apart from each other by the separator (SPR). The unit electrodes (E2_U) may be respectively disposed on the pixel circuit blocks (PCB''). That is, one unit electrode (E2_U) may be disposed on one pixel circuit block (PCB''). The unit electrodes (E2_U) may be electrically independent of each other.

[0212] In one embodiment, the separator (SPR) may define an open area (OA) corresponding to each of the unit electrodes (E2_U). The unit electrodes (E2_U) may be respectively positioned in the open area (OA). For example, the planar shape of each of the unit electrodes (E2_U) may be substantially identical to the planar shape of the open area (OA).

[0213] For example, in one embodiment, the output power connection wiring (PV_CL) may be connected to the switching circuit (SPC) through a first contact hole (CNT1_S), the first power voltage wiring (PVL_H) may be connected to the switching circuit (SPC) through a second contact hole (CNT2_S), the second power voltage wiring (PVL_L) may be connected to the switching circuit (SPC) through a third contact hole (CNT3_S), and the second data wiring (DL_S) may be connected to the switching circuit (SPC) through a fourth contact hole (CNT4_S).

[0214] In one embodiment, the connection patterns (CNP) may be arranged to correspond to each pixel circuit block (PCB'') and switching circuit unit (SPC) on the plane. In one embodiment, the output power connection wiring (PV_CL) may be connected to the first to third light-emitting elements (LEDa, LEDb, LEDc) through the connection patterns (CNP).

[0215] In one embodiment, the connection patterns (CNP) may include a transparent conductive oxide. Examples of the transparent conductive oxide that can be used as the connection patterns (CNP) include indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), zinc oxide (ZnO), indium oxide (InO), tin oxide (SnO), gallium oxide (GaO), aluminum zinc oxide (AZO), and the like. These may be used alone or in combination with each other.

[0216] However, the present invention is not necessarily limited thereto, and the connecting patterns (CNP) may include conductive materials such as metals, alloys, and conductive metal nitrides. Examples of the conductive materials that can be used as the connecting patterns (CNP) include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), an alloy containing aluminum (Al), an alloy containing silver (Ag), an alloy containing copper (Cu), an alloy containing molybdenum (Mo), aluminum nitride (AlN), tungsten nitride (WN), titanium nitride (TiN), chromium nitride (CrN), tantalum nitride (TaN), and the like. These can be used alone or in combination with each other.

[0217] In one embodiment, the connecting patterns (CNP) may each have a single-layer structure or a multi-layer structure in which multiple conductive layers are stacked.

[0218] In one embodiment, the connection patterns (CNP) may not overlap the light-emitting areas (EAa, EAb, EAc) on the plane. That is, the connection patterns (CNP) may be spaced apart from the light-emitting areas (EAa, EAb, EAc) on the plane.

[0219] In one embodiment, in each region where one pixel circuit block (PCB'') and one switching circuit unit (SPC) are arranged, the connection patterns (CNP) may have a shape that surrounds at least a portion of the light-emitting regions (EAa, EAb, EAc) on a plane. For example, in each region where one pixel circuit block (PCB'') and one switching circuit unit (SPC) are arranged, the connection patterns (CNP) may have a closed ring shape that entirely surrounds the light-emitting regions (EAa, EAb, EAc) on a plane.

[0220] In one embodiment, in each region where a pixel circuit block (PCB'') and a switching circuit unit (SPC) are arranged, an output power connection wiring (PV_CL) can be connected to a unit electrode (E2_U) of a light-emitting element (LEDa, LEDb, LEDc) through a connection pattern (CNP). For example, the connection pattern (CNP) can contact the output power connection wiring (PV_CL) and the unit electrode (E2_U) of the light-emitting element (LEDa, LEDb, LEDc). Accordingly, the output power connection wiring (PV_CL) can be electrically connected to the pixel circuit block (PCB''). As a result, the switching circuit unit (SPC) can be electrically connected to the pixel circuit block (PCB'') through the output power connection wiring (PV_CL).

[0221] In one embodiment, the output power connection wiring (PV_CL) may include a light-emitting connection portion (CN_P) that contacts the connection pattern (CNP). In one embodiment, there may be at least one light-emitting connection portion (CN_P) per pixel circuit block (PCB'') (i.e., the unit electrode (E2_U)). For example, as illustrated in FIGS. 7 and 8, there may be four light-emitting connection portions (CN_P) per pixel circuit block (PCB'') (i.e., the unit electrode (E2_U)). However, the present invention is not necessarily limited thereto.

[0222] For example, in one embodiment, the positions of the light-emitting connectors (CN_P) for each pixel circuit block (PCB'') (i.e., unit electrodes (E2_U)) may be substantially the same. However, the present invention is not necessarily limited thereto.

[0223] In one embodiment, in each area where a pixel circuit block (PCB'') is arranged, a planar profile of an area where a unit electrode (E2_U) and a connection pattern (CNP) are in contact (e.g., a contact area (CA) of FIGS. 9 and 10) may be substantially the same as or similar to a planar profile of an edge of the connection pattern (CNP). For example, when the connection pattern (CNP) has a closed ring shape that entirely surrounds the pixel circuit block (PCB'') on a plane, an area where the unit electrode (E2_U) and the connection pattern (CNP) are in contact may have a closed ring shape on a plane.

[0224] In one embodiment, the separator (SPR) may overlap the connection patterns (CNP) on a plane. Specifically, the separator (SPR) may cover a portion of the connection patterns (CNP) and be disposed between adjacent connection patterns (CNP). That is, at least a portion of the separator (SPR) may extend along the edge of each of the connection patterns (CNP) on a plane. Accordingly, the areas where the unit electrodes (E2_U) and the connection patterns (CNP) come into contact (e.g., the contact areas (CA) of FIGS. 9 and 10) may partially overlap the areas where the separator (SPR) is disposed on a plane.

[0225] FIG. 9 is a cross-sectional view showing an example of a cross-section taken along line II' of FIG. 8 according to one embodiment. FIG. 10 is a cross-sectional view showing an example of a cross-section taken along line II' of FIG. 8 according to one embodiment.

[0226] For example, Fig. 9 is a cross-sectional view showing the cross-sectional structure of one embodiment of a display device (DD) centered on the first light-emitting area (EAa). The following description regarding the cross-sectional structure of the display device (DD) can be equally applied to all light-emitting areas.

[0227] In the following, any content that overlaps with the content described with reference to Fig. 8 is omitted or simplified.

[0228] In one embodiment, referring to FIGS. 9 and 10, the display device (DD) may include a substrate (SUB), a transistor (TR), a first capacitor (CAP1), a second capacitor (CAP2), first to sixth insulating layers (IL1, IL2, IL3, IL4, IL5, IL6), an output power connection wiring (PV_CL), a connection pattern (CNP), a pixel defining film (PDL), a first light-emitting element (LEDa), a separator (SPR), a first dummy layer (DP1), a second dummy layer (DP2), and an encapsulation layer (ENC) sequentially arranged in a third direction (DR3). For example, the third direction (DR3) may be oriented perpendicular to a plane defined by the first direction (DR1) and the second direction (DR2) of FIGS. 1A and 1B.

[0229] Here, in one embodiment, the substrate (SUB), the transistor (TR), the first capacitor (CAP1) and the second capacitor (CAP2) and the insulating layers (IL1, IL2, IL3, IL4, IL5, IL6) may be components of the first pixel driving circuit unit (PCa).

[0230] In one embodiment, the transistor (TR) may include an active pattern (AP), a gate electrode (GE), a first contact electrode (SE), and a second contact electrode (DE). The first capacitor (CAP1) may include a first capacitor electrode (CPE1) and a second capacitor electrode (CPE2). The second capacitor (CAP2) may include a second capacitor electrode (CPE2) and a third capacitor electrode (CPE3). The first light-emitting element (LEDa) may include a first electrode (E1), an emission layer (EML), an intermediate layer (ML), and a unit electrode (E2_U).

[0231] In one embodiment, the transistor (TR), the first capacitor (CAP1), and the second capacitor (CAP2) may be components included in the first pixel driving circuit (PCa). For example, the transistor (TR) may correspond to the sixth transistor (T6) or the seventh transistor (T7) of FIG. 6, the second capacitor (CAP2) may correspond to the first capacitor (C1) of FIG. 6, and the first capacitor (CAP1) may correspond to the second capacitor (C2) of FIG. 6.

[0232] In one embodiment, a first capacitor electrode (CPE1) and a lower conductive layer (BML) may be disposed on a substrate (SUB). For example, the first capacitor electrode (CPE1) and the lower conductive layer (BML) may include a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a transparent conductive oxide, or the like. These may be used alone or in combination with each other. The first capacitor electrode (CPE1) and the lower conductive layer (BML) may include the same material and may be disposed on the same layer.

[0233] In one embodiment, a first insulating layer (IL1) may be disposed on a substrate (SUB) to cover a first capacitor electrode (CPE1) and a lower conductive layer (BML). The first insulating layer (IL1) may prevent metal atoms or impurities from diffusing from the substrate (SUB) to the transistor (TR). For example, the first insulating layer (IL1) may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or the like. These may be used alone or in combination with each other.

[0234] In one embodiment, the active pattern (AP) may be disposed on the first insulating layer (IL1). In one embodiment, the active pattern (AP) may overlap the lower conductive layer (BML) on a plane. The active pattern (AP) may include a metal oxide semiconductor, a silicon semiconductor, and / or an organic semiconductor. The active pattern (AP) may include a first contact region (SR), a second contact region (DR), and a channel region (CH) between the first contact region (SR) and the second contact region (DR). The first contact region (SR) and the second contact region (DR) may have higher conductivity than the channel region (CH).

[0235] In one embodiment, the active pattern (AP) may include a silicon semiconductor, such as polysilicon. However, the present invention is not necessarily limited thereto.

[0236] In one embodiment, a second insulating layer (IL2) may be disposed on the first insulating layer (IL1) to cover the active pattern (AP). For example, the second insulating layer (IL2) may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or the like. These may be used alone or in combination with each other.

[0237] In one embodiment, the gate electrode (GE) may be disposed on the second insulating layer (IL2). The gate electrode (GE) may overlap the channel region (CH) of the active pattern (AP). For example, the gate electrode (GE) may include a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a transparent conductive oxide, or the like. These may be used alone or in combination with each other.

[0238] For example, in one embodiment, the gate electrode (GE) may be in contact with the lower conductive layer (BML). In this case, the first contact electrode (SE) may not be in contact with the lower conductive layer (BML).

[0239] In one embodiment, the second capacitor electrode (CPE2) may be disposed on the second insulating layer (IL2). The first capacitor electrode (CPE1) may overlap the second capacitor electrode (CPE2) on a plane. The first capacitor electrode (CPE1) and the second capacitor electrode (CPE2) may form the first capacitor (CAP1). For example, the second capacitor electrode (CPE2) may include a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a transparent conductive oxide, or the like. These may be used alone or in combination with each other.

[0240] In one embodiment, the gate electrode (GE) and the second capacitor electrode (CPE2) may comprise the same material and be arranged in the same layer.

[0241] In one embodiment, a third insulating layer (IL3) may be disposed on the second insulating layer (IL2) to cover the gate electrode (GE) and the second capacitor electrode (CPE2). For example, the third insulating layer (IL3) may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or the like. These may be used alone or in combination with each other.

[0242] In one embodiment, the third capacitor electrode (CPE3) may be disposed on the third insulating layer (IL3). The third capacitor electrode (CPE3) may overlap the second capacitor electrode (CPE2). The second capacitor electrode (CPE2) and the third capacitor electrode (CPE3) may form a second capacitor (CAP2). For example, the third capacitor electrode (CPE3) may include a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a transparent conductive oxide, or the like. These may be used alone or in combination with each other.

[0243] In one embodiment, a fourth insulating layer (IL4) may be disposed on the third insulating layer (IL3) to cover the third capacitor electrode (CPE3). For example, the fourth insulating layer (IL4) may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or the like. These may be used alone or in combination with each other.

[0244] In one embodiment, the contact electrodes (SE, DE) may be disposed on the fourth insulating layer (IL4). The first contact electrode (SE) may be in contact with the first contact region (SR) of the active pattern (AP), and the second contact electrode (DE) may be in contact with the second contact region (DR) of the active pattern (AP). For example, the contact electrodes (SE, DE) may include a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a transparent conductive oxide, or the like. These may be used alone or in combination with each other. The contact electrodes (SE, DE) may include the same material and may be disposed on the same layer.

[0245] In one embodiment, the first contact electrode (SE) may be in contact with the lower conductive layer (BML). However, the present invention is not necessarily limited thereto. For example, when the gate electrode (GE) is in contact with the lower conductive layer (BML), the first contact electrode (SE) may not be in contact with the lower conductive layer (BML).

[0246] In one embodiment, a fifth insulating layer (IL5) may be disposed on the fourth insulating layer (IL4) to cover the contact electrodes (SE, DE). For example, the fifth insulating layer (IL5) may include an organic insulating material. Examples of the organic insulating material that may be used as the fifth insulating layer (IL5) may include a photoresist, a polyacryl-based resin, a polyimide-based resin, a polyamide-based resin, a siloxane-based resin, an acrylic resin, an epoxy-based resin, and the like. These may be used alone or in combination with each other.

[0247] In one embodiment, as illustrated in FIG. 9, the output power connection wiring (PV_CL) may be disposed on the fifth insulating layer (IL5). In this case, the output power connection wiring (PV_CL) may be in direct contact with the connection pattern (CNP). The output power connection wiring (PV_CL) may include a light-emitting connection portion (CN_P) that is in contact with the connection pattern (CNP).

[0248] In another embodiment, as illustrated in FIG. 10, the output connection wiring (PV_CL) may be disposed on the same layer as the lower conductive layer (BML). In this case, the output connection wiring (PV_CL) may be connected to the connection pattern (CNP) through the pixel connection pattern (PCP) and the auxiliary wiring (AL). The pixel connection pattern (PCP) may be disposed on the same layer as the contact electrodes (SE, DE), and the auxiliary wiring (AL) may be disposed on the fifth insulating layer (IL5). The auxiliary wiring (AL) may be in direct contact with the connection pattern (CNP). In addition, the auxiliary wiring (AL) may include a light-emitting connection portion (CN_P) that is in contact with the connection pattern (CNP).

[0249] In one embodiment, the sixth insulating layer (IL6) may be disposed on the fifth insulating layer (IL5) and partially cover the output power connection wiring (PV_CL) of FIG. 9 or the auxiliary wiring (AL) of FIG. 10. The sixth insulating layer (IL6) may define a first sub-opening (SO1) that exposes at least a portion of the output power connection wiring (PV_CL) of FIG. 9 or the auxiliary wiring (AL) of FIG. 10. For example, the sixth insulating layer (IL6) may include an organic insulating material. Examples of the organic insulating material that may be used as the sixth insulating layer (IL6) may include a photoresist, a polyacryl-based resin, a polyimide-based resin, a polyamide-based resin, a siloxane-based resin, an acrylic resin, an epoxy-based resin, and the like. These can be used alone or in combination with each other.

[0250] In this specification, the insulating layers (IL1, IL2, IL3, IL4) may each be referred to as inorganic insulating layers, and the insulating layers (IL5, IL6) may each be referred to as organic insulating layers.

[0251] In one embodiment, a first electrode (E1) may be disposed on the sixth insulating layer (IL6). The first electrode (E1) may overlap the first light-emitting area (EAa). For example, the first electrode (E1) may include a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a transparent conductive oxide, or the like. These may be used alone or in combination with each other.

[0252] In one embodiment, a pixel defining layer (PDL) may be disposed on the sixth insulating layer (IL6) and the first electrode (E1). The pixel defining layer (PDL) may define a pixel opening that exposes at least a portion of the first electrode (E1). A first light-emitting area (EAa) may be defined by the pixel opening. For example, the pixel defining layer (PDL) may include an organic insulating material or an inorganic insulating material.

[0253] In one embodiment, the pixel defining layer (PDL) can further define a second sub-aperture (SO2) corresponding to the first sub-aperture (SO1) of the sixth insulating layer (IL6). The second sub-aperture (SO2) can overlap the first sub-aperture (SO1) on a plane, and the first sub-aperture (SO1) and the second sub-aperture (SO2) can be spatially connected to each other. That is, an opening (OP) in which the first sub-aperture (SO1) and the second sub-aperture (SO2) are connected can be defined, and the opening (OP) can expose at least a part of the output power connection wiring (PV_CL) of FIG. 9 or the auxiliary wiring (AL) of FIG. 10.

[0254] In one embodiment, the connection pattern (CNP) may be disposed on the sixth insulating layer (IL6) and the pixel defining layer (PDL). The connection pattern (CNP) may contact the output power connection line (PV_CL) of FIG. 9 or the auxiliary line (AL) of FIG. 10 through the opening (OP) of the sixth insulating layer (IL6) and the pixel defining layer (PDL). Accordingly, the light-emitting connection part (CN_P) may be exposed by the opening (OP).

[0255] In one embodiment, a separator (SPR) may be disposed on a pixel defining layer (PDL) and a connection pattern (CNP). The separator (SPR) may overlap the connection pattern (CNP) in a plane. For example, the separator (SPR) may cover a portion of the connection pattern (CNP).

[0256] In one embodiment, the separator (SPR) may have a shape in which the width of the upper portion is greater than the width of the lower portion. That is, the side surface of the separator (SPR) connecting the upper surface of the separator (SPR) and the lower surface of the separator (SPR) may have a reverse tapered slope. That is, the cross-section of at least a portion of the separator (SPR) may be an inverse trapezoid.

[0257] In one embodiment, the side surface of the separator (SPR) may have a plurality of reverse tapered slopes. That is, the separator (SPR) may have a double reverse tapered structure. Accordingly, the separation (or disconnection) of the second electrode layer by the separator (SPR) may be more easily implemented.

[0258] In one embodiment, an emission layer (EML) may be disposed on the first electrode (E1). Specifically, the emission layer (EML) may be disposed within the pixel opening. For example, the emission layer (EML) may include a luminescent material that generates light of a specific color (e.g., red, green, or blue).

[0259] In one embodiment, the intermediate layer (ML) may be disposed on the first electrode (E1), the pixel defining layer (PDL), and the connection pattern (CNP). Specifically, the intermediate layer (ML) may be disposed in the open area (OA) of the separator (SPR). For example, the intermediate layer (ML) may include a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, etc.

[0260] In one embodiment, a shadow region may exist around a separator (SPR) having a reverse tapered slope, where it is difficult to deposit an intermediate layer (ML). Accordingly, the intermediate layer (ML) in the shadow region and / or around the shadow region may have a structure separated (or disconnected) by the separator (SPR).

[0261] Since the intermediate layer (ML) has a separated (or disconnected) structure, the intermediate layer (ML) may not entirely cover the connection pattern (CNP). That is, the intermediate layer (ML) may expose at least a portion of the connection pattern (CNP) at a position adjacent to or overlapping the separator (SPR). Accordingly, the unit electrode (E2_U) of the first light-emitting element (LEDa) may come into contact with the connection pattern (CNP).

[0262] In one embodiment, a first dummy layer (DP1) may be disposed on a separator (SPR). The first dummy layer (DP1) may be formed by having a structure in which the intermediate layer (ML) is separated (or disconnected) by the separator (SPR). That is, the first dummy layer (DP1) may be formed through the same process as the intermediate layer (ML). In another embodiment, the first dummy layer (DP1) may be omitted.

[0263] In one embodiment, the unit electrode (E2_U) may be disposed on the intermediate layer (ML). For example, the unit electrode (E2_U) may include a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a transparent conductive oxide, or the like. These may be used alone or in combination with each other.

[0264] In one embodiment, the unit electrode (E2_U) may have a single-layer structure. However, the present invention is not necessarily limited thereto, and the unit electrode (E2_U) may have a multi-layer structure in which a plurality of conductive layers are laminated. For example, the unit electrode (E2_U) may have a two-layer structure in which a first sub-electrode layer including a metal material and a second sub-electrode layer disposed on the first sub-electrode layer and including a transparent conductive oxide are laminated.

[0265] In one embodiment, a shadow region where the second electrode layer is difficult to be deposited may exist around a separator (SPR) having a reverse tapered slope. Accordingly, the second electrode layer may have a structure in which it is separated (or disconnected) by the separator (SPR) in the shadow region and / or around the shadow region. For example, the second electrode layer may be separated (or disconnected) by the unit electrodes (E2_U) of the first to third light-emitting elements (LEDa, LEDb, LEDc) of FIGS. 7 and 8, which are respectively disposed in the open regions (OA) of the separator (SPR). That is, the unit electrodes (E2_U) may be electrically independent of each other.

[0266] In one embodiment, the unit electrode (E2_U) of the first light-emitting element (LEDa) can be in contact with the connection pattern (CNP). Specifically, the unit electrode (E2_U) can be in contact with the connection pattern (CNP) at a position adjacent to or overlapping the separator (SPR). A contact area (CA) where the unit electrode (E2_U) of the first light-emitting element (LEDa) is in contact with the connection pattern (CNP) can overlap with an edge of the separator (SPR) on a plane.

[0267] For example, in one embodiment, when the deposition angle of the deposition process for forming the second electrode layer is greater than the deposition angle of the deposition process for forming the intermediate layer (ML), the unit electrode (E2_U) can be formed to cover the side of the disconnected intermediate layer (ML) and contact the connection pattern (CNP). As a result, the unit electrode (E2_U) can be connected to the output power connection wiring (PV_CL) through the connection pattern (CNP).

[0268] In one embodiment, a second dummy layer (DP2) may be disposed on the separator (SPR). Specifically, the second dummy layer (DP2) may be disposed on the first dummy layer (DP1). The second dummy layer (DP2) may be formed by having a structure in which the unit electrodes (E2_U) are separated (or disconnected) by the separator (SPR). That is, the second dummy layer (DP2) may be formed through the same process as the unit electrodes (E2_U). In another embodiment, the second dummy layer (DP2) may be omitted.

[0269] In one embodiment, the encapsulation layer (ENC) may be disposed on the unit electrode (E2_U). The encapsulation layer (ENC) may entirely cover the unit electrode (E2_U), the connection pattern (CNP), the separator (SPR), the first dummy layer (DP1), and the second dummy layer (DP2). In one embodiment, the encapsulation layer (ENC) may include a first inorganic encapsulation layer (IEL1) including an inorganic insulating material, an organic encapsulation layer (OEL) disposed on the first inorganic encapsulation layer (IEL1) and including an organic insulating material, and a second inorganic encapsulation layer (IEL2) disposed on the organic encapsulation layer (OEL) and including an inorganic insulating material.

[0270] Fig. 11 is an enlarged plan view of a pixel circuit block, light-emitting elements connected to the pixel circuit block, and a switching circuit unit of Fig. 7 according to one embodiment. Fig. 12 is a cross-sectional view taken along line II-II' of Fig. 11 according to one embodiment.

[0271] In one embodiment, the display device (DD) described with reference to FIGS. 7, 11, and 12 may be substantially the same as or similar to the display device (DD) described with reference to FIGS. 7 to 10, except for the output power connection wiring (PV_CL') and the light-emitting connection portion (CN_P'). Hereinafter, overlapping descriptions are omitted or simplified.

[0272] First, in one embodiment, referring to FIGS. 7 and 11, the display device (DD) may include pixel driving circuits (PCa, PCb, PCc), light emitting elements (LEDa', LEDb', LEDc'), a switching circuit (SPC), and a separator (SPR') arranged in a display area (DA).

[0273] In one embodiment, the light-emitting elements (LEDa', LEDb', LEDc') may each include a first electrode (e.g., the first electrode (E1) of FIG. 12), a light-emitting layer (e.g., the light-emitting layer (EML') of FIG. 12) disposed on the first electrode, an intermediate layer (e.g., the intermediate layer (ML') of FIG. 12) disposed on the light-emitting layer, and a second electrode layer disposed on the intermediate layer. In one embodiment, the first electrode may be an anode electrode, and the second electrode layer may be a cathode electrode.

[0274] In one embodiment, the separator (SPR') may have a mesh structure surrounding the pixel circuit blocks (PCB'') and the switching circuit (SPC) on a plane.

[0275] In one embodiment, the second electrode layer of the light emitting elements (LEDa', LEDb', LEDc') may be separated (or disconnected) by a separator (SPR'). Accordingly, the second electrode layer may be separated (or disconnected) into a plurality of unit electrodes (E2_U') that are spaced apart from each other by the separator (SPR'). The unit electrodes (E2_U') may be respectively disposed on pixel circuit blocks (PCB''). That is, one unit electrode (E2_U') may be disposed on one pixel circuit block (PCB'').

[0276] In one embodiment, the separator (SPR') may define an open area (OA) corresponding to each of the unit electrodes (E2_U'). The unit electrodes (E2_U') may be respectively disposed in the open area (OA). For example, the planar shape of each of the unit electrodes (E2_U') may be substantially identical to the planar shape of the open area (OA).

[0277] For example, in one embodiment, the output power connection wiring (PV_CL') may be connected to the switching circuit (SPC) through a first contact hole (CNT1_S), the first power voltage wiring (PVL_H) may be connected to the switching circuit (SPC) through a second contact hole (CNT2_S), the second power voltage wiring (PVL_L) may be connected to the switching circuit (SPC) through a third contact hole (CNT3_S), and the second data wiring (DL_S) may be connected to the switching circuit (SPC) through a fourth contact hole (CNT4_S).

[0278] In one embodiment, in each area where a pixel circuit block (PCB'') is arranged, an output power connection wiring (PV_CL') may be connected to a unit electrode (E2_U') of a light-emitting element (LEDa', LEDb', LEDc'). In one embodiment, the output power connection wiring (PV_CL') may be in direct contact with the unit electrode (E2_U'). Accordingly, the output power connection wiring (PV_CL') may be electrically connected to the pixel circuit block (PCB'').

[0279] In one embodiment, the output power connection wiring (PV_CL') may include a light-emitting connection portion (CN_P') that contacts the unit electrode (E2_U'). In one embodiment, there may be at least one light-emitting connection portion (CN_P') per pixel circuit block (PCB') (i.e., per unit electrode (E2_U')). For example, as illustrated in FIG. 11, there may be four light-emitting connection portions (CN_P') per pixel circuit block (PCB') (i.e., per unit electrode (E2_U'). However, the present invention is not necessarily limited thereto.

[0280] For example, the positions of the light-emitting connectors (CN_P') for each pixel circuit block (PCB'') (i.e., unit electrodes (E2_U')) may be substantially the same. However, the present invention is not necessarily limited thereto.

[0281] Hereinafter, the cross-sectional structure of the display device (DD) will be described in more detail with reference to FIG. 12, focusing on the first light-emitting area (EAa). The following description of the cross-sectional structure of the display device (DD) can be equally applied to all light-emitting areas. In addition, any description that overlaps with the description made with reference to FIGS. 9 and 10 will be omitted or simplified.

[0282] In one embodiment, referring further to FIG. 12, the display device (DD) may include a substrate (SUB), a transistor (TR), a first capacitor (CAP1), a second capacitor (CAP2), first to sixth insulating layers (IL1, IL2, IL3, IL4, IL5, IL6), an output power connection wiring (PV_CL'), a pixel defining film (PDL), a first light-emitting element (LEDa'), a separator (SPR'), a first dummy layer (DP1'), a second dummy layer (DP2'), and an encapsulation layer (ENC) sequentially arranged in a third direction (DR3).

[0283] In one embodiment, the substrate (SUB), the transistor (TR), the first capacitor (CAP1) and the second capacitor (CAP2), and the insulating layers (IL1, IL2, IL3, IL4, IL5, IL6) may be components of the first pixel driving circuit unit (PCa).

[0284] In one embodiment, the output power connection wiring (PV_CL') may be disposed on the fifth insulating layer (IL5). For example, the output power connection wiring (PV_CL') may include a first conductive layer (CL1), a second conductive layer (CL2), and a third conductive layer (CL3) sequentially laminated.

[0285] In one embodiment, the first conductive layer (CL1) may include a metal and / or a transparent conductive oxide. Examples of the metal that can be used as the first conductive layer (CL1) may include titanium (Ti), molybdenum (Mo), etc. Examples of the transparent conductive oxide that can be used as the first conductive layer (CL1) may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (InO), indium gallium oxide (IGO), aluminum zinc oxide (AZO), etc. Each of these may be used alone or in combination with each other. The first conductive layer (CL1) may have a relatively thin thickness compared to the second conductive layer (CL2).

[0286] In one embodiment, the second conductive layer (CL2) may include a different material from the first conductive layer (CL1). For example, the second conductive layer (CL2) may include a different metal from the first conductive layer (CL1). Examples of the metal that may be used as the second conductive layer (CL2) include aluminum (Al), copper (Cu), etc. These may be used alone or in combination. The second conductive layer (CL2) may have a relatively thicker thickness than the first conductive layer (CL1).

[0287] In one embodiment, the third conductive layer (CL3) may include a different material from the second conductive layer (CL2). For example, the third conductive layer (CL3) may include a different metal and / or transparent conductive oxide from the second conductive layer (CL2). Examples of the metal that can be used as the third conductive layer (CL3) may include titanium (Ti), molybdenum (Mo), etc. Examples of the transparent conductive oxide that can be used as the third conductive layer (CL3) may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (InO), indium gallium oxide (IGO), aluminum zinc oxide (AZO), etc. Each of these may be used alone or in combination with each other. The third conductive layer (CL3) may have a relatively thin thickness compared to the second conductive layer (CL2).

[0288] In one embodiment, the first conductive layer (CL1) and the third conductive layer (CL3) may comprise the same material. However, the present invention is not necessarily limited thereto.

[0289] In one embodiment, the side surface (CL1-S) of the first conductive layer (CL1) and the side surface (CL3-S) of the third conductive layer (CL3) may protrude outwardly relative to the side surface (CL2-S) of the second conductive layer (CL2). Accordingly, the output power connection wiring (PV_CL') may have a tip structure due to the protruding portion of the third conductive layer (CL3) compared to the second conductive layer (CL2). For example, when the second conductive layer (CL2) is etched using an etching material having a higher etching rate for the second conductive layer (CL2) than for the first conductive layer (CL1) and the third conductive layer (CL3) based on the same etching process, the output power connection wiring (PV_CL') may be formed to have the tip structure.

[0290] However, the present invention is not necessarily limited thereto, and in another embodiment, the output power connection wiring (PV_CL') may have a two-layer structure in which the first conductive layer (CL1) is omitted and the second conductive layer (CL2) and the third conductive layer (CL3) are laminated.

[0291] In one embodiment, unlike as illustrated in FIG. 12, the output power connection wiring (PV_CL') may also contact the unit electrode (E2_U') via a pixel connection pattern and auxiliary wiring, as illustrated in FIG. 10. In this case, the auxiliary wiring may have a three-layer structure including three sequentially stacked conductive layers and may have a tip structure.

[0292] In one embodiment, the sixth insulating layer (IL6) can define a first sub-opening (SO1') that exposes at least a portion of the output power connection wiring (PV_CL'). Specifically, the first sub-opening (SO1') can expose the tip structure (i.e., the first to third side surfaces (CL1-S, CL2-S, CL3-S)) of the output power connection wiring (PV_CL').

[0293] In one embodiment, the pixel defining layer (PDL) can further define a second sub-aperture (SO2') corresponding to the first sub-aperture (SO1') of the sixth insulating layer (IL6). The second sub-aperture (SO2') can overlap the first sub-aperture (SO1') on a plane, and the first sub-aperture (SO1') and the second sub-aperture (SO2') can be spatially connected to each other. That is, an opening (OP') to which the first sub-aperture (SO1') and the second sub-aperture (SO2') are connected can be defined, and the opening (OP') can expose at least a part of the output power connection wiring (PV_CL'). Specifically, the opening (OP') can expose the tip structure (i.e., the first to third side surfaces (CL1-S, CL2-S, CL3-S)) of the output power connection wiring (PV_CL').

[0294] In one embodiment, the separator (SPR') may be disposed on the pixel defining layer (PDL). The separator (SPR') may have a shape in which the width of the upper portion is greater than the width of the lower portion. That is, the side surface of the separator (SPR') connecting the upper surface of the separator (SPR') and the lower surface of the separator (SPR') may have a reverse tapered slope. That is, the cross section of the separator (SPR') may be an inverse trapezoid.

[0295] For example, as illustrated in Fig. 12, the side surface of the separator (SPR') may have a single reverse tapered slope. However, the present invention is not necessarily limited thereto, and the side surface of the separator (SPR') may have a plurality of reverse tapered slopes. That is, the separator (SPR') may have a double reverse tapered structure.

[0296] In one embodiment, a first dummy layer (DP1') may be disposed on a separator (SPR'). The first dummy layer (DP1') may be formed by having a structure in which the intermediate layer (ML') is separated (or disconnected) by the separator (SPR').

[0297] In one embodiment, the intermediate layer (ML') may also be separated (or disconnected) by the tip structure of the output power connection wiring (PV_CL'). As the intermediate layer (ML') is separated (or disconnected) by the tip structure of the output power connection wiring (PV_CL'), the intermediate layer (ML') may expose at least a portion of the side surface (CL2-S) of the second conductive layer (CL2). Accordingly, the unit electrode (E2_U') of the first light-emitting element (LEDa') may be brought into contact with the side surface (CL2-S) of the second conductive layer (CL2) and the side surface (CL3-S) of the third conductive layer (CL3).

[0298] In one embodiment, the unit electrode (E2_U') of the first light-emitting element (LEDa') may be connected to the output power connection wiring (PV_CL'). Specifically, the unit electrode (E2_U') may be in contact with the side surface (CL2-S) of the second conductive layer (CL2). For example, when the deposition angle of the deposition process for forming the second electrode layer is greater than the deposition angle of the deposition process for forming the intermediate layer (ML'), the unit electrode (E2_U') may be formed to be in contact with the side surface (CL2-S) of the second conductive layer (CL2) while covering the intermediate layer (ML') disconnected by the tip structure. As a result, the unit electrode (E2_U') may be in contact with the output power connection wiring (PV_CL') by the tip structure of the output power connection wiring (PV_CL').

[0299] In one embodiment, the second electrode layer may be separated (or disconnected) by the tip structure of the output power connection wiring (PV_CL'). However, the present invention is not necessarily limited thereto, and the second electrode layer may be formed to extend without being disconnected by the tip structure.

[0300] In one embodiment, a second dummy layer (DP2') may be disposed on a separator (SPR'). Specifically, the second dummy layer (DP2') may be disposed on a first dummy layer (DP1'). The second dummy layer (DP2') may be formed by having a structure in which the second electrode layer is separated (or disconnected) by the separator (SPR').

[0301] Fig. 13 is an enlarged plan view of a pixel circuit block, light-emitting elements connected to the pixel circuit block, and a switching circuit unit of Fig. 7 according to one embodiment. Fig. 14 is a cross-sectional view showing an example of a cross-section taken along line III-III' of Fig. 13 according to one embodiment. Fig. 15 is a cross-sectional view showing an example of a cross-section taken along line III-III' of Fig. 13 according to one embodiment.

[0302] In one embodiment, the display device (DD) described with reference to FIGS. 7, 13, 14, and 15 may be substantially the same as or similar to the display device (DD) described with reference to FIGS. 11 and 12, except for the engraved pattern (EP). Hereinafter, overlapping descriptions are omitted or simplified.

[0303] First, in one embodiment, referring to FIGS. 7 and 13, the display device (DD) may include pixel driving circuits (PCa, PCb, PCc), light-emitting elements (LEDa', LEDb', LEDc'), a switching circuit (SPC), and an engraved pattern (EP) arranged in a display area (DA).

[0304] In one embodiment, the engraved pattern (EP) may have a mesh structure surrounding the pixel circuit blocks (PCB'') and the switching circuit unit (SPC) on a plane. Specifically, the engraved pattern (EP) may be arranged between adjacent pixel circuit blocks (PCB''), and between the switching circuit unit (SPC) and the pixel circuit block (PCB'') adjacent to the switching circuit unit (SPC) in the first direction (DR1). However, the present invention is not limited thereto, and the engraved pattern (EP) may also have a mesh structure surrounding the light-emitting areas (EAa, EAb, EAc) on a plane.

[0305] In one embodiment, the negative pattern (EP) can be formed by removing a portion of a pixel defining layer (e.g., the pixel defining layer (PDL) of FIG. 15).

[0306] In one embodiment, the second electrode layer of the light emitting elements (LEDa', LEDb', LEDc') may be separated (or disconnected) by an engraved pattern (EP). Accordingly, the second electrode layer may be separated (or disconnected) into a plurality of unit electrodes (E2_U') that are spaced apart from each other by the engraved pattern (EP). The unit electrodes (E2_U) may be respectively disposed on the pixel circuit blocks (PCB''). That is, one unit electrode (E2_U) may be disposed on one pixel circuit block (PCB''). The unit electrodes (E2_U) may be electrically independent of each other.

[0307] For example, in one embodiment, the output power connection wiring (PV_CL') may be connected to the switching circuit (SPC) through a first contact hole (CNT1_S), the first power voltage wiring (PVL_H) may be connected to the switching circuit (SPC) through a second contact hole (CNT2_S), the second power voltage wiring (PVL_L) may be connected to the switching circuit (SPC) through a third contact hole (CNT3_S), and the second data wiring (DL_S) may be connected to the switching circuit (SPC) through a fourth contact hole (CNT4_S).

[0308] In one embodiment, in each area where a pixel circuit block (PCB'') is arranged, an output power connection wiring (PV_CL') may be connected to the unit electrode (E2_U') of the first to third light-emitting elements (LEDa', LEDb', LEDc'). In one embodiment, the output power connection wiring (PV_CL') may be in direct contact with the unit electrode (E2_U'). Accordingly, the output power connection wiring (PV_CL') may be electrically connected to the pixel circuit block (PCB'').

[0309] In one embodiment, the output power connection wiring (PV_CL') may include a light-emitting connection portion (CN_P') that contacts the unit electrode (E2_U'). In one embodiment, there may be at least one light-emitting connection portion (CN_P') per pixel circuit block (PCB') (i.e., per unit electrode (E2_U')). For example, as illustrated in FIG. 13, there may be four light-emitting connection portions (CN_P') per pixel circuit block (PCB') (i.e., per unit electrode (E2_U'). However, the present invention is not necessarily limited thereto.

[0310] For example, in one embodiment, the positions of the light-emitting connectors (CN_P') for each of the pixel circuit blocks (PCB'') (i.e., the unit electrodes (E2_U')) may be substantially the same. However, the present invention is not necessarily limited thereto.

[0311] Hereinafter, the cross-sectional structure of the display device (DD) will be described in more detail with reference to FIGS. 14 and 15, focusing on the first light-emitting area (EAa). In one embodiment, the following description of the cross-sectional structure of the display device (DD) can be equally applied to all light-emitting areas. In addition, any description that overlaps with the description made with reference to FIGS. 9, 10, and 12 will be omitted or simplified.

[0312] In one embodiment, with further reference to FIGS. 14 and 15, the display device (DD) may include a substrate (SUB), a transistor (TR), a first capacitor (CAP1), a second capacitor (CAP2), insulating layers (IL1, IL2, IL3, IL4, IL5, IL6), an output power connection wiring (PV_CL'), a pixel defining layer (PDL), a first light-emitting element (LEDa'), an engraved pattern (EP), a first dummy layer (DP1''), a second dummy layer (DP2''), and an encapsulation layer (ENC) that are sequentially arranged in a third direction (DR3).

[0313] In one embodiment, the substrate (SUB), the transistor (TR), the first capacitor (CAP1) and the second capacitor (CAP2), and the insulating layers (IL1, IL2, IL3, IL4, IL5, IL6) may be components of the first pixel driving circuit unit (PCa).

[0314] In one embodiment, the output power connection wiring (PV_CL') may be disposed on the fifth insulating layer (IL5). For example, the output power connection wiring (PV_CL') may include a first conductive layer (CL1), a second conductive layer (CL2), and a third conductive layer (CL3) that are sequentially laminated. That is, the output power connection wiring (PV_CL') may be substantially the same as the output power connection wiring (PV_CL') of FIG. 12.

[0315] In one embodiment, the side surface (CL1-S) of the first conductive layer (CL1) and the side surface (CL3-S) of the third conductive layer (CL3) may protrude outwardly relative to the side surface (CL2-S) of the second conductive layer (CL2). Accordingly, the output power connection wiring (PV_CL') may have a tip structure due to the portion of the third conductive layer (CL3) that protrudes relative to the second conductive layer (CL2).

[0316] In one embodiment, unlike as illustrated in FIGS. 14 and 15, the output power connection wiring (PV_CL') may be in contact with the unit electrode (E2_U') through the pixel connection pattern and auxiliary wiring, as illustrated in FIG. 10. In this case, the auxiliary wiring may have a three-layer structure including three sequentially stacked conductive layers and may have a tip structure.

[0317] In one embodiment, the pixel defining layer (PDL) may include an engraved pattern (EP). The engraved pattern (EP) may be formed by removing a portion of the pixel defining layer (PDL). That is, the sixth insulating layer (IL6) may not be exposed by the engraved pattern (EP). The engraved pattern (EP) may replace the role of the separator (SPR, SPR') of FIGS. 7 to 12.

[0318] In one embodiment, the intermediate layer (ML') may have a structure that is separated (or disconnected) by the negative pattern (EP). A first dummy layer (DP1'') may be arranged within the negative pattern (EP). The first dummy layer (DP1'') may be formed as the intermediate layer (ML') has a structure that is separated (or disconnected) by the negative pattern (EP).

[0319] In one embodiment, the intermediate layer (ML') may also be separated (or disconnected) by the tip structure of the output power connection wiring (PV_CL'). As the intermediate layer (ML') is separated (or disconnected) by the tip structure of the output power connection wiring (PV_CL'), the intermediate layer (ML') may expose at least a portion of the side surface (CL2-S) of the second conductive layer (CL2). Accordingly, the unit electrode (E2_U') of the first light-emitting element (LEDa') may come into contact with the side surface (CL2-S) of the second conductive layer (CL2).

[0320] In one embodiment, the unit electrode (E2_U') of the first light-emitting element (LEDa') may be connected to the output power connection wiring (PV_CL'). Specifically, the unit electrode (E2_U') may be in contact with the side surface (CL2-S) of the second conductive layer (CL2).

[0321] In one embodiment, the second electrode layer may have a structure that is separated (or, disconnected) by an engraved pattern (EP). A second dummy layer (DP2'') may be arranged within the engraved pattern (EP). Specifically, the second dummy layer (DP2'') may be arranged on the first dummy layer (DP1''). The second dummy layer (DP2') may be formed because the second electrode layer has a structure that is separated (or, disconnected) by the engraved pattern (EP).

[0322] In one embodiment, the second electrode layer may be separated (or disconnected) by the tip structure of the output power connection wiring (PV_CL'). However, the present invention is not necessarily limited thereto, and the second electrode layer may be formed to extend without being disconnected by the tip structure.

[0323] In one embodiment, as illustrated in FIG. 14, the display device (DD) may further include a metal pattern (MP) disposed on a pixel defining layer (PDL), overlapping an edge of an engraved pattern (EP) on a plane, and covered by an intermediate layer (ML'). The metal pattern (MP) may have a tip structure protruding toward the engraved pattern (EP). For example, the metal pattern (MP) may include a transparent conductive oxide. In another embodiment, the metal pattern (MP) may include a conductive material such as a metal, an alloy, or a conductive metal nitride. However, the present invention is not necessarily limited thereto, and as illustrated in FIG. 15, the metal pattern (MP) may be omitted.

[0324] Fig. 16 is a plan view schematically illustrating a portion of the display area of ​​Figs. 1a and 1b according to one embodiment. Fig. 17 is an enlarged plan view of one pixel circuit block, light-emitting elements connected to one pixel circuit block, and one switching circuit unit of Fig. 16 according to one embodiment.

[0325] In one embodiment, the display device (DD) described with reference to FIGS. 16 and 17 may be substantially the same as or similar to the display device (DD) described with reference to FIGS. 7 and 8, except for the separator (SPR''). Hereinafter, overlapping descriptions are omitted or simplified.

[0326] In one embodiment, referring to FIGS. 16 and 17, the display device (DD) may include pixel driving circuits (PCa, PCb, PCc), first to third light-emitting elements (LEDa, LEDb, LEDc), connection patterns (CNPa, CNPb, CNPc), a switching circuit (SPC), and a separator (SPR'') arranged in a display area (DA).

[0327] In one embodiment, the light-emitting elements (LEDa, LEDb, LEDc) may each include a first electrode (e.g., the first electrode (E1) of FIGS. 9 and 10), a light-emitting layer (e.g., the light-emitting layer (EML') of FIGS. 9 and 10) disposed on the first electrode, an intermediate layer (e.g., the intermediate layer (ML) of FIGS. 9 and 10) disposed on the light-emitting layer, and a second electrode layer (E2) disposed on the intermediate layer. In one embodiment, the first electrode may be an anode electrode, and the second electrode layer (E2) may be a cathode electrode.

[0328] In one embodiment, the second electrode layer (E2) can be separated (or disconnected) by a separator (SPR''). Accordingly, the second electrode layer (E2) can be separated (or disconnected) into second electrodes (E2a, E2b, E2c) that are spaced apart from each other by the separator (SPR''). That is, the second electrode (E2a) of the first light-emitting element (LEDa), the second electrode (E2b) of the second light-emitting element (LEDb), and the second electrode (E2c) of the third light-emitting element (LEDc) can be electrically independent from each other by the separator (SPR'').

[0329] In one embodiment, the separator (SPR'') may have a mesh structure surrounding the light-emitting areas (EAa, EAb, EAc) and the second electrodes (E2a, E2b, E2c) on a plane. Accordingly, the leakage current of the display device (DD) can be reduced.

[0330] In one embodiment, the separator (SPR'') can define open areas (OA1, OA2, OA3) corresponding to the second electrodes (E2a, E2b, E2c), respectively. The second electrode (E2a) of the first light-emitting element (LEDa) can be disposed in the first open area (OA1), the second electrode (E2b) of the second light-emitting element (LEDb) can be disposed in the second open area (OA2), and the second electrode (E2c) of the third light-emitting element (LEDc) can be disposed in the third open area (OA3).

[0331] In one embodiment, the planar shape of the first open area (OA1) may be substantially the same as the planar shape of the second electrode (E2a) of the first light-emitting element (LEDa), the planar shape of the second open area (OA2) may be substantially the same as the planar shape of the second electrode (E2b) of the second light-emitting element (LEDb), and the planar shape of the third open area (OA3) may be substantially the same as the planar shape of the second electrode (E2c) of the third light-emitting element (LEDc).

[0332] In one embodiment, the connection patterns (CNPa, CNPb, CNPc) may not overlap the light-emitting areas (EAa, EAb, EAc) on a plane, respectively. In one embodiment, the connection patterns (CNPa, CNPb, CNPc) may surround at least a portion of the light-emitting areas (EAa, EAb, EAc) on a plane, respectively. For example, the connection patterns (CNPa, CNPb, CNPc) may have a closed ring shape that entirely surrounds the light-emitting areas (EAa, EAb, EAc) on a plane, respectively. However, the present invention is not necessarily limited thereto.

[0333] In one embodiment, the output power connection wiring (PV_CL) can be connected to the light-emitting elements (LEDa, LEDb, LEDc) through the connection patterns (CNPa, CNPb, CNPc). Specifically, the output power connection wiring (PV_CL) can be connected to the second electrode (E2a) of the first light-emitting element (LEDa) through the first connection pattern (CNPa), connected to the second electrode (E2b) of the second light-emitting element (LEDb) through the second connection pattern (CNPb), and connected to the second electrode (E2c) of the third light-emitting element (LEDc) through the third connection pattern (CNPc). Accordingly, the output power connection wiring (PV_CL) can be electrically connected to the pixel circuit block (PCB''). As a result, the switching circuit unit (SPC) can be electrically connected to the pixel circuit block (PCB'') through the output power connection wiring (PV_CL).

[0334] In one embodiment, the material and cross-sectional structure of the connection patterns (CNPa, CNPb, CNPc) may be substantially the same as the connection pattern (CNP) of FIGS. 7 to 10.

[0335] In one embodiment, the output power connection wiring (PV_CL) may include a first light-emitting connection portion (CNa_P) in contact with the first connection pattern (CNPa), a second light-emitting connection portion (CNb_P) in contact with the second connection pattern (CNPb), and a third light-emitting connection portion (CNc_P) in contact with the third connection pattern (CNPc).

[0336] For example, in one embodiment, the positions of the light-emitting connectors (CNa_P, CNb_P, CNc_P) in each first unit light-emitting area (UEA1) may be substantially the same. In addition, the positions of the light-emitting connectors (CNa_P, CNb_P, CNc_P) in each second unit light-emitting area (UEA2) may be substantially the same. However, the present invention is not necessarily limited thereto.

[0337] In one embodiment, the planar profile of the area where the first connection pattern (CNPa) and the second electrode (E2a) of the first light-emitting element (LEDa) come into contact may be substantially the same as or similar to the planar profile of the edge of the first connection pattern (CNPa). For example, when the first connection pattern (CNPa) has a closed ring shape that entirely surrounds the first light-emitting area (EAa) on a plane, the area where the first connection pattern (CNPa) and the second electrode (E2a) of the first light-emitting element (LEDa) come into contact may have a closed ring shape on a plane.

[0338] Likewise, in one embodiment, the planar profile of the area where the second connection pattern (CNPb) and the second electrode (E2b) of the second light-emitting element (LEDb) come into contact may be substantially the same as or similar to the planar profile of the edge of the second connection pattern (CNPb), and the planar profile of the area where the third connection pattern (CNPc) and the second electrode (E2c) of the third light-emitting element (LEDc) come into contact may be substantially the same as or similar to the planar profile of the edge of the third connection pattern (CNPc).

[0339] In one embodiment, the separator (SPR'') may overlap the connection patterns (CNPa, CNPb, CNPc) on a plane. Specifically, the separator (SPR'') may cover a portion of the connection patterns (CNPa, CNPb, CNPc) and a region between adjacent connection patterns (CNPa, CNPb, CNPc). That is, at least a portion of the separator (SPR'') may extend along an edge of each of the connection patterns (CNPa, CNPb, CNPc) on a plane. Accordingly, the connection patterns (CNPa, CNPb, CNPc) may partially overlap an area where the separator (SPR'') is arranged on a plane.

[0340] In one embodiment, the cross-sectional structure of each light-emitting region of FIGS. 16 and 17 may be substantially the same as or similar to the cross-sectional structure of any one of FIGS. 9, 10, and 12. When the cross-sectional structure of each light-emitting region of FIGS. 16 and 17 is substantially the same as or similar to the cross-sectional structure of FIG. 12, the connection patterns (CNPa, CNPb, CNPc) may be omitted.

[0341] Fig. 18 is a plan view schematically illustrating a portion of the display area of ​​Figs. 1a and 1b according to one embodiment. Fig. 19 is an enlarged plan view of one pixel circuit block, light-emitting elements connected to one pixel circuit block, and one switching circuit unit of Fig. 18 according to one embodiment.

[0342] In one embodiment, the display device (DD) described with reference to FIGS. 18 and 19 may be substantially the same as or similar to the display device (DD) described with reference to FIGS. 16 and 17, except for the separator (SPR''). Hereinafter, overlapping descriptions are omitted or simplified.

[0343] In one embodiment, referring to FIGS. 18 and 19, the display device (DD) may include pixel driving circuits (PCa, PCb, PCc), light emitting elements (LEDa, LEDb, LEDc), connection patterns (CNPa, CNPb, CNPc), switching circuits (SPC), and separators (SPR'') arranged in the display area (DA).

[0344] In one embodiment, the second electrode layer (E2) can be separated (or disconnected) by a separator (SPR''). Accordingly, the second electrode layer (E2) can be separated (or disconnected) into second electrodes (E2a, E2b, E2c) that are spaced apart from each other by the separator (SPR''). That is, the second electrode (E2a) of the first light-emitting element (LEDa), the second electrode (E2b) of the second light-emitting element (LEDb), and the second electrode (E2c) of the third light-emitting element (LEDc) can be electrically independent from each other by the separator (SPR'').

[0345] In one embodiment, the separator (SPR'') may have a mesh structure surrounding the light-emitting areas (EAa, EAb, EAc) and the second electrodes (E2a, E2b, E2c) on a plane. In this case, within one pixel circuit block (PCB''), the separator (SPR'') may not be arranged between adjacent third light-emitting areas (EAc). The separator (SPR'') may be arranged between the third light-emitting areas (EAc) corresponding to adjacent pixel circuit blocks (PCB'').

[0346] In one embodiment, the cross-sectional structure of each light-emitting region of FIGS. 18 and 19 may be substantially the same as or similar to the cross-sectional structure of any one of FIGS. 9, 10, and 12. When the cross-sectional structure of each light-emitting region of FIGS. 16 and 17 is substantially the same as or similar to the cross-sectional structure of FIG. 12, the connection patterns (CNPa, CNPb, CNPc) may be omitted.

[0347] In one embodiment, referring again to FIGS. 6 to 19, the display device (DD) may include a plurality of pixel circuit blocks, each including at least one pixel driving circuit including a plurality of transistors, and a switching circuit (SPC) electrically connected one-to-one to the pixel circuit blocks to selectively provide a high-level first power voltage (ELVSS_H) or a low-level first power voltage (ELVSS_L). The plurality of transistors may generate a driving current (ID) and include a driving transistor that is a PMOS transistor. For example, a low-level first power voltage (ELVSS_L) may be applied to the pixel circuit blocks disposed in a high-brightness area of ​​the display area (DA), and a high-level first power voltage (ELVSS_D) may be applied to the pixel circuit blocks disposed in a low-brightness area of ​​the display area (DA). Accordingly, power consumption of the display device (DD) may be reduced.

[0348] FIG. 20 is a block diagram illustrating an electronic device according to one embodiment.

[0349] In one embodiment, referring to FIG. 20, the electronic device (10) may include a display module (11), a processor (12), a memory (13), and a power module (14).

[0350] A display device according to one embodiment (e.g., a display device (DD or Dda) of FIGS. 1 to 19) can be applied to various electronic devices (10). The electronic device (10) includes the above-described display device, and may further include a module or device having additional functions in addition to the display device.

[0351] In one embodiment, the processor (12) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller. The processor (12) may control the display device.

[0352] In one embodiment, the memory (13) may store data information necessary for the operation of the processor (12) or the display module (11). When the processor (12) executes an application stored in the memory (13), an image data signal and / or an input control signal is transmitted to the display module (11), and the display module (11) can process the received signal and output image information through a display screen.

[0353] In one embodiment, the power module (14) may include a power supply module, such as a power adapter or a battery device, and a power conversion module that converts power supplied by the power supply module to generate power required for the operation of the electronic device (10).

[0354] In one embodiment, at least one of the components of the electronic device (10) described above may be included in the display device. In addition, some of the individual modules functionally included in one module may be included in the display device, while others may be provided separately from the display device. For example, in another embodiment, the display device may include a display module (11), and the processor (12), memory (13), and power module (14) may be provided in the form of other devices within the electronic device (10) other than the display device.

[0355] FIG. 21 is a schematic diagram showing an electronic device according to various embodiments.

[0356] In one embodiment, referring to FIG. 21, various electronic devices (10) to which display devices according to embodiments (for example, display devices (DD or Dda) of FIGS. 1 to 19) are applied may include not only image display electronic devices such as a smart phone (10_1a), a tablet PC (10_1b), a laptop (10_1c), a TV (10_1d), and a desk monitor (10_1e), but also wearable electronic devices including display modules such as smart glasses (10_2a), a head-mounted display (10_2b), and a smart watch (10_2c), and vehicle electronic devices (10_3) including display modules such as a CID (Center Information Display) and a room mirror display arranged on an instrument panel, center fascia, or dashboard of an automobile.

[0357] Although the present invention has been described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various modifications and changes may be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

[0358] The present invention can be applied to various display devices that can include a display device. For example, the present invention can be applied to high-resolution smartphones, mobile phones, smart pads, smart watches, tablet PCs, vehicle navigation systems, televisions, computer monitors, laptops, and the like.

[0359] <Explanation of symbols>

[0360] DD, DDa: Display device DA: Display area

[0361] NDA: Peripheral Area PX: Pixels

[0362] PX1, PX1', PX1'': first pixel PX2, PX2', PX2'': second pixel

[0363] PX3, PX3', PX3'': Third pixel PX4, PX4', PX4'': Fourth pixel

[0364] PC: Pixel driving circuit

[0365] PC1, PC1', PC1'': first pixel driving circuit

[0366] PC2, PC2', PC2'': Second pixel driving circuit

[0367] PC3, PC3', PC3'': Third pixel driving circuit

[0368] PC4, PC4', PC4'': 4th pixel driving circuit

[0369] SPC: Switching circuit M1: First switching element

[0370] M2: Second switching element M3: Third switching element

[0371] C_S: Third capacitor PVL_H: First power voltage wiring

[0372] PVL_L: Second power voltage wiring DL_S: Second data wiring

[0373] PV_CL, PV_CL': Output power connection wiring

[0374] SPR, SPR', SPR'': Separator

[0375] CNP, CNPa, CNPb, CNPc: Connection patterns

[0376] EP: Engraved Pattern

Claims

1. A plurality of pixel circuit blocks each including at least one pixel driving circuit section including a plurality of transistors; A light emitting element electrically connected to the pixel driving circuit and including an anode electrode and a cathode electrode; A first power voltage wiring that receives a high level power voltage; A second power voltage wiring that receives a low level power voltage; Electrically connected one-to-one with the above plurality of pixel circuit blocks, A first switching element connected to the first power voltage wiring and turned on by a data voltage of a first voltage level; and A switching circuit unit including a second switching element connected to the second power voltage wiring and turned on by a data voltage of a second voltage level different from the first voltage level; and A display device including a data wiring electrically connected to the switching circuit and providing a data voltage of the first voltage level or a data voltage of the second voltage level to the switching circuit.

2. A display device according to claim 1, characterized in that the switching circuit selectively provides the high-level power supply voltage or the low-level power supply voltage to any one of the plurality of pixel circuit blocks electrically connected to the switching circuit.

3. A display device characterized in that in the first paragraph, the first switching element is turned off by the data voltage of the second voltage level, and the second switching element is turned off by the data voltage of the first voltage level.

4. A display device characterized in that, in the third paragraph, when the first switching element is turned on, the second switching element is turned off, and when the first switching element is turned off, the second switching element is turned on.

5. In the first paragraph, if the first switching element is a PMOS transistor, the second switching element is an NMOS transistor, A display device characterized in that when the first switching element is an NMOS transistor, the second switching element is a PMOS transistor.

6. In the first paragraph, a power wiring to which a common voltage is applied is connected to the cathode electrode, A display device characterized in that the power supply voltage is a driving voltage having a voltage level higher than the voltage level of the common voltage.

7. In the 6th paragraph, the plurality of transistors, A switching transistor comprising a gate electrode, a source electrode, and a drain electrode controlled by a light emission control signal, A display device characterized in that it further includes an output power connection wiring that connects the source electrode of the switching transistor and the switching circuit and selectively receives the high-level power voltage or the low-level power voltage through the switching circuit.

8. In paragraph 1, A display device characterized in that it further includes an output power connection wiring that connects the anode electrode and the switching circuit and selectively receives the high-level power voltage or the low-level power voltage through the switching circuit.

9. In paragraph 1, A display device characterized in that it further includes an output power connection wiring that connects the cathode electrode and the switching circuit and selectively receives the high-level power voltage or the low-level power voltage.

10. In paragraph 9, Further comprising a separator disposed on the pixel driving circuit portion and surrounding the pixel circuit blocks on a plane, A display device characterized in that the cathode electrode is disconnected by the separator.

11. A display device according to claim 10, characterized in that the side surface of the separator has a reverse tapered slope.

12. In the 10th paragraph, the pixel driving circuit unit, An inorganic insulating layer disposed on a substrate; A first organic insulating layer disposed on the inorganic insulating layer; A second organic insulating layer disposed on the first organic insulating layer and having a first sub-opening defined therein that exposes at least a portion of the output power connection wiring; and A display device characterized in that it further includes a pixel defining film disposed on the second organic insulating layer and having a second sub-aperture defined therein, the second sub-aperture being spatially connected to the first sub-aperture.

13. In paragraph 12, A display device further comprising a connection pattern disposed on the pixel definition film, contacting the cathode electrode in an area overlapping an edge of the separator, and contacting the output power connection wiring through the first and second sub-openings.

14. In the 13th paragraph, the light emitting element further includes a light emitting layer disposed between the anode electrode and the cathode electrode and overlapping the light emitting region, A display device characterized in that the above connection pattern has a shape surrounding the light-emitting area on a plane.

15. A display device characterized in that in the 14th paragraph, the connection pattern is spaced apart from the light-emitting area on a plane.

16. In the 12th paragraph, the output power connection wiring includes a first conductive layer, a second conductive layer, and a third conductive layer sequentially laminated, A display device characterized in that each side surface of the first and third conductive layers protrudes outward more than the side surface of the second conductive layer.

17. In the 16th paragraph, the cathode electrode is disconnected by the output power connection wiring, A display device characterized in that the cathode electrode is in contact with the side surface of the second conductive layer and the side surface of the third conductive layer.

18. In the 9th paragraph, the pixel driving circuit unit, An inorganic insulating layer disposed on a substrate; A first organic insulating layer disposed on the inorganic insulating layer; A second organic insulating layer disposed on the first organic insulating layer and having a first sub-opening defined therein that exposes at least a portion of the output power connection wiring; and Further comprising a pixel defining film disposed on the second organic insulating layer and having a second sub-aperture spatially connected to the first sub-aperture; A display device characterized in that the pixel defining film includes an engraved pattern surrounding the pixel circuit blocks on a plane.

19. A display device according to claim 18, characterized in that the cathode electrode is disconnected by the negative pattern.

20. Display device; and including a processor controlling the display device; The above display device, A plurality of pixel circuit blocks each including at least one pixel driving circuit section including a plurality of transistors; A light emitting element electrically connected to the pixel driving circuit and including an anode electrode and a cathode electrode; A first power voltage wiring that receives a high level power voltage; A second power voltage wiring that receives a low level power voltage; Electrically connected one-to-one with the above plurality of pixel circuit blocks, A first switching element connected to the first power voltage wiring and turned on by a data voltage of a first voltage level; and A switching circuit unit including a second switching element connected to the second power voltage wiring and turned on by a data voltage of a second voltage level different from the first voltage level; and An electronic device comprising a data wiring electrically connected to the switching circuit and providing a data voltage of the first voltage level or a data voltage of the second voltage level to the switching circuit.

Images