Electronic system and control method therefor

Abstract

Embodiments of the present invention provide an electronic system and a control method therefor. The electronic system comprises an electronic device. The electronic device at least comprises: a charging circuit, wherein the charging circuit has a first input end, a second input end, and a first output end, and the charging circuit comprises a first transistor, a second transistor, a third transistor, and a fourth transistor; a switch circuit, wherein an input end of the switch circuit is connected to the first output end, an output end of the switch circuit is connected to a power supply of the electronic device, and the switch circuit is used for connecting or disconnecting a connection path between the first output end and the power supply; and a communication device, wherein in a communication mode, the communication device is connected to the first input end and the second input end so as to communicate with the electronic device by means of the first input end or the second input end. The embodiments of the present invention at least can prolong the service life of an electronic device.

Description

An electronic system and its control method Technical Field

[0001] The present invention relates to the field of electronic circuit technology, and in particular to an electronic system and its control method. Background Technology

[0002] Portable electronic devices include products such as Bluetooth headsets and Bluetooth smart glasses. Currently, the charging methods for portable electronic devices are as follows: For TWS (True Wireless Stereo) headsets and OWS (Open Wearable Stereo) headsets, they are generally equipped with a charging case. The charging case has a charging compartment. When charging the headset, a USB (Universal Serial Bus) cable needs to be connected to the power adapter to charge the charging case. Then, the headset placed in the charging case and the charging case are connected to the charging case via a spring probe POGO PIN. The charging case charges the headset. For Bluetooth smart glasses, they are generally charged through a charging cable with charging management. One end of the charging cable is connected to the power source, and the other end branches into two charging sockets. The two charging sockets are connected to the corresponding temples of the glasses to charge the Bluetooth smart glasses. Technical issues

[0003] However, when the earbuds are placed in the charging case, some charging cases are designed so that the earbuds may be placed upside down, causing the positive and negative charging ports of the earbuds to be reversed with the two output ports of the charging case, resulting in a short circuit. This can affect the lifespan of the earbuds or even damage the product, and in severe cases, cause the battery to catch fire. The connection between the temples of Bluetooth smart glasses and the charging cable also has the same problem. Therefore, the current charging methods for portable electronic devices need to be improved. Technical solutions

[0004] This invention provides an electronic system and its control method, which at least helps to extend the service life of electronic devices.

[0005] One embodiment of the present invention provides an electronic system, including: an electronic device, the electronic device including at least: a charging circuit, the charging circuit having a first input terminal, a second input terminal, and a first output terminal, and the charging circuit including a first transistor, a second transistor, a third transistor, and a fourth transistor, the source of the first transistor being connected to the source of the third transistor, the source of the first transistor being connected to ground, the gate of the first transistor being connected to the gate of the second transistor, the drain of the first transistor being connected to the drain of the second transistor, the drain of the first transistor serving as the first input terminal, the source of the second transistor being connected to the source of the fourth transistor, the source of the second transistor serving as the first output terminal, the drain of the third transistor being connected to the drain of the fourth transistor, and the third transistor... The drain of the transistor serves as the second input terminal. The gate of the third transistor is connected to the gate of the fourth transistor. The gate of the third transistor is connected to the first input terminal, and the gate of the first transistor is connected to the second input terminal. A switching circuit is used to connect or disconnect the connection path between the first output terminal and the power supply. When the switching circuit connects the first output terminal to the power supply, the electronic device is in charging mode. When the switching circuit disconnects the first output terminal from the power supply, the electronic device is in communication mode. In communication mode, a communication device is connected to the first and second input terminals to communicate with the electronic device through either the first or second input terminal.

[0006] In some embodiments, the electronic device further includes a main control module, which includes at least a first enable terminal; the switching circuit includes a fifth transistor, the gate of which is connected to the first enable terminal, the source of which serves as the input terminal of the switching circuit, and the drain of which serves as the output terminal of the switching circuit; the fifth transistor is in a conducting state when its gate receives a first enable signal from the first enable terminal, and is in a cut-off state when its gate does not receive the first enable signal from the first enable terminal.

[0007] In some embodiments, the switching circuit further includes a first resistor, and the gate of the fifth transistor is connected to the first enable terminal through the first resistor.

[0008] In some embodiments, the electronic device further includes a main control module, which has at least a second enable terminal, a third enable terminal, a first detection terminal, a second detection terminal, and a third detection terminal. The first detection terminal is connected to a first input terminal, the second detection terminal is connected to a second input terminal, and the third detection terminal is connected to a first output terminal. The electronic device also includes a communication control circuit, which has a second output terminal and a third output terminal. The communication control circuit includes: a sixth transistor, the source of which serves as the second output terminal, the drain of which is connected to the first input terminal, and the gate of which is connected to the second enable terminal; and a seventh transistor, the source of which serves as the third output terminal, the drain of which is connected to the second input terminal, and the gate of which is connected to the third enable terminal. If the third detection terminal receives a communication signal from the first output terminal, the main control module controls the sixth transistor to be turned on or off according to the signal received by the first detection terminal, and controls the seventh transistor to be turned on or off according to the signal received by the second detection terminal.

[0009] In some embodiments, at the same time, one of the first input terminal or the second input terminal sends a first signal to the main control module through a corresponding detection terminal; while the first detection terminal receives the first signal from the first input terminal, the main control module sends a second enable signal from the second enable terminal; while the gate of the sixth transistor receives the second enable signal, the sixth transistor is in a conducting state, and the second output terminal is connected to the first input terminal to realize communication between the communication device and the electronic device; while the second detection terminal receives the first signal from the second input terminal, the main control module sends a third enable signal from the third enable terminal; while the gate of the seventh transistor receives the third enable signal, the seventh transistor is in a conducting state, and the third output terminal is connected to the second input terminal to realize communication between the communication device and the electronic device; while the gate of the sixth transistor does not receive the second enable signal, the sixth transistor is in a cutoff state; while the gate of the seventh transistor does not receive the third enable signal, the seventh transistor is in a cutoff state.

[0010] In some embodiments, the electronic device further includes: a second resistor, a third resistor, a fourth resistor, and a fifth resistor; the first detection terminal is connected to the first input terminal via the second resistor; one end of the third resistor is connected to the first detection terminal, and the other end of the third resistor is connected to ground; the second detection terminal is connected to the second input terminal via the fourth resistor; one end of the fifth resistor is connected to the second detection terminal, and the other end of the fifth resistor is connected to ground.

[0011] In some embodiments, the electronic device further includes: a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor, wherein the gate of the sixth transistor is connected to a second enable terminal via the sixth resistor, one end of the seventh resistor is connected to the gate of the sixth transistor, and the other end of the seventh resistor is connected to ground; the gate of the seventh transistor is connected to a third enable terminal via the eighth resistor, one end of the ninth resistor is connected to the gate of the seventh transistor, and the other end of the ninth resistor is connected to ground.

[0012] In some embodiments, the communication control circuit further includes a tenth resistor, an eleventh resistor, and a twelfth resistor. The first end of the tenth resistor is connected to the first output terminal. The first end of the eleventh resistor is connected to the second end of the tenth resistor. The second end of the eleventh resistor is connected to the first end of the twelfth resistor. The second end of the twelfth resistor is connected to ground. The second end of the eleventh resistor is connected to the third detection terminal. The first output terminal is connected to the third detection terminal through the tenth resistor and the eleventh resistor.

[0013] In some embodiments, the sixth transistor and the seventh transistor are both NMOS transistors.

[0014] In some embodiments, the first transistor and the third transistor are both NMOS transistors, and the second transistor and the fourth transistor are both PMOS transistors.

[0015] In some embodiments, the communication device communicates with the electronic device via a two-to-one converter circuit. The two-to-one converter circuit has a first connection terminal and a second connection terminal. The two-to-one converter circuit includes an inverter chip and a multi-level buffer chip. The multi-level buffer chip includes at least a first-level buffer, a second-level buffer, and a third-level buffer. The input terminal of the third-level buffer is used to receive the TXD signal output by the communication device. The output terminal of the third-level buffer is connected to the enable terminal of the second-level buffer, the input terminal of the first-level buffer, and the input terminal of the inverter chip. The output terminal of the inverter chip is connected to the enable terminal of the first-level buffer. The output terminal of the first-level buffer serves as the first connection terminal. The input terminal of the second-level buffer is connected to the first connection terminal. The output terminal of the second-level buffer is used to output the RXD signal to the communication device. The second connection terminal is connected to ground. In communication mode, the first connection terminal is connected to one of the first input terminal or the second input terminal, and the second connection terminal is connected to the other of the first input terminal or the second input terminal. The first connection terminal transmits the DATA signal with the electronic device.

[0016] In some embodiments, the two-wire to single-wire circuit further includes: a thirteenth resistor, a fourteenth resistor, and a fifteenth resistor. One end of the thirteenth resistor is connected to the output terminal of the first-stage buffer, and the other end of the thirteenth resistor is connected to the power supply voltage. One end of the fifteenth resistor is connected to the input terminal of the inverter chip, and the other end of the fifteenth resistor is connected to the power supply voltage. The enable terminal of the third-stage buffer is connected to the power supply voltage through the fourteenth resistor.

[0017] In some embodiments, the electronic system includes a communication component, a two-wire to one-wire circuit is disposed within the communication component, and the communication component further includes a connector, which includes a first port, a second port, a third port, a fourth port, and a fifth port. The first port or the fifth port provides a power supply voltage to the two-wire to one-wire circuit, the fourth port provides a ground voltage to the two-wire to one-wire circuit, the second port is connected to the input terminal of the third-stage buffer for receiving the TXD signal, and the third port is connected to the output terminal of the first-stage buffer for outputting the RXD signal.

[0018] In some embodiments, the communication component further includes a sixteenth resistor and a seventeenth resistor. One end of the sixteenth resistor is connected to a first port, and the other end of the sixteenth resistor is connected to a first voltage signal. One end of the seventeenth resistor is connected to a fifth port, and the other end of the seventeenth resistor is connected to a second voltage signal. The voltage values ​​of the first voltage signal and the second voltage signal are different. The resistance of one of the sixteenth resistor and the seventeenth resistor is zero, and the resistance of the other is infinite.

[0019] Another aspect of this invention provides a control method for an electronic system, comprising: providing an electronic system as described in any of the above embodiments, the electronic system including: an electronic device and a communication device, the electronic device including at least: a charging circuit and a switching circuit, the input terminal of the switching circuit being connected to a first output terminal of the charging circuit, the output terminal of the switching circuit being connected to a power supply of the electronic device, and controlling the switching circuit to connect or disconnect the connection path between the first output terminal and the power supply; during the period when the switching circuit connects the first output terminal and the power supply, the electronic device is in a charging mode, and during the period when the switching circuit disconnects the connection path between the first output terminal and the power supply, the electronic device is in a communication mode, in the communication mode, the communication device being connected to a first input terminal and a second input terminal of the charging circuit to communicate with the electronic device through the first input terminal or the second input terminal.

[0020] The beneficial effects of the present invention are as follows: The present solution provides an electronic system and its control method. The electronic system includes an electronic device, which includes at least a charging circuit and a switching circuit. The charging circuit has a first input terminal and a second input terminal for connecting to an external charging cable, charging device or communication device, and a first output terminal connected to the input terminal of the switching circuit. The output terminal of the switching circuit is connected to the power supply inside the electronic device. The charging circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor connected in a bridge configuration. When charging an electronic device, the positive and negative terminals of an external charging cable or charging device are connected to the first and second input terminals, respectively. The charging circuit is then activated, and the charging voltage output from the first output terminal is transmitted to the power supply of the electronic device. Regardless of whether the positive terminal is connected to the first or second input terminal, the charging voltage can be output from the first output terminal. In other words, there is no need to distinguish between positive and negative terminals. As long as one of the first and second input terminals is connected to the positive terminal of the external charging cable or charging device, and the other is connected to the negative terminal of the external charging cable or charging device, the power supply of the electronic device can be charged. This avoids short circuits caused by incorrect polarity connections, improves the user experience of the electronic device, extends its service life, and prevents safety hazards caused by reverse polarity connections during charging.

[0021] In addition, by using the switching circuit to disconnect the connection path between the first output terminal and the power supply, the device can be connected to an external communication device through the first and second input terminals without disassembling the device. This enables communication between the electronic device and the external communication device, thereby achieving functions such as serial communication and software burning. This helps to avoid the impact of disassembly on the electronic device and facilitates a simple and efficient communication connection between the electronic device and the external communication device. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrative descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 is a schematic diagram of the structure of an electronic system provided in an embodiment of the present invention;

[0024] Figure 2 is a schematic diagram of a partial circuit structure in an electronic device provided by an embodiment of the present invention;

[0025] Figure 3 is a schematic diagram of a partial circuit structure of an electronic system provided in an embodiment of the present invention. Embodiments of the present invention

[0026] As can be seen from the background technology, the current charging methods for portable electronic devices need to be improved.

[0027] Furthermore, analysis revealed that most current wired communication control technologies use dual-wire UART (Universal Asynchronous Receiver / Transmitter) communication. In general, electronic devices do not have communication interfaces, making wired upgrades and debugging impossible. If debugging is required, the device must be disassembled, which can easily damage the product.

[0028] To address the aforementioned problems, embodiments of the present invention provide an electronic system and its control method. The electronic system includes an electronic device, which includes at least a charging circuit and a switching circuit. The charging circuit has a first input terminal and a second input terminal for connection to an external charging cable, charging device, or communication device, and a first output terminal connected to the input terminal of the switching circuit. The output terminal of the switching circuit is connected to the power supply inside the electronic device. As long as one of the first and second input terminals is connected to the positive terminal of the external charging cable or charging device, and the other is connected to the negative terminal of the external charging cable or charging device, the power supply of the electronic device can be charged, avoiding short circuits caused by incorrect positive and negative connections. This improves the user experience of the electronic device and extends its service life.

[0029] In addition, by using the switching circuit to disconnect the connection path between the first output terminal and the power supply, it is possible to connect to an external communication device through the first and second input terminals without disassembling the device. This enables communication between the electronic device and the external communication device, thereby realizing functions such as serial communication and software burning. This avoids the impact of disassembly on the electronic device and facilitates a simple and efficient communication connection between the electronic device and the communication device.

[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the various embodiments of this invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the various embodiments of this invention to facilitate a better understanding of the invention. However, the technical solutions claimed in this invention can be implemented even without these technical details and with various variations and modifications based on the following embodiments.

[0031] Figure 1 is a schematic diagram of the structure of an electronic system provided in an embodiment of the present invention; Figure 2 is a schematic diagram of a partial circuit structure in an electronic device provided in an embodiment of the present invention.

[0032] Referring to Figures 1 and 2, the electronic system provided in this embodiment of the invention includes: an electronic device 100, which can be a portable electronic device. In some embodiments, the electronic device 100 can be a Bluetooth headset or Bluetooth smart glasses.

[0033] The electronic device 100 has two modes: a charging mode and a communication mode. In the charging mode, the electronic device 100 can be connected to an external charging device or charging cable to charge the electronic device 100. In the communication mode, the electronic device 100 can be connected to a communication device 200 to enable communication between the electronic device 100 and the communication device 200.

[0034] The electronic device 100 includes at least a charging circuit 110. In some embodiments, the electronic device 100 has a housing, and the charging circuit 110 may be disposed within the housing.

[0035] The charging circuit 110 has a first input terminal TP1 and a second input terminal TP2. The first input terminal TP1 and the second input terminal TP2 can be metal contacts for mating with the POGO PIN on the charging case, or charging interfaces for connecting to an external charging cable. In charging mode, the first input terminal TP1 and the second input terminal TP2 are used to connect to an external charging cable or charging device to charge the electronic device 100. When charging the electronic device 100 through the first input terminal TP1 and the second input terminal TP2, one of the first input terminal TP1 and the second input terminal TP2 is connected to the positive terminal of the external charging cable or charging device, and the other of the first input terminal TP1 and the second input terminal TP2 is connected to the negative terminal of the external charging cable or charging device. In communication mode, the first input terminal TP1 and the second input terminal TP2 are used to connect to a communication device 200 to enable communication between the electronic device 100 and the external communication device 200, thereby realizing serial communication and software burning, etc.

[0036] Referring to Figures 1 and 2, the charging circuit 110 also has a first output terminal TP3. In the charging mode, the first output terminal TP3 is used to output the charging voltage CHG+. In the communication mode, the voltage of the first output terminal TP3 can be used to determine whether it is in the communication mode, thereby realizing the communication between the electronic device 100 and the external communication device 200.

[0037] Specifically, referring to Figure 2, the charging circuit 110 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4. The source of the first transistor Q1 is connected to the source of the third transistor Q3, and the source of the first transistor Q1 is connected to ground (GND). The gate of the first transistor Q1 is connected to the gate of the second transistor Q2, and the drain of the first transistor Q1 is connected to the drain of the second transistor Q2. The drain of the first transistor Q1 serves as the first input terminal TP1. The source of the second transistor Q2 is connected to the source of the fourth transistor Q4, and the source of the second transistor Q2 serves as the first output terminal TP3. The drain of the third transistor Q3 is connected to the drain of the fourth transistor Q4, and the drain of the third transistor Q3 serves as the second input terminal TP2. The gate of the third transistor Q3 is connected to the gate of the fourth transistor Q4, and the gate of the third transistor Q3 is connected to the first input terminal TP1. The gate of the first transistor Q1 is connected to the second input terminal TP2.

[0038] In some embodiments, the first transistor Q1 and the third transistor Q3 are both NMOS (N-channel metal oxide semiconductor) transistors, and the second transistor Q2 and the fourth transistor Q4 are both PMOS (P-channel metal oxide semiconductor) transistors.

[0039] The working principle of the charging circuit 110 is as follows: When the first input terminal TP1 is connected to the positive terminal of the external charging cable or charging device, and the second input terminal TP2 is connected to the negative terminal of the external charging cable or charging device, the input voltage VINA of the first input terminal TP1 is a high-level voltage, and the input voltage VINB of the second input terminal TP2 is a low-level voltage. The gates of the first transistor Q1 and the second transistor Q2 both receive a low-level voltage, while the gates of the third transistor Q3 and the fourth transistor Q4 both receive a high-level voltage. The first transistor Q1 and the fourth transistor Q4 are in the off state, while the second transistor Q2 and the third transistor Q3 are in the on state. The input voltage VINA of the first input terminal TP1 is transmitted to the first output terminal TP3 through the on-state second transistor Q2, and the first output terminal TP3 outputs a high-level voltage.

[0040] When the first input terminal TP1 is connected to the negative terminal of an external charging cable or charging device, and the second input terminal TP2 is connected to the positive terminal of an external charging cable or charging device, the input voltage VINA of the first input terminal TP1 is a low-level voltage, and the input voltage VINB of the second input terminal TP2 is a high-level voltage. The gates of the first transistor Q1 and the second transistor Q2 both receive a high-level voltage, while the gates of the third transistor Q3 and the fourth transistor Q4 both receive a low-level voltage. The first transistor Q1 and the fourth transistor Q4 are in the on state, while the second transistor Q2 and the third transistor Q3 are in the off state. The input voltage VINB of the second input terminal TP2 is transmitted to the first output terminal TP3 through the on-state fourth transistor Q4, and the first output terminal TP3 outputs a high-level voltage.

[0041] Therefore, regardless of whether the positive terminal is connected to the first input terminal TP1 or the second input terminal TP2, a high-level voltage can be output from the first output terminal TP3 as the charging voltage CHG+. In other words, the first input terminal TP1 and the second input terminal TP2 do not need to be distinguished as positive or negative. As long as one of the first input terminal TP1 and the second input terminal TP2 is connected to the positive terminal of the external charging cable or charging device, and the other of the first input terminal TP1 and the second input terminal TP2 is connected to the negative terminal of the external charging cable or charging device, the power supply 130 of the electronic device 100 can be charged. This avoids short circuits caused by incorrect positive and negative connections, which is beneficial to improving the user experience of the electronic device 100, extending the service life of the electronic device 100, and avoiding safety hazards caused by reverse connection of positive and negative terminals during charging.

[0042] Referring to Figures 1 and 2, the charging circuit 110 further includes a switching circuit 120. The input terminal of the switching circuit 120 is connected to the first output terminal TP3, and the output terminal TP4 of the switching circuit 120 is connected to the power supply 130 of the electronic device 100. The switching circuit 120 is used to connect or disconnect the connection path between the first output terminal TP3 and the power supply 130. When the switching circuit 120 connects the first output terminal TP3 and the power supply 130, the electronic device 100 is in charging mode; when the switching circuit 120 disconnects the connection path, the electronic device 100 is in communication mode. In charging mode, the charging voltage CHG+ output by the first output terminal TP3 is transmitted to the power supply 130 of the electronic device 100 through the connected switching circuit 120, thereby charging the power supply 130. In communication mode, the communication device 200 is connected to the first input terminal TP1 and the second input terminal TP2 to communicate with the electronic device 100 through either the first input terminal TP1 or the second input terminal TP2.

[0043] The switching circuit 120 switches the charging state and communication state of the electronic device 100. In this way, the first input terminal TP1 and the second input terminal TP2 can be used to achieve charging connection, and the first input terminal TP1 and the second input terminal TP2 can be used to achieve communication connection between the electronic device 100 and the external communication device 200 without disassembling the device. This enables serial communication and software burning functions, which helps to avoid the impact of disassembly on the electronic device 100 and facilitates a simple and efficient communication connection between the electronic device 100 and the external communication device 200.

[0044] It should be noted that the communication between the communication device 200 and the electronic device 100 mainly refers to wired upgrades and / or debugging of the product, such as serial communication control and software programming through the communication connection.

[0045] In some embodiments, referring to Figures 1 and 2, the electronic device 100 further includes a main control module 140, which includes at least a first enable terminal EN1; the switching circuit 120 includes a fifth transistor Q5, the gate of which is connected to the first enable terminal EN1, the source of which serves as the input terminal of the switching circuit 120, and the drain of which serves as the output terminal TP4 of the switching circuit 120; when the gate of the fifth transistor Q5 receives a first enable signal from the first enable terminal EN1, the fifth transistor Q5 is in a conducting state; when the gate of the fifth transistor Q5 does not receive a first enable signal from the first enable terminal EN1, the fifth transistor Q5 is in a cutoff state. Thus, by controlling the gate voltage of the fifth transistor Q5, the conduction or cutoff of the fifth transistor Q5 is controlled. When the fifth transistor Q5 is in a conducting state, the electronic device 100 is in a charging mode. The charging voltage CHG+ output from the first output terminal TP3 is transmitted to the output terminal TP4 of the switching circuit 120 through the fifth transistor Q5, and then the charging voltage VCGH is transmitted to the power supply 130 of the electronic device 100. Since transistors can be integrated onto a chip via integrated circuits, using the fifth transistor Q5 as the switching component in the switching circuit 120 helps to reduce the space occupied by the switching circuit 120 in the electronic device 100, making it easier to apply the switching circuit 120 to small portable electronic devices such as portable headphones or portable smart glasses.

[0046] In some embodiments, the fifth transistor Q5 can be a PMOS transistor, and the first enable signal is a low-level signal. In other embodiments, the fifth transistor Q5 can also be an NMOS transistor, and the first enable signal is a high-level signal.

[0047] In some embodiments, the fifth transistor Q5 can be a PMOS transistor, and the switching circuit 120 further includes a first resistor R1. The gate of the fifth transistor Q5 is connected to the first enable terminal EN1 through the first resistor R1. The first resistor R1 is used to ensure that the voltage signal output by the first enable terminal EN1 can be matched to the gate of the fifth transistor Q5, and to improve circuit stability and avoid malfunctions.

[0048] In some embodiments, the resistance value of the first resistor R1 can be 9.5kΩ to 10.5kΩ, for example, it can be 9.5kΩ, 9.8kΩ, 10kΩ, 10.1kΩ or 10.2kΩ.

[0049] In some embodiments, referring to Figures 1 and 2, the electronic device 100 further includes a main control module 140 and a communication control circuit 150. The main control module 140 has at least a second enable terminal EN2, a third enable terminal EN3, a first detection terminal VA-EN, a second detection terminal VB-EN, and a third detection terminal COM3. The first detection terminal VA-EN is connected to the first input terminal TP1, the second detection terminal VB-EN is connected to the second input terminal TP2, and the third detection terminal COM3 is connected to the first output terminal TP3. The third detection terminal COM3 of the main control module 140 is used to detect the output voltage of the first output terminal TP3. Based on the output voltage of the third detection terminal COM3, it determines whether the switching circuit 120 is in a conducting state or a disconnected state. When the switching circuit 120 is in a disconnected state, the third detection terminal COM3 detects a communication signal at the first output terminal TP3. When the main control module 140 detects a communication signal, it can control the communication control circuit 150 based on the voltage values ​​detected by the first detection terminal VA-EN and the second detection terminal VB-EN. Specifically, the communication control module can be controlled through the second enable terminal EN2 and the third enable terminal EN3, thereby enabling the electronic device 100 to communicate with the communication device 200.

[0050] Referring to Figures 1 and 2, the communication control circuit 150 has a second output terminal COM1 and a third output terminal COM2. The communication control circuit 150 includes: a sixth transistor Q6, the source of the sixth transistor Q6 serving as the second output terminal COM1, the drain of the sixth transistor Q6 connected to the first input terminal TP1, and the gate of the sixth transistor Q6 connected to the second enable terminal EN2; a seventh transistor Q7, the source of the seventh transistor Q7 serving as the third output terminal COM2, the drain of the seventh transistor Q7 connected to the second input terminal TP2, and the gate of the seventh transistor Q7 connected to the third enable terminal EN3; if the third detection terminal COM3 receives a communication signal from the first output terminal TP3, the main control module 140 controls the sixth transistor Q6 to be turned on or off according to the signal received by the first detection terminal VA-EN, and controls the seventh transistor Q7 to be turned on or off according to the signal received by the second detection terminal VB-EN.

[0051] In other words, the main control module 140 can be used to detect the communication status of the electronic device 100. When the main control module 140 detects that the electronic device 100 is in a communication state, it uses the first detection terminal VA-EN of the main control module 140 to detect the first input terminal TP1, and uses the second detection terminal VB-EN of the main control module 140 to detect the second input terminal TP2. Then, it uses the second output terminal COM1 and the third output terminal COM2 to perform communication control, debugging or software burning of the internal circuit of the electronic device 100.

[0052] In some embodiments, referring to Figures 1 and 2, at the same time, either the first input terminal TP1 or the second input terminal TP2 sends a first signal to the main control module 140 through the corresponding detection terminal; that is, data transmission between the electronic device 100 and the communication device 200 is achieved through either the first input terminal TP1 or the second input terminal TP2. When the electronic device 100 transmits data with the communication device 200 through the first input terminal TP1, the first detection terminal VA-EN of the main control module 140 detects the first signal from the first input terminal TP1. When the electronic device 100 transmits data with the communication device 200 through the second input terminal TP2, the second detection terminal VB-EN of the main control module 140 detects the first signal from the second input terminal TP2.

[0053] During the period when the first detection terminal VA-EN receives the first signal from the first input terminal TP1, the main control module 140 sends a second enable signal from the second enable terminal EN2. During the period when the gate of the sixth transistor Q6 receives the second enable signal, the sixth transistor Q6 is in the on state, and the second output terminal COM1 is connected to the first input terminal TP1. The first signal is transmitted to the second output terminal COM1 through the sixth transistor Q6 to realize communication between the communication device 200 and the electronic device 100. At the same time, the third enable terminal EN3 is in the state of not sending the third enable signal. During the period when the gate of the seventh transistor Q7 does not receive the third enable signal, the seventh transistor Q7 is in the off state, and the third output terminal COM2 is disconnected from the second input terminal TP2.

[0054] During the period when the second detection terminal VB-EN receives the first signal from the second input terminal TP2, the main control module 140 sends a third enable signal from the third enable terminal EN3. During the period when the gate of the seventh transistor Q7 receives the third enable signal, the seventh transistor Q7 is in the on state, and the third output terminal COM2 is connected to the second input terminal TP2. The first signal is transmitted to the third output terminal COM2 through the seventh transistor Q7 to realize communication between the communication device 200 and the electronic device 100. At the same time, the second enable terminal EN2 is in the state of not sending the second enable signal. During the period when the gate of the sixth transistor Q6 does not receive the second enable signal, the sixth transistor Q6 is in the off state, and the second output terminal COM1 is disconnected from the first input terminal TP1.

[0055] Thus, the main control module 140 can determine which of the two terminals, the voltage signal of the first input terminal TP1 and the voltage signal of the second input terminal TP2, is the communication port for communication transmission. Then, it controls the corresponding transistor in the communication control circuit 150 connected to the communication port to turn on the transistor connected to the communication port, thereby making the communication port connected to the corresponding output port, and realizing communication between the electronic device 100 and the communication device 200.

[0056] In some embodiments, referring to FIG1 and FIG2, the electronic device 100 further includes: a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The first detection terminal VA-EN is connected to the first input terminal TP1 through the second resistor R2. One end of the third resistor R3 is connected to the first detection terminal VA-EN, and the other end of the third resistor R3 is connected to ground GND. The second detection terminal VB-EN is connected to the second input terminal TP2 through the fourth resistor R4. One end of the fifth resistor R5 is connected to the second detection terminal VB-EN, and the other end of the fifth resistor R5 is connected to ground GND.

[0057] In this circuit, the first end of the second resistor R2 is connected to the first input terminal TP1, and the second end of the second resistor R2 is connected to the first detection terminal VA-EN. The second resistor R2 is used to ensure that the voltage signal output from the first input terminal TP1 can match the first detection terminal VA-EN of the main control module 140, and to improve circuit stability and prevent malfunctions. In some embodiments, the resistance value of the first resistor R1 can be 0.5kΩ to 1.5kΩ, for example, 0.5kΩ, 0.8kΩ, 1kΩ, 1.1kΩ, or 1.2kΩ.

[0058] The first end of the fourth resistor R4 is connected to the second input terminal TP2, and the second end of the fourth resistor R4 is connected to the second detection terminal VB-EN. The fourth resistor R4 is used to ensure that the voltage signal output from the second input terminal TP2 can be matched to the second detection terminal VB-EN of the main control module 140, and to improve circuit stability and avoid malfunctions. In some embodiments, the resistance value of the second resistor R2 can be 0.5kΩ to 1.5kΩ, for example, it can be 0.5kΩ, 0.8kΩ, 1kΩ, 1.1kΩ, or 1.2kΩ.

[0059] In this circuit, the third resistor R3 serves as a pull-down resistor for the first detection terminal VA-EN. When the first signal is not input to the first input terminal TP1, it clamps the signal at the first detection terminal VA-EN to a low level to prevent the signal line from becoming unpredictable due to floating, which could lead to undesirable system states. This improves circuit stability and avoids malfunctions. In some embodiments, the resistance value of the third resistor R3 can be 90kΩ to 110kΩ, for example, 95kΩ, 98kΩ, 100kΩ, 101kΩ, or 102kΩ.

[0060] In this circuit, the fifth resistor R5 acts as a pull-down resistor for the second detection terminal VB-EN. When the first signal is not input to the second input terminal TP2, it clamps the signal at the second detection terminal VB-EN to a low level to prevent the signal line from becoming unpredictable due to floating, which could lead to undesirable system states. This improves circuit stability and avoids malfunctions. In some embodiments, the resistance value of the fifth resistor R5 can be 90kΩ to 110kΩ, for example, 95kΩ, 98kΩ, 100kΩ, 101kΩ, or 102kΩ.

[0061] In some embodiments, referring to Figures 1 and 2, the sixth transistor Q6 and the seventh transistor Q7 are both NMOS transistors.

[0062] In some embodiments, referring to FIG1 and FIG2, the electronic device 100 further includes: a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9. The gate of the sixth transistor Q6 is connected to the second enable terminal EN2 through the sixth resistor R6. One end of the seventh resistor R7 is connected to the gate of the sixth transistor Q6, and the other end of the seventh resistor R7 is connected to ground GND. The gate of the seventh transistor Q7 is connected to the third enable terminal EN3 through the eighth resistor R8. One end of the ninth resistor R9 is connected to the gate of the seventh transistor Q7, and the other end of the ninth resistor R9 is connected to ground GND.

[0063] In this circuit, the first terminal of the sixth resistor R6 is connected to the gate of the sixth transistor Q6, and the second terminal of the sixth resistor R6 is connected to the second enable terminal EN2. The sixth resistor R6 is used to ensure that the voltage signal output by the second enable terminal EN2 can match the gate of the sixth transistor Q6, and to improve circuit stability and prevent malfunctions. In some embodiments, the resistance value of the sixth resistor R6 can be 0.5kΩ to 1.5kΩ, for example, 0.5kΩ, 0.8kΩ, 1kΩ, 1.1kΩ, or 1.2kΩ.

[0064] In this circuit, the first terminal of the eighth resistor R8 is connected to the gate of the seventh transistor Q7, and the second terminal of the eighth resistor R8 is connected to the third enable terminal EN3. The eighth resistor R8 is used to ensure that the voltage signal output by the third enable terminal EN3 can match the gate of the seventh transistor Q7, and to improve circuit stability and prevent malfunctions. In some embodiments, the resistance value of the eighth resistor R8 can be 0.5kΩ to 1.5kΩ, for example, it can be 0.5kΩ, 0.8kΩ, 1kΩ, 1.1kΩ, or 1.2kΩ.

[0065] In this circuit, the seventh resistor R7 acts as a pull-down resistor for the gate of the sixth transistor Q6. When the second enable terminal EN2 does not output the second enable signal, it clamps the gate of the sixth transistor Q6 to a low level to prevent the gate of the sixth transistor Q6 from becoming unpredictable due to being floating, which could lead to an undesirable state in the system. This improves circuit stability and avoids malfunctions. In some embodiments, the resistance value of the seventh resistor R7 can be 90kΩ to 110kΩ, for example, 95kΩ, 98kΩ, 100kΩ, 101kΩ, or 102kΩ.

[0066] In this circuit, the ninth resistor R9 acts as a pull-down resistor for the gate of the seventh transistor Q7. When the third enable terminal EN3 does not output the third enable signal, it clamps the gate of the seventh transistor Q7 to a low level to prevent the gate of the seventh transistor Q7 from becoming unpredictable due to being floating, which could lead to an undesirable state in the system. This improves circuit stability and avoids malfunctions. In some embodiments, the resistance value of the ninth resistor R9 can be 90kΩ to 110kΩ, for example, 95kΩ, 98kΩ, 100kΩ, 101kΩ, or 102kΩ.

[0067] In some embodiments, referring to Figures 1 and 2, the communication control circuit 150 further includes a tenth resistor R10, an eleventh resistor R11, and a twelfth resistor R12. The first end of the tenth resistor R10 is connected to the first output terminal TP3, and the second end of the tenth resistor R10 is connected to DET-VBUS. DET-VBUS is used to connect to the IO port of the back-end main control chip and serves as a power-on detection function. The first end of the eleventh resistor R11 is connected to the second end of the tenth resistor R10, and the second end of the eleventh resistor R11 is connected to the first end of the twelfth resistor R12. The second end of the twelfth resistor R12 is connected to ground GND, and the second end of the eleventh resistor R11 is connected to the third detection terminal COM3. The first output terminal TP3 is connected to the third detection terminal COM3 through the tenth resistor R10 and the eleventh resistor R11.

[0068] In some embodiments, the resistance value of the tenth resistor R10 can be 18kΩ to 22kΩ, for example, 18kΩ, 19kΩ, 20kΩ, 21kΩ or 22kΩ.

[0069] In some embodiments, the resistance value of the eleventh resistor R11 can be 75k~90k, for example, it can be 75k, 78k, 80k, 81k or 82k.

[0070] In some embodiments, the resistance value of the twelfth resistor R12 can be 110kΩ to 130kΩ, for example, it can be 110kΩ, 112kΩ, 115kΩ, 120kΩ or 122kΩ.

[0071] Figure 3 is a schematic diagram of a partial circuit structure of an electronic system provided in an embodiment of the present invention.

[0072] In some embodiments, referring to Figures 1 and 3, the communication device 200 communicates with the electronic device 100 via a two-to-one converter circuit 310. The two-to-one converter circuit 310 has a first connection terminal TP5 and a second connection terminal TP6. The two-to-one converter circuit 310 includes an inverter chip U2 and a multi-level buffer chip U1. The multi-level buffer chip U1 includes at least a first-level buffer, a second-level buffer, and a third-level buffer. The input terminal 3A of the third-level buffer is used to receive the TXD signal output by the communication device 200. The output terminal 3Y of the third-level buffer is connected to the enable terminal 2OE of the second-level buffer, the input terminal 1A of the first-level buffer, and the input terminal of the inverter chip U2. A. The output terminal Y of inverter chip U2 is connected to the enable terminal 1OE of the first-stage buffer. The output terminal 1Y of the first-stage buffer serves as the first connection terminal TP5. The input terminal 2A of the second-stage buffer is connected to the first connection terminal TP5. The output terminal 2Y of the second-stage buffer is used to output the RXD signal to the communication device 200. The second connection terminal TP6 is connected to ground GND. In communication mode, the first connection terminal TP5 is connected to either the first input terminal TP1 or the second input terminal TP2, and the second connection terminal TP6 is connected to the other one of the first input terminal TP1 or the second input terminal TP2. The first connection terminal TP5 transmits the DATA signal to the electronic device 100. The two-wire to single-wire circuit 310 can convert the two-ended communication port into a single-ended communication port, thereby enabling the communication connection between the electronic device 100 and the external communication device 200 using the charging port. Serial communication and software programming functions are achieved through the charging port, which helps avoid the impact of disassembly on the electronic device 100 and facilitates simple and efficient communication between the electronic device 100 and the external communication device 200.

[0073] Specifically, the enable pins of buffer chip U1 are all active low. When communication device 200 sends a TXD signal to electronic device 100, the input pin 3A of the third-level buffer receives the TXD signal, the enable pin 3OE of the third-level buffer is low, and the output pin 3Y of the third-level buffer outputs the TXD-0 signal. The TXD-0 signal is transmitted to the input pin A of inverter chip U2, and the output pin Y of inverter chip U2 outputs the TXEN signal. At this time, the TXD signal is high, the TXD-0 signal is high, and the TXEN signal is low. The TXEN signal is transmitted to the enable pin 1OE of the first-level buffer, the input pin 1A of the first-level buffer receives the TXD-0 signal, and the output pin 1Y of the first-level buffer outputs the DATA signal. The DATA signal is transmitted to electronic device 100 through either the first input pin TP1 or the second input pin TP2.

[0074] It should be noted that the DATA signal is the first signal in the aforementioned embodiment.

[0075] When the communication device 200 receives the RXD signal sent by the electronic device 100, the electronic device 100 sends a DATA signal through either the first input terminal TP1 or the second input terminal TP2. The DATA signal is transmitted from the first connection terminal TP5 to the input terminal 2A of the second-stage buffer. The input terminal A of the inverter chip U2 is set to a low level, so the TXEN signal output by the output terminal Y of the inverter chip U2 is a high level and the TXD-0 signal is a low level signal. Therefore, the output terminal 2Y of the second-stage buffer can output the RXD signal, and the communication device 200 receives the RXD signal.

[0076] In some embodiments, the inverter chip U2 may be of model 74HC1G04.

[0077] In some embodiments, the multi-level buffer chip U1 can be a four-level buffer chip. In some examples, the model of the four-level buffer chip U1 can be 74HC126.

[0078] In some embodiments, referring to FIG3, the two-wire to single-wire circuit 310 further includes: a thirteenth resistor R13, a fourteenth resistor R14, and a fifteenth resistor R15. One end of the thirteenth resistor R13 is connected to the output terminal 1Y of the first-stage buffer, and the other end of the thirteenth resistor R13 is connected to the power supply voltage VDD. One end of the fifteenth resistor R15 is connected to the input terminal A of the inverter chip U2, and the other end of the fifteenth resistor R15 is connected to the power supply voltage VDD. The enable terminal of the third-stage buffer is connected to the power supply voltage VDD through the fourteenth resistor R14.

[0079] The thirteenth resistor R13 is used as a pull-up resistor for the first connection terminal TP5. In some embodiments, the resistance value of the thirteenth resistor R13 can be 1.8k to 2.4k, for example, it can be 1.8k, 1.9k, 2k, 2.1k or 2.2k.

[0080] The first terminal of the fourteenth resistor R14 is connected to the power supply voltage VDD, and the second terminal of the fourteenth resistor R14 is connected to the enable terminal 3OE of the third-stage buffer. In some embodiments, the resistance value of the fourteenth resistor R14 can be 8kΩ to 12kΩ, for example, 8kΩ, 9kΩ, 10kΩ, 11kΩ, or 12kΩ. The fourteenth resistor R14 keeps the enable terminal 3OE of the third-stage buffer at a low level.

[0081] In some embodiments, the resistance value of the fifteenth resistor R15 can be 0.5kΩ to 1.5kΩ, for example, 0.5kΩ, 0.8kΩ, 1kΩ, 1.1kΩ, or 1.2kΩ. When the TXD signal is in an invalid state, the fifteenth resistor R15 causes the input terminal A of the inverter chip U2 to be at a low level, and causes the TXD-0 signal received by the enable terminal 2OE of the second-stage buffer to be at a low level.

[0082] In some embodiments, the electronic system includes a communication component 300, a two-wire to one-wire circuit 310 disposed within the communication component 300, and a connector J1 including a first port, a second port, a third port, a fourth port, and a fifth port. The first port or the fifth port provides a power supply voltage VDD to the two-wire to one-wire circuit 310, the fourth port provides a ground voltage to the two-wire to one-wire circuit 310, the second port is connected to the input terminal 3A of the third-stage buffer for receiving the TXD signal, and the third port is connected to the output terminal 1Y of the first-stage buffer for outputting the RXD signal. The advantage of providing the power supply voltage VDD to the two-wire to one-wire circuit 310 through the first port or the fifth port is that the port providing the power supply voltage VDD can be selected according to the actual requirements of the power supply voltage VDD in the two-wire to one-wire circuit 310, which helps to improve the application flexibility of the communication component 300 in different scenarios.

[0083] In some embodiments, the communication component 300 may be a connection circuit board independent of the electronic device 100 and the communication device 200.

[0084] In some embodiments, the communication component 300 further includes a sixteenth resistor R16 and a seventeenth resistor R17. One end of the sixteenth resistor R16 is connected to a first port, and the other end of the sixteenth resistor R16 is connected to a first voltage signal VDD01. One end of the seventeenth resistor R17 is connected to a fifth port, and the other end of the seventeenth resistor R17 is connected to a second voltage signal VDD02. The voltage values ​​of the first voltage signal VDD01 and the second voltage signal VDD02 are different. The resistance of one of the sixteenth resistor R16 and the seventeenth resistor is zero, and the resistance of the other is infinite.

[0085] For example, the voltage value of the first voltage signal VDD01 can be 3V, and the voltage value of the second voltage signal VDD02 can be 5V. When the power supply voltage VDD required by the two-wire to single-wire circuit 310 is 3V, the resistance value of the sixteenth resistor R16 is set to zero, and the resistance value of the seventeenth resistor R17 is set to infinity. The 3V power supply voltage VDD can then be supplied to the two-wire to single-wire circuit 310 through the first port. When the power supply voltage VDD required by the two-wire to single-wire circuit 310 is 5V, the resistance value of the sixteenth resistor R16 is set to infinity, and the resistance value of the seventeenth resistor R17 is set to zero. The 5V power supply voltage VDD can then be supplied to the two-wire to single-wire circuit 310 through the fifth port.

[0086] In the electronic system provided in the above embodiments, as long as one of the first input terminal and the second input terminal is connected to the positive terminal of an external charging cable or charging device, and the other is connected to the negative terminal of an external charging cable or charging device, the electronic device can be charged. This avoids short circuits caused by incorrect positive and negative connections, improves the user experience of the electronic device, extends its service life, and avoids safety hazards caused by reverse polarity during charging. Furthermore, it meets the requirements for use in low-voltage circuits, which refer to power supply circuits equal to or less than 5V, avoiding insufficient power supply due to voltage drops caused by transistor characteristics. In addition, by disconnecting the first output terminal from the power supply using a switching circuit, the electronic device can be connected to an external communication device through the first and second input terminals without disassembling the device. This enables communication between the electronic device and the external communication device, thereby achieving serial communication and software programming functions. This helps avoid the impact of disassembly on the electronic device and facilitates simple and efficient communication between the electronic device and the external communication device.

[0087] Another aspect of the present invention provides a control method for an electronic system. It should be noted that the control method for the electronic system is used to control the electronic system provided in the above embodiments of the present invention. The control method for the electronic system has been described in detail in the foregoing embodiments. The control method for the electronic system provided in the present invention can be referred to the foregoing embodiments. The parts that are the same as or corresponding to the foregoing embodiments will not be described again here.

[0088] The control method for the electronic system includes: providing an electronic system as described in any of the above embodiments of the present invention, the electronic system comprising: an electronic device and a communication device, the electronic device comprising at least: a charging circuit and a switching circuit, the input terminal of the switching circuit being connected to a first output terminal of the charging circuit, the output terminal of the switching circuit being connected to a power supply of the electronic device, and controlling the switching circuit to connect or disconnect the connection path between the first output terminal and the power supply; during the period when the switching circuit connects the first output terminal and the power supply, the electronic device is in charging mode; during the period when the switching circuit disconnects the connection path between the first output terminal and the power supply, the electronic device is in communication mode; in communication mode, the communication device is connected to the first input terminal and the second input terminal of the charging circuit to communicate with the electronic device through the first input terminal or the second input terminal.

[0089] By controlling the electronic system, charging and communication can be achieved using the charging port of the electronic device. Without disassembling the device, it can be connected to an external communication device through the first and second input terminals to realize communication between the electronic device and the external communication device, thereby realizing functions such as serial communication and software burning. This helps to avoid the impact of disassembly on the electronic device and facilitates simple and efficient communication between the electronic device and the external communication device.

[0090] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of the present invention. Any person skilled in the art can make their own variations and modifications without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An electronic system, characterized in that, include: An electronic device, the electronic device comprising at least: A charging circuit has a first input terminal, a second input terminal, and a first output terminal. The charging circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The source of the first transistor is connected to the source of the third transistor, and the source of the first transistor is connected to ground. The gate of the first transistor is connected to the gate of the second transistor, and the drain of the first transistor is connected to the drain of the second transistor. The drain of the first transistor serves as the first input terminal. The source of the second transistor is connected to the source of the fourth transistor, and the source of the second transistor serves as the first output terminal. The drain of the third transistor is connected to the drain of the fourth transistor, and the drain of the third transistor serves as the second input terminal. The gate of the third transistor is connected to the gate of the fourth transistor, and the gate of the third transistor is connected to the first input terminal. The gate of the first transistor is connected to the second input terminal. A switching circuit, wherein the input terminal of the switching circuit is connected to the first output terminal, and the output terminal of the switching circuit is connected to the power supply of the electronic device, and the switching circuit is used to connect or disconnect the connection path between the first output terminal and the power supply. During the period when the switching circuit connects the first output terminal to the power supply, the electronic device is in charging mode; during the period when the switching circuit disconnects the first output terminal from the power supply, the electronic device is in communication mode. In the communication mode, the communication device is connected to the first input terminal and the second input terminal to communicate with the electronic device through the first input terminal or the second input terminal.

2. The electronic system according to claim 1, characterized in that, The electronic device further includes a main control module, which includes at least a first enable terminal; The switching circuit includes a fifth transistor, the gate of which is connected to the first enable terminal, the source of which serves as the input terminal of the switching circuit, and the drain of which serves as the output terminal of the switching circuit. During the period when the gate of the fifth transistor receives the first enable signal from the first enable terminal, the fifth transistor is in the on state; during the period when the gate of the fifth transistor does not receive the first enable signal from the first enable terminal, the fifth transistor is in the off state.

3. The electronic system according to claim 2, characterized in that, The switching circuit further includes a first resistor, and the gate of the fifth transistor is connected to the first enable terminal through the first resistor.

4. The electronic system according to claim 1, characterized in that, The electronic device also includes a main control module. The main control module has at least a second enable terminal, a third enable terminal, a first detection terminal, a second detection terminal, and a third detection terminal. The first detection terminal is connected to the first input terminal, the second detection terminal is connected to the second input terminal, and the third detection terminal is connected to the first output terminal. The electronic device further includes a communication control circuit, which has a second output terminal and a third output terminal. The communication control circuit includes: The sixth transistor has its source as the second output terminal, its drain connected to the first input terminal, and its gate connected to the second enable terminal. The seventh transistor has its source as the third output terminal, its drain connected to the second input terminal, and its gate connected to the third enable terminal. If the third detection terminal receives a communication signal from the first output terminal, the main control module controls the sixth transistor to turn on or off according to the signal received by the first detection terminal, and controls the seventh transistor to turn on or off according to the signal received by the second detection terminal.

5. The electronic system according to claim 4, characterized in that, At the same time, either the first input terminal or the second input terminal sends a first signal to the main control module through the corresponding detection terminal; During the period when the first detection terminal receives the first signal emitted by the first input terminal, the main control module emits a second enable signal from the second enable terminal. During the period when the gate of the sixth transistor receives the second enable signal, the sixth transistor is in the on state, and the second output terminal is connected to the first input terminal to realize the communication device and the electronic device. During the period when the second detection terminal receives the first signal emitted by the second input terminal, the main control module emits a third enable signal from the third enable terminal. During the period when the gate of the seventh transistor receives the third enable signal, the seventh transistor is in the on state, and the third output terminal is connected to the second input terminal to realize the communication device and the electronic device. The sixth transistor is in a cutoff state when its gate does not receive the second enable signal, and the seventh transistor is in a cutoff state when its gate does not receive the third enable signal.

6. The electronic system according to claim 4 or 5, characterized in that, The electronic device further includes: a second resistor, a third resistor, a fourth resistor, and a fifth resistor. The first detection terminal is connected to the first input terminal through the second resistor, one end of the third resistor is connected to the first detection terminal, and the other end of the third resistor is connected to ground; The second detection terminal is connected to the second input terminal through the fourth resistor, one end of the fifth resistor is connected to the second detection terminal, and the other end of the fifth resistor is connected to ground.

7. The electronic system according to claim 4 or 5, characterized in that, The electronic device further includes: a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor. The gate of the sixth transistor is connected to the second enable terminal through the sixth resistor, one end of the seventh resistor is connected to the gate of the sixth transistor, and the other end of the seventh resistor is connected to ground. The gate of the seventh transistor is connected to the third enable terminal through the eighth resistor. One end of the ninth resistor is connected to the gate of the seventh transistor, and the other end of the ninth resistor is connected to ground.

8. The electronic system according to claim 4 or 5, characterized in that, The communication control circuit also includes a tenth resistor, an eleventh resistor, and a twelfth resistor. The first end of the tenth resistor is connected to the first output terminal, the first end of the eleventh resistor is connected to the second end of the tenth resistor, the second end of the eleventh resistor is connected to the first end of the twelfth resistor, the second end of the twelfth resistor is connected to ground, and the second end of the eleventh resistor is connected to the third detection terminal. The first output terminal is connected to the third detection terminal through the tenth and eleventh resistors.

9. The electronic system according to claim 4 or 5, characterized in that, Both the sixth transistor and the seventh transistor are NMOS transistors.

10. The electronic system according to claim 1, characterized in that, The first transistor and the third transistor are both NMOS transistors, and the second transistor and the fourth transistor are both PMOS transistors.

11. The electronic system according to any one of claims 1 to 4, characterized in that, The communication device communicates with the electronic device via a two-to-one converter circuit. The two-to-one converter circuit has a first connection terminal and a second connection terminal. The two-to-one converter circuit includes: An inverter chip and a multi-stage buffer chip are provided. The multi-stage buffer chip includes at least a first-stage buffer, a second-stage buffer, and a third-stage buffer. The input terminal of the third-stage buffer is used to receive the TXD signal output by the communication device. The output terminal of the third-stage buffer is connected to the enable terminal of the second-stage buffer, the input terminal of the first-stage buffer, and the input terminal of the inverter chip. The output terminal of the inverter chip is connected to the enable terminal of the first-stage buffer. The output terminal of the first-stage buffer serves as the first connection terminal. The input terminal of the second-stage buffer is connected to the first connection terminal. The output terminal of the second-stage buffer is used to output the RXD signal to the communication device. The second connection terminal is connected to ground. In the communication mode, the first connection terminal is connected to either the first input terminal or the second input terminal, and the second connection terminal is connected to either the first input terminal or the second input terminal. The first connection terminal transmits DATA signals to the electronic device.

12. The electronic system according to claim 11, characterized in that, The two-wire to single-wire circuit also includes: a thirteenth resistor, a fourteenth resistor, and a fifteenth resistor. One end of the thirteenth resistor is connected to the output terminal of the first-stage buffer, and the other end of the thirteenth resistor is connected to the power supply voltage; One end of the fifteenth resistor is connected to the input terminal of the inverter chip, and the other end of the fifteenth resistor is connected to the power supply voltage. The enable terminal of the third-level buffer is connected to the power supply voltage through the fourteenth resistor.

13. The electronic system according to claim 11, characterized in that, The electronic system includes a communication component, the two-wire to single-wire circuit is disposed within the communication component, and the communication component also includes a connector. The connector includes a first port, a second port, a third port, a fourth port, and a fifth port. The first port or the fifth port provides power to the two-wire to single-wire circuit, and the fourth port provides ground voltage to the two-wire to single-wire circuit. The second port is connected to the input terminal of the third-stage buffer to receive the TXD signal, and the third port is connected to the output terminal of the first-stage buffer to output the RXD signal.

14. The electronic system according to claim 13, characterized in that, The communication component also includes a sixteenth resistor and a seventeenth resistor. One end of the sixteenth resistor is connected to the first port, and the other end of the sixteenth resistor is connected to the first voltage signal. One end of the seventeenth resistor is connected to the fifth port, and the other end of the seventeenth resistor is connected to the second voltage signal. The voltage value of the first voltage signal is different from the voltage value of the second voltage signal. Among them, the resistance of the sixteenth resistor and the seventeenth resistor is zero, and the resistance of the other is infinite.

15. A control method for an electronic system, characterized in that, include: Provide an electronic system as claimed in any one of claims 1-14, said electronic system comprising: Electronic devices and communication devices, wherein the electronic devices include at least: a charging circuit and a switching circuit, wherein the input terminal of the switching circuit is connected to the first output terminal of the charging circuit, and the output terminal of the switching circuit is connected to the power supply of the electronic devices, and the connection path between the first output terminal and the power supply is turned on or off by controlling the switching circuit; During the period when the switching circuit connects the first output terminal to the power supply, the electronic device is in charging mode. During the period when the switching circuit disconnects the first output terminal from the power supply, the electronic device is in communication mode. In communication mode, the communication device is connected to the first input terminal and the second input terminal of the charging circuit to communicate with the electronic device through the first input terminal or the second input terminal.

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