Power conversion apparatus and electronic device

Abstract

Provided in the embodiments of the present invention are a power conversion apparatus and an electronic device. The power conversion apparatus comprises: a power conversion circuit, which comprises a first switch transistor, a second switch transistor and an inductor unit, wherein one end of the inductor unit is connected to a first bias voltage, and the other end of the inductor unit is connected to a second bias voltage by means of the first switch transistor; a signal processing circuit, which is connected to the power conversion circuit, wherein the signal processing circuit is used for performing pulse width modulation on an input signal, so as to obtain a first PWM signal and a second PWM signal, which are timing-matched, and outputting the first PWM signal and the second PWM signal to the first switch transistor and the second switch transistor, respectively, so as to alternately control the on-off of the first switch transistor and the second switch transistor; and a power output circuit, which is connected to the other end of the inductor unit by means of the second switch transistor, wherein the power output circuit is used for outputting an output conversion signal for the input signal.

Description

Power conversion devices and electronic equipment

[0001] This application claims priority to Chinese Patent Application No. 202410913803.X, filed on July 8, 2024, entitled "Power Conversion Device and Electronic Equipment", the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention relates to the field of electronic circuit technology, and in particular to a power conversion device and an electronic device. Background Technology

[0003] Power conversion devices, such as power converters, change signal voltage by boosting or bucking it. Signal processing circuits process the signal to obtain a series of PWM (Pulse Width Modulation) signals, which are then amplified and output to drive capacitive loads. These power conversion devices are widely used in applications requiring voltage conversion and power amplification, such as audio amplifiers, power supplies, and motor drivers.

[0004] In the prior art, power conversion devices require PWM signals to control the on and off of a large number of switching transistors when performing signal conversion. However, a large number of switching transistors often occupy a large area, which is not conducive to the miniaturization of power conversion devices and electronic devices carrying power conversion devices.

[0005] Summary of the Invention

[0006] In view of this, embodiments of the present invention provide a power conversion device and an electronic device to solve the above problems.

[0007] According to a first aspect of the present invention, a power conversion device is provided, comprising: a power conversion circuit including a first switching transistor, a second switching transistor, and an inductor unit, wherein one end of the inductor unit is connected to a first bias voltage, and the other end of the inductor unit is connected to a second bias voltage through the first switching transistor; a signal processing circuit connected to the power conversion circuit, the signal processing circuit being configured to perform pulse width modulation on an input signal to obtain a timing-matched first PWM signal and a second PWM signal, and outputting the first PWM signal and the second PWM signal to the first switching transistor and the second switching transistor respectively, so as to alternately control the on / off state of the first switching transistor and the second switching transistor; and a power output circuit connected to the other end of the inductor unit through the second switching transistor, the power output circuit being configured to output an output conversion signal of the input signal.

[0008] In another implementation of the present invention, the power conversion circuit further includes a third switching transistor, and the power output circuit is connected to the other end of the inductor unit through the third switching transistor; the signal processing circuit is used to: perform pulse width modulation on the input signal in the first half of the whole cycle of the input signal to obtain a timing-matched first PWM signal and a second PWM signal, and perform pulse width modulation on the input signal in the second half of the whole cycle of the input signal to obtain a timing-matched first PWM signal and a third PWM signal, wherein the first PWM signal and the third PWM signal are respectively used to control the on / off state of the first switching transistor and the third switching transistor.

[0009] In another implementation of the present invention, the signal processing circuit is configured to: perform pulse width modulation on the input signal at the sampling point of the first half-cycle according to a first preset duty cycle to obtain a first PWM signal and a second PWM signal with timing matching in the first half-cycle; and perform pulse width modulation on the sampling point of the second half-cycle according to a second preset duty cycle to obtain a first PWM signal and a third PWM signal with timing matching in the second half-cycle, wherein the first preset duty cycle and the second preset duty cycle are complementary.

[0010] In another implementation of the present invention, the third PWM signal is used to control the third switch to be in a normally off state during the second half-cycle, and the second PWM signal is used to control the second switch to be in a normally off state during the second half-cycle.

[0011] In another implementation of the present invention, the power output circuit includes a first output terminal and a second output terminal. The first output terminal is connected to the other end of the inductor unit through the second switch, and the second output terminal is connected to the other end of the inductor unit through the third switch. The power output circuit outputs an output conversion signal of the input signal between the first output terminal and the second output terminal.

[0012] In another implementation of the invention, the power output circuit further includes a fourth switch and a fifth switch, the fourth switch being connected between the first output terminal and the third bias voltage, and the fifth switch being connected between the second output terminal and the third bias voltage. The signal processing circuit is further configured to: generate a first commutation signal and a second commutation signal, the first commutation signal controlling the fourth switch to be normally off in the first half-cycle and normally on in the second half-cycle, wherein the second commutation signal controls the fifth switch to be normally on in the first half-cycle and normally off in the second half-cycle.

[0013] In another implementation of the present invention, in the in-phase conversion mode, the first output terminal is connected to the positive terminal of the capacitive load, and the second output terminal is connected to the negative terminal of the capacitive load; in the out-of-phase conversion mode, the first output terminal is connected to the negative terminal of the capacitive load, and the second output terminal is connected to the positive terminal of the capacitive load.

[0014] In another embodiment of the present invention, the power conversion device further includes a substrate selection circuit, wherein at least one of the second and third switching transistors is a MOSFET, and the substrate selection circuit is connected to the source, drain, and substrate of the MOSFET, respectively. Specifically, when the MOSFET is a P-type MOSFET, the substrate selection circuit connects the substrate to the higher voltage of the drain and source, and when the MOSFET is an N-type MOSFET, the substrate connects the substrate to the lower voltage of the drain and source.

[0015] In another implementation of the present invention, in the boost conversion mode, the first bias voltage is greater than the second bias voltage; in the buck conversion mode, the first bias voltage is less than the second bias voltage.

[0016] According to a second aspect of the present invention, an electronic device is provided, comprising: a capacitive load; and a power conversion device according to the first aspect, wherein the power conversion device provides an output conversion signal to the capacitive load.

[0017] In the capacitive load driving scheme of this invention, the switching on and off of the first and second switching transistors are alternately controlled by the converted first PWM signal and second PWM signal, and the power output circuit obtains a voltage signal that matches the waveform of the input signal. Furthermore, when the first and second switching transistors are alternately switched on and off, a back electromotive force is generated because the transient current of the inductor unit remains constant. Therefore, through the voltage difference between the second bias voltage and the first bias voltage, the power output circuit obtains the voltage signal after the first bias voltage has been boosted or bucked. Thus, by reusing the aforementioned switching transistors for power conversion and waveform matching, the number of switching transistors used in the power conversion device is reduced, thereby facilitating the miniaturization of the power conversion device. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0019] Figure 1 is a schematic structural diagram of a power conversion device according to some embodiments of the present invention.

[0020] Figure 2 is a schematic structural diagram of a power conversion device, a further example of the embodiment of Figure 1.

[0021] Figure 3 is a circuit diagram of the power conversion device of the embodiments in Figures 1 and 2.

[0022] Figure 4 is a signal timing diagram of each switching transistor in the embodiment of Figure 3.

[0023] Figure 5 is a circuit diagram of the substrate selection circuit in the embodiment of Figure 1 in the power conversion device.

[0024] Figure 6 is a schematic structural diagram of the substrate selection circuit in Figure 5.

[0025] Figures 7A and 7B are structural diagrams of other variations of the switching transistor.

[0026] Figure 8 is a schematic diagram of the structure of an electronic device according to some other embodiments of the present invention. Detailed Implementation

[0027] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art should fall within the protection scope of the present invention.

[0028] The specific implementation of the embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0029] Figure 1 illustrates a power conversion device according to some embodiments of the present invention. The power conversion device 100 of Figure 1 includes a power conversion circuit 110, a signal processing circuit 120, and a power output circuit 130.

[0030] Specifically, the power conversion circuit 110 includes a first switching transistor, a second switching transistor, and an inductor unit, wherein one end of the inductor unit is connected to a first bias voltage, and the other end of the inductor unit is connected to a second bias voltage through the first switching transistor.

[0031] It should be understood that transistor M1 can be an example of a first switching transistor, transistor M2 can be an example of a second switching transistor, and inductor L is an example of an inductor unit. An inductor unit can also include a structure formed by multiple inductors connected in series or parallel. Furthermore, in boost conversion mode, the first bias voltage is greater than the second bias voltage; for example, the voltage value of VDD (an example of the first bias voltage) is greater than the voltage value of ground (an example of the second bias voltage). In buck conversion mode, the first bias voltage is less than the second bias voltage; for example, the voltage value of ground (an example of the first bias voltage) is less than the voltage value of VDD (an example of the second bias voltage).

[0032] Furthermore, the signal processing circuit 120 is connected to the power conversion circuit. The signal processing circuit 120 is used to perform pulse width modulation on the input signal to obtain a timing-matched first PWM signal (e.g., PWM1 signal in Figure 1) and a second PWM signal (e.g., PWM2 signal in Figure 1). The first PWM signal and the second PWM signal are output to the first switch and the second switch respectively to alternately control the on and off of the first switch and the second switch. That is, the other end SW (switch) of the inductor unit switches between the state connected to the second bias voltage and the state connected to the first output terminal.

[0033] It should be understood that in some examples, the signal processing circuit can perform pulse width modulation (PWM) on the sampling points of the input signal according to a first preset duty cycle to obtain a timing-matched first PWM signal and a second PWM signal. For example, the timing matching of the first PWM signal and the second PWM signal is used to alternately turn the first switch and the second switch on and off, so as to alternately output high and low voltages at the first output terminal, forming an output conversion signal. That is, the voltage after the first bias voltage is boosted is used as the high voltage, and the third bias voltage is used as the low voltage, or the third bias voltage is used as the high voltage, and the voltage after the first bias voltage is bucked is used as the low voltage.

[0034] Furthermore, the power output circuit 130 is connected to the other end of the inductor unit through the second switching transistor, and the power output circuit 130 is used to output the output conversion signal of the input signal.

[0035] It should be understood that the power output circuit 130 includes a first output terminal (Vout1) and a second output terminal (not shown), and a capacitive load, such as a capacitor or a piezoelectric appliance, can be connected between the first and second output terminals. Generally, a capacitive load is a load that exhibits capacitive characteristics when current flows through it; that is, a capacitive load can store electrical energy and release that energy when needed. In some examples, one of the first and second output terminals can be connected to the other end of an inductor unit via a second switching transistor, and the other can be connected to a third bias voltage, which may have a voltage value independent of the first and second bias voltages.

[0036] In the embodiment shown in Figure 1, the waveform of the input signal can be a periodic waveform, which can be half-period symmetrical or not.

[0037] In the capacitive load driving scheme of this invention, the switching on and off of the first and second switching transistors are alternately controlled by the converted first PWM signal and second PWM signal, and the power output circuit obtains a voltage signal that matches the waveform of the input signal. Furthermore, when the first and second switching transistors are alternately switched on and off, a back electromotive force is generated because the transient current of the inductor unit remains constant. Therefore, through the voltage difference between the second bias voltage and the first bias voltage, the power output circuit obtains the voltage signal after the first bias voltage has been boosted or bucked. Thus, by reusing the aforementioned switching transistors for power conversion and waveform matching, the number of switching transistors used in the power conversion device is reduced, which is beneficial for the miniaturization of the power conversion device.

[0038] Figure 2 illustrates a further example of the power conversion device of the embodiment of Figure 1. As shown in Figure 2, the power conversion circuit 110 further includes a third switching transistor, and the power output circuit 130 includes a capacitive load. The two ends of the capacitive load serve as a first output terminal and a second output terminal. The first output terminal is connected to the other end of the inductor unit through the second switching transistor, and the second output terminal is connected to the other end of the inductor unit through the third switching transistor (M3 is an example of the third switching transistor). Furthermore, examples of the first PWM signal, the second PWM signal, and the third PWM signal are PWM1, PWM2, and PWM3 signals in Figure 2, respectively.

[0039] In the embodiment of Figure 2, the waveform of the input signal has half-cycle symmetry, that is, the first half-cycle and the second half-cycle are symmetrical about the horizontal axis representing time. More specifically, for a sinusoidal input signal, the first half-cycle can also be a positive half-cycle, and the second half-cycle can be a negative half-cycle. This is because the sinusoidal waveform has a positive signal amplitude in the vertical axis representing signal amplitude in the first half-cycle, and a negative signal amplitude in the vertical axis representing signal amplitude in the second half-cycle. Accordingly, the signal processing circuit 120 is used to: perform pulse width modulation on the input signal in the first half-cycle of the entire cycle of the input signal to obtain a timing-matched first PWM signal and a second PWM signal, and perform pulse width modulation on the input signal in the second half-cycle of the entire cycle of the input signal to obtain a timing-matched first PWM signal and a third PWM signal, wherein the first PWM signal and the third PWM signal are used to control the on / off state of the first switch and the third switch, respectively.

[0040] In other words, during the first half of the cycle, the other end (SW) of the inductor unit switches between being connected to the second bias voltage and being connected to the first output terminal via the first PWM signal and the second PWM signal. During the second half of the cycle, the other end (SW) of the inductor unit switches between being connected to the second bias voltage and being connected to the second output terminal via the first PWM signal and the third PWM signal.

[0041] In the embodiment of the invention, the switching on and off of the first and third switching transistors are alternately controlled by the converted first and third PWM signals, and the power output circuit obtains a voltage signal that matches the waveform of the input signal. Furthermore, when the switching on and off of the first and third switching transistors are alternately controlled, a back electromotive force is generated due to the constant transient current of the inductor unit. Therefore, through the voltage difference between the second and first bias voltages, the power output circuit obtains the voltage signal after the first bias voltage has been boosted or bucked. Thus, by reusing the aforementioned switching transistors for power conversion and waveform matching, the number of switching transistors used in the power conversion device is reduced, thereby facilitating the miniaturization of the power conversion device.

[0042] Furthermore, the first and second PWM signals are time-matched in the first half of the cycle, and the first and third PWM signals are time-matched in the second half of the cycle, achieving the conversion of inversely symmetrical waveform signals such as sine or triangular waveforms within the entire cycle. The first PWM signal controls the on / off state of the first switching transistor throughout the entire cycle, fully utilizing the waveform conversion capability of the first switching transistor, thereby further reducing the number of switching transistors used. For waveform signals such as sine waves, in some examples, the first half of the cycle can be a positive half-cycle and the second half of the cycle can be a negative half-cycle; alternatively, the first half of the cycle can be a negative half-cycle and the second half of the cycle can be a positive half-cycle.

[0043] Furthermore, in this embodiment, the first output terminal can be connected to the other end of the inductor unit through the second switching transistor, and the second output terminal can be connected to the other end of the inductor unit through the third switching transistor.

[0044] Without loss of generality, when connecting via a switching transistor, the non-controllable terminals of the switching transistor can be connected. In the example where the switching transistor is a MOSFET, the source and drain are non-controllable terminals, and the gate is the control terminal. When the switching transistor is a transistor, one of the collector, emitter, and base can be the control terminal, and the other two can be non-controllable terminals (the first and second terminals). For example, the first terminal of the second switching transistor is connected to the first output terminal, and the second terminal of the second switching transistor is connected to the other end of the inductor unit. As another example, the first terminal of the third switching transistor is connected to the second output terminal, and the second terminal of the third switching transistor is connected to the other end of the inductor unit.

[0045] In other words, the first output terminal is connected to the other end of the inductor unit through the second switching transistor, and the second output terminal is connected to the other end of the inductor unit through the third switching transistor. The power output circuit outputs the output conversion signal of the input signal between the first output terminal and the second output terminal.

[0046] In the connection relationship of this embodiment, the input terminal of the signal processing circuit receives the input signal, and after processing the input signal, outputs a timing-matched first PWM signal, a second PWM signal, and a third PWM signal from the first output terminal, the second output terminal, and the third output terminal (not shown), respectively. The first output terminal, the second output terminal, and the third output terminal are respectively connected to the control terminals of the first switch, the second switch, and the third switch.

[0047] In other specific examples, the signal processing circuit is used to: perform pulse width modulation on the sampling points of the input signal in the first half of the cycle according to a first preset duty cycle, to obtain a first PWM signal and a second PWM signal that are time-matched in the first half of the cycle. For example, the first PWM signal and the second PWM signal are time-matched in the first half of the cycle to alternately turn the first switch and the second switch on and off, so as to alternately output high and low voltages at the first output terminal, forming an output conversion signal.

[0048] The signal processing circuit is also used to: perform pulse width modulation at the sampling points in the second half of the cycle according to the second preset duty cycle, to obtain a first PWM signal and a third PWM signal with timing matching in the second half of the cycle, wherein the first preset duty cycle and the second preset duty cycle are complementary. For example, the first PWM signal and the third PWM signal are time-matched in the second half of the cycle to alternately turn the first switch and the third switch on and off, so as to alternately output high and low voltages at the second output terminal, forming an output conversion signal.

[0049] For example, as an example of the first preset duty cycle and the second preset duty cycle being complementary, the sum of the first preset duty cycle and the second preset duty cycle is 1. In this case, the amplitude of the output waveform in the first half cycle and the amplitude of the output waveform in the second half cycle are precisely symmetrical about the time axis.

[0050] In other specific examples, the third PWM signal is used to control the third switch to be normally off in the second half of the cycle, and the second PWM signal is used to control the second switch to be normally off in the second half of the cycle. This ensures that the second and third switches are normally off in their respective half-cycles while maintaining a continuous PWM signal output. Furthermore, this method can counteract the effect of the third bias voltage on the output conversion signal between the first and second output terminals.

[0051] In other embodiments, the power output circuit further includes a fourth switch and a fifth switch. The fourth switch is connected between the first output terminal and the third bias voltage, and the fifth switch is connected between the second output terminal and the third bias voltage. The signal processing circuit is further configured to generate a first commutation signal and a second commutation signal. The first commutation signal controls the fourth switch to be normally off in the first half-cycle and normally on in the second half-cycle. The second commutation signal controls the fifth switch to be normally on in the first half-cycle and normally off in the second half-cycle. This ensures that the fourth and fifth switches are in their normally off and normally on states in corresponding half-cycles while maintaining a continuous output commutation signal, avoiding the simultaneous on or off states of the fourth and fifth switches. Furthermore, the normally off and normally on states of the fourth and fifth switches in corresponding half-cycles reduce the overall number of on / off operations of the switches in the power conversion circuit, saving power consumption caused by on / off operations.

[0052] The signal conversion process of some embodiments of the present invention will now be described in detail with reference to Figures 3 and 4. Figure 3 illustrates the circuit diagram applicable to the signal conversion process of this embodiment. Figure 4 shows the timing diagrams of the corresponding control signals, specifically described and explained in conjunction with the positive and negative half-cycles of the sinusoidal waveform signal.

[0053] It should be understood that in the example of Figure 3, the first switching transistor is M1, the second switching transistor is M2, and the third switching transistor is M3, and the inductor unit is exemplarily implemented as inductor L. During the first half-cycle (e.g., time period T1 in Figure 4), the other end (SW) of the inductor unit switches between being connected to the second bias voltage and being connected to the first output terminal via the first PWM signal and the second PWM signal. During the second half-cycle (e.g., time period T2 in Figure 4), the other end (SW) of the inductor unit switches between being connected to the second bias voltage and being connected to the second output terminal via the first PWM signal and the third PWM signal.

[0054] Furthermore, the first bias voltage is VDD, and the second bias voltage is the ground voltage. Also, as shown in Figure 3, the first output terminal Vout1 outputs the HDP signal, and the second output terminal Vout2 outputs the HDN signal. In the embodiments of Figures 3 and 4, taking a sinusoidal waveform (i.e., a sine wave) signal as an example, the entire period of the sinusoidal waveform can be divided into a first half-period and a second half-period. The first half-period can be a positive half-period, and the second half-period can be a negative half-period. For example, the positive half-period and the negative half-period are time periods T1 and T2 in Figure 4, respectively. That is, the first half-period of each entire period is time-continuous with the second half-period of that entire period, and the second half-period of each entire period is time-continuous with the first half-period of the next entire period. For a sinusoidal waveform signal, the first half-period is the positive half-period, and the second half-period is the negative half-period.

[0055] It should also be understood that in this embodiment, the power conversion device performs signal amplification processing, that is, the first bias voltage is greater than the second bias voltage, for example, the first bias voltage is VDD and the second bias voltage is ground voltage.

[0056] It should also be understood that in the example shown in Figure 3, the power output circuit includes a fourth switch and a fifth switch, with M4 being an example of the fourth switch and M5 being an example of the fifth switch. The LS1 signal is an example of the first commutation signal used to control the on / off state of M4, and the LS2 signal is an example of the second commutation signal used to control the on / off state of M5. The power output circuit also includes a first output terminal and a second output terminal. The first output terminal is used to output a high-side positive drive signal (HDP), and the second output terminal is used to output a high-side negative drive signal (HDN). Furthermore, a capacitive load, such as a capacitor or piezoelectric appliance, is connected between the first and second output terminals; that is, the input signal, after being converted by the power conversion device, is output between the first and second output terminals.

[0057] It should also be understood that, as the input signal to be converted, in boost conversion mode, the voltage difference Vpp between the peak and valley values ​​of the input signal has a small amplitude, while the voltage difference Vpp between the peak and valley values ​​of the output converted signal has a large amplitude. Furthermore, the signal processing circuit performs pulse width modulation on the input signal to obtain a first PWM signal, a second PWM signal, and a third PWM signal containing "input signal" information, for example, PWM1, PWM2, and PWM3 signals as shown in Figure 4. Additionally, the first PWM signal, the second PWM signal, and the third PWM signal are used to control transistors M1, M2, and M3, respectively.

[0058] As shown in Figure 4, the output conversion signal of the HDP signal during time period T1 is a sine wave signal with a positive half-cycle, and the signal of the HDN signal during time period T2 is a sine wave signal with a negative half-cycle. After concatenating the positive and negative half-cycle sine wave signals, a sine wave signal with a full cycle is obtained. It should be understood that the switching between the polarity of the output conversion signal in the first half-cycle and the polarity in the second half-cycle is performed by transistors M4 and M5.

[0059] It should be understood that although in the example of Figure 4, a schematic high level indicates that the switch is in the ON state and a schematic low level indicates that the switch is in the OFF state, the OFF state of the switch has actual voltage levels, and is not necessarily a schematic voltage level, depending on the specific implementation of the switch. For example, in the first half of the cycle, the PWM1 signal and the PWM2 signal have opposite voltage levels, and in the second half of the cycle, the PWM1 signal and the PWM3 signal have opposite voltage levels. However, the above examples are merely for illustrative and explanatory purposes and should not be construed as limiting the embodiments of the present invention.

[0060] Furthermore, during time period T1, the amplification factor of the power conversion device is determined by the signal processing circuit, which generates the corresponding PWM1 and PWM2 signals. As shown in Figure 4, during time period T1, transistor M3 is normally off, transistor M4 is normally off under the control of signal LS1, and transistor M5 is normally on under the control of signal LS2. The signal processing circuit receives the positive half-cycle of the sinusoidal waveform signal as the input signal, performs pulse width modulation on the sinusoidal waveform signal, and obtains the PWM1 and PWM2 signals containing the signal information of the input signal. During time period T1, the on / off state of transistors M1 and M2 is controlled by the PWM1 and PWM2 signals respectively, amplifying the sinusoidal waveform signal to the HDP signal for output. At this time, the output of the HDN signal during time period T1 is VS (an example of the third bias voltage). That is, transistor M5 is normally on during time period T1, the voltage of the HDN signal during time period T1 is VS, and the HDP signal during time period T1 is the amplified positive half-cycle sinusoidal waveform signal. Correspondingly, during the T1 period, the voltage difference Vp between the HDP signal and the HDN signal is a sinusoidal waveform signal with a positive half-cycle (in the boost conversion mode, VDD is boosted to PVDD), which is applied to the capacitive load between the first output terminal of the HDP signal and the second output terminal of the HDN signal.

[0061] Without loss of generality, the third PWM signal is used to control the third switch to be normally off during the second half-cycle, and the second PWM signal is used to control the second switch to be normally off during the second half-cycle. This ensures that the second and third switches are normally off during their respective half-cycles while maintaining a continuous PWM signal output. Furthermore, this method can counteract the effect of the third bias voltage on the output conversion signal between the first and second output terminals.

[0062] Furthermore, during time period T2, the amplification factor of the power conversion device is determined by the signal processing circuit, generating the corresponding PWM1 and PWM3 signals. As shown in Figure 4, at time T2, transistor M2 is normally off, transistor M5 is normally off under the control of signal LS2, and transistor M4 is normally on under the control of signal LS1. The signal processing circuit receives the negative half-cycle of the sinusoidal waveform signal as the input signal, performs pulse width modulation on the sinusoidal waveform signal, and obtains the PWM1 and PWM3 signals containing the signal information of the input signal. During time period T2, the on / off state of transistors M1 and M3 is controlled by the PWM1 and PWM3 signals respectively, amplifying the sinusoidal waveform signal to the HDN signal for output. At this time, the output of the HDP signal during time period T1 is VS (an example of the third bias voltage). That is, transistor M4 is normally on during time period T2, the voltage of the HDP signal during time period T2 is VS, and the HDN signal during time period T2 is the amplified sinusoidal waveform signal of the negative half-cycle. Correspondingly, the voltage difference Vp between the HDP signal and the HDN signal is a sinusoidal waveform signal with a negative half-cycle (in boost conversion mode, VDD is boosted to PVDD), which is applied to the capacitive load between the first output terminal of the HDP signal and the second output terminal of the HDN signal. This ensures that the amplified sinusoidal waveform signal, which is the output conversion signal, is in phase with the sinusoidal waveform signal, which is the input signal, thus forming a full-cycle signal output. For example, the voltage difference Vpp between the peak and valley values ​​of the output conversion signal can reach up to 2PVDD.

[0063] Without loss of generality, the third PWM signal is used to control the third switch to be normally off during the second half-cycle, and the second PWM signal is used to control the second switch to be normally off during the second half-cycle. This ensures that the second and third switches are normally off during their respective half-cycles while maintaining a continuous PWM signal output. Furthermore, this method can counteract the effect of the third bias voltage on the output conversion signal between the first and second output terminals.

[0064] It should also be understood that the HDP signal is the output signal of the first output terminal, and the HDN signal is the output signal of the second output terminal. Without loss of generality, the signal processing circuit outputs a first commutation signal (e.g., LS1 signal) and a second commutation signal (e.g., LS2 signal) from the fourth and fifth output terminals, respectively. The first and second commutation signals are output to the control terminals of the fourth switch (e.g., M4) and the fifth switch (e.g., M5), respectively. For example, the fourth and fifth output terminals (not shown) are connected to the control terminals of the fourth and fifth switches, respectively. It should be understood that the normally off and normally on states of the fourth and fifth switches in corresponding half-cycles reduce the overall number of on / off operations of each switch in the power conversion circuit, saving power consumption caused by on / off operations.

[0065] Alternatively, in the case of signal commutation, if transistor M3 is normally off during period T2, transistor M4 is normally off during period T2 controlled by signal LS1, and transistor M5 is normally on during period T2 controlled by signal LS2, the signal processing circuit performs pulse width modulation on the received negative half-cycle sinusoidal waveform signal to obtain PWM1 and PWM2 signals. PWM1 and PWM2 signals are then used to control transistors M1 and M2, respectively. Simultaneously, the sinusoidal waveform signal is amplified to output as HDP, and the output of HDN is VS. At this time, the voltage difference between HDP and HDN signals is equal to the positive half-cycle sinusoidal waveform signal, achieving inversion of the output conversion signal and input signal in the inverting conversion mode.

[0066] Without loss of generality, in the in-phase conversion mode, the first output terminal is connected to the positive terminal of the capacitive load, and the second output terminal is connected to the negative terminal of the capacitive load. That is, the output terminal connected to the positive terminal of the capacitive load is considered the first output terminal, and the output terminal connected to the negative terminal of the capacitive load is considered the second output terminal.

[0067] Accordingly, in the inverting conversion mode, the first output terminal is connected to the negative terminal of the capacitive load, and the second output terminal is connected to the positive terminal of the capacitive load. That is, the output terminal connected to the positive terminal of the capacitive load is considered the second output terminal, and the output terminal connected to the negative terminal of the capacitive load is considered the first output terminal.

[0068] In other embodiments, the power conversion device 100 further includes a substrate selection circuit, wherein at least one of the second and third switching transistors is a MOSFET, and the substrate selection circuit is connected to the source, drain, and substrate of the MOSFET, respectively. Specifically, when the MOSFET is a P-type MOSFET, the substrate selection circuit connects the substrate to the higher voltage of the drain and source terminals, and when the MOSFET is an N-type MOSFET, the substrate connects the substrate to the lower voltage of the drain and source terminals. As shown in FIG5, as some examples, the substrate selection circuit is connected to the second switching transistor (e.g., transistor M2) and the third switching transistor (e.g., transistor M3). Generally, when any of the first, second, third, fourth, and fifth switching transistors is a MOSFET, the substrate selection circuit may be connected to the source, drain, and substrate of that MOSFET.

[0069] Specifically, as shown in Figure 6, in the example where the MOSFET is either M2 or M3, the substrate selection circuit includes a comparator. The first and second input terminals of the comparator are connected to the drain and source of the MOSFET, respectively. For example, as shown in Figure 6, the positive input terminal "+" of the comparator is connected to the drain of the MOSFET, and the negative input terminal "-" is connected to the source of the MOSFET. The comparator compares the drain voltage and the source voltage. If the MOSFET is a P-type MOSFET, the comparator outputs the voltage with the higher drain-source voltage. The substrate selection circuit then connects the substrate to the higher drain-source voltage. If the MOSFET is an N-type MOSFET, the comparator outputs the voltage with the lower drain-source voltage. The substrate selection circuit then connects the substrate to the lower drain-source voltage.

[0070] In other embodiments, any of the switching transistors in the power conversion device (e.g., the first, second, third, fourth, and fifth switching transistors) can be implemented using at least two MOSFETs connected in series. For example, in the example of Figure 7A, transistors M11 and M12 are both P-type MOSFETs, the drain of transistor M11 is connected to the drain of transistor M12, the source of transistor M11 and the source of transistor M12 are the two non-control terminals of the switching transistor, and the gate of transistor M11 and the gate of transistor M12 can be used as the control terminals of the switching transistor. As another example, in the example of Figure 7B, transistors M13 and M14 are both P-type MOSFETs, the source of transistor M13 is connected to the source of transistor M14, the drain of transistor M13 and the drain of transistor M14 are the two non-control terminals of the switching transistor, and the gate of transistor M13 and the gate of transistor M14 can be used as the control terminals of the switching transistor.

[0071] This invention also provides an electronic device 800, which includes a power conversion device 100 and a capacitive load 810. It should be understood that the specific implementation in the electronic device can be found in the corresponding steps, modules, or units described in the embodiments of the power conversion device, and will have corresponding beneficial effects; therefore, it will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the power conversion device in the electronic device can be referred to the corresponding process descriptions in the foregoing embodiments of the power conversion device, and will not be repeated here.

[0072] Specific embodiments of the subject matter have now been described. Other embodiments are within the scope of the appended claims. In some cases, the actions described in the claims can be performed in a different order and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing can be advantageous.

[0073] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0074] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0075] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0076] The above description is merely an embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of this application should be included within the scope of the claims of this application.

Claims

1. A power conversion device, characterized in that, include: A power conversion circuit includes a first switching transistor, a second switching transistor, and an inductor unit, wherein one end of the inductor unit is connected to a first bias voltage, and the other end of the inductor unit is connected to a second bias voltage through the first switching transistor; A signal processing circuit is connected to the power conversion circuit. The signal processing circuit is used to perform pulse width modulation on the input signal to obtain a timing-matched first PWM signal and a second PWM signal, and outputs the first PWM signal and the second PWM signal to the first switch and the second switch respectively, so as to alternately control the on and off of the first switch and the second switch. The power output circuit is connected to the other end of the inductor unit through the second switching transistor, and the power output circuit is used to output the output conversion signal of the input signal.

2. The power conversion device according to claim 1, characterized in that, The power conversion circuit also includes a third switching transistor, and the power output circuit is connected to the other end of the inductor unit through the third switching transistor. The signal processing circuit is used to: perform pulse width modulation on the input signal in the first half of the whole cycle of the input signal to obtain a timing-matched first PWM signal and a second PWM signal, and perform pulse width modulation on the input signal in the second half of the whole cycle of the input signal to obtain a timing-matched first PWM signal and a third PWM signal, wherein the first PWM signal and the third PWM signal are used to control the on / off state of the first switch and the third switch, respectively.

3. The power conversion device according to claim 2, characterized in that, The signal processing circuit is used to: perform pulse width modulation on the input signal at the sampling point of the first half-cycle according to a first preset duty cycle to obtain a first PWM signal and a second PWM signal with timing matching in the first half-cycle; and perform pulse width modulation on the sampling point of the second half-cycle according to a second preset duty cycle to obtain a first PWM signal and a third PWM signal with timing matching in the second half-cycle, wherein the first preset duty cycle and the second preset duty cycle are complementary.

4. The power conversion device according to claim 2, characterized in that, The third PWM signal is used to control the third switch to be in a normally off state during the second half of the cycle, and the second PWM signal is used to control the second switch to be in a normally off state during the second half of the cycle.

5. The power conversion device according to claim 4, characterized in that, The power output circuit includes a first output terminal and a second output terminal. The first output terminal is connected to the other end of the inductor unit through the second switch, and the second output terminal is connected to the other end of the inductor unit through the third switch. The power output circuit outputs an output conversion signal of the input signal between the first output terminal and the second output terminal.

6. The power conversion device according to claim 5, characterized in that, The power output circuit further includes a fourth switch and a fifth switch. The fourth switch is connected between the first output terminal and the third bias voltage, and the fifth switch is connected between the second output terminal and the third bias voltage. The signal processing circuit is further configured to: generate a first commutation signal and a second commutation signal, wherein the first commutation signal is configured to control the fourth switch to be normally off in the first half-cycle and normally on in the second half-cycle, and wherein the second commutation signal is configured to control the fifth switch to be normally on in the first half-cycle and normally off in the second half-cycle.

7. The power conversion device according to claim 5, characterized in that, In the in-phase conversion mode, the first output terminal is connected to the positive terminal of the capacitive load, and the second output terminal is connected to the negative terminal of the capacitive load; in the out-of-phase conversion mode, the first output terminal is connected to the negative terminal of the capacitive load, and the second output terminal is connected to the positive terminal of the capacitive load.

8. The power conversion device according to claim 5, characterized in that, The power conversion device further includes a substrate selection circuit, wherein at least one of the second switch and the third switch is a MOSFET, and the substrate selection circuit is connected to the source, drain and substrate of the MOSFET respectively. In this circuit, when the MOS transistor is a P-type MOS transistor, the substrate is connected to the one with the higher voltage between the drain and the source. When the MOS transistor is an N-type MOS transistor, the substrate is connected to the one with the lower voltage between the drain and the source.

9. The power conversion device according to any one of claims 1-8, characterized in that, In boost conversion mode, the first bias voltage is greater than the second bias voltage; in buck conversion mode, the first bias voltage is less than the second bias voltage.

10. An electronic device, characterized in that, include: Capacitive load; The power conversion device according to any one of claims 1-9 provides an output conversion signal to the capacitive load.

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