Multiplexed framing method and apparatus and terminal device

Abstract

The present application relates to the technical field of data communications, and in particular to a multiplexed framing method and apparatus and a terminal device. The apparatus comprises: by means of a depth and bit width configuration interface, receiving a depth and bit width of a buffer space configured according to a requirement and, by means of a check mode configuration interface, receiving a check calculation mode configured according to the requirement; by means of input interfaces respectively corresponding to a frame header, frame data and a frame trailer, correspondingly receiving frame header information, frame data information and frame trailer information, adding a frame identifier, and then storing all of the frame header information, the frame data information, the frame trailer information and the frame identifier in the buffer space; on the basis of the frame header information, the frame data information, the frame trailer information, and the frame identifier, forming a frame and, during the framing, calculating a check value of the current frame on the basis of the check calculation mode, the check value being encapsulated in the current frame; and storing the current formed frame in a storage space. The present application can solve the problem that framing and buffer development have great difficulty, long cycles, and high costs in complex application scenarios.

Description

A multiplexing framing method, apparatus and terminal equipment

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410911707.1, filed on July 9, 2024, entitled "A Multiplexing Framing Method, Apparatus and Terminal Equipment", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of data communication technology, and in particular to a multiplexing framing method, apparatus and terminal equipment. Background Technology

[0004] In digital logic development, when application scenarios involve communication and interaction, it is necessary to design related functionalities such as frame assembly and frame storage to meet protocol requirements. During development, when encountering scenarios requiring frame assembly and caching operations, the common approach is to directly design the logic for frame assembly, frame caching, and frame reading based on the application scenario's needs. This approach is feasible for simple application scenarios. However, if the application scenario involves a large variety of functionalities, this method obviously requires a significant investment of time and effort. Summary of the Invention

[0005] In view of this, embodiments of this application provide a method, apparatus and terminal device for reusing frames, which can effectively solve the problems of high difficulty, long development cycle and high cost in the design and development of frame buffers in existing complex application scenarios.

[0006] This application provides a multiplexing framing method, including the following steps:

[0007] The interface for configuring the depth and bit width of the cache space according to requirements is used to receive the depth and bit width of the cache space according to requirements, and the interface for configuring the verification method is used to receive the verification calculation method according to requirements.

[0008] The frame header information, frame data information, and frame tail information are received through the corresponding input interfaces of the frame header, frame data, and frame tail, and a frame identifier is added. Then, the frame header information, frame data information, frame tail information, and frame identifier are stored in the cache space respectively.

[0009] Frames are assembled based on the frame header information, frame data information, frame tail information, and frame identifier. During frame assembly, the check value of the current frame is calculated according to the check calculation method. The check value is used to assemble the current frame.

[0010] Store the current frame, after it has been assembled, into the storage space.

[0011] In some embodiments, the method further includes reading and outputting a frame from the buffer space according to the frame identifier via a read interface; the frame includes frame header information, frame data information, checksum, frame tail information, and frame identifier.

[0012] In some embodiments, when storing the frame header information, frame data information, frame tail information, and frame identifier into the cache space, the method further includes:

[0013] Record the total length of the input frames;

[0014] The method further includes receiving a configured read buffer threshold, and determining, based on the read buffer threshold and the total length of the input frames, to output a read signal through the read-ready interface; the read signal is used by an external module to determine whether to read a frame.

[0015] Driven by the external module, the frame is read from the buffer space according to the frame identifier through the read interface and output to the external module.

[0016] In some embodiments, the frame identifier includes a frame header identifier and a frame tail identifier; the frame tail information includes an initial frame tail marker, and the frame tail identifier is determined based on the initial frame tail marker; when outputting the frame tail to the external module, a frame tail indication signal is output.

[0017] In some embodiments, the verification calculation method includes one of the following: cumulative sum, cumulative difference, parity check, and bitwise XOR.

[0018] This application embodiment also provides a multiplexing framing device, the device comprising: a framing logic module, a verification calculation logic module, a write cache logic module, and a cache management module; the framing logic module is provided with an input interface;

[0019] The cache management module includes a depth and bit width configuration interface; the cache management module is used to receive the configured depth and bit width through the depth and bit width configuration interface, and configure the size of the cache space and the bit width of each frame according to the depth and bit width.

[0020] The framing logic module is used to receive frame header information, frame data information, and frame tail information through the corresponding input interfaces of frame header, frame data, and frame tail, respectively, add a frame identifier, and then store the frame header information, frame data information, frame tail information, and frame identifier into the cache space respectively.

[0021] The verification calculation logic module includes a verification method configuration interface; the verification calculation logic module is used to receive the verification calculation method configured through the verification method configuration interface, and calculate the verification value of the current frame according to the verification calculation method when the framing logic module performs framing, and the verification value is used to encapsulate the current frame;

[0022] The write cache logic module is used to store the current frame after it has been assembled into the storage space; the current frame after it has been assembled includes the frame header information, frame data information, frame tail information, check value and frame identifier.

[0023] In some embodiments, the apparatus further includes a read cache logic module; the read cache logic module includes a read interface;

[0024] The read cache logic module is used to read and output a frame from the cache space according to the frame identifier through the read interface; the frame includes frame header information, frame data information, check value, frame tail information and frame identifier.

[0025] In some embodiments, the write cache logic module is further configured to record the total length of the input frames; the read cache logic module further includes a read-ready interface and a read cache threshold configuration interface;

[0026] The read buffer logic module is specifically used to receive the configured read buffer threshold, and determine the output of a read signal through the read ready interface based on the read buffer threshold and the total length of the input frames; the read signal is used for external modules to determine to read frames;

[0027] The read cache logic module is used to read frames from the cache space according to the frame identifier through the read interface and output them to the external module under the drive of the read frame task of the external module.

[0028] In some embodiments, the frame identifier includes a frame header identifier and a frame tail identifier; the frame tail information includes an initial frame tail marker, and the frame tail identifier is determined based on the initial frame tail marker; the read buffer logic module outputs a frame tail indication signal when outputting the frame tail.

[0029] In some embodiments, the initial frame end marker includes a 1-bit signal to indicate that the data is valid.

[0030] In some embodiments, the read buffer logic module is used to determine the relationship between the total length of the input frames in the previous frame step and the size of the read buffer threshold, and set the read ready interface level high when the total length of the input frames is greater than the read buffer threshold, otherwise keep the read ready interface at a low level.

[0031] In some embodiments, the verification calculation method in the verification calculation logic module includes at least one of the following: cumulative sum, cumulative difference, parity check, and bitwise XOR.

[0032] This application also provides a terminal device, which includes a processor and a memory. The memory stores a computer program, and the processor executes the computer program to implement a multiplexing framing method provided in this application.

[0033] The beneficial effects of the embodiments of this application include, for example:

[0034] To meet the diverse functional requirements of complex engineering scenarios, this application employs a customizable, reusable design for frame assembly and caching functions. For external modules, it provides depth and bit width configuration interfaces, as well as verification method configuration interfaces, allowing for customization of cache depth and bit width, and the chosen verification calculation method based on business needs. This application also provides frame header input interfaces, frame data input interfaces, and frame tail input interfaces, enabling external modules to customize frame assembly parameters and content as required. Then, a frame assembly logic module assembles frames and stores them in the cache space. A cache management module manages the cache based on depth and bit width. A verification calculation logic module performs verification and stores the verification results. A write cache logic module stores the frame header, frame data, frame tail, verification value, and frame identifier. The content of the depth and bit width configuration interfaces, verification method configuration interfaces, frame header input interfaces, frame data input interfaces, and frame tail input interfaces can all be customized to meet various application scenarios. Therefore, this application effectively solves the problems of high difficulty, long development cycle, and high cost in the design and development of frame caching in complex application scenarios. Attached Figure Description

[0035] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 shows a structural block diagram of a multiplexing framing device according to an embodiment of this application;

[0037] Figure 2 shows another structural block diagram of the multiplexing framing device according to an embodiment of this application;

[0038] Figure 3 shows a flowchart of a multiplexing framing method according to an embodiment of this application.

[0039] Key component symbols: 110 - Cache management module; 120 - Frame assembly logic module; 130 - Verification calculation logic module; 140 - Write cache logic module; 150 - Cache space; 160 - Read cache logic module. Detailed Implementation

[0040] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0041] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0042] In the following text, the terms "comprising," "having," and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more combinations thereof. Furthermore, the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0043] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be construed as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.

[0044] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0045] In related technologies, frame assembly and buffer design is performed directly based on the application scenario requirements, involving logic designs for frame assembly, frame caching, and frame reading. However, complex scenarios with numerous and diverse functionalities require multiple frame assembly logic designs and frame buffer designs. This approach obviously demands significant effort and time, leading to problems such as high development difficulty, long development cycles, and high costs. Therefore, this application provides a reusable frame assembly method, apparatus, and terminal device, which can effectively solve the problems of high development difficulty, long development cycles, and high costs associated with multiple frame assembly logic designs and frame buffer designs required for multifunctional external output in complex scenarios.

[0046] To meet the diverse application needs of complex scenarios in engineering, this application presents a custom reusable design for functions such as framing and caching. The main idea of ​​this application is to utilize the control of the chip's internal storage space and the configurable framing logic design to customize the cache space size and framing content of use cases, providing a reusable framing cache design that can adapt to different functional scenarios.

[0047] The multiplexing and framing device will be described below with reference to some specific embodiments.

[0048] Figure 1 shows a structural block diagram of a multiplexing and framing apparatus according to an embodiment of this application. Exemplarily, the multiplexing and framing apparatus includes: a cache management module 110, a framing logic module 120, a verification calculation logic module 130, and a write cache logic module 140.

[0049] The cache management module 110 includes a depth and bit width configuration interface; the cache management module 110 is used to receive the configured depth and bit width through the depth and bit width configuration interface, and configure the size of the cache space 150 and the bit width of each frame according to the depth and bit width.

[0050] In some embodiments, when designing the cache management module 110, a depth and bit width configuration interface is provided to set the size of the frame cache space 150 and the bit width of the content of each base frame unit. The depth and bit width can be customized according to requirements to be applied to different functional scenarios.

[0051] The framing logic module 120 is provided with input interfaces. The framing logic module 120 receives frame header information, frame data information, and frame trailer information through the corresponding input interfaces for the frame header, frame data, and frame trailer, respectively, adds a frame identifier, and then stores the frame header information, frame data information, frame trailer information, and frame identifier into the buffer space 150. Framing includes adding a frame header and frame trailer to the beginning and end of the frame data information. The frame header and frame trailer contain a lot of control information, such as frame delimitation to determine the frame boundaries, and frame synchronization, i.e., the receiver should be able to distinguish the start and end of the frame from the received binary bit stream (frame synchronization is from the receiver's perspective). In addition, a frame identifier needs to be added for identification when reading the frame.

[0052] In some embodiments, the framing logic module 120 is designed to provide external input interfaces, including a frame header input interface, a frame data input interface, and a frame tail input interface. Frame header information, frame data information, and frame tail information are input through the corresponding input interfaces. The framing logic module 120 receives the frame header information, frame data information, and frame tail information respectively, performs framing, and then stores them in the buffer space 150, adding their respective start markers (frame header identifier) ​​and end markers (frame tail identifier) ​​for differentiation when reading frames. The framing logic module 120 can execute multiple times to buffer multiple frames. The content input from the frame header input interface, frame data input interface, and frame tail input interface can be customized according to requirements to be applied to different functional scenarios. For example, different frame header information, frame data information, and frame tail information input from external functions will result in different frame formats, completely customized by the external application.

[0053] The verification calculation logic module 130 includes a verification method configuration interface. The verification calculation logic module 130 receives a verification calculation method configured through the verification method configuration interface, calculates the verification value of the current frame according to the verification calculation method when the framing logic module 120 performs framing, and caches the verification value. The verification value is used to encapsulate the current frame. In other words, the verification calculation logic module 130 can be configured externally with a verification calculation method. During the framing process, it simultaneously calculates the verification value of the current frame, calculates until the end of the frame data, and caches the result. The verification calculation method in the verification calculation logic module 130 includes at least one of cumulative summation, cumulative difference, parity check, and bitwise XOR. The verification calculation method used can be configured through the verification method configuration interface.

[0054] The write cache logic module 140 is used to store the frame header information, frame data information, checksum, frame trailer information, and frame identifier into the storage space. The frame identifier includes a frame header identifier and a frame trailer identifier, which are used to mark the start and end positions of the current frame.

[0055] The write cache logic module 140 stores the frame, which includes frame header information, frame data information, frame tail information and frame identifier, obtained by the framing logic module 120, into the chip storage space, and stores the start and end positions of the verification value obtained by the verification calculation logic module 130 of the framing logic module into the chip storage space.

[0056] In one embodiment, to facilitate frame reading by external modules, as shown in FIG2, the device further includes a read cache logic module 160; the read cache logic module 160 includes a read interface. The read cache logic module 160 is used to read and output frames from the cache space 150 according to the frame identifier through the read interface; the frame includes frame header information, frame data information, checksum, frame trailer information, and frame identifier.

[0057] Optionally, the write cache logic module 140 is also used to record the total length of the input frames; the read cache logic module 160 further includes a read-ready interface and a read cache threshold configuration interface.

[0058] The read cache logic module 160 is specifically used to receive a configured read cache threshold and, based on the read cache threshold and the total length of the input frames, determine to output a read signal through the read-ready interface; the read signal is used by an external module to determine whether to read a frame. The read cache logic module 160, driven by the external module's frame reading task, reads a frame from the cache space 150 through the read interface according to the frame identifier and outputs it to the external module. The customizable read cache threshold described above can adapt to special application scenarios such as early reading and preventing cache fullness.

[0059] Optionally, the frame identifier includes a frame header identifier and a frame tail identifier; the frame tail information includes an initial frame tail mark, and the frame tail identifier is determined based on the initial frame tail mark; the initial frame tail mark contains a 1-bit signal to indicate that the data is valid, and this 1-bit signal data needs to be removed first to obtain the frame tail identifier, and then the frame tail identifier is re-added. The read buffer logic module 160 outputs a frame tail indicator signal when outputting the frame tail to indicate that a complete frame has been output. For example, the frame tail indicator signal can be a pulse signal, and this application does not limit this.

[0060] Exemplarily, the storage space is chip storage space. The read cache logic module 160 is used to determine the relationship between the total length of the input frames in the previous frame step and the size of the read cache threshold, and sets the read ready interface level high when the total length of the input frames is greater than the read cache threshold; otherwise, it keeps the read ready interface low. The read cache logic module 160 outputs a pulse signal and sets the read ready signal low when outputting the end of the frame according to the frame end mark.

[0061] Figure 3 illustrates a flowchart of a multiplexing framing method according to an embodiment of this application. Exemplarily, the multiplexing framing method includes:

[0062] S10 receives the depth and bit width of the cache space of 150 configured according to requirements through the depth and bit width configuration interface, and receives the verification calculation method configured according to requirements through the verification method configuration interface.

[0063] This embodiment provides a depth and bit width configuration interface for external modules, allowing them to customize the depth and bit width of the 150-bit cache space according to their needs. For example, the cache depth configuration for this use case is at least greater than the maximum length of the complete frame, and the cache bit width configuration is equal to the data bit width of each base frame unit. This embodiment also provides a verification method configuration interface for external modules, allowing them to set the verification calculation method according to their needs. Verification calculation methods include one of the following: summation, difference, parity check, and bitwise XOR. Only after defining the configuration interface can the method of this application be adapted to the specified functional scenario. Exemplarily, the aforementioned depth and bit width configuration interface and verification method configuration interface can be chip ports.

[0064] S20: Frame header information, frame data information, and frame tail information are received through the corresponding input interfaces of frame header, frame data, and frame tail, and a frame identifier is added. Then, the frame header information, frame data information, frame tail information, and frame identifier are stored in the buffer space 150.

[0065] When the frame assembly logic starts working, it receives the frame header information, frame data information, frame tail information, length, and valid signal from each input interface. The information is cached according to the content. The above information is entirely determined by the application scenario input, which determines the required frame format. For example, the specific content of each part of the frame and its continuous cache length are all customized according to the application scenario.

[0066] During the framing process, each input base frame unit is stored in the buffer space 150 through write buffer logic, and frame header and frame tail identifiers are added to determine their respective start and end positions and record the total length of the input frames.

[0067] S30: Frames are assembled based on the frame header information, frame data information, frame tail information, and frame identifier. During frame assembly, the checksum of the current frame is calculated according to the checksum calculation method. The checksum is used to assemble the current frame. Simultaneously with writing to the buffer, the checksum logic calculates the result according to the configured checksum calculation method and records it, waiting to continue calculation when the next base frame unit is written, until the frame data ends and the calculation result is cached.

[0068] The input of information for each part of a frame is a continuous process. The verification logic, framing logic, and write buffer logic are performed synchronously. While framing, the verification value is also being accumulated and calculated until the end of the frame. The write buffer logic caches the result of the framing logic before the end of the frame and caches the verification result of the current frame at the end of the frame.

[0069] S40, the current frame, after framing is complete, is stored in the storage space. The current frame, after framing is complete, includes the frame header identifier, frame header information, frame data information, checksum, frame trailer information, and frame trailer identifier. For example, the storage space can be the chip's storage space. When reading a frame, the frame needs to be read from the buffer space first based on the frame header identifier and frame trailer identifier in the chip's storage space.

[0070] In one embodiment, the method further includes step S50.

[0071] S50: A frame is read from the buffer space 150 according to the frame identifier via the read interface and output; the frame includes frame header information, frame data information, checksum, and frame trailer information. A read interface is provided to external modules for reading frames.

[0072] Optionally, when storing the frame header information, frame data information, frame tail information and frame identifier into the cache space 150, the method further includes: recording the total length of the input frames;

[0073] The method further includes receiving a configured read buffer threshold and determining, based on the read buffer threshold and the total length of the input frames, to output a read-ready signal through a read-ready interface provided to an external module; the read signal is used by the external module to determine whether to read a frame; under the drive of the external module, a frame is read from the buffer space 150 according to the corresponding storage location through the read interface and output to the external module. The frame tail includes a frame tail marker; outputting a frame tail indication signal includes outputting a frame tail indicator signal when outputting the frame tail to the external module.

[0074] In some embodiments, the relationship between the total length of the input frames recorded in the previous step and the configured read buffer threshold is determined. When the total length of the input frames is greater than the read buffer threshold, the read-ready interface signal is set high; otherwise, the read-ready interface remains low. After the external module determines that the read-ready interface signal is high, it can read the buffered frames. When the end of the frame is read, a pulse signal indicating the end of frame reading is output, and the read-ready interface signal is set low. The module then continues to determine the relationship between the total length of the input frames recorded in the previous two steps and the set read buffer threshold to continue reading frames.

[0075] After completing one frame assembly and caching operation, multiple frame assemblies and caching operations can be supported based on the set cache depth. When a full frame or more is completed, the read-ready interface signal will remain high, and the read interface supports continuous reading of multiple full frames. The specific number of cached full frames and the required cache depth can be defined by the application scenario.

[0076] It is understood that the apparatus in this embodiment corresponds to the multiplexing framing method in the above embodiments, and the options in the above embodiments are also applicable to this embodiment, so they will not be described again here.

[0077] To meet the diverse functional requirements of complex engineering scenarios, this application employs a customized, reusable design for framing and caching functions. For external modules, this application provides interfaces for depth and bit width configuration, verification method configuration, and read cache thresholds, allowing for customization of cache depth and bit width, verification calculation methods, and read cache thresholds according to business needs. This application also includes frame header input interfaces, frame data input interfaces, and frame trailer input interfaces, enabling external modules to customize framing parameters and content as required. Then, the framing logic module 120 assembles the frames and stores them in the cache space 150. The cache management module 110 manages the cache based on depth and bit width, the verification calculation logic module 130 performs verification and stores the verification results, and the write cache logic module 140 stores the frame header, frame data, frame trailer, verification value, and frame identifier. This application also includes read-ready interfaces and a read interface for outputting read-ready signals and reading frames. Therefore, this application effectively solves the problems of high design and development difficulty, long development cycle, and high cost in existing complex application scenarios for framing and caching.

[0078] This application also provides a terminal device, exemplary of which includes a processor and a memory, wherein the memory stores a computer program, and the processor executes the computer program to enable the terminal device to perform the functions of the various modules in the above-described multiplexing framing method or multiplexing framing apparatus.

[0079] The processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including at least one of a Central Processing Unit (CPU), Graphics Processing Unit (GPU), Network Processor (NP), Digital Signal Processor (DSP), Application-Specific Integrated Circuit (ASIC), Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor or any conventional processor, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application.

[0080] The memory can be, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), etc. The memory is used to store computer programs, and the processor can execute the computer programs accordingly after receiving execution instructions.

[0081] This application also provides a readable storage medium for storing the computer program used in the aforementioned terminal device.

[0082] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that, in alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0083] In addition, the functional modules or units in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0084] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0085] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Industrial applicability

[0086] This application provides a method, apparatus, and terminal device for reusing frames, which can effectively solve the problems of high difficulty, long development cycle, and high cost in the design and development of frame buffers in existing complex application scenarios.

[0087] Furthermore, it is understood that the multiplexing framing method, apparatus, and terminal equipment of this application are reproducible and can be widely applied in the field of data communication technology.

Claims

1. A multiplexing framing method, characterized in that, include: The interface for configuring the depth and bit width of the cache space according to requirements is used to receive the depth and bit width of the cache space according to requirements, and the interface for configuring the verification method is used to receive the verification calculation method according to requirements. The frame header information, frame data information, and frame tail information are received through the corresponding input interfaces of the frame header, frame data, and frame tail, and a frame identifier is added. Then, the frame header information, frame data information, frame tail information, and frame identifier are stored in the cache space respectively. Frames are assembled based on the frame header information, frame data information, frame tail information, and frame identifier. During frame assembly, the check value of the current frame is calculated according to the check calculation method. The check value is used to assemble the current frame. Store the current frame, after it has been assembled, into the storage space; When storing the frame header information, frame data information, frame tail information, and frame identifier into the cache space, the method further includes: Record the total length of the input frames; The method further includes: receiving a configured read buffer threshold, and determining, based on the read buffer threshold and the total length of the input frames, to output a read signal through the read-ready interface; the read signal is used by an external module to determine whether to read a frame. Driven by the external module, the frame is read from the buffer space according to the frame identifier through the read interface and output to the external module.

2. The multiplexing and framing method according to claim 1, characterized in that, The method further includes reading and outputting a frame from the buffer space according to the frame identifier through the read interface; the frame includes frame header information, frame data information, check value, frame tail information and frame identifier.

3. The multiplexing and framing method according to claim 1, characterized in that, The frame identifier includes a frame header identifier and a frame tail identifier; the frame tail information includes an initial frame tail marker, and the frame tail identifier is determined based on the initial frame tail marker; when outputting the frame tail to the external module, a frame tail indication signal is output.

4. The multiplexing and framing method according to any one of claims 1-3, characterized in that, The verification calculation method includes one of the following: cumulative sum, cumulative difference, parity check, and bitwise XOR.

5. A multiplexing and framing device, characterized in that, The device includes: a framing logic module, a verification calculation logic module, a write cache logic module, and a cache management module; the framing logic module is provided with an input interface. The cache management module includes a depth and bit width configuration interface; the cache management module is used to receive the configured depth and bit width through the depth and bit width configuration interface, and configure the size of the cache space and the bit width of each frame according to the depth and bit width. The framing logic module is used to receive frame header information, frame data information, and frame tail information through the corresponding input interfaces of frame header, frame data, and frame tail, respectively, add a frame identifier, and then store the frame header information, frame data information, frame tail information, and frame identifier into the cache space respectively. The verification calculation logic module includes a verification method configuration interface; the verification calculation logic module is used to receive the verification calculation method configured through the verification method configuration interface, and calculate the verification value of the current frame according to the verification calculation method when the framing logic module performs framing, and the verification value is used to assemble the current frame; The write cache logic module is used to store the current frame after it has been assembled into the storage space; the current frame after it has been assembled includes the frame header information, frame data information, frame tail information, check value and frame identifier; The device further includes a read cache logic module; the read cache logic module includes a read interface; the write cache logic module is also used to record the total length of the input frames; the read cache logic module further includes a read-ready interface and a read cache threshold configuration interface; The read buffer logic module is specifically used to receive the configured read buffer threshold, and determine the output of a read signal through the read ready interface based on the read buffer threshold and the total length of the input frames; the read signal is used for external modules to determine to read frames; The read cache logic module is used to read frames from the cache space according to the frame identifier through the read interface and output them to the external module under the drive of the read frame task of the external module.

6. The multiplexing and framing apparatus according to claim 5, characterized in that, The read cache logic module is used to read and output a frame from the cache space according to the frame identifier through the read interface; the frame includes frame header information, frame data information, check value, frame tail information and frame identifier.

7. The multiplexing and framing apparatus according to claim 5, characterized in that, The frame identifier includes a frame header identifier and a frame tail identifier; the frame tail information includes an initial frame tail marker, and the frame tail identifier is determined based on the initial frame tail marker; the read buffer logic module outputs a frame tail indicator signal when outputting the frame tail.

8. The multiplexing and framing apparatus according to claim 7, characterized in that, The initial frame end marker contains a 1-bit signal to indicate that the data is valid.

9. The multiplexing and framing apparatus according to claim 7 or 8, characterized in that, The read buffer logic module is used to determine the relationship between the total length of the input frames in the previous frame step and the size of the read buffer threshold, and sets the read ready interface level high when the total length of the input frames is greater than the read buffer threshold, otherwise keeps the read ready interface at a low level.

10. The multiplexing and framing apparatus according to any one of claims 5-9, characterized in that, The verification calculation logic module includes at least one of the following verification calculation methods: cumulative sum, cumulative difference, parity check, and bitwise XOR.

11. A terminal device, characterized in that, The terminal device includes a processor and a memory, the memory storing a computer program, and the processor executing the computer program to implement the multiplexing framing method according to any one of claims 1-4.

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