Addressing circuit, display panel, display screen and display device

Abstract

An addressing circuit, which is respectively connected to the current-stage gate drive circuit and a previous-stage gate drive circuit. The addressing circuit comprises: an enable writing module (100), which is configured to receive an enable control signal (EN), and generate a first selection signal on the basis of the enable control signal (EN); and a selection module (200), which is connected to the enable writing module (100), wherein the selection module (200) is configured to receive a frame start signal (STV), and a first gate drive signal (in) outputted by the previous-stage gate drive circuit, and output one of the frame start signal (STV) and the first gate drive signal (in) to the current-stage gate drive circuit on the basis of the first selection signal, so as to trigger the current-stage gate drive circuit to generate a second gate drive signal.

Description

Addressing circuits, display panels, displays and display devices

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 2024109394182, filed on July 12, 2024, entitled “Addressing Circuit, Display Panel, Display Screen and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of display technology, and in particular to an addressing circuit, a display panel, a display screen, and a display device. Background Technology

[0004] The statements herein are provided only as background information in connection with this application and do not necessarily constitute exemplary technology.

[0005] With the continuous development of display technology, users are placing increasingly higher demands on display panels. Among these demands, power consumption is a key indicator that users are concerned about. To reduce the power consumption of display panels, partial refresh technology has emerged. However, the flexibility of partial refresh technology is insufficient to meet user needs. Summary of the Invention

[0006] According to various embodiments of this application, an addressing circuit, a display panel, a display screen, and a display device are provided.

[0007] In a first aspect, this application provides an addressing circuit, which is connected to a current-stage gate driving circuit and a previous-stage gate driving circuit, respectively. The current-stage gate driving circuit and the previous-stage gate driving circuit are respectively connected to two adjacent rows of pixel circuits. The addressing circuit includes:

[0008] An enable write module is used to receive an enable control signal and generate a first selection signal based on the enable control signal.

[0009] The selection module is connected to the enable write module. The selection module is used to receive the frame start signal and the first gate drive signal output by the previous stage gate drive circuit, and output one of the frame start signal and the first gate drive signal to the current stage gate drive circuit according to the first selection signal, so as to trigger the current stage gate drive circuit to generate a second gate drive signal.

[0010] Secondly, this application provides a display panel, including:

[0011] Multiple pixel circuits are arranged in multiple rows, and each pixel circuit includes multiple transistors.

[0012] Multiple gate driving circuits, the output of each gate driving circuit being respectively connected to at least a portion of the transistors in the multiple pixel circuits located in each row, so as to control the connected transistors to be turned on and off by the gate driving signal;

[0013] Multiple addressing circuits as described above are connected to the gate driving circuits of two adjacent stages, respectively, for triggering the next stage gate driving circuit to generate a second gate driving signal based on one of the frame start signal and a first gate driving signal from the previous stage gate driving circuit.

[0014] Thirdly, this application provides a display screen, including:

[0015] As shown in the display panel above;

[0016] A cover plate is disposed on the light-emitting side of the display panel and covers the display panel.

[0017] Fourthly, this application provides a display device, comprising:

[0018] As shown in the above display screen.

[0019] Details of one or more embodiments of this application are set forth in the following drawings and description. Other features, objects, and advantages of this application will become apparent from the specification, drawings, and claims. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments or exemplary technologies of this application, the accompanying drawings used in the description of the embodiments or exemplary technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0021] Figure 1 is a circuit diagram of a pixel circuit according to an embodiment;

[0022] Figure 2 is a schematic diagram of one embodiment of an addressing circuit;

[0023] Figure 3 is one of the circuit diagrams of an embodiment of the enable write module;

[0024] Figure 4 is a second circuit diagram of an embodiment of the enable write module;

[0025] Figure 5 is a second schematic diagram of the addressing circuit in one embodiment;

[0026] Figure 6 is a circuit diagram of the second writing unit in one embodiment;

[0027] Figure 7 is a circuit diagram of the third writing unit in one embodiment;

[0028] Figure 8 is a circuit diagram of the initial writing module of one embodiment;

[0029] Figure 9 is a circuit diagram of a selection module according to an embodiment;

[0030] Figure 10 is a circuit diagram of an addressing circuit according to an embodiment;

[0031] Figure 11 is a schematic diagram of a display panel according to an embodiment;

[0032] Figure 12 is a schematic diagram of the structure of a display screen according to an embodiment;

[0033] Figure 13 is an internal structural diagram of a display device according to an embodiment.

[0034] Component labeling: Enable write module: 100; First write unit: 110; First reset unit: 111; First lock unit: 120; First inverter: 121; Second inverter: 122; Selection module: 200; First selection unit: 210; Second selection unit: 220; Initial write module: 300; Second write unit: 310; Third inverter: 311; Holding unit: 312; Second lock unit: 313; Fifth inverter: 3131; Sixth inverter: 3132; Third write unit: 320; Fourth inverter: 321; Second reset unit: 330. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0036] It is understood that the terms "first," "second," etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first selection signal may be referred to as a second selection signal, and similarly, a second selection signal may be referred to as a first selection signal.

[0037] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. "Multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. "Several" means at least one, such as one, two, etc., unless otherwise explicitly specified.

[0038] In the display field, the display area (Active Area, AA area) of a display panel includes multiple light-emitting elements and multiple pixel circuits. The pixel circuits include connected storage capacitors and multiple transistors. The non-display area of ​​the display panel has multiple gate driving circuits, each connected to a transistor in one of the pixel circuits located in the same row. The gate driving circuits control the pixel circuits to perform reset, write, and light-emitting processes via gate driving signals, thereby driving the light-emitting elements to emit light, thus displaying an image on the display panel. The light-emitting elements can be, but are not limited to, organic light-emitting diodes (OLEDs) or micro light-emitting diodes (Micro-LEDs). The transistors in the pixel circuits can be made using low-temperature polycrystalline silicon (LTPS) or low-temperature polycrystalline oxide (LTPO) technology. LTPO transistors can be IGZO type transistors. IGZO transistors have low leakage current, thus effectively reducing the power consumption of the display panel, and are increasingly used in display devices.

[0039] Furthermore, to reduce the size of the gate driving circuit in display devices, current display devices mostly use a GOA (Gate On Array) approach to integrate the gate driving circuit onto the array substrate. LTPS type pixel circuits typically only require two GOAs: P_gate GOA and EM GOA. The P_gate GOA controls the reset and writing of the pixel circuit, while the EM GOA controls the pixel circuit's ability to drive the light-emitting devices. However, because the switching mechanism of IGZO type transistors differs from that of LTPS, pixel circuits including IGZO type transistors require three or even five GOAs to control all transistors in the pixel circuit. These three GOAs are P_GOA, N_GOA, and EM GOA. Figure 1 is a circuit diagram of a pixel circuit according to an embodiment. Referring to Figure 1, N_GOA is used to control IGZO TFTs (T1 and T2), P_GOA is used to control P_TFTs (T4, T7 and T8) to realize the reset and writing of the pixel circuit, and EM_GOA is used to control P_TFTs (T5 and T6) to drive the light-emitting device to emit light. It should be noted that the 7T1C pixel circuit shown in Figure 1 is only for illustrative purposes. The gate driving circuit of this embodiment can also be applied to other pixel circuits, such as 8T1C, etc.

[0040] Multiple gate drive circuits employ a cascaded architecture. During display refresh, the gate drive signal propagates from top to bottom to achieve line-by-line refresh of the pixel circuits. However, in some scenarios, the refresh rates of each row in the display panel are not entirely the same. For example, only some rows of data in the display panel need to be refreshed, while the data of the remaining rows can be refreshed at intervals of one or more frames. Therefore, considering factors such as power consumption and response speed, during data writing, the conduction of the pixel circuits in the refreshed rows can be controlled by controlling whether each gate drive circuit outputs a gate drive signal, thereby achieving partial refresh of the display panel.

[0041] Therefore, this application provides an addressing circuit that is connected to both a display driver chip and a gate driver circuit. Under the drive of the display driver chip, the addressing circuit can control whether the connected gate driver circuit outputs a gate drive signal. Specifically, the addressing circuit is connected to both the current gate driver circuit and the previous gate driver circuit. The current gate driver circuit and the previous gate driver circuit are respectively connected to two adjacent rows of pixel circuits. The display driver chip outputs an enable control signal to drive the addressing circuit.

[0042] Figure 2 is a schematic diagram of one embodiment of an addressing circuit. Referring to Figure 2, the addressing circuit includes an enable write module 100 and a selection module 200.

[0043] In this design, the input node of the enable writing module 100 is point M, and the output node of the enable writing module 100 and the input node of the selection module 200 are points N. The enable writing module 100 receives the enable control signal EN and generates a first selection signal based on the enable control signal EN, thereby changing the level state of point N. Specifically, the enable control signal EN originates from the display driver chip. The display driver chip can transmit different enable control signals EN to the addressing circuits corresponding to different pixel rows according to the local refresh requirements of the display panel. That is, the display driver chip can transmit a valid enable control signal EN to the addressing circuit corresponding to the pixel row that needs to be refreshed, and transmit an invalid enable control signal EN to the addressing circuit corresponding to the pixel row that does not need to be refreshed.

[0044] It is understandable that, since the enable control signal EN is directly generated by the display driver chip, the transition speed of the enable control signal EN during level state switching is very fast, resulting in short rise time (TR) and fall time (TF) of the enable control signal EN. For example, the rise time of the enable control signal EN can be less than 200ns, and the fall time can be less than 300ns. Based on the fast level state switching characteristic of the enable control signal EN, the first selection signal generated by the enable writing module 100 will also have better signal quality, thereby better controlling the selection module 200. Optionally, the first selection signal can be generated entirely based on the enable control signal EN. For example, the first selection signal can switch its level state at the rising or falling edge of the enable control signal EN. The first selection signal can also be generated jointly based on the enable control signal EN and one or more other signals. These other one or more signals can come from at least one of the previous stage gate driving circuit and the display driver chip, which is not limited in this embodiment.

[0045] The selection module 200 is connected to the enable / write module 100. The selection module 200 receives the frame start signal STV and the first gate drive signal in output by the previous stage gate drive circuit. It is understood that since the frame start signal STV is directly generated by the display driver chip, the transition speed during level switching is very fast, resulting in short rise time (TR) and fall time (TF) of the frame start signal STV. For example, the rise time of the frame start signal STV can be less than 200ns, and the fall time can be less than 300ns. The first gate drive signal in, however, is generated by the previous stage gate drive circuit, and the transition speed during level switching is slightly slower, resulting in slightly slower rise time (TR) and fall time (TF) of the first gate drive signal in. For example, the rise time of the first gate drive signal in can be less than 300ns, and the fall time can be less than 500ns. The selection module 200 is used to output one of the frame start signal STV and the first gate drive signal in according to the first selection signal to the current level gate drive circuit, so as to trigger the current level gate drive circuit to generate a second gate drive signal. Specifically, if the refresh frequency of the nth pixel row and the (n-1)th pixel row are the same, the nth level addressing circuit can choose to output the first gate drive signal in of the (n-1)th level gate drive circuit to trigger the nth level gate drive circuit to generate a second gate drive signal. If the refresh frequency of the nth pixel row and the (n-1)th pixel row are different, the nth level addressing circuit can choose to output the frame start signal STV to trigger the nth level gate drive circuit to generate a second gate drive signal.

[0046] In the embodiments of the application, by introducing addressing circuits connected to the gate driving circuits of two adjacent stages respectively, flexible selection of the refreshed pixel rows can be achieved based on the enable control signal EN from the display driver chip. Specifically, for adjacent rows with the same refresh frequency, the addressing circuit can select to transmit the first gate driving circuit output by the gate driving circuit of the previous stage to the gate driving circuit of the next stage according to the enable control signal EN, so as to trigger the gate driving circuit of the next stage, thereby allowing the gate driving circuits of adjacent stages to sequentially drive the corresponding pixel rows for data refresh. For adjacent rows with different refresh frequencies, the addressing circuit can also select to trigger the gate driving circuit of the next stage through the frame start signal STV according to the enable control signal EN, so as to refresh the data of the next pixel row when the previous pixel row has not been refreshed. Thus, the refresh control of the pixel row by the gate driving circuit of the next stage does not depend on the first gate driving signal in of the previous stage, thereby realizing flexible selection of the refreshed pixel rows, that is, realizing partial refresh of the display panel.

[0047] Figure 3 is a circuit diagram of one embodiment of the enable write module 100. Referring to Figure 3, in one embodiment, the enable write module 100 includes a first write unit 110. The first write unit 110 is used to receive an address enable signal and an enable control signal EN, respectively. The address enable signal is a signal from point M, and it is used to determine whether the enable control signal EN can affect the level state of the signal output by the first write unit 110. Specifically, when the address enable signal is in a first level state and the enable control signal EN is in a second level state, the first write unit 110 generates a first selection signal with a target level state to change the level state of point N1. The first level state and the second level state are determined according to the circuit settings in the first write unit 110. For example, the first level state can be a low level state and the second level state can be a high level state. When the address enable signal is in the second level state, the first write unit 110 can change the level state of the output signal according to other signals, which is not limited in this embodiment. Furthermore, when both the address selection enable signal and the enable control signal EN are in the first level state, the first write unit 110 can output a signal that is the same as the target level state or a signal that is different from the target level state; this embodiment does not impose any limitations. Further, the address selection enable signal can come from the previous stage gate drive circuit or from the display driver chip; this embodiment does not impose any limitations. In the embodiment of the application, by setting the address selection enable signal, the control timing of the enable control signal EN can be selected more easily, and the situation where an abnormal enable control signal EN causes an abnormal output of the back-end selection module 200 can be reduced, thereby improving the reliability of the addressing circuit.

[0048] Referring again to Figure 3, in one embodiment, the first write unit 110 includes a first switch transistor, which is a first type of switch transistor used to turn on when the signal received at the control terminal is low. That is, the first switch transistor can be a first PMOS transistor QP1. It should be noted that, for ease of explanation, in subsequent embodiments, the first type of switch transistor is also taken as a PMOS transistor and the second type of switch transistor is taken as an NMOS transistor, but each switch transistor in each embodiment can also be other types of voltage-controlled transistors, which is not limited in this application. The control terminal of the first switch transistor QP1 is used to receive an address enable signal, and the first terminal of the first switch transistor QP1 is used to receive an enable control signal EN. When the address enable signal is in a first level state and the enable control signal EN is in a second level state, the first switch transistor QP1 is used to output a first selection signal in a second level state through the second terminal of the first switch transistor QP1. In the embodiment of the application, the use of the first switch transistor QP1 can provide a fast response to the enable control signal EN, thereby enabling timely switching of the level state of the output terminal of the first write unit 110.

[0049] Referring again to Figure 3, in one embodiment, the enable write module 100 further includes a first reset unit 111. The first reset unit 111 is connected to the output terminal of the first write unit 110. The first reset unit 111 is used to reset the level state of the output terminal of the first write unit 110 after the selection module 200 outputs either a frame start signal STV or a first gate drive signal in. For example, if the first write unit 110 includes a first switch QP1, the first reset unit 111 is connected to the second terminal of the first switch QP1 to reset the level state of the second terminal of the first switch QP1. Optionally, the first reset unit 111 can reset the level state of the second terminal of the first switch QP1 after the address enable signal returns to the second level state, or it can reset the level state of the second terminal of the first switch QP1 after the enable control signal EN returns to the first level state; this embodiment does not limit the scope of the reset unit. In the embodiments of the application, by setting a first reset unit 111, the charge at the output terminal of the first write unit 110 can be released, thereby reducing the influence of residual charge on the first write unit 110, thereby reducing the distortion of the first selection signal generated next time and improving the reliability of the addressing circuit.

[0050] Referring again to Figure 3, in one embodiment, the first reset unit 111 includes a second switch. The second switch is a second type NMOS transistor QN1, and the control terminal of the second switch QN1 is used to receive a first reset signal TRST1. The first reset signal TRST1 can originate from the display driver chip. After the selection module 200 completes its output, the display driver chip generates a first reset signal TRST1 with a target level state to prevent premature reset that could cause abnormal triggering of the downstream gate drive circuit, thus preventing the generation of the second gate drive signal. It is understood that the target level states of different signals can be different and can be determined according to the type of switch they control. For example, the target level state of the address enable signal is a low level state, and the target level state of the first reset signal TRST1 is a high level state. Therefore, when the second switch QN1 is a second type NMOS transistor, the target level state of the first reset signal TRST1 is a high level state, so that the second switch QN1 is turned on when the first reset signal TRST1 is in a high level state. The first terminal of the second switch QN1 is connected to a low-level voltage VGL, and the second terminal of the second switch QN1 is connected to the second terminal of the first switch QP1. That is, the second switch QN1 is turned on when the first reset signal TRST1 is in a high-level state to provide a low-level signal to the output terminal of the first write unit 110, thereby resetting the first write unit 110.

[0051] Figure 4 is a second circuit diagram of an enable write module 100 according to one embodiment. Referring to Figure 4, in one embodiment, the enable write module 100 further includes a first locking unit 120. The first locking unit 120 is connected to the first write unit 110 and the selection module 200, respectively, and is used to maintain the level state of the output terminal of the first write unit 110. Specifically, the first locking unit 120 can be understood as a 1-bit latch, used to latch the first selection signal output by the first write unit. It is understood that as the time interval between the write time and the enable control signal EN increases, the signal at the output terminal of the first write unit 110 will also drift, which may lead to the selection error of the selection module 200, and thus the incorrect triggering of the gate drive circuit at the back end. In the embodiment of the application, locking the first selection signal by the first locking unit 120 can make the first selection signal received by the selection module 200 more stable.

[0052] Further, continuing to refer to FIG4, in one embodiment, the first locking unit 120 is also used to generate a second selection signal based on the first selection signal. That is, the enable write module 100 also has another output node N2. The selection module 200 is used to output one of the frame start signal STV and the first gate drive signal in based on the first selection signal and the second selection signal. Therefore, by further generating a second selection signal that is associated with the level state of the first selection signal, and by making the selection module 200 controlled by the first selection signal and the second selection signal, the correct selection of the first gate drive signal in and the frame start signal STV can still be guaranteed even if the level state of either selection signal is not stable enough, thereby improving the reliability of the addressing circuit. The level state of the first selection signal may be opposite to the level state of the second selection signal.

[0053] Referring again to FIG4, in one embodiment, the first locking unit 120 includes a first inverter 121 and a second inverter 122.

[0054] The input terminal (N1 point) of the first inverter 121 is connected to the first writing unit 110 and the selection module 200, respectively. The first inverter 121 is used to flip the level state of the input first selection signal to generate a second selection signal. The input terminal (N2 point) of the second inverter 122 is connected to the output terminal of the first inverter 121, and the output terminal of the second inverter 122 is connected to the input terminal of the first inverter 121 and the selection module 200, respectively. The second inverter 122 is used to flip the level state of the input second selection signal to maintain the level state of the output terminal of the first writing unit 110.

[0055] Taking point N1 as a high-level state as an example, the first inverter 121, under the influence of the high-level state of point N1, outputs a low-level signal to the input of the second inverter 122. The second inverter 122, in turn, under the influence of the low-level state at its input, outputs a high-level signal to point N1. This cyclical action stabilizes the level of point N2 at a low level. Similarly, when point N1 is low, point N2 can also be stabilized at a high level under the combined action of the second inverter 122 and the first inverter 121. That is, this embodiment provides a strong-point interlocking first locking unit 120, where the outputs of the two inverters are each other's inputs, forming a bistable structure. This structure can maintain a constant level until a new state is written. Therefore, it can effectively resist interference factors such as temperature, making the level of the signal output by the first locking unit 120 more stable, thereby improving the stability of the gate drive signal output by the addressing circuit. Moreover, latches have a relatively simple structure, occupy less space, and can quickly respond to changes in input signals, enabling fast signal processing.

[0056] In one embodiment, the first inverter 121 includes a fourteenth switch and a fifteenth switch. The fourteenth switch is a first-type PMOS transistor QP8, and the fifteenth switch is a second-type NMOS transistor QN8. The control terminal of the fourteenth switch QP8 is connected to the second terminal of the first PMOS transistor QP1, the first terminal of the fourteenth switch QP8 is connected to a high-level voltage VGH, and the second terminal of the fourteenth switch QP8 serves as the output terminal of the first inverter 121. The control terminal of the fifteenth switch QN8 is connected to the second terminal of the first PMOS transistor QP1, the first terminal of the fifteenth switch QN8 is connected to a low-level voltage VGL, and the second terminal of the fifteenth switch QN8 is connected to the second terminal of the fourteenth switch QP8. The second inverter 122 includes a sixteenth switch and a seventeenth switch. The sixteenth switch is a first-type PMOS transistor QP9, and the seventeenth switch is a second-type NMOS transistor QN9. Similarly, the control terminal of the sixteenth switch QP9 is connected to the second terminal of the fourteenth switch QP8, the first terminal of the sixteenth switch QP9 is connected to the high-level voltage VGH, the second terminal of the sixteenth switch QP9 serves as the output terminal of the second inverter 122, and is connected to the second terminal of the first PMOS transistor QP1. The control terminal of the seventeenth switch QN9 is connected to the second terminal of the fourteenth switch QP8, the first terminal of the seventeenth switch QN9 is connected to the low-level voltage VGL, and the second terminal of the seventeenth switch QN9 is connected to the second terminal of the sixteenth switch QP9. In the embodiment of the application, the fourteenth switch QP8 and the fifteenth switch QN8 are used to form the first inverter 121, and the sixteenth switch QP9 and the seventeenth switch QN9 are used to form the second inverter 122. The circuit components are few and the connection relationship is simple, thereby providing a small-sized addressing circuit.

[0057] Figure 5 is a second schematic diagram of the addressing circuit in one embodiment. Referring to Figure 5, in one embodiment, the addressing circuit further includes an initial write module 300. The output node of the initial write module 300 is point M, which is also the input node of the write-capable module 100. The initial write module 300 is used to receive a clock signal and a frame start signal STV, and generates an address enable signal based on the frame start signal STV when the clock signal meets a preset level condition. The clock signal is directly powered by the display driver chip, and the transition speed of the clock signal during level switching is very fast. That is, the rise time and fall time of the clock signal are both short, resulting in better signal quality. Therefore, the address enable signal generated by the initial write module 300 based on the clock signal also has good signal quality. In the embodiments of the application, compared to directly controlling the on / off state of the first switch QP1 with a fixed-level address enable signal, the address enable signal generated by the initial write module 300 has higher reliability. Specifically, when the address enable signal is generated by the initial write module 300, it also has good timing due to the timing control of the clock signal and the start-of-frame signal STV. Therefore, if there are deviations in the characteristics of devices such as switches in the enable write module 100, the voltage at the output node N1 of the enable write module 100 can be controlled by the timing of the address enable signal, thereby reducing the probability of voltage abnormalities at the output node of the enable write module 100 and improving the stability and reliability of the addressing circuit.

[0058] Referring again to Figure 5, in one embodiment, the initial write module 300 includes a second write unit 310 and a third write unit 320, with the third write unit 320 connected to the second write unit 310. The output node of the second write unit 310 and the input node of the third write unit 320 are both Q-points, and the output node of the third write unit 320 is an M-point. The second write unit 310 receives a frame start signal STV and, when the first clock signal TCK1 is at a second level, generates an addressing initial signal based on the frame start signal STV to change the level state of the Q-point. The second write unit 310 is also used to maintain the level state of its output terminal unchanged when the first clock signal TCK1 is at a first level. By maintaining the level state of the output terminal of the second write unit 310 unchanged, the signal received by the third write unit 320 can be made stable and reliable. The third write unit 320 generates an address enable signal based on the addressing initial signal when the second clock signal TCK2 is at a second level to change the level state of the M-point. In this embodiment, the first clock signal TCK1 and the second clock signal TCK2 are not simultaneously in the second level state to avoid timing errors in the initial write module 300. In the application embodiment, through the cooperation of the second write unit 310 and the third write unit 320, a timing-reliable address enable signal can be generated, enabling the write module 100 to locate the local refresh area based on the address enable signal and the enable control signal EN.

[0059] Figure 6 is a circuit diagram of a second write unit 310 according to one embodiment. Referring to Figure 6, in one embodiment, the second write unit 310 includes a third switch, a fourth switch, and a third inverter 311. The third switch is a first-type switch QP2, and the fourth switch is a second-type NMOS transistor QN2. The control terminal of the third switch QP2 is used to receive a third clock signal TCK1B, and the first terminal of the third switch QP2 is used to connect to a high-level voltage VGH. The third switch QP2 is turned on when the third clock signal TCK1B is low and turned off when the third clock signal TCK1B is high. The first terminal of the fourth switch QN2 is used to connect to a low-level voltage VGL, and the control terminal of the fourth switch QN2 is used to receive a first clock signal TCK1. The fourth switch QN2 is turned on when the first clock signal TCK1 is high and turned off when the first clock signal TCK1 is low. The level of the first clock signal TCK1 is opposite to that of the third clock signal TCK1B, so that the third switch QP2 and the fourth switch QN2 are turned on synchronously.

[0060] The third inverter 311 is connected to the second terminals of the third switch QP2 and the fourth switch QN2, respectively. That is, at the falling edge of the third clock signal TCK1B, a high-level voltage VGH is transmitted to the third inverter 311. Simultaneously, at the rising edge of the first clock signal TCK1, a low-level voltage VGL is also transmitted to the third inverter 311. The third inverter 311 is used to generate an addressing initial signal by flipping the level of the frame start signal STV input to the third inverter 311 when the third switch QP2 and the fourth switch QN2 are turned on. Optionally, the addressing circuit can directly output the signal flipped by the third inverter 311 as the addressing initial signal. Alternatively, the addressing circuit can connect other circuit modules after the third inverter 311 and process the signal flipped by the third inverter 311 to generate the addressing initial signal. That is, this embodiment only limits the signal output by the third inverter 311 to be associated with the addressing initial signal, but does not limit the signal output by the third inverter 311 to be the addressing initial signal.

[0061] Furthermore, the level state of the frame start signal STV received by the third inverter 311 is switched when the third clock signal TCK1B is high. That is, the level state of the frame start signal STV is switched when both the third switch QP2 and the fourth switch QN2 are off, so that the output of the third inverter 311 can remain unchanged when the third switch QP2 and the fourth switch QN2 are on, thereby avoiding abnormal gate drive signals output by the timing conflict addressing circuit.

[0062] In the embodiment of the application, at the falling edge of the third clock signal TCK1B, a high-level voltage VGH is transmitted to the third inverter 311. Simultaneously, the first clock signal TCK1 is at its rising edge, and a low-level voltage VGL is also synchronously transmitted to the third inverter 311. This allows the third inverter 311 to flip the frame start signal STV under the combined action of the high-level voltage VGH and the low-level voltage VGL. Therefore, the timing of the level flip by the third inverter 311 is only determined by the clock signal. Based on the good signal quality of the clock signal, the quality of the address initial signal output by the third inverter 311 can be ensured, thereby improving the display effect and reliability of the display panel.

[0063] Referring again to Figure 6, in one embodiment, the third inverter 311 includes an eighteenth switch and a nineteenth switch. The eighteenth switch is a first-type PMOS transistor QP10, and the nineteenth switch is a second-type NMOS transistor QN10. The control terminal of the eighteenth switch QP10 is used to receive the frame start signal STV. The first terminal of the eighteenth switch QP10 is connected to the second terminal of the third switch QP2, and the second terminal of the eighteenth switch QP10 serves as the output terminal of the third inverter 311. The control terminal of the nineteenth switch QN10 is used to receive the frame start signal STV. The first terminal of the nineteenth switch QN10 is connected to the second terminal of the fourth switch QN2, and the second terminal of the nineteenth switch QN10 is connected to the second terminal of the eighteenth switch QP10. Therefore, when the third switch QP2 is turned on, the first terminal of the eighteenth switch QP10 receives a high-level voltage VGH. Simultaneously, the fourth switch QN2 is turned on, causing the first terminal of the nineteenth switch QN10 to receive a low-level voltage VGL, thus forming the structure of the third inverter 311. In the embodiment of the application, the eighteenth switch QP10 and the nineteenth switch QN10 are used to form the third inverter 311, resulting in fewer circuit components and simpler connections, thereby providing a small-sized addressing circuit.

[0064] Referring again to Figure 6, in one embodiment, the second write unit 310 further includes a holding unit 312. The holding unit 312 is connected to the output of the third inverter 311, and its input node is point P. The holding unit 312 is used to maintain the level of the output of the third inverter 311 when the third clock signal TCK1B is high. It is understood that the pixel circuit of the display panel needs to be refreshed line by line. Accordingly, the third switch QP2 and the fourth switch QN2 in the addressing circuit corresponding to the non-refreshed line will not always be on. Therefore, the third inverter 311 will not receive the high-level voltage VGH and the low-level voltage VGL during certain periods, resulting in the third inverter 311 being unable to flip the input frame start signal STV, causing the third inverter 311 to have no signal output during those periods. Therefore, this embodiment introduces the holding unit 312 to maintain the level of the output of the third inverter 311. Optionally, the holding unit 312 can be, for example, an output capacitor, which can store charge when the third switch QP2 and the fourth switch QN2 are turned on, and release charge when the third switch QP2 and the fourth switch QN2 are turned off, so as to maintain the level state of the output terminal of the third inverter 311.

[0065] Furthermore, the holding unit 312 is also used to generate an addressing initial signal, which is opposite to the level state of the output terminal of the third inverter 311. That is, the addressing initial signal and the signal output by the third inverter 311 have the same duty cycle, but the voltage amplitude and phase of the signal may not be exactly the same. It is understood that even when the third switch QP2 and the fourth switch QN2 are off, there may still be residual charge in the third inverter 311, which will cause slight fluctuations in the output signal of the third inverter 311. In the embodiment of the application, by inverting the input signal based on the holding unit 312, slight fluctuations in the input signal can be filtered out, thereby making the stability of the output addressing initial signal higher than that of the signal output by the third inverter 311, so as to greatly improve the reliability of the addressing initial signal while ensuring that the information carried by the signal remains unchanged.

[0066] Referring again to FIG6, in one embodiment, the holding unit 312 includes a fifth switch, a sixth switch, and a second locking unit 313.

[0067] In this design, the fifth switch is a type-1 PMOS transistor QP3, and the sixth switch is a type-2 NMOS transistor QN3. The control terminal of the fifth switch QP3 receives the first clock signal TCK1, and its first terminal is connected to a high-level voltage VGH. The fifth switch QP3 is turned on when the first clock signal TCK1 is low and turned off when TCK1 is high. Similarly, the control terminal of the sixth switch QN3 receives the third clock signal TCK1B, and its first terminal is connected to a low-level voltage VGL. The sixth switch QN3 is turned on when the third clock signal TCK1B is high and turned off when TCK1B is low.

[0068] The second locking unit 313 is connected to the output terminal of the third inverter 311, the second terminal of the fifth switch QP3, and the second terminal of the sixth switch QN3, respectively. The second locking unit 313 is used to maintain the level state of the output terminal of the third inverter 311 unchanged and generate an addressing initial signal when the fifth switch QP3 and the sixth switch QN3 are turned on. Specifically, the second locking unit 313 can be understood as a 1-bit latch used to latch the input signal. It is understood that although the output capacitor can maintain the stability of the output signal to a certain extent, as the output capacitor continuously discharges, the signal at point Q of the output terminal of the second locking unit 313 will also drift, which may lead to control errors in the third write unit 320. In the embodiment of the application, the second locking unit 313, which adopts a latch structure, is directly powered by a high-level voltage VGH and a low-level voltage VGL when the fifth switch QP3 and the sixth switch QN3 are turned on, providing a stable addressing initial signal, thereby improving the stability and reliability of the addressing circuit output signal.

[0069] Referring again to FIG6, in one embodiment, the second locking unit 313 includes a sixth inverter 3132 and a fifth inverter 3131.

[0070] The input terminal of the fifth inverter 3131 is connected to the output terminals of the third inverter 311 and the sixth inverter 3132, respectively. The output terminal of the fifth inverter 3131 is connected to the input terminal of the sixth inverter 3132. The fifth inverter 3131 is used to flip the level state of the input signal. The sixth inverter 3132 is connected to the second terminal of the fifth switch QP3 and the second terminal of the sixth switch QN3, respectively. The sixth inverter 3132 is used to flip the level state of the input signal when the fifth switch QP3 and the sixth switch QN3 are turned on.

[0071] Specifically, taking point P as a high-level state as an example, the fifth inverter 3131, under the influence of the high-level state of point P, outputs a low-level signal to the input of the sixth inverter 3132. The sixth inverter 3132, in turn, under the influence of the low-level state at its input, outputs a high-level signal to point P. This cyclical action stabilizes the level of point Q at a low level. Similarly, when point P is low, point Q can also be stabilized at a high level under the combined action of the sixth inverter 3132 and the fifth inverter 3131. That is, this embodiment provides a strong-point interlocking second locking unit 313 structure, where the outputs of the two inverters are each other's inputs, forming a bistable structure. This structure can maintain a constant level until a new state is written. Therefore, it can effectively resist interference factors such as temperature, making the level of the address initial signal output by the second locking unit 313 more stable, thereby improving the stability of the address initial signal output by the addressing circuit. Moreover, latches have a relatively simple structure, occupy less space, and can quickly respond to changes in input signals, enabling fast signal processing.

[0072] Referring again to Figure 6, in one embodiment, the fifth inverter 3131 includes a twentieth switch and a twenty-first switch. The twentieth switch is a first-type PMOS transistor QP11, and the twenty-first switch is a second-type NMOS transistor QN11. The control terminal of the twentieth switch QP11 is connected to the output terminal of the sixth inverter 3132. The first terminal of the twentieth switch QP11 is connected to a high-level voltage VGH, and the second terminal of the twentieth switch QP11 is connected to the input terminal of the sixth inverter 3132. The control terminal of the twenty-first switch QN11 is connected to the output terminal of the sixth inverter 3132. The first terminal of the twenty-first switch QN11 is connected to a low-level voltage VGL, and the second terminal of the twenty-first switch QN11 is connected to the second terminal of the twentieth switch QP11. In the embodiment of the application, the fifth inverter 3131 is formed using the twentieth switch QP11 and the twenty-first switch QN11, resulting in fewer circuit components and simpler connections, thereby providing a small-sized addressing circuit.

[0073] Referring again to Figure 6, in one embodiment, the sixth inverter 3132 includes a twenty-second switch and a twenty-third switch. The twenty-second switch is a first-type PMOS transistor QP12, and the twenty-third switch is a second-type PMOS transistor QN12. The second terminal of the twenty-second switch QP12 is connected to its first terminal, and the first terminal of QP12 is connected to the output terminal of the third inverter 311. The control terminal of the twenty-second switch QP12 is connected to the output terminal of the fifth inverter 3131. Similarly, the second terminal of the twenty-third switch QN12 is connected to its first terminal, and the first terminal of QN12 is connected to the first terminal of the twenty-second switch QP12. The control terminal of QN12 is connected to the output terminal of the fifth inverter 3131. Therefore, when the 22nd switch QP12 is turned on, its second terminal receives a high-level voltage VGH. Simultaneously, the 23rd switch QN12 is turned on, causing its second terminal to receive a low-level voltage VGL, thus forming the structure of the sixth inverter 3132. In the embodiment of the application, the 22nd and 23rd switches QP12 are used to form the sixth inverter 3132, resulting in fewer circuit components and simpler connections, thereby providing a small-sized addressing circuit.

[0074] Figure 7 is a circuit diagram of a third writing unit 320 according to an embodiment. Referring to Figure 7, in one embodiment, the third writing unit 320 includes a fourth inverter 321 and an eighth switch.

[0075] The fourth inverter 321 is connected to both the second write unit 310 and the enable write module 100. When the second clock signal TCK2 is at its second level, the fourth inverter 321 inverts the address initial signal and transmits it to the enable write module 100 as an address enable signal. Further, the third write unit 320 includes a ninth switch, which is a second-type NMOS transistor QN5. The control terminal of the ninth switch QN5 receives the second clock signal TCK2, the first terminal of the ninth switch QN5 is connected to a low-level voltage VGL, and the second terminal of the ninth switch QN5 is connected to the fourth inverter 321. Specifically, when the second clock signal TCK2 is at its second level, the ninth switch QN5 provides a low-level signal to the fourth inverter 321, causing the fourth inverter 321 to invert the address initial signal as an address enable signal. The eighth switch is a first-type PMOS transistor QP4. The control terminal of the eighth switch QP4 is used to receive the second clock signal TCK2. The first terminal of the eighth switch QP4 is used to connect to the high-level voltage VGH. The second terminal of the eighth switch QP4 is connected to the enable write module 100. When the second clock signal TCK2 is in the first level state, the eighth switch QP4 is used to transmit a high-level signal to the enable write module 100 as an address selection enable signal.

[0076] In the embodiment of the application, under the control of the second clock signal TCK2, the fourth inverter 321 and the eighth switch QP4 time-divisionally control the level state of the output terminal of the third writing unit 320, thereby controlling the first switch QP1 to periodically turn on and off, so that the enable control signal EN is written at an appropriate time period and changes the level state of the first selection signal received by the selection module 200. Moreover, during the time period when the enable control signal EN does not need to be written, the eighth switch QP4 can remain on under the control of the second clock signal TCK2 to clamp the control terminal of the first switch QP1 to a high level state, avoiding the influence of the enable control signal EN on the level state of the first selection signal transmitted to the module.

[0077] Referring again to Figure 7, in one embodiment, the fourth inverter 321 includes a twenty-fourth switch and a twenty-fifth switch. The twenty-fourth switch is a first-type PMOS transistor QP13, and the twenty-fifth switch is a second-type NMOS transistor QN13. The control terminal of the twenty-fourth switch QP13 is connected to the second write unit 310, its first terminal is connected to a high-level voltage VGH, and its second terminal serves as the output terminal of the fourth inverter 321. The control terminal of the twenty-fifth switch QN13 is connected to the second write unit 310, its first terminal is connected to a low-level voltage VGL, and its second terminal is connected to the second terminal of the twenty-fourth switch QP13.

[0078] Figure 8 is a circuit diagram of an initial write module 300 according to one embodiment. Referring to Figure 8, in one embodiment, the initial write module 300 further includes a second reset unit 330. The second reset unit 330 is connected to the second write unit 310 and is used to receive a second reset signal TRST2 and, under the control of the second reset signal TRST2, reset the level state of the output terminal (i.e., Q point) of the second write unit 310. Specifically, the second reset unit 330 can reset the level state of the output terminal of the second write unit 310 in response to the rising or falling edge of the second reset signal TRST2. In the embodiments of the application, the second reset unit 330 can release the charge of the Q point by switching the level state of the output terminal of the second write unit 310, thereby reducing the distortion of the addressing initial signal and improving the reliability of the addressing initial signal. It is understood that if the Q point is reset during the display process, it may cause the display panel to flicker. Therefore, the display driver chip can provide the above-mentioned edge that can control the second reset unit 330 to reset when the display panel is not displaying an image. For example, the second reset unit 330 can be controlled to reset when the display panel is powered on or off, thereby reducing the problem of display panel flickering and improving the user's viewing experience.

[0079] Referring again to Figure 8, in one embodiment, the second reset unit 330 includes a seventh switch, which is a second type NMOS transistor QN4. The control terminal of the seventh switch QN4 is used to receive the second reset signal TRST2. The first terminal of the seventh switch QN4 is connected to a low-level voltage VGL, and the second terminal of the seventh switch QN4 is connected to the output terminal of the second write unit 310. That is, the seventh switch QN4 is turned on when the second reset signal TRST2 is in a high-level state to provide a low-level signal to the output terminal of the second write unit 310, thereby resetting the second write unit 310.

[0080] Figure 9 is a circuit diagram of a selection module 200 according to one embodiment. Referring to Figure 9, in one embodiment, the selection module 200 includes a first selection unit 210 and a second selection unit 220. The first selection unit 210 is connected to the enable / write module 100 and is used to receive a first gate drive signal in and a first selection signal. The first selection unit 210 is used to output the first gate drive signal in when the first selection signal is at a first level. The second selection unit 220 is connected to the enable / write module 100 and is used to receive a frame start signal STV and the first selection signal. The second selection unit 220 is used to output the frame start signal STV when the first selection signal is at a second level. That is, the first selection unit 210 and the second selection unit 220 output in a time-division multiplexing manner, and the signals output by the first selection unit 210 and the second selection unit 220 do not interfere with each other, thereby improving the stability of the output signal of the selection module 200.

[0081] In one embodiment, the first selection unit 210 includes a tenth switch and an eleventh switch. The tenth switch is a first-type PMOS transistor QP6, the control terminal of which is used to receive a first selection signal, and the first terminal of which is used to receive a first gate drive signal in. The eleventh switch is a second-type NMOS transistor QN6, the control terminal of which is used to receive a second selection signal, and the first terminal of which is used to receive the first gate drive signal in. The second terminals of the tenth and eleventh switches serve as the output terminals of the selection module 200. Specifically, because the first selection signal and the second selection signal have opposite levels under the action of the first locking unit 120, and the on / off logic of the tenth and eleventh switches QP6 and QN6 is also opposite, the tenth and eleventh switches QP6 and QN6 can be synchronously turned on under the control of their respective selection signals. Therefore, if the tenth and eleventh switches QP6 and QN6...

[0082] In one embodiment, the second selection unit 220 includes a twelfth switch and a thirteenth switch. The twelfth switch is a second type of NMOS transistor, its control terminal is used to receive a first selection signal, and its first terminal is used to receive a frame start signal (STV). The thirteenth switch is a first type of switch, its control terminal is used to receive a second selection signal, and its first terminal is used to receive the frame start signal (STV). The second terminals of the tenth switch (QP6), the eleventh switch (QN6), the twelfth switch, and the thirteenth switch are connected to serve as the output terminals of the selection module 200.

[0083] Figure 10 is a circuit diagram of an addressing circuit according to an embodiment. Referring to Figure 10, the addressing circuit includes an initial write module 300, an enable write module 100, and a selection module 200. The initial write module 300 includes a second write unit 310, a third write unit 320, and a second reset unit 330. The second write unit 310 includes a third switch QP2, a fourth switch QN2, a third inverter 311, and a holding unit 312. The enable write module 100 includes a first write unit 110 and a first locking unit 120. The first locking unit 120 includes a first inverter 121 and a second inverter 122. The selection module 200 includes a first selection unit 210 and a second selection unit 220. It is understood that the connection relationships and composition of the above structures can be referred to the foregoing embodiments, and will not be repeated here.

[0084] This application also provides a display panel. FIG11 is a schematic diagram of a display panel according to an embodiment. Referring to FIG11, the display panel includes multiple pixel circuits 20, multiple gate driving circuits 30, and multiple addressing circuits 10 as described above. The multiple pixel circuits 20 are arranged in multiple rows, and each pixel circuit 20 includes multiple transistors. The output terminal of each gate driving circuit 30 is respectively connected to at least a portion of the transistors in the multiple pixel circuits 20 located in each row, so as to control the connected transistors to turn on and off through a gate driving signal. The addressing circuits 10 are respectively connected to the gate driving circuits 30 of two adjacent stages, and are used to trigger the next stage gate driving circuit 30 to generate a second gate driving signal based on one of the frame start signal STV and the first gate driving signal in from the previous stage gate driving circuit 30. Specifically, if the display panel is in a global refresh scenario, each pixel row needs to be refreshed row by row. The nth stage addressing circuit 10 can output the first gate driving signal in of the (n-1)th stage gate driving circuit 30 to trigger the nth stage gate driving circuit 30 to generate a second gate driving signal, making the control logic simple and convenient. If the display panel is under partial overclocking or partial frequency conversion, only a portion of the pixel rows need to be refreshed during certain periods. Therefore, the addressing circuit 10 corresponding to the target row can output a frame start signal STV, and the nth-level addressing circuit 10 corresponding to other rows besides the target row can output the first gate drive signal in of the (n-1)th-level gate drive circuit 30. Here, the target row refers to a pixel row with a different refresh rate than the previous row; that is, the target row and its predecessor are not refreshed sequentially, so the target row cannot be triggered by the first gate drive signal in of the previous row. In the embodiments described in the application, the aforementioned addressing circuit 10 enables flexible, frequency-converting refresh of a portion of the pixel rows.

[0085] In one embodiment, the same gate drive signal can drive multiple pixel circuits 20 in adjacent rows. For example, by driving multiple pixel circuits 20 in two adjacent rows with the same gate drive signal, the power consumption of the gate drive circuit 30 can be reduced. Specifically, the gate drive circuits 30 of each odd-numbered level can be cascaded sequentially, and the gate drive circuits 30 of each even-numbered level can be cascaded sequentially. Each pair of adjacent gate drive circuits 30 forms a gate drive circuit group 30, and each gate drive circuit group 30 corresponds to two adjacent rows of pixel circuits 20. The two gate drive circuits 30 in the same gate drive circuit group 30 are electrically connected to the gate lines of the corresponding two rows of pixel circuits 20. When the gate drive circuit 30 is working, the gate drive circuits 30 of odd-numbered levels and the gate drive circuits 30 of even-numbered levels work alternately according to a preset switching cycle. When the gate drive circuit 30 of odd-numbered levels is working, it receives a clock signal and uses the clock signal to generate a gate drive signal to drive the transistors in the connected two rows of pixel circuits 20. When the even-numbered gate drive circuits 30 are operating, they receive a clock signal and use it to generate a gate drive signal to drive the transistors in the two connected pixel circuits 20. Corresponding to this configuration of the gate drive circuits 30, during partial refresh, the phase of the enable control signal EN needs to be aligned with the clock signal according to the connection relationship of the gate drive circuits 30 corresponding to the target row to ensure the correct writing of the enable control signal EN.

[0086] This application also provides a display screen. Figure 12 is a schematic diagram of the structure of a display screen according to an embodiment. Referring to Figure 12, the display screen includes a cover plate 40 and a display panel as described above. The cover plate is disposed on the light-emitting side of the display panel and covers the display panel. In the embodiments of this application, by providing the cover plate 40, the display panel can be protected, reducing damage to the display panel from external forces, thereby improving the reliability of the display panel.

[0087] In one embodiment, the display screen further includes a display driver chip 50. The display driver chip 50 is connected to the display panel and outputs a frame start signal STV and an enable control signal EN to the addressing circuit 10. In the embodiments described, by controlling the switching timing of the level state of the frame start signal STV output by the display driver chip 50, timing conflicts between the frame start signal STV and the clock signal can be effectively avoided, thereby preventing abnormalities in the addressing circuit 10 caused by timing conflicts and improving the operational reliability of the addressing circuit 10. Furthermore, the enable control signal EN output by the display driver chip 50 allows the addressing circuit 10 to select either the frame start signal STV or the first gate drive signal in to trigger the current gate drive circuit 30, enabling flexible, variable-frequency refresh of certain pixel rows.

[0088] This application embodiment also provides a display device, including the display screen as described above. Specifically, the display device can be, but is not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices. IoT devices can be smart speakers, smart TVs, smart air conditioners, smart in-vehicle devices, etc. Portable wearable devices can be smartwatches, smart bracelets, head-mounted devices, etc. Figure 13 is an internal structural diagram of a display device according to an embodiment. Referring to Figure 13, the display device includes a processor, a memory, a communication interface, a display screen, and an input device connected via a system bus. The processor of the display device provides computing and control capabilities. The memory of the display device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The communication interface of the display device is used for wired or wireless communication with external terminals. Wireless communication can be achieved through WIFI, mobile cellular networks, NFC (Near Field Communication), or other technologies. The input device of the display device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the display device, or external keyboards, touchpads, or mice, etc.

[0089] Those skilled in the art will understand that the structure shown in FIG13 is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the display device to which the present application is applied. A specific display device may include more or fewer components than those shown in FIG13, or combine certain components, or have different component arrangements.

[0090] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0091] The above embodiments merely illustrate several implementation methods of the embodiments of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the embodiments of this application, and these all fall within the protection scope of the embodiments of this application. Therefore, the protection scope of the patent for the embodiments of this application should be determined by the appended claims.

Claims

1. An addressing circuit, the addressing circuit being connected to a current stage gate driving circuit and a previous stage gate driving circuit respectively, the addressing circuit comprising: An enable write module is used to receive an enable control signal and generate a first selection signal based on the enable control signal. The selection module is connected to the enable write module. The selection module is used to receive the frame start signal and the first gate drive signal output by the previous stage gate drive circuit, and output one of the frame start signal and the first gate drive signal to the current stage gate drive circuit according to the first selection signal, so as to trigger the current stage gate drive circuit to generate a second gate drive signal.

2. The addressing circuit according to claim 1, wherein the enable write module comprises: The first writing unit is configured to receive the address enable signal and the enable control signal respectively. The first writing unit is configured to generate the first selection signal having a target level state when the address enable signal is in a first level state and the enable control signal is in a second level state.

3. The addressing circuit according to claim 2, wherein the first writing unit comprises: The first switching transistor has a control terminal for receiving the address enable signal, a first terminal for receiving the enable control signal, and a second terminal for outputting the first selection signal at the second level when the address enable signal is at a first level and the enable control signal is at a second level. The first switching transistor is a first type of switching transistor, which is used to turn on when the signal received at the control terminal is in a low-level state.

4. The addressing circuit according to claim 3, wherein the enable write module further comprises: The first reset unit, connected to the second terminal of the first switch, is used to reset the level state of the output terminal of the first write unit after the selection module outputs one of the frame start signal and the first gate drive signal.

5. The addressing circuit according to claim 4, wherein the first reset unit comprises: The second switch is a second type of switch. The control terminal of the second switch is used to receive the first reset signal. The first terminal of the second switch is used to connect to a low-level voltage. The second terminal of the second switch is connected to the second terminal of the first switch.

6. The addressing circuit according to claim 2, wherein the enable write module further comprises: The first locking unit is connected to the first writing unit and the selection module respectively, and is used to maintain the level state of the output terminal of the first writing unit and generate a second selection signal according to the first selection signal; The level states of the first selection signal and the second selection signal are opposite. The selection module is used to output one of the frame start signal and the first gate drive signal according to the first selection signal and the second selection signal.

7. The addressing circuit according to claim 6, wherein the first locking unit comprises: A first inverter, the input terminals of which are respectively connected to the first writing unit and the selection module, is used to flip the level state of the input first selection signal to generate a second selection signal; The second inverter has its input connected to the output of the first inverter, and its output connected to both the input of the first inverter and the selection module. The second inverter is used to flip the level of the input second selection signal to maintain the level of the output of the first writing unit.

8. The addressing circuit according to claim 2, further comprising: The initial write module is used to receive a clock signal and the frame start signal, and generate the address enable signal according to the frame start signal when the clock signal meets a preset level condition.

9. The addressing circuit according to claim 8, wherein the initial write module comprises: The second writing unit is used to receive the frame start signal, generate an address initial signal according to the frame start signal when the first clock signal is in the second level state, and keep the level state of the output terminal of the second writing unit unchanged when the first clock signal is in the first level state. The third write unit, connected to the second write unit, is used to generate the address enable signal according to the address initial signal when the second clock signal is in the second level state. Wherein, the first clock signal and the second clock signal are not simultaneously in the second level state.

10. The addressing circuit according to claim 9, wherein the second writing unit comprises: The third switch is a first type of switch. The control terminal of the third switch is used to receive a third clock signal, and the first terminal of the third switch is used to connect to a high-level voltage. The third switch is used to turn on when the third clock signal is in a first-level state. The level state of the third clock signal is opposite to the level state of the first clock signal. The fourth switch is a second type of switch. The control terminal of the fourth switch is used to receive the first clock signal, the first terminal of the fourth switch is used to connect to a low-level voltage, and the fourth switch is used to turn on when the first clock signal is in a second-level state. The third inverter is connected to the second terminal of the third switch and the second terminal of the fourth switch, respectively. The third inverter is used to receive the frame start signal and to flip the level state of the frame start signal when the first clock signal is in the second level state to generate the address initial signal.

11. The addressing circuit according to claim 10, wherein the second writing unit further comprises: A holding unit is connected to the third inverter. The holding unit is used to maintain the level state of the output terminal of the third inverter when the first clock signal is in the second level state, and to generate the address initial signal according to the level state of the output terminal of the third inverter.

12. The addressing circuit according to claim 11, wherein the holding unit comprises: The fifth switching transistor is a first type of switching transistor. The control terminal of the fifth switching transistor is used to receive a first clock signal, and the first terminal of the fifth switching transistor is used to connect to a high-level voltage. The sixth switch is a second type of switch. The control terminal of the sixth switch is used to receive the third clock signal, and the first terminal of the sixth switch is used to connect to a low-level voltage. The level state of the third clock signal is opposite to that of the first clock signal. The second locking unit is connected to the second terminal of the fifth switch, the second terminal of the sixth switch, and the output terminal of the third inverter, respectively. The second locking unit is used to maintain the level state of the output terminal of the third inverter when the first clock signal is in the second level state, and to generate the address initial signal according to the level state of the output terminal of the third inverter.

13. The addressing circuit according to claim 9, wherein the initial write module further comprises: The second reset unit is connected to the second write unit and is used to receive the second reset signal and, under the control of the second reset signal, reset the level state of the output terminal of the second write unit.

14. The addressing circuit according to claim 13, wherein the second reset unit comprises: The seventh switch is a second type of switch. The control terminal of the seventh switch is used to receive the second reset signal. The first terminal of the seventh switch is used to connect to a low-level voltage. The second terminal of the seventh switch is connected to the output terminal of the second write unit.

15. The addressing circuit according to claim 9, wherein the third writing unit comprises: The fourth inverter is connected to the second writing unit and the enable writing module respectively. The fourth inverter is used to invert the address initial signal when the second clock signal is in the second level state, and transmit it to the enable writing module as the address enable signal. The eighth switch is a first type of switch. The control terminal of the eighth switch is used to receive the second clock signal. The first terminal of the eighth switch is used to connect to a high-level voltage. The second terminal of the eighth switch is connected to the enable write module. The eighth switch is used to transmit a high-level signal to the enable write module when the second clock signal is in the first level state, as the address selection enable signal.

16. The addressing circuit according to claim 15, wherein the third writing unit further comprises: The ninth switch is a second type of switch. The control terminal of the ninth switch is used to receive the second clock signal. The first terminal of the ninth switch is used to connect to a low-level voltage. The second terminal of the ninth switch is connected to the fourth inverter.

17. The addressing circuit according to claim 1, wherein the selection module comprises: The first selection unit is connected to the enable write module and is used to receive the first gate drive signal. The first selection unit is used to output the first gate drive signal when the first selection signal is in a first level state. The second selection unit, connected to the enable write module, is used to receive the frame start signal. The second selection unit is used to output the frame start signal when the first selection signal is in a second level state.

18. The addressing circuit according to claim 17, wherein the first selection unit comprises a tenth switch and an eleventh switch; The tenth switch is a first type of switch, the control terminal of the tenth switch is used to receive the first selection signal, and the first terminal of the tenth switch is used to receive the first gate drive signal. The eleventh switch is a second type of switch, the control terminal of the eleventh switch is used to receive the second selection signal, and the first terminal of the eleventh switch is used to receive the first gate drive signal. in, The second terminal of the tenth switch and the second terminal of the eleventh switch are connected to serve as the output terminal of the selection module.

19. The addressing circuit according to claim 17, wherein the second selection unit comprises a twelfth switch and a thirteenth switch; The twelfth switch is a second type of switch, the control terminal of the twelfth switch is used to receive the first selection signal, and the first terminal of the twelfth switch is used to receive the frame start signal. The thirteenth switch is a first type of switch, the control terminal of the thirteenth switch is used to receive the second selection signal, and the first terminal of the thirteenth switch is used to receive the frame start signal. in, The second terminal of the twelfth switch and the second terminal of the thirteenth switch are connected to serve as the output terminal of the selection module.

20. A display panel, comprising: Multiple pixel circuits are arranged in multiple rows, and each pixel circuit includes multiple transistors. Multiple gate driving circuits, the output of each gate driving circuit being respectively connected to at least a portion of the transistors in the multiple pixel circuits located in each row, so as to control the connected transistors to be turned on and off by the gate driving signal; Multiple addressing circuits as described in any one of claims 1 to 19, wherein the addressing circuits are respectively connected to the gate driving circuits of two adjacent stages, for triggering the next stage gate driving circuit to generate a second gate driving signal based on one of a frame start signal and a first gate driving signal from the previous stage gate driving circuit.

21. A display screen, comprising: The display panel as described in claim 20; A cover plate is disposed on the light-emitting side of the display panel and covers the display panel.

22. The display screen according to claim 21, further comprising: The display driver chip is connected to the display panel and is used to output a frame start signal and an enable control signal to the addressing circuit.

23. A display device, comprising: The display screen as claimed in any one of claims 21 to 22.

Images