Coding method, decoding method and related apparatus

Abstract

Disclosed in the present application are a coding method, a decoding method, and a related apparatus. On the basis of a codeword length, a preconstructed check matrix can be divided into N check submatrices; when N>1, subdata corresponding to the jth check submatrix and stored data of M preset first registers at the (j+1)th moment can be used for updating stored data at the jth moment; and iteratively updating a current input and stored data at the previous moment can obtain stored data of the M first registers at the 1st moment, so as to determine a syndrome and further calculate redundant check data or invalid data. In this way, the stored data of the M first registers can be iteratively updated in units of the check submatrices, which is equivalent to segmenting the execution logic of coding and decoding in units of the check submatrices, thereby helping to reduce the computing complexity in coding and decoding.

Description

An encoding method, a decoding method, and related apparatus

[0001] This application claims priority to Chinese Patent Application No. 202410918533.1, filed on July 9, 2024, entitled "An Encoding Method, Decoding Method and Related Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of data processing technology, and in particular to an encoding method, a decoding method, and related apparatus. Background Technology

[0003] The explosive growth of data has brought challenges to storage systems, especially the increase in cold data, making storage reliability a hot research topic in the industry. In storage systems, erasure coding (EC) is an important means of solving data loss problems. Its technical implementation mainly involves encoding to generate redundant data blocks, ensuring that the original data can be recovered using these redundant blocks in the event of data loss. EC not only guarantees data storage reliability but also saves storage space and achieves better storage costs. However, current EC encoding and decoding algorithms suffer from high computational complexity based on the parity check matrix, resulting in low encoding and decoding efficiency and requiring a large amount of storage space. Summary of the Invention

[0004] This application provides an encoding method, a decoding method, and related apparatus that can perform encoding and decoding operations on a parity submatrix basis, thereby reducing the computational scale and complexity, and requiring only a small number of registers to complete the encoding and decoding.

[0005] In a first aspect, embodiments of this application provide an encoding method applied to an electronic device or a chip within an electronic device. Taking the application of this method to an electronic device as an example, the method includes:

[0006] Get the data to be encoded and the codeword length;

[0007] N check submatrices are determined from the pre-constructed check matrix based on the codeword length;

[0008] When N > 1, for the j-th parity submatrix among the N parity submatrixes, the storage data of the M first registers at time j is determined based on the first sub-data corresponding to the j-th parity submatrix in the data to be encoded and the storage data of the M first registers at time (j+1), so as to obtain the storage data of the M first registers at time 1; the storage data of the M first registers at time N is determined based on the second sub-data corresponding to the N-th parity submatrix in the data to be encoded and the initial values ​​of the M first registers; where 0 ≤ j ≤ N-1;

[0009] The first corrector is determined based on the stored data of the M first registers at time 1.

[0010] Redundancy check data is determined based on the first corrector to obtain the encoded codeword.

[0011] As can be seen in this embodiment, the pre-constructed parity matrix can be divided into N parity sub-matrices based on the codeword length. When N > 1, the first sub-data corresponding to the j-th parity sub-matrix and the stored data of the M pre-defined first registers at time (j+1) can be used to update the stored data at time j. Iterative updates based on the current input and the stored data at the previous time can obtain the stored data of the M first registers at time 1, thereby determining the first corrector and calculating the redundant parity data to complete the encoding. This iterative update of the stored data of the M first registers in units of parity sub-matrices is equivalent to dividing the encoding execution logic in units of parity sub-matrices. Compared with the scheme of using the entire parity matrix and all the data to be encoded for calculation, the number of elements of the parity matrix and the amount of data to be encoded involved in a single calculation are reduced, thereby reducing the computational scale of encoding and thus helping to reduce the computational complexity of encoding.

[0012] In one possible implementation, the stored data of the M first registers at time j is determined based on the first sub-data corresponding to the j-th parity sub-matrix in the data to be encoded and the stored data of the M first registers at time (j+1), including:

[0013] The first sub-data is grouped to obtain multiple first sub-data groups;

[0014] Based on a preset set of T second registers, the Reid-Muller RM transform algorithm is used to register multiple first sub-data groups to obtain the stored data of T1 second registers at time j; where T1≤T;

[0015] Based on the stored data of T1 second registers at time j and the stored data of M first registers at time (j+1), determine the stored data of M first registers at time j.

[0016] In this implementation, grouping the first sub-data based on t can reduce the processing step size of the first sub-data; then, based on the preset T second registers, the RM transformation algorithm is used to register multiple first sub-data groups, which helps to reduce the interleaving in the RM transformation algorithm's calculation structure, thereby producing fewer intermediate calculation results. That is, the encoding calculation can be completed with fewer registers, reducing the complexity of the register space.

[0017] In one possible implementation, the M first registers include M1 registers A; the M1 registers A store the corrector at time (j+1); the T1 second registers include multiple target registers C;

[0018] Based on the stored data of T1 second registers at time j and the stored data of M first registers at time (j+1), determine the stored data of the M first registers at time j, including:

[0019] Based on the stored data of multiple target registers C at time j, the coefficients corresponding to the j-th check matrix, and the corrector at time (j+1), the first target bit corrector in the corrector at time j is determined;

[0020] Based on the first target bit corrector, the corrector at time j is determined; the data stored in registers A of M1 at time j is the corrector at time j.

[0021] In this implementation, the electronic device can calculate the first target bit corrector in the corrector at time j by using the stored data of multiple target registers C obtained by the RM transformation algorithm at time j, the coefficients corresponding to the j-th check matrix, and the corrector at time (j+1). Based on the first target bit corrector and the calculated other bit correctors, the corrector at time j is determined. This allows for iterative updates of the corrector within a single check matrix using the RM transformation algorithm and simple operations. Compared to calculating the corrector based on the entire check matrix, this approach achieves both lower computational space complexity and lower computational complexity.

[0022] In one possible implementation, the data stored in M1 registers A at time 1 is the corrector at time 1; the first corrector is the corrector at time 1.

[0023] In this implementation, the first corrector can be obtained by updating the corrector of the M1 registers A at each time step.

[0024] In one possible implementation, the M first registers include M2 ​​registers B; the T1 second registers include multiple destination registers C;

[0025] Based on the stored data of T1 second registers at time j and the stored data of M first registers at time (j+1), determine the stored data of the M first registers at time j, including:

[0026] Based on M2 registers B, the RM transformation algorithm is used to register the stored data of multiple target registers C at time j, resulting in multiple sets of stored data of M2 registers B at time j. The stored data of multiple target registers C at time j corresponds one-to-one with the stored data of multiple sets of M2 registers B at time j. The stored data of each set of M2 registers B at time j is obtained based on the stored data of M2 registers B at time (j+1) and the corresponding stored data of target register C at time j.

[0027] In this implementation, the RM transformation algorithm is executed on the stored data of multiple target registers C at time j to obtain multiple sets of M2 registers B at time j. By updating the stored data of these M2 registers B, the second target bit corrector in the first corrector can be directly calculated without updating the corrector at each time. This helps to avoid the multiplication operation performed when updating the second target bit corrector at each time, thereby further reducing the computational complexity.

[0028] In one possible implementation, the first corrector is determined based on the stored data of the M first registers at time 1, including:

[0029] Based on the stored data of multiple sets of M2 registers B at time 1, the first target bit corrector in the first corrector is determined;

[0030] The first corrector is determined based on the first target position corrector.

[0031] In this implementation, the first target bit corrector in the first corrector is determined based on the stored data of multiple sets of M2 registers B at time 1, which avoids the multiplication operation performed when updating the second target bit corrector at each time, thereby further reducing the complexity of calculating the corrector.

[0032] In one possible implementation, when the length t of the redundancy check data is within a first preset range, the T1 second registers also include a target register D. The data stored in the target register D at time j is used to calculate the second target bit corrector in the corrector at time j or to calculate the second target bit corrector in the first corrector; t is determined based on the length of the data to be encoded and the codeword length.

[0033] In this implementation, when t belongs to the first preset range, an additional register (i.e., target register D) is used to store the intermediate results required for calculating the second target bit corrector in the corrector at time j or the second target bit corrector in the first corrector, which can reduce the complexity of calculating the second target bit corrector.

[0034] In one possible implementation, before determining the first corrector based on the stored data of the M first registers at time 1, the method further includes:

[0035] The parity check matrix is ​​divided into a first submatrix and a second submatrix; the first submatrix is ​​the matrix composed of columns 1 to t of the parity check matrix; the second submatrix is ​​the matrix composed of the remaining columns of the parity check matrix.

[0036] Redundancy check data is determined based on the first corrector, including:

[0037] Based on the data to be encoded, the first corrector, the first submatrix, and the second submatrix, the redundant check data is determined.

[0038] In this implementation, the parity check matrix is ​​divided into a first submatrix and a second submatrix. Since the first submatrix is ​​a Vandermonde matrix, it can be decomposed quickly. The product of the data to be encoded and the second submatrix is ​​the first corrector. Based on the data to be encoded, the first corrector, the first submatrix, and the second submatrix, the redundant parity check data can be calculated quickly, thus improving the encoding efficiency.

[0039] In one possible implementation, the Reid-Muller RM transform algorithm is used to register multiple first sub-data sets, including:

[0040] The RM transformation algorithm is used to register multiple first sub-data groups in reverse or partial reverse order; or,

[0041] When the codeword length is within the second preset range, the RM transformation algorithm is used to register multiple first sub-data groups in a group synchronization manner.

[0042] In this implementation, the RM transform algorithm is used to register multiple first sub-data groups in reverse order of the first sub-data. This gives the encoding process incremental computation characteristics, meaning that synchronous encoding can be performed during data transmission. This results in high encoding efficiency and facilitates coordination between encoding operations and data communication, further improving the overall system performance. When the codeword length is within the second preset range, the RM transform algorithm is used to register multiple first sub-data groups in an inter-group synchronous manner. The entire calculation process does not require the introduction of temporary registers, further reducing register requirements. By using the RM transform algorithm to register multiple first sub-data groups in reverse order of the first sub-data, an additional register can be used to store the intermediate results required for calculating the second target bit corrector in the corrector at time j or the second target bit corrector in the first corrector, reducing the complexity of calculating the second target bit corrector at each time step.

[0043] In one possible implementation, the parity-check matrix is ​​over a finite field F. 16 [x] / (1+αx+x 2 The Vandermonde matrix constructed on α; where / denotes the modular operation, and α is the annular domain F. 16 =F2[α] / (1+α+α) 2 +α 3 +α 4 The elements in ) are variables, where x is a variable.

[0044] In this implementation, through a special finite field F 16 [x] / (1+αx+x 2 The parity check matrix is ​​constructed based on the Vandermonde matrix, which gives the parity check matrix some special properties (such as: the parity check matrix can be divided into N parity check submatrices based on the groupability of the second row elements, and the fourth row elements are monomials, etc.). Encoding based on these properties of the parity check matrix helps to reduce computational complexity.

[0045] Secondly, embodiments of this application provide a decoding method applied to an electronic device or a chip within an electronic device. Taking the application of this method to an electronic device as an example, the method includes:

[0046] Obtain the codeword to be decoded;

[0047] Based on the length of the codeword, N check sub-matrices are determined from the pre-constructed check matrix;

[0048] When N > 1, for the j-th parity submatrix among the N parity submatrixes, the storage data of the M first registers at time j is determined based on the fourth sub-data corresponding to the j-th parity submatrix in the codeword and the preset storage data of the M first registers at time (j+1), so as to obtain the storage data of the M first registers at time 1; the storage data of the M first registers at time N is determined based on the fifth sub-data corresponding to the N-th parity submatrix in the codeword and the initial values ​​of the M first registers; where 0 ≤ j ≤ N-1;

[0049] The second corrector is determined based on the stored data of the M first registers at time 1;

[0050] Data failures were recovered based on the second corrector.

[0051] As can be seen in this embodiment, the pre-constructed parity matrix can be divided into N parity sub-matrices based on the length of the codeword. When N > 1, the first sub-data corresponding to the j-th parity sub-matrix and the stored data of the M pre-defined first registers at time (j+1) can be used to update the stored data at time j. Iterative updates based on the current input and the stored data at the previous time can obtain the stored data of the M first registers at time 1, thereby determining the second corrector, calculating the failed data, and completing the decoding. This iterative update of the stored data of the M first registers in units of parity sub-matrices is equivalent to dividing the decoding execution logic in units of parity sub-matrices. Compared with the calculation scheme using the entire parity matrix and all codewords, the number of elements of the parity matrix and the amount of codeword data involved in a single calculation are reduced, thereby reducing the computational scale of decoding and thus helping to reduce the computational complexity of decoding.

[0052] In one possible implementation, the stored data of the M first registers at time j is determined based on the fourth sub-data corresponding to the j-th parity sub-matrix in the codeword and the stored data of the M first registers at time (j+1), including:

[0053] The fourth sub-data is grouped based on the length t of the redundancy check data to obtain multiple fourth sub-data groups; where t is determined based on the length of the encoded data and the length of the codeword.

[0054] Based on a preset set of T second registers, the Reid-Muller RM transform algorithm is used to register multiple fourth sub-data groups to obtain the stored data of T1 second registers at time j; where T1≤T;

[0055] Based on the stored data of T1 second registers at time j and the stored data of M first registers at time (j+1), determine the stored data of M first registers at time j.

[0056] In this implementation, grouping the fourth sub-data based on t can reduce the processing step size of the fourth sub-data; then, based on the preset T second registers, the RM transformation algorithm is used to register multiple groups of fourth sub-data, which helps to reduce the interleaving in the calculation structure of the RM transformation algorithm, thereby producing fewer intermediate calculation results. That is, the encoding calculation can be completed with fewer registers, reducing the complexity of the register space.

[0057] In one possible implementation, the M first registers include M1 registers A; the M1 registers A store the corrector at time (j+1); the T1 second registers include multiple target registers C;

[0058] Based on the stored data of T1 second registers at time j and the stored data of M first registers at time (j+1), determine the stored data of the M first registers at time j, including:

[0059] Based on the stored data of multiple target registers C at time j, the coefficients corresponding to the j-th check matrix, and the corrector at time (j+1), the first target bit corrector in the corrector at time j is determined;

[0060] Based on the first target bit corrector, the corrector at time j is determined; the data stored in registers A of M1 at time j is the corrector at time j.

[0061] In this implementation, the electronic device can calculate the first target bit corrector in the corrector at time j by using the stored data of multiple target registers C obtained by the RM transformation algorithm at time j, the coefficients corresponding to the j-th check matrix, and the corrector at time (j+1). Based on the first target bit corrector and the calculated other bit correctors, the corrector at time j is determined. This allows for iterative updates of the corrector within a single check matrix using the RM transformation algorithm and simple operations. Compared to calculating the corrector based on the entire check matrix, this approach achieves both lower computational space complexity and lower computational complexity.

[0062] In one possible implementation, the data stored in registers A at time 1 is the corrector at time 1; the second corrector is the corrector at time 1.

[0063] In this implementation, by updating the corrector of the M1 registers A at each time step, the corrector at the first time step can be obtained, and thus the second corrector can be obtained.

[0064] In one possible implementation, the M first registers include M2 ​​registers B; the T1 second registers include multiple destination registers C;

[0065] Based on the stored data of T1 second registers at time j and the stored data of M first registers at time (j+1), determine the stored data of the M first registers at time j, including:

[0066] Based on M2 registers B, the RM transformation algorithm is used to register the stored data of multiple target registers C at time j, resulting in multiple sets of stored data of M2 registers B at time j. The stored data of multiple target registers C at time j corresponds one-to-one with the stored data of multiple sets of M2 registers B at time j. The stored data of each set of M2 registers B at time j is obtained based on the stored data of M2 registers B at time (j+1) and the corresponding stored data of target register C at time j.

[0067] In this implementation, the RM transformation algorithm is executed on the stored data of multiple target registers C at time j to obtain multiple sets of M2 registers B at time j. By updating the stored data of these M2 registers B, the second target bit corrector in the second corrector can be directly calculated without updating the corrector at each time. This helps to avoid the multiplication operation performed when updating the second target bit corrector at each time, thereby further reducing the computational complexity.

[0068] In one possible implementation, the second corrector is determined based on the stored data of the M first registers at time 1, including:

[0069] Based on the stored data of multiple sets of M2 registers B at time 1, the first target bit corrector in the second corrector is determined;

[0070] The second corrector is determined based on the first target position corrector.

[0071] In this implementation, the first target bit corrector in the second corrector is determined based on the stored data of multiple sets of M2 registers B at time 1. This avoids the multiplication operation performed when updating the second target bit corrector at each time, thereby further reducing the complexity of calculating the corrector.

[0072] In one possible implementation, when the length t of the redundancy check data is within a first preset range, the T1 second registers also include a target register D. The data stored in the target register D at time j is used to calculate the second target bit corrector in the corrector at time j or to calculate the second target bit corrector in the second corrector; t is determined based on the length of the data to be encoded and the length of the codeword.

[0073] In this implementation, when t belongs to the first preset range, an additional register (i.e., target register D) is used to store the intermediate results required for calculating the second target bit corrector or the second target bit corrector in the corrector at time j, which can reduce the complexity of calculating the second target bit corrector.

[0074] In one possible implementation, before determining the second corrector based on the stored data of the M first registers at time 1, the method further includes:

[0075] The check matrix is ​​divided into a third submatrix and a fourth submatrix; the third submatrix is ​​a matrix composed of the columns corresponding to the invalid data in the check matrix; the fourth submatrix is ​​a matrix composed of the remaining columns in the check matrix.

[0076] Data based on the recovery failure of the second corrector includes:

[0077] Based on the codeword, the second corrector, the third submatrix, and the fourth submatrix, recover the invalid data.

[0078] In this implementation, the parity check matrix is ​​divided into a third submatrix and a fourth submatrix. Since the third submatrix is ​​a Vandermonde matrix, it can be decomposed quickly. The product of the non-failed data and the fourth submatrix is ​​the second corrector. Based on the codeword, the second corrector, the third submatrix, and the fourth submatrix, the failed data can be calculated quickly, thus improving decoding efficiency.

[0079] In one possible implementation, if the number of bits of the invalid data is less than or equal to t, the third submatrix is ​​a Vandermonde square matrix, and the number of bits of the second corrector is equal to the number of bits of the invalid data.

[0080] In this implementation, when the number of bits of the invalid data is less than t, the number of bits of the calculated second corrector can be reduced, which further reduces the computational complexity compared to the scheme that calculates a t-bit corrector.

[0081] In one possible implementation, the Reid-Muller RM transform algorithm is used to register multiple fourth sub-data sets, including:

[0082] The RM transformation algorithm is used to register multiple fourth sub-data groups in reverse or partial reverse order; or,

[0083] When the length of the codeword is within the second preset range, the RM transformation algorithm is used to register multiple fourth sub-data groups in a group synchronization manner.

[0084] In this implementation, the RM transform algorithm is used to register multiple fourth sub-data groups in reverse order of the fourth sub-data. This gives the decoding process incremental computation characteristics, meaning synchronous decoding can be performed during data transmission. This results in high decoding efficiency and facilitates coordination between decoding operations and data communication, further improving the overall system performance. When the codeword length is within the second preset range, the RM transform algorithm is used to register multiple fourth sub-data groups in a synchronized manner between groups. The entire calculation process does not require the introduction of temporary registers, further reducing register requirements. By using the RM transform algorithm to register multiple fourth sub-data groups in reverse order of the fourth sub-data, an additional register can be used to store the intermediate results required for calculating the second target bit corrector in the corrector at time j, or the second target bit corrector in the second corrector, reducing the complexity of calculating the second target bit corrector at each time step.

[0085] In one possible implementation, the parity-check matrix is ​​over a finite field F. 16 [x] / (1+αx+x 2 The Vandermonde matrix constructed on α; where / denotes the modular operation, and α is the annular domain F. 16 =F2[α] / (1+α+α) 2 +α 3 +α 4 The elements in ) are variables, where x is a variable.

[0086] In this implementation, through a special finite field F 16 [x] / (1+αx+x 2 The parity check matrix is ​​constructed based on the Vandermonde matrix, which gives the parity check matrix some special properties (such as: the parity check matrix can be divided into N parity check submatrices based on the groupability of the second row elements, and the fourth row elements are monomials, etc.). Encoding based on these properties of the parity check matrix helps to reduce computational complexity.

[0087] Thirdly, embodiments of this application provide an encoding device applied to an electronic device or a chip in an electronic device; the device includes a first acquisition unit and a first processing unit; wherein:

[0088] The first acquisition unit is used to acquire the data to be encoded and the codeword length;

[0089] The first processing unit is used to determine N parity sub-matrices from a pre-constructed parity matrix based on the codeword length; when N > 1, for the j-th parity sub-matrice among the N parity sub-matrices, based on the first sub-data corresponding to the j-th parity sub-matrice in the data to be encoded and the stored data of the M first registers at time (j+1), the stored data of the M first registers at time j is determined to obtain the stored data of the M first registers at time 1; the stored data of the M first registers at time N is determined based on the second sub-data corresponding to the N-th parity sub-matrice in the data to be encoded and the initial values ​​of the M first registers; based on the stored data of the M first registers at time 1, a first corrector is determined; based on the first corrector, redundant parity data is determined to obtain the encoded codeword; where 0 ≤ j ≤ N-1.

[0090] In one possible implementation, regarding determining the stored data of the M first registers at time j based on the first sub-data corresponding to the j-th parity sub-matrix in the data to be encoded and the stored data of the M first registers at time (j+1), the first processing unit is specifically used for:

[0091] The first sub-data is grouped to obtain multiple first sub-data groups;

[0092] Based on a preset set of T second registers, the Reid-Muller RM transform algorithm is used to register multiple first sub-data groups to obtain the stored data of T1 second registers at time j; where T1≤T;

[0093] Based on the stored data of T1 second registers at time j and the stored data of M first registers at time (j+1), determine the stored data of M first registers at time j.

[0094] In one possible implementation, the M first registers include M1 registers A; the M1 registers A store the corrector at time (j+1); the T1 second registers include multiple target registers C;

[0095] In determining the stored data of the M first registers at time j based on the stored data of the T1 second registers at time j and the stored data of the M first registers at time (j+1), the first processing unit is specifically used for:

[0096] Based on the stored data of multiple target registers C at time j, the coefficients corresponding to the j-th check matrix, and the corrector at time (j+1), the first target bit corrector in the corrector at time j is determined;

[0097] Based on the first target bit corrector, the corrector at time j is determined; the data stored in registers A of M1 at time j is the corrector at time j.

[0098] In one possible implementation, the data stored in M1 registers A at time 1 is the corrector at time 1; the first corrector is the corrector at time 1.

[0099] In one possible implementation, the M first registers include M2 ​​registers B; the T1 second registers include multiple destination registers C;

[0100] In determining the stored data of the M first registers at time j based on the stored data of the T1 second registers at time j and the stored data of the M first registers at time (j+1), the first processing unit is specifically used for:

[0101] Based on M2 registers B, the RM transformation algorithm is used to register the stored data of multiple target registers C at time j, resulting in multiple sets of stored data of M2 registers B at time j. The stored data of multiple target registers C at time j corresponds one-to-one with the stored data of multiple sets of M2 registers B at time j. The stored data of each set of M2 registers B at time j is obtained based on the stored data of M2 registers B at time (j+1) and the corresponding stored data of target register C at time j.

[0102] In one possible implementation, regarding determining the first corrector based on the stored data in the M first registers at time 1, the first processing unit is specifically configured to:

[0103] Based on the stored data of multiple sets of M2 registers B at time 1, the first target bit corrector in the first corrector is determined;

[0104] The first corrector is determined based on the first target position corrector.

[0105] In one possible implementation, when the length t of the redundancy check data is within a first preset range, the T1 second registers also include a target register D. The data stored in the target register D at time j is used to calculate the second target bit corrector in the corrector at time j or to calculate the second target bit corrector in the first corrector; t is determined based on the length of the data to be encoded and the codeword length.

[0106] In one possible implementation, the first processing unit is further configured to:

[0107] The parity check matrix is ​​divided into a first submatrix and a second submatrix; the first submatrix is ​​the matrix composed of columns 1 to t of the parity check matrix; the second submatrix is ​​the matrix composed of the remaining columns of the parity check matrix.

[0108] In determining redundant check data based on the first corrector, the first processing unit is specifically used for:

[0109] Based on the data to be encoded, the first corrector, the first submatrix, and the second submatrix, the redundant check data is determined.

[0110] In one possible implementation, in registering multiple first sub-data sets using the Reid-Muller RM transform algorithm, the first processing unit is specifically used for:

[0111] The RM transformation algorithm is used to register multiple first sub-data groups in reverse or partial reverse order; or,

[0112] When the codeword length is within the second preset range, the RM transformation algorithm is used to register multiple first sub-data groups in a group synchronization manner.

[0113] In one possible implementation, the parity-check matrix is ​​over a finite field F. 16 [x] / (1+αx+x 2 The Vandermonde matrix constructed on α; where / denotes the modular operation, and α is the annular domain F. 16 =F2[α] / (1+α+α) 2 +α 3 +α 4 The elements in ) are variables, where x is a variable.

[0114] It should be understood that since the method embodiments and the device embodiments are different presentations of the same technical concept, the content of the first aspect of the embodiments of this application should be adapted to the third aspect of the embodiments of this application simultaneously, and can achieve the same or similar beneficial effects, which will not be repeated here.

[0115] Fourthly, embodiments of this application provide a decoding device applied to an electronic device or a chip in an electronic device; the device includes a second acquisition unit and a second processing unit; wherein:

[0116] The second acquisition unit is used to acquire the codeword to be decoded;

[0117] The second processing unit is used to determine N parity sub-matrices from a pre-constructed parity matrix based on the length of the codeword; when N > 1, for the j-th parity sub-matrice among the N parity sub-matrices, based on the fourth sub-data corresponding to the j-th parity sub-matrice in the codeword and the stored data of the M first registers at time (j+1), the stored data of the M first registers at time j is determined, so as to obtain the stored data of the M first registers at time 1; the stored data of the M first registers at time N is determined based on the fifth sub-data corresponding to the N-th parity sub-matrice in the codeword and the initial values ​​of the M first registers; based on the stored data of the M first registers at time 1, a second corrector is determined; and the failed data is recovered based on the second corrector; where 0 ≤ j ≤ N-1.

[0118] In one possible implementation, regarding determining the stored data of the M first registers at time j based on the fourth sub-data corresponding to the j-th parity sub-matrix in the codeword and the stored data of the preset M first registers at time (j+1), the second processing unit is specifically used for:

[0119] The fourth sub-data is grouped to obtain multiple fourth sub-data groups;

[0120] Based on a preset set of T second registers, the Reid-Muller RM transform algorithm is used to register multiple fourth sub-data groups to obtain the stored data of T1 second registers at time j; where T1≤T;

[0121] Based on the stored data of T1 second registers at time j and the stored data of M first registers at time (j+1), determine the stored data of M first registers at time j.

[0122] In one possible implementation, the M first registers include M1 registers A; the M1 registers A store the corrector at time (j+1); the T1 second registers include multiple target registers C;

[0123] In determining the stored data of the M first registers at time j based on the stored data of the T1 second registers at time j and the stored data of the M first registers at time (j+1), the second processing unit is specifically used for:

[0124] Based on the stored data of multiple target registers C at time j, the coefficients corresponding to the j-th check matrix, and the corrector at time (j+1), the first target bit corrector in the corrector at time j is determined;

[0125] Based on the first target bit corrector, the corrector at time j is determined; the data stored in registers A of M1 at time j is the corrector at time j.

[0126] In one possible implementation, the data stored in registers A at time 1 is the corrector at time 1; the second corrector is the corrector at time 1.

[0127] In one possible implementation, the M first registers include M2 ​​registers B; the T1 second registers include multiple destination registers C;

[0128] In determining the stored data of the M first registers at time j based on the stored data of the T1 second registers at time j and the stored data of the M first registers at time (j+1), the second processing unit is specifically used for:

[0129] Based on M2 registers B, the RM transformation algorithm is used to register the stored data of multiple target registers C at time j, resulting in multiple sets of stored data of M2 registers B at time j. The stored data of multiple target registers C at time j corresponds one-to-one with the stored data of multiple sets of M2 registers B at time j. The stored data of each set of M2 registers B at time j is obtained based on the stored data of M2 registers B at time (j+1) and the corresponding stored data of target register C at time j.

[0130] In one possible implementation, regarding the determination of the second corrector based on the stored data in the M first registers at time 1, the second processing unit is specifically used for:

[0131] Based on the stored data of multiple sets of M2 registers B at time 1, the first target bit corrector in the second corrector is determined;

[0132] The second corrector is determined based on the first target position corrector.

[0133] In one possible implementation, when the length t of the redundancy check data is within a first preset range, the T1 second registers also include a target register D. The data stored in the target register D at time j is used to calculate the second target bit corrector in the corrector at time j or to calculate the second target bit corrector in the second corrector; t is determined based on the length of the data to be encoded and the length of the codeword.

[0134] In one possible implementation, the second processing unit is further used for:

[0135] The check matrix is ​​divided into a third submatrix and a fourth submatrix; the third submatrix is ​​a matrix composed of the columns corresponding to the invalid data in the check matrix; the fourth submatrix is ​​a matrix composed of the remaining columns in the check matrix.

[0136] Regarding the recovery of failed data based on the second corrector, the second processing unit is specifically used for:

[0137] Based on the codeword, the second corrector, the third submatrix, and the fourth submatrix, recover the invalid data.

[0138] In one possible implementation, if the number of bits of the invalid data is less than or equal to t, the third submatrix is ​​a Vandermonde square matrix, and the number of bits of the second corrector is equal to the number of bits of the invalid data.

[0139] In one possible implementation, the second processing unit is specifically used for registering multiple fourth sub-data sets using the Reid-Muller RM transform algorithm:

[0140] The RM transformation algorithm is used to register multiple fourth sub-data groups in reverse or partial reverse order; or,

[0141] When the length of the codeword is within the second preset range, the RM transformation algorithm is used to register multiple fourth sub-data groups in a group synchronization manner.

[0142] In one possible implementation, the parity-check matrix is ​​over a finite field F. 16 [x] / (1+αx+x 2 The Vandermonde matrix constructed on α; where / denotes the modular operation, and α is the annular domain F. 16 =F2[α] / ( 1 +α+α 2 +α 3 +α 4 The elements in ) are variables, where x is a variable.

[0143] It should be understood that since the method embodiments and the device embodiments are different presentations of the same technical concept, the content of the second aspect of the embodiments of this application should be adapted to the fourth aspect of the embodiments of this application simultaneously, and can achieve the same or similar beneficial effects, which will not be repeated here.

[0144] Fifthly, embodiments of this application provide an electronic device including at least one processor coupled to at least one memory for storing one or more computer programs; the at least one processor is configured to cause the electronic device to implement the method described in any one of the first or second aspects when executing one or more computer programs.

[0145] In a sixth aspect, embodiments of this application provide a chip, including: a processor, configured to call and run a computer program from a memory, causing a device on which the chip is installed to perform the method as described in any of the embodiments of the first or second aspect above.

[0146] In a seventh aspect, embodiments of this application provide a computer-readable storage medium storing a computer program for execution by a device, wherein the computer program, when executed, implements the method as described in any of the embodiments of the first or second aspect above.

[0147] Eighthly, embodiments of this application provide a computer program product that, when run by a device, causes the device to perform the method as described in any of the embodiments of the first or second aspect above. Attached Figure Description

[0148] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application or the background art will be described below.

[0149] Figure 1 is a schematic diagram of encoding using RM transformation in a related technology;

[0150] Figure 2 is a schematic diagram of the second row elements of a verification matrix provided in an embodiment of this application;

[0151] Figure 3 is a schematic diagram of a storage system provided in an embodiment of this application;

[0152] Figure 4 is a flowchart illustrating an encoding method provided in an embodiment of this application;

[0153] Figure 5 is a schematic diagram of the computational structure of an RM transform algorithm provided in an embodiment of this application;

[0154] Figure 6 is a schematic diagram of the computational structure of another RM transformation algorithm provided in an embodiment of this application;

[0155] Figure 7 is a schematic diagram of the computational structure of another RM transform algorithm provided in an embodiment of this application;

[0156] Figure 8 is a schematic diagram of the computational structure of another RM transformation algorithm provided in an embodiment of this application;

[0157] Figure 9 is a schematic diagram of a verification matrix provided in an embodiment of this application;

[0158] Figure 10 is a schematic diagram of the computational structure of another RM transformation algorithm provided in an embodiment of this application;

[0159] Figure 11 is a schematic diagram of the computational structure of another RM transformation algorithm provided in an embodiment of this application;

[0160] Figure 12 is a schematic diagram of the computational structure of another RM transformation algorithm provided in an embodiment of this application;

[0161] Figure 13 is a schematic diagram of the computational structure of another RM transformation algorithm provided in an embodiment of this application;

[0162] Figure 14 is a flowchart illustrating another encoding method provided in an embodiment of this application;

[0163] Figure 15 is a flowchart illustrating a decoding method provided in an embodiment of this application;

[0164] Figure 16 is a flowchart illustrating another decoding method provided in an embodiment of this application;

[0165] Figure 17 is a line graph of computational complexity provided in an embodiment of this application;

[0166] Figure 18 is a schematic diagram of an encoding device provided in an embodiment of this application;

[0167] Figure 19 is a schematic diagram of a decoding device provided in an embodiment of this application;

[0168] Figure 20 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0169] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0170] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0171] The terms “component,” “module,” “system,” etc., used in this specification are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on electronic devices and electronic devices themselves can be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0172] First, a brief introduction to the relevant terms and technical background used in this application will be provided to facilitate understanding by those skilled in the art.

[0173] (1) Maximum Distance Separable Codes (MDS codes): In communication and data storage systems, MDS codes are often used to ensure high reliability and integrity of data. Because they have the largest minimum distance, MDS codes can effectively correct or detect errors even in the worst-case environment of noise and errors.

[0174] (2) Reed-Muller transform (RM transform): This is the process of converting a Boolean function into a polynomial form, usually using a binary finite field. Although it is not coding in the traditional sense (such as error-correcting codes or encryption codes), the application of RM transform in information theory overlaps with coding theory to some extent, especially in the process of data compression and conversion.

[0175] Please refer to Figure 1, which is a schematic diagram of encoding using RM transformation in a related technique. As shown in Figure 1, Figure 1 shows the code length n = 16 (denoted as x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x...). 10 ,x 11 ,x 12 ,x 13 ,x 14 ,x 15The computational dependencies involved in the RM transform are such that the parent node in the tree is the sum of its two child nodes. It can be seen that intermediate computation results at lower levels of the tree are shared in higher-level computations. The encoding scheme shown in Figure 1 encodes data in a finite field based on the Vandermonde matrix. Based on the characteristics of the RM transform and the Vandermonde matrix, the corrector can be calculated quickly, thus completing the encoding. As can be seen from Figure 1, this scheme involves a large amount of interleaving at lower levels when processing the input data (which can also be understood as a long data processing step). A large amount of interleaving produces many intermediate results, requiring more register space to complete the computation, making it unsuitable for environments with limited register space. Furthermore, calculating the data with the entire codeword length or a long step size results in a large computational scale, and the algorithm involves multiplication operations in a finite field, leading to high computational complexity. Another related technology involves MDS array codes, which are usually constructed on polynomial rings. The encoding and decoding process only involves XOR operations and cyclic shift operations. However, most MDS array code constructions lack structures that can effectively utilize intermediate calculation results or involve complex matrix multiplication operations when using intermediate calculation results for the next step of calculation, resulting in high computational complexity.

[0176] To overcome the shortcomings of the prior art, the embodiments of this application are implemented in the finite field F 16 [x] / (1+αx+x 2 An n×t parity check matrix H was constructed on the ring F. Here, / represents the modulo operation, and α is the ring domain F. 16 =F2[α] / (1+α+α) 2 +α 3 +α 4 In the array, x is a variable, n is the codeword length, and t is the length of the redundancy check data. 16 =F2[α] / (1+α+α) 2 +α 3 +α 4 F is a ring region with 16 elements. 16 =F2[α] / (1+α+α) 2 +α 3 +α 4 The basis vectors on α can be represented as: α = [1, α, α] 2 ,α 3 Define the binary vector of the number l as: β l =[b0,b1,b2,b3] T Then any element μ l ∈F 16 It can be represented as:

[0177] In this embodiment of the application, a Vandermonde matrix is ​​used to construct the verification matrix H. A Vandermonde matrix can be represented as:

[0178] It can be seen that the parity-check matrix H is completely determined by the elements of its second row (the elements of subsequent rows can be obtained from the elements of the second row), and the elements of its second row are defined by the finite field F. 16 [x] / (1+αx+x 2 Different elements μ on ) l and μ f If the composition is such that the second row element can be represented as: μ l x+μ f , 0 ≤ l, f < 16. When n ≤ 256, the constructed array code satisfies the MDS property. In the case of n ≤ 256, the elements of the second row of the parity-check matrix H can be grouped:

[0179] Where, γ j =x+μ j-1 γ j Let Gj represent the coefficient of the element in the j-th group, N be the number of groups, G0 be the element in the 1st group, and Gj be the coefficient of the element in the j-th group. j This is the element of the j-th group. Since the elements of the second row of the parity check matrix H are derived from the finite field F... 16 [x] / (1+αx+x 2 The second row of the parity check matrix H is composed of different elements from n, as shown in Figure 2. j Let represent the number of elements in each group, where the first group (j=0) contains 16 elements, and the subsequent 16 groups each contain 15 elements. Then the codeword length n satisfies:

[0180] Based on the principle of grouping the elements in the second row of the parity check matrix H, the parity check matrix H can also be divided into N parity check submatrices, as follows:

[0181] Based on the embodiments of this application, in the finite field F 16 [x] / (1+αx+x 2 The groupable test matrix H is constructed, and the encoding and decoding operations can be performed on a group-by-group basis. Furthermore, due to F... 16 =F2[α] / (1+α+α) 2 +α 3 +α 4 Given the properties of ), then all processes in the polynomial ring F during encoding and decoding... 16 =F2[α] / (1+α+α) 2 +α 3 +α 4All operations on the polynomial ring F2[α] / (1+α) can be performed first on the polynomial ring F2[α] / (1+α) 5 The operation is performed on the polynomial 1 + α + ... + α at the end of the calculation. 4 This further reduces computational complexity.

[0182] Based on the construction of the above-mentioned parity check matrix, this application proposes corresponding encoding and decoding methods, which can be implemented based on the storage system shown in Figure 3. As shown in Figure 3, the storage system may include n storage nodes or disks, and the original file data can be divided into k original data blocks (m0,…,m…). k-1 The original data blocks are erasure encoded using an MDS array code with parameters (n,k), and (t=nk) redundant parity data (p0,…,p) are added. t-1 The MDS array code with parameters (n,k) can accommodate any t node failures. That is, even if any t nodes or disks in the n storage nodes or disks fail, the lost data (or failed data) can be correctly decoded from the data in the other (k=nt) valid nodes or undamaged disks.

[0183] The technical solution provided in this application will be described in detail below with reference to specific implementation methods.

[0184] Please refer to Figure 4, which is a flowchart illustrating an encoding method provided in an embodiment of this application. This method can be implemented based on the storage system shown in Figure 3, and can be specifically executed by an electronic device. As shown in Figure 4, the method includes steps 401-405:

[0185] 401: Get the data to be encoded and the codeword length.

[0186] In this embodiment of the application, the length k of the data to be encoded can be determined based on the data to be encoded, the codeword length is n, and (n,k) is the input parameter during encoding and decoding. Here, "length" can be understood as "bits".

[0187] 402: Determine N parity submatrices from a pre-constructed parity matrix based on the codeword length.

[0188] In this embodiment of the application, due to the finite field F 16 [x] = F2[x] / (1+α+…+α) 4 Each element on ) can be obtained from F 16 =F2[α] / (1+α+α) 2 +α 3 +α 4The parity check matrix H is obtained by combining the 16 elements of ) with x. Therefore, the parity check matrix H is a matrix with 256 columns. Based on the grouping principle in Figure 2, given that the codeword length is n, the parity check matrix H can be divided into N parity check submatrices H. j For example: when 16 < n ≤ 31, N = 2; when n ≤ 16, N = 1; when n = 256, N = 17. That is, N ≥ 1 and is an integer.

[0189] 403: When N > 1, for the j-th parity submatrix among the N parity submatrixes, based on the first sub-data corresponding to the j-th parity submatrix in the data to be encoded and the stored data of the M first registers at time (j+1), determine the stored data of the M first registers at time j, so as to obtain the stored data of the M first registers at time 1.

[0190] The data stored in the M first registers at time N is determined based on the second sub-data corresponding to the Nth parity sub-matrix in the data to be encoded and the initial values ​​of the M first registers. Here, 0 ≤ j ≤ N-1. It should be noted that j is merely an identifier; for the j-th parity sub-matrix, when j = 0, it actually represents the 1st parity sub-matrix. That is, the data stored at time 1 is actually the data stored when j = 0.

[0191] In one possible implementation of this application embodiment, the M first registers include M1 registers A, for example: the M1 registers A can be registers used to store the corrector. The corrector S = [S0, ..., S...]. t-1 If M1 registers A can be S0's register, S1's register, ..., S1's register, respectively. t-1 The registers. In another possible implementation, the M first registers include M2 ​​registers B, for example: the M2 registers B are registers used to store the sum of intermediate calculation results during the RM transformation calculation, and the M2 registers B can be represented as: {y0, y1, ..., y ξ},in, This is for rounding up.

[0192] For example, this application embodiment improves the calculation structure or calculation process of the RM transform algorithm based on the value of t. Based on the preset T second registers, it designs a method for using the RM transform algorithm to process the parity submatrix H. j The calculation process for the corresponding first sub-data. For example, if t≤5, it can be determined that not many intermediate calculation results are needed to calculate the corrector. Therefore, the interleaving in the calculation structure shown in Figure 1 can be reduced by decreasing the processing step size of the first sub-data, thus producing fewer intermediate calculation results. The implementation of step 403 can then be described as follows:

[0193] S4031: Group the first sub-data to obtain multiple first sub-data groups.

[0194] Specifically, the first sub-data is described as follows: Taking the first parity submatrix as an example, since its second row has 16 elements, then X0 = {x 0,j ,x 1,j ,…,x 15,j}. X j Divided into 4 groups: {x 12,j ,x 13,j ,x 14,j ,x 15,j}, {x 8,j ,x 9,j ,x 10,j ,x 11,j}, {x 4,j ,x 5,j ,x 6,j ,x 7,j}, {x 0,0 ,x 1,j ,x 2,j ,x 3,j It should be noted that x only exists when j = 0. 0,0 .

[0195] S4032: Based on T preset second registers, the RM transformation algorithm is used to register multiple first sub-data groups to obtain the stored data of T1 second registers at time j; where T1≤T. Several methods for registering multiple first sub-data groups are described below:

[0196] The first approach: Define T second registers as {T0, T1, T2, T3, T4, T5}. Based on the computational structure of the RM transform algorithm in Figure 5, the registering process for multiple first sub-data groups can be described as follows:

[0197] (1) Input x 15,j Deposit Deposit

[0198] Enter x 14,j renew Deposit

[0199] Enter x 13,j renew renew

[0200] Enter x 12,j renew

[0201] (2) Input x11,j Deposit renew

[0202] Enter x 10,j renew renew

[0203] Enter x 9,j renew renew

[0204] Enter x 8,j renew renew renew

[0205] (3) Input x 7,j Deposit renew

[0206] Enter x 6,j renew renew

[0207] Enter x 5,j renew renew

[0208] Enter x 4,j renew renew renew

[0209] (4) Input x 3,j renew renew

[0210] Enter x 2,j renew renew renew

[0211] Enter x 1,j renew renew

[0212] Enter x 0,0 Update (when j=0)

[0213] As can be seen from the calculation flow of the RM transform algorithm shown in Figure 5, the embodiment of this application registers multiple first sub-data groups in reverse order of the first sub-data. This reverse order calculation method gives the improved RM transform algorithm the property of incremental calculation, enabling encoding operations to be performed simultaneously with data input. Through the calculation of the RM transform algorithm, the stored data of T0, T1, T2, T3, and T4 at time j are obtained, which can also be understood as the values ​​at time j, i.e., the stored data of the T1 second registers at time j. The embodiment shown in Figure 5 is applicable to encoding and decoding scenarios where t ≤ 5.

[0214] The second register T0 actually uses the register of the first corrector S0 and is not an additional register. Therefore, the embodiment shown in Figure 5 only needs to introduce five additional registers, T1, T2, T3, T4 and T5, to complete the calculation of the RM transformation algorithm. T5 is a temporary register introduced for the convenience of calculation.

[0215] In this implementation, the RM transformation algorithm is used to register multiple first sub-data groups in reverse order of the first sub-data, which enables the encoding process to have the characteristics of incremental calculation. That is, synchronous encoding can be performed during data transmission, which has high encoding efficiency and is conducive to the coordination between encoding operation and data communication, further improving the overall system performance.

[0216] The second approach: When the codeword length falls within a second preset range, for example, n ≤ 31, define T second registers as {T0, T1, T2, T3, T4}. Based on the computational structure of the RM transform algorithm in Figure 6, the registering process for multiple first sub-data groups can be described as follows:

[0217] (1) Update (Update when j=0) );

[0218] renew renew renew

[0219] renew

[0220] (2) Update

[0221] renew

[0222] renew

[0223] renew

[0224] (3) Update

[0225] renew

[0226] renew

[0227] renew

[0228] renew

[0229] (4) Update

[0230] renew

[0231] As can be seen from the calculation flow of the RM transformation algorithm shown in Figure 6, in this embodiment, when the codeword length is within the second preset range, multiple first sub-data groups are registered in an inter-group synchronization manner. This inter-group synchronization method abandons the incremental calculation characteristic. However, the embodiment shown in Figure 6 only requires the additional introduction of four registers, T1, T2, T3, and T4, to complete the RM transformation algorithm calculation, further reducing the computational space complexity. Through the calculation of the RM transformation algorithm, the stored data of T0, T1, T2, T3, and T4 at time j is obtained, which can also be understood as the value at time j, i.e., the stored data of the T1 second registers at time j.

[0232] In this implementation, when the codeword length is within the second preset range, the RM transformation algorithm is used to register multiple first sub-data groups in a group-to-group synchronization manner. The entire calculation process does not require the introduction of temporary registers, which can further reduce the need for registers.

[0233] The third approach: When t falls within the first preset range, for example, 4 ≤ t ≤ 5, define T second registers as {T0, T1, T2, T3, T4, T5, T6}. Based on the calculation structure of the RM transformation algorithm in Figure 7, the registering process of multiple first sub-data groups can be described as follows:

[0234] (1) Input x 15,j Deposit Deposit

[0235] Enter x 14,j renew Deposit

[0236] Enter x 13,j Deposit renew

[0237] Enter x12,j renew renew

[0238] (2) Input x 11,j Deposit renew

[0239] Enter x 10,j renew renew

[0240] Enter x 9,j renew renew

[0241] Enter x 8,j renew renew renew

[0242] (3) Input x 7,j Deposit renew

[0243] Enter x 5,j renew renew renew

[0244] Enter x 6,j renew renew

[0245] Enter x 4,j renew renew renew

[0246] (4) Input x 3,j renew renew

[0247] Enter x 2,j renew renew renew

[0248] Enter x 1,j renew renew

[0249] Enter x 0,0 Update (when j=0)

[0250] As can be seen from the calculation flow of the RM transformation algorithm shown in Figure 7, in this embodiment, when t belongs to the first preset range, the T1 second registers also include a target register D, that is, an additional register space T6 is introduced. The data stored in register T6 at time j is used to calculate the second target bit corrector in the corrector at time j, that is, S3 at time j. Through the calculation of the RM transformation algorithm, the stored data of T0, T1, T2, T3, T4, and T6 at time j are obtained, which can also be understood as the value at time j, that is, the stored data of the T1 second registers at time j.

[0251] It should be noted that when n≤31, the register of the corrector S3 (second target bit corrector) can be used directly as the target register D, without the need to introduce an additional register T6.

[0252] In this implementation, the RM transformation algorithm is used to register multiple first sub-data groups in reverse order of the first sub-data parts. An additional register (i.e., target register D) can be used to store the intermediate results required to calculate the second target bit corrector in the corrector at time j or the second target bit corrector in the first corrector, which can reduce the complexity of calculating the second target bit corrector.

[0253] S4033: Based on the stored data of T1 second registers at time j and the stored data of M first registers at time (j+1), determine the stored data of M first registers at time j.

[0254] For example, in an embodiment where M first registers include M1 registers A, the data stored in M1 registers A at time (j+1) is the corrector at time (j+1); T1 second registers include multiple target registers C, namely T1, T2, T3, and T4. The corrector at time (j+1) includes the correctors at times (j+2) to N, that is, the corrector corresponding to the parity matrix composed of the parity matrix composed of the parity matrix from the (j+1)th to the Nth parity matrix.

[0255] For example, based on the stored data of T1 second registers at time j and the stored data of M first registers at time (j+1), the stored data of the M first registers at time j is determined, including:

[0256] Based on the stored data of multiple target registers C at time j, the coefficients corresponding to the j-th check matrix, and the corrector at time (j+1), the first target bit corrector in the corrector at time j is determined; where the first target bit corrector is the p-th corrector in the t-bit corrector; p = 2 q +1, 0≤q≤2;

[0257] Based on the first target bit corrector, the corrector at time j is determined; the data stored in registers A of M1 at time j is the corrector at time j.

[0258] In the example shown in Figure 5, specifically, at t=5, the calibrator S=[S0,…,S4], then the calibrator at time j is... Here, the superscript j represents the update time of the corrector, which is also the calculation time of the first sub-data corresponding to the j-th corrector matrix. It can be calculated using the following formula:

[0259] Here, T0 uses the register space of S0, and the register space of S0 stores S0 at time (j+1). Therefore, T0 can also be regarded as being composed of... The updated result is the first target bit corrector, which is the second bit corrector. The third syndrome The 5th syndrome In the case of 4≤t≤5, there exists a second target position corrector, which is the corrector among the t-position correctors excluding the first position corrector (S0) and the first target position corrector. (x+μ) j-1 The power of ) represents the coefficient γ of the row corresponding to the j-th parity submatrix. j Thanks to F 16 =F2[α] / (1+α+α) 2 +α 3 +α 4 Given the property that the elements in the fourth row of the verification matrix H are monomials, when calculating S3, the corresponding sub-data can be multiplied by the elements in the fourth row. Compared to the existing method of multiplying by polynomials, this reduces the computational complexity. Where 1, α, α 2 ,α 3 Multiplying each power by T indicates the storage location of the corresponding T in F. 16 [x] / (x 2 A circular shift is performed on T1 (+αx+1). Since T5 is only a temporary register, after its stored data is released, the sum of the stored data of T1, T2, T3, and T4 can be stored in T5.

[0260] Based on Formula 1 and the execution flow of the RM transform algorithm shown in Figures 5-7, it can be seen that in the RM transform algorithm stage, the stored data T0, T1, T2, T3, T4, and T6 can be obtained by simply performing XOR calculations. Only when the corrector time at time j is calculated is the data combined with the coefficient γ. jMultiply, and the stored data of T1, T2, T3, T4 are passed through F 16 [x] / (x 2 The cyclic shift on (+αx+1) reduces the overall computational complexity considerably.

[0261] In the example shown in Figure 6, if the number of groups N = 2, when j = 1, The following formula can be used to calculate it:

[0262] The parentheses “S1=" indicate that the corresponding summation result is stored in the register of S1.

[0263] When j = 0 The result can be calculated using the following formula:

[0264] In the example shown in Figure 7, when t = 5, The following formula can be used to calculate it:

[0265] In this implementation, the electronic device can calculate the first target bit corrector in the corrector at time j by using the stored data of multiple target registers C obtained by the RM transformation algorithm at time j, the coefficients corresponding to the j-th check matrix, and the corrector at time (j+1). Based on the first target bit corrector and the calculated other bit correctors, the corrector at time j is determined. This allows for iterative updates of the corrector within a single check matrix using the RM transformation algorithm and simple operations. Compared to calculating the corrector based on the entire check matrix, this approach achieves both lower computational space complexity and lower computational complexity.

[0266] The data stored in the M first registers at time N is determined based on the second sub-data corresponding to the Nth parity matrix in the data to be encoded and the initial values ​​of the M first registers. For example, in an embodiment where the M first registers include M1 registers A, the initial value of the M1 registers A is the initial value of the corrector, which is 0.

[0267] For example, in an embodiment where M first registers include M2 ​​registers B, T1 second registers include multiple target registers C, namely T1, T2, T3, and T4.

[0268] For example, based on the stored data of T1 second registers at time j and the stored data of M first registers at time (j+1), the stored data of the M first registers at time j is determined, including:

[0269] Based on M2 registers B, the RM transformation algorithm is used to respectively register the stored data of multiple target registers C at the j-th moment, and multiple groups of stored data of M2 registers B at the j-th moment are obtained; the stored data of multiple target registers C at the j-th moment corresponds one-to-one with multiple groups of stored data of M2 registers B at the j-th moment; the stored data of each group of M2 registers B at the j-th moment is obtained based on the stored data of M2 registers B at the (j + 1)-th moment and the stored data of the corresponding target register C at the j-th moment. Among them, the stored data of each register B at the (j + 1)-th moment is the sum of the stored data of T1, T2, T3, T4 at the (j + 1)-th moment and the stored data of T1, T2, T3, T4 from the (j + 2)-th moment to the N-th moment.

[0270] Specifically, since the syndrome at the j-th moment is obtained based on the syndrome at the (j + 1)-th moment and the stored data of T1 second registers at the j-th moment, based on this iterative principle, the syndrome at the 1st moment can be calculated using the following formula five:

[0271] In this embodiment, when t belongs to the first preset range, the stored data of the target register D (register T6) at the j-th moment is used to calculate the second target bit syndrome in the first syndrome, that is, S3 at the 1st moment. By using an additional register (i.e., the target register D) to store the intermediate result required for calculating the second target bit syndrome in the first syndrome, the complexity of calculating the second target bit syndrome can be reduced. It can be seen from formula five that for the calculation of the syndrome with i = 1, 2, 4, when 0 < j ≤ N - 1, it is necessary to multiply with the coefficient γ j i The nature of which is similar to the nature of the elements in the second row of the parity-check matrix H. Therefore, for the stored data {T 1,j , T 2,j , T 3,j , T 4,j} of T1, T2, T3, T4 obtained by using any one of the RM transformation algorithm calculation structures in FIGS. 5 - 7 at the j-th moment, based on ξ + 2 registers, the RM transformation algorithm can be executed again respectively to obtain 4 groups of stored data of {y0, y1, …, y ξ} at the j-th moment, which is expressed as: Y m = {y m,0 , y m,1 , …, y m,ξ}, 1 ≤ m ≤ 4. For example: performing the RM transformation algorithm on T 1,j to obtain Y1 = {y 1,0 , y 1,1 , …, y 1,ξ}, performing the RM transformation algorithm on T 2,j to obtain Y2 = {y2,0 ,y 2,1 ,…,y 2,ξ}, for T 3,j Performing the RM transform algorithm yields Y3 = {y 3,0 ,y 3,1 ,…,y 3,ξ}, for T 4,j Performing the RM transform algorithm yields Y4 = {y 4,0 ,y 4,1 Taking 17 parity sub-matrices as an example, the structure can be calculated using any of the RM transformation algorithms shown in Figures 5-7, resulting in 16 T1 values, represented as: {T 1,1 ,T 1,2 ,T 1,3 ,T 1,4 ,T 1,5 ,T 1,6 ,T 1,7 ,T 1,8 ,T 1,9 ,T 1,10 ,T 1,11 ,T 1,12 ,T 1,13 ,T 1,14 ,T 1,15 T 1,16 Based on the settlement structure shown in Figure 5, and as shown in Figure 8, the registration process for the 16 T1 values ​​can be described as follows:

[0272] (1) Input T 1,16 Deposit

[0273] Enter T 1,15 renew Deposit

[0274] Enter T 1,14 renew renew

[0275] Enter T 1,13 renew

[0276] (2) Input T 1,12 Deposit renew

[0277] Enter T 1,11 renew renew

[0278] Enter T 1,10 renew renew

[0279] Enter T 1,9 renew renew renew

[0280] (3) Input T 1,8 Deposit renew

[0281] Enter T 1,7 renew renew

[0282] Enter T 1,6 renew renew

[0283] Enter T 1,5 renew renew renew

[0284] (4) Input T 1,4 renew renew

[0285] Enter T 1,3 renew renew renew

[0286] Enter T 1,2 renew renew

[0287] Enter T 1,1 renew

[0288] It should be noted that the T1 second registers are released after completing the calculation for each parity submatrix, in order to process the calculation for the next parity submatrix, while the ξ+2 registers need to process the stored data {T} obtained at each time step. 1,j ,T 2,j ,T 3,j ,T 4,j The summation will not be released until the first time step y0, y1, ..., y is obtained. ξ The stored data.

[0289] As can be seen from Figure 9, for {T 1,j ,T 2,j ,T3,j ,T 4,j Each execution of the RM transformation algorithm requires ξ+2 registers. Therefore, executing it 4 times requires an additional 4(ξ+2) registers on top of the T second registers.

[0290] The data stored in the M first registers at time N is determined based on the second sub-data corresponding to the Nth parity sub-matrix in the data to be encoded and the initial values ​​of the M first registers. For example, in an embodiment where the M first registers include M2 ​​registers B, the initial values ​​of the M2 registers B are y0, y1, ..., y ξ The initial value is 0.

[0291] In this implementation, the RM transformation algorithm is executed on the stored data of multiple target registers C at time j to obtain multiple sets of M2 registers B at time j. By updating the stored data of these M2 registers B, the second target bit corrector in the first corrector can be directly calculated without updating the corrector at each time. This helps to avoid the multiplication operation performed when updating the second target bit corrector at each time, thereby further reducing the computational complexity.

[0292] As can be seen from the RM transform algorithm calculation structure shown in Figures 5-7, grouping the first sub-data based on t can reduce the processing step size of the first sub-data; and then, based on the preset T second registers, the RM transform algorithm is used to register multiple first sub-data groups, which helps to reduce the interleaving in the RM transform algorithm calculation structure, thereby producing fewer intermediate calculation results. That is, the encoding calculation can be completed with fewer registers, reducing the complexity of the register space.

[0293] For example, when N=1, the stored data of the M first registers at time 1 is determined based on the data to be encoded and the initial values ​​of the M first registers.

[0294] 404: Determine the first corrector based on the stored data of the M first registers at time 1.

[0295] For example, in an embodiment where M first registers include M1 registers A, the data stored in M1 registers A at time 1 is the corrector at time 1, and the first corrector is the corrector at time 1.

[0296] In this implementation, the first corrector can be obtained by updating the corrector of the M1 registers A at each time step.

[0297] Exemplarily, in an embodiment where the M first registers include M2 register Bs, based on the stored data of multiple groups of M2 register Bs at the first moment, determine the first target bit syndrome in the first syndrome (i.e., the syndrome when i = 1, 2, 4 in Formula 5, that is, the p-th bit syndrome), and based on the first target bit syndrome, determine the first syndrome.

[0298] Specifically, for the calculation formula of S when i = 1, 2, 4 in Formula 5 i Perform transformation to obtain Formula 6:

[0299] Where is the stored data of M2 register Bs when j = 0, is the sum of the stored data of M2 register Bs when 0 < j ≤ N.

[0300] That is, the first target bit syndrome in the first syndrome can be calculated through Formula 6. Combining with the method of calculating S0 in Formula 5, the 1st bit syndrome in the first syndrome can be obtained. Combining with the method of calculating S3 in Formula 5, the second target bit syndrome in the first syndrome can be obtained.

[0301] In this implementation method, based on the stored data of multiple groups of M2 register Bs at the first moment, determine the first target bit syndrome in the first syndrome, avoiding the multiplication coefficient operation when updating the second target bit syndrome at each moment, and thus can further reduce the complexity of calculating the syndrome.

[0302] 405: Determine redundant check data based on the first syndrome to obtain the encoded codeword.

[0303] In the embodiment of this application, if the codeword is represented as c, it can be divided into c T = [p T | m T T ], where the vector p contains t bits of check data, the vector m contains k bits of data to be encoded, p T is the transpose of p, and m T is the transpose of m. Then, correspondingly, the check matrix H can be divided into two sub-matrices H = [H p | H m ], where H p is the first sub-matrix, and H m is the second sub-matrix. The first sub-matrix is the matrix composed of the 1st column to the t-th column of the check matrix; the second sub-matrix is the matrix composed of the remaining columns in the check matrix. Determine redundant check data based on the data to be encoded, the first syndrome, the first sub-matrix, and the second sub-matrix. Specifically, use m, H p , H m to construct the first linear equation:

[0304] in, For H p The inverse of , S is the corrector at time 1, here it is the first corrector. Since H p It is a t×t Vandermonde matrix composed of the first t columns of the parity-check matrix H. Therefore, it can be obtained by analyzing H. p Perform LU (LU Factorization) decomposition and quickly calculate t redundant check data based on S. The codeword is composed of t redundant check data and k bits of data to be encoded.

[0305] In this implementation, the parity check matrix is ​​divided into a first submatrix and a second submatrix. Since the first submatrix is ​​a Vandermonde matrix, it can be decomposed quickly. The product of the data to be encoded and the second submatrix is ​​the first corrector. Based on the data to be encoded, the first corrector, the first submatrix, and the second submatrix, the redundant parity check data can be calculated quickly, thus improving the encoding efficiency.

[0306] As can be seen in this embodiment, the pre-constructed parity matrix can be divided into N parity sub-matrices based on the codeword length. When N > 1, the first sub-data corresponding to the j-th parity sub-matrix and the stored data of the M pre-defined first registers at time (j+1) can be used to update the stored data at time j. Iterative updates based on the current input and the stored data at the previous time can obtain the stored data of the M first registers at time 1, thereby determining the first corrector and calculating the redundant parity data to complete the encoding. This iterative update of the stored data of the M first registers in units of parity sub-matrices is equivalent to dividing the encoding execution logic in units of parity sub-matrices. Compared with the scheme of using the entire parity matrix and all the data to be encoded for calculation, the number of elements of the parity matrix and the amount of data to be encoded involved in a single calculation are reduced, thereby reducing the computational scale of encoding and thus helping to reduce the computational complexity of encoding.

[0307] To better understand the encoding method provided in the embodiments of this application, a brief explanation is given below using specific values ​​of parameters (n,k) as an example.

[0308] In Example 1.1 of a calibration calculation, based on parameters (n,k)=(29,25), t=4 can be obtained, and the constructed check matrix H can be shown in Figure 9. When n=29, the check matrix H is divided into two submatrices H0 and H1, N=2, n1=16, n2=13. Using five additional registers T1, T2, T3, T4, T5, incremental calculations are performed in reverse order. Furthermore, when n<31, the register of S3 can be used as the target register D to optimize the calculation of S3. As shown in Figure 10, the register process for the sub-data of j=1 can be described as follows:

[0309] (1) Input x 28 Deposit Deposit

[0310] Enter x 27 renew Deposit

[0311] (2) Input x 26 Deposit renew

[0312] Enter x 25 renew Deposit

[0313] Enter x 24 renew renew

[0314] Enter x 23 renew renew Deposit

[0315] (3) Input x 22 Deposit renew

[0316] Enter x 20 renew renew renew

[0317] Enter x 21 renew renew

[0318] Enter x 19 renew renew renew

[0319] (4) Input x 18 renew renew

[0320] Enter x 17 renew renew renew

[0321] Enter x 16 renew renew

[0322] After obtaining the stored data T0, T1, T2, T3, and T4, the corrector for j=1 is calculated using the following formula:

[0323] S0 = T0;

[0324] S1=x·(T5=T1+αT2+α 2 T3+α 3 T4);

[0325] S2=x 2 ·(T5=T1+α 2 T2+α 4 T3+α 6 T4);

[0326] S3=x 3 ·(T5=S3+x 16 +α 3 x 17 +α 4 x 18 +αx 19 +α 2 x 21 +α 4 x 23 +α 2 x 24 +αx 25 +α 4 x 26 ;

[0327] After obtaining the corrector j=1, the sub-data corresponding to j=0 is registered, as shown in Figure 11. The registration process for the sub-data of j=0 can be described as follows:

[0328] (1) Input x 15 Deposit Deposit

[0329] Enter x 14 renew

[0330] Enter x 13 renew Deposit

[0331] Enter x 12 renew Deposit

[0332] (2) Input x 11 Deposit renew

[0333] Enter x 10 renew renew

[0334] Enter x9 to update renew

[0335] Enter x8 to update renew renew

[0336] (3) Input x7 register renew

[0337] Enter x5 to update renew renew

[0338] Enter x6 to update renew

[0339] Enter x4 to update renew renew

[0340] (4) Enter x3 to update renew

[0341] Enter x2 to update renew renew

[0342] Enter x1 to update renew

[0343] Enter x0 to update

[0344] It should be noted that during the encoding process, x0, ..., x3 represent redundant check data and do not participate in the calculation of the above algorithm. Alternatively, x0, ..., x3 can be set to 0 and included in the calculation of the above algorithm. After obtaining the stored data T0, T1, T2, T3, T4, the corrector for j = 0 is calculated using the following formula: S0 = T0;

[0345] After completing the calculation of the corrector S, by adjusting H... p By performing LU decomposition, p can be calculated. Assume H... p If the matrix is ​​a 4th-order Vandermonde matrix, its LU decomposition process can be described as follows:

[0346] In this example, the calculation and encoding of the corrector can be completed using only 5 additional registers.

[0347] In another example of computing the corrector, 1.2, as shown in Figure 12, the registering process for the sub-data of j=1 can be described as follows:

[0348] (1) Deposit

[0349] Deposit

[0350] Deposit Deposit

[0351] Deposit Deposit

[0352] (2) Deposit

[0353] renew

[0354] renew

[0355] renew

[0356] (3) Update

[0357] renew

[0358] renew

[0359] (4) Update

[0360] renew

[0361] After obtaining the stored data T0, T1, T2, T3, and T4, the corrector for j=1 is calculated using the following formula: S0=T0; S1=x·(S1=T1+αT2+α 2 T3+α 3 T4); S2=x 2 ·(S2=T1+α 2 T2+α 4 T3+α 6 T4); S3 = x 3 ·(T1=S3+x 16 +α 3 x 17 +α 4 x 18 +αx 19 +α 2 x 21 +α 4 x 23 +α 2 x 24 +αx 25 +α 4 x 26 );

[0362] After obtaining the corrector j=1, the sub-data corresponding to j=0 is registered, as shown in Figure 13. The registration process for the sub-data of j=0 can be described as follows:

[0363] (1) Update

[0364] renew renew renew

[0365] renew renew

[0366] (2) Update

[0367] renew

[0368] renew

[0369] renew

[0370] (3) Update

[0371] renew

[0372] renew

[0373] Update

[0374] Update

[0375] (4) Update

[0376] Update

[0377] It should be noted that during the encoding process, x0, …, x3 represent redundant check data and do not participate in the calculation of the above algorithm. Or x0, …, x3 can be taken as 0 to participate in the calculation of the above algorithm. After obtaining the stored data of T0, T1, T2, T3, T4, the syndrome for j = 0 is calculated using the following formula: S0 = T0;

[0378] In this example, only 4 additional registers are required to complete the calculation and encoding of the syndrome.

[0379] In another example 1.3 of syndrome calculation, based on the parameters (n, k) = (256, 252), t = 4 can be obtained, and the parity-check matrix H is divided into 17 sub-syndrome matrices, where n0 = 16, n j = 15, 1 ≤ j < 17. Swap the calculation order of x 5,j , x 6,j corresponding to each sub-matrix in the input, and at the same time introduce an additional register T 6,j to collect some intermediate results. For each group of codeword inputs X j = {x 0,0 , x 1,j , …, x 15,j}, where x 0,0 is only input when j = 0. Through the calculation structure shown in Figure 7, the intermediate results {T 0,j , T 1,j , T 2,j , T 3,j , T 4,j} of each group can be obtained. The initial value of the syndrome S = [S0, …, S t-1 [[ID=​​​​​​​​​​​​​​​​​,…,T m,16}, 1≤m≤4, are then used as input to the improved RM transform algorithm, resulting in 4 sets of results Y. m ={y m,0 ,y m,1 ,…,y m,4}, 1≤m≤4, finally S i For i = 1, 2, 4, the formula is: S1 = x(y 1,0 +ay 2,0 +a 2 y 3,0 +a 3 y 4,0 )+T 1,0 +αT 2,0 +α 2 T 3,0 +α 3 T 4,0 +(y 1,1 +ay 1,2 +a 2 y 1,3 + a 4 y 1,4 +a(y 2,1 +ay 2,2 +a 2 y 2,3 +a 4 y 2,4 )+a 2 (y 3,1 +ay 3,2 +a 2 y 3,3 +a 4 y 3,4 )+a 3 (y 4,1 +ay 4,2 +a 2 y 4,3 +a 4 y 4,4 S2 = x 2 (y 1,0 +a 2 y 2,0 +a 4 y 3,0 +a 6 y 4,0 )+T 1,0 +α 2 T 2,0 +α 4 T 3,0 +α 6 T 4,0 +(y 1,1 +a 2 y 1,2 +a4 y 1,3 + a 6 y 1,4 )+a 2 (y 2,1 +a 2 y 2,2 +a 4 y 2,3 +a 6 y 2,4 )+a 4 (y 3,1 +a 2 y 3,2 +a 4 y 3,3 +a 6 y 3,4 )+a 6 (y 4,1 +a 2 y 4,2 +a 4 y 4,3 +a 6 y 4,4 );

[0381] In this example, the computational complexity of the calibrator can be further reduced by adding 4(ξ+2) registers.

[0382] Please refer to Figure 14, which is a flowchart illustrating another encoding method provided in an embodiment of this application. As shown in Figure 14, it may include steps 1401-1404:

[0383] 1401: Read the raw data from k information disks;

[0384] 1402: The corrector is calculated and updated using an improved RM transform algorithm;

[0385] 1403: Obtaining redundancy check data by solving the encoded linear equation using LU decomposition;

[0386] 1404: Write the redundancy check data to the redundancy disk.

[0387] The specific implementation of steps 1401-1403 can be referred to the corresponding description in the embodiment shown in Figure 4, and can achieve the same or similar beneficial effects.

[0388] Please refer to Figure 15, which is a flowchart illustrating a decoding method provided in an embodiment of this application. This method can be implemented based on the system architecture shown in Figure 3. As shown in Figure 15, the method includes steps 1501-1505:

[0389] 1501: Obtain the codeword to be decoded.

[0390] In this embodiment of the application, the codeword is represented as c, and the length of the codeword is a known parameter n.

[0391] 1502: Determine N check submatrices from a pre-constructed check matrix based on the length of the codeword.

[0392] In this embodiment, based on the grouping principle shown in Figure 2, given that the codeword length is n, the parity check matrix H can be divided into N parity check sub-matrices H. j For example: when 16 < n ≤ 31, N = 2; when n ≤ 16, N = 1; when n = 256, N = 17. That is, N ≥ 1.

[0393] 1503: When N > 1, for the j-th check submatrix among the N check submatrixes, based on the fourth sub-data corresponding to the j-th check submatrix in the codeword and the preset storage data of the M first registers at time (j+1), determine the storage data of the M first registers at time j, so as to obtain the storage data of the M first registers at time 1.

[0394] The data stored in the M first registers at time N is determined based on the fifth sub-data corresponding to the Nth parity sub-matrix in the codeword and the initial values ​​of the M first registers. Where 0 ≤ j ≤ N-1.

[0395] In one possible implementation of this application embodiment, the M first registers include M1 registers A, for example: the M1 registers A can be registers used to store the corrector. The corrector S = [S0, ..., S...]. t-1 If M1 registers A can be S0's register, S1's register, ..., S1's register, respectively. t-1 The registers. In another possible implementation, the M first registers include M2 ​​registers B, for example: the M2 registers B are registers used to store the sum of intermediate calculation results during the RM transformation calculation, and the M2 registers B can be represented as: {y0, y1, ..., y ξ},in, This is for rounding up.

[0396] For example, the implementation of step 1503 can be described as follows:

[0397] S15031: Group the fourth sub-data to obtain multiple fourth sub-data groups;

[0398] In this embodiment, the grouping method of the fourth sub-data can refer to the grouping method of the first sub-data. It should be noted that x only exists when j = 0. 0,0 .

[0399] S15032: Based on the preset T second registers, the Reid-Muller RM transform algorithm is used to register multiple fourth sub-data groups to obtain the stored data of T1 second registers at time j; where T1≤T.

[0400] In this embodiment, multiple fourth sub-data groups can be registered using any of the methods shown in Figures 5-7 to obtain the stored data of T1 second registers at time j. For any fourth sub-data group, if there is invalid data, that data will not participate in the RM transform algorithm calculation, or its value will be set to 0 and participated in the RM transform algorithm calculation. That is, the fourth and fifth sub-data can be non-invalid sub-data corresponding to the parity sub-matrix in the codeword, or they can be complete sub-data corresponding to the parity sub-matrix in the codeword.

[0401] For example, the Reid-Muller RM transform algorithm is used to register multiple fourth sub-data sets, including:

[0402] The RM transformation algorithm is used to register multiple fourth sub-data groups in reverse or partial reverse order; or,

[0403] When the length of the codeword is within the second preset range, the RM transformation algorithm is used to register multiple fourth sub-data groups in a group synchronization manner.

[0404] In this implementation, the RM transform algorithm is used to register multiple fourth sub-data groups in reverse order of the fourth sub-data. This gives the decoding process incremental computation characteristics, meaning synchronous decoding can be performed during data transmission. This results in high decoding efficiency and facilitates coordination between decoding operations and data communication, further improving the overall system performance. When the codeword length is within the second preset range, the RM transform algorithm is used to register multiple fourth sub-data groups in a synchronized manner between groups. The entire calculation process does not require the introduction of temporary registers, further reducing register requirements. By using the RM transform algorithm to register multiple fourth sub-data groups in reverse order of the fourth sub-data, an additional register can be used to store the intermediate results required for calculating the second target bit corrector in the corrector at time j, or the second target bit corrector in the second corrector, reducing the complexity of calculating the second target bit corrector at each time step.

[0405] S15033: Based on the stored data of T1 second registers at time j and the stored data of M first registers at time (j+1), determine the stored data of M first registers at time j.

[0406] For example, in an embodiment where M first registers include M1 registers A, the data stored in M1 registers A at time (j+1) is the corrector at time (j+1); T1 second registers include multiple target registers C, namely T1, T2, T3, and T4. The corrector at time (j+1) includes the correctors at times (j+2) to N, that is, the corrector corresponding to the parity matrix composed of the parity matrix composed of the parity matrix from the (j+1)th to the Nth parity matrix.

[0407] For example, based on the stored data of T1 second registers at time j and the stored data of M first registers at time (j+1), the stored data of the M first registers at time j is determined, including:

[0408] Based on the stored data of multiple target registers C at time j, the coefficients corresponding to the j-th check matrix, and the corrector at time (j+1), the first target bit corrector in the corrector at time j is determined;

[0409] Based on the first target bit corrector, the corrector at time j is determined; the data stored in registers A of M1 at time j is the corrector at time j.

[0410] When 4 ≤ t ≤ 5, there is a second target bit corrector, which is the corrector other than the first bit corrector (S0) and the first target bit corrector among the t-bit correctors. When t belongs to the first preset range, the T1 second registers also include a target register D, that is, an additional register space T6 is introduced. The data stored in register T6 at time j is used to calculate the second target bit corrector in the corrector at time j, that is, S3 at time j.

[0411] In this implementation, the electronic device can calculate the first target bit corrector in the corrector at time j by using the stored data of multiple target registers C obtained by the RM transformation algorithm at time j, the coefficients corresponding to the j-th check matrix, and the corrector at time (j+1). Based on the first target bit corrector and the calculated other bit correctors, the corrector at time j is determined. This allows for iterative updates of the corrector within a single check matrix using the RM transformation algorithm and simple operations. Compared to calculating the corrector based on the entire check matrix, this approach achieves both lower computational space complexity and lower computational complexity.

[0412] For example, in an embodiment where M first registers include M2 ​​registers B, T1 second registers include multiple target registers C; based on the stored data of T1 second registers at time j and the stored data of M first registers at time (j+1), the stored data of M first registers at time j is determined, including:

[0413] Based on M² registers B, the RM transformation algorithm is used to register the stored data of multiple target registers C at time j, resulting in multiple sets of stored data for M² registers B at time j. Each set of stored data for M² registers B at time j corresponds one-to-one with the stored data of the corresponding sets of M² registers B at time j. The stored data for each set of M² registers B at time j is obtained based on the stored data of M² registers B at time (j+1) and the corresponding stored data of the target register C at time j. Specifically, the stored data of each register B at time (j+1) is the sum of the stored data of time (j+1) T1, T2, T3, T4 and the stored data of time (j+2) to time N T1, T2, T3, T4.

[0414] In this embodiment, when t belongs to the first preset range, the data stored in the target register D (register T6) at time j is used to calculate the second target bit corrector in the second corrector, i.e., S3 at time 1. By using an additional register (i.e., the target register D) to store the intermediate results required for calculating the second target bit corrector in the second corrector, the complexity of calculating the second target bit corrector can be reduced.

[0415] For the stored data {T1,j,T2,j,T4} at time j obtained by calculating the structure using any of the RM transform algorithms in Figures 5-7... 3,j ,T 4,j Based on ξ+2 registers, the RM transformation algorithm can be executed again to obtain 4 sets {y0,y1,…,y}. ξ The stored data at time j. As can be seen from Figure 9, for {T} 1,j ,T 2,j ,T 3,j ,T 4,j Each execution of the RM transformation algorithm requires ξ+2 registers. Therefore, executing it 4 times requires an additional 4(ξ+2) registers on top of the T second registers.

[0416] The data stored in the M first registers at time N is determined based on the second sub-data corresponding to the Nth parity sub-matrix in the data to be encoded and the initial values ​​of the M first registers. For example, in an embodiment where the M first registers include M2 ​​registers B, the initial values ​​of the M2 registers B are y0, y1, ..., y ξ The initial value is 0.

[0417] In this implementation, the RM transformation algorithm is executed on the stored data of multiple target registers C at time j to obtain multiple sets of M2 registers B at time j. By updating the stored data of these M2 registers B, the second target bit corrector in the second corrector can be directly calculated without updating the corrector at each time. This helps to avoid the multiplication operation performed when updating the second target bit corrector at each time, thereby further reducing the computational complexity.

[0418] For example, when N=1, the stored data of the M first registers at time 1 is determined based on the data to be encoded and the initial values ​​of the M first registers.

[0419] 1504: Determine the second corrector based on the stored data of the M first registers at time 1.

[0420] For example, in an embodiment where M first registers include M1 registers A, the data stored in M1 registers A at time 1 is the corrector at time 1, and the second corrector is the corrector at time 1.

[0421] For example, in an embodiment where M first registers include M2 ​​registers B, the first target bit corrector in the second corrector (i.e., the corrector when i = 1, 2, 4 in Formula 5, which is the p-th bit corrector) is determined based on the stored data of multiple sets of M2 registers B at time 1. Based on the first target bit corrector, the second corrector is determined. The specific implementation can be referred to the corresponding description of step 404 in Figure 4.

[0422] 1505: Data recovered from failure based on the second corrector.

[0423] In this embodiment of the application, the ρ invalid data in codeword c is represented as e, and the n-ρ non-invalid data is represented as c. e Therefore, the parity check matrix H can be divided into two submatrices H0. e and Among them, H e For the third submatrix, The fourth submatrix is ​​the matrix consisting of the columns corresponding to the failed data in the parity check matrix H, the third submatrix is ​​the matrix consisting of the remaining columns in the parity check matrix H. The failed data is recovered based on the codeword, the second corrector, the third submatrix, and the fourth submatrix. Specifically, c... e , H e Construct the second linear equation:

[0424] in, For H eThe inverse of , S is the corrector at time 1, and here it is the second corrector. Since H e It is a Vandermonde matrix, therefore, it can be determined by adjusting H. e Perform LU (LU Factorization) decomposition and quickly calculate ρ invalid data based on S to complete the decoding.

[0425] In this implementation, the parity check matrix is ​​divided into a third submatrix and a fourth submatrix. Since the third submatrix is ​​a Vandermonde matrix, it can be decomposed quickly. The product of the non-failed data and the fourth submatrix is ​​the second corrector. Based on the codeword, the second corrector, the third submatrix, and the fourth submatrix, the failed data can be calculated quickly, thus improving decoding efficiency.

[0426] For example, when the number of faulty data bits ρ is less than or equal to t, the third submatrix is ​​a Vandermonde square matrix, and the number of bits in the second corrector is equal to the number of faulty data bits. In this case, it is only necessary to calculate the first ρ corrector bits S′=[S0,…,S ρ -1], and take H at the same time e The first ρ rows form a ρ×ρ Vandermonde square H′ e The LU decomposition of the ρ-order Vandermonde matrix can be used to calculate e = H′. e -1 ·S′.

[0427] In this implementation, when ρ is less than t, the number of bits in the calculated second corrector can be reduced, further reducing the computational complexity compared to the scheme that calculates a t-bit corrector.

[0428] For example, when ρ is less than t, n-ρ unexpired data points need to be downloaded for calculation, resulting in a relatively large download volume. Matrix H e If the number of columns is less than t, then H can be used. e Take column t to make H e By constructing a t×t Vandermonde matrix, the amount of data that needs to be downloaded is relatively reduced, and it can be dynamically adapted to the system bandwidth.

[0429] As can be seen in this embodiment, the pre-constructed parity matrix can be divided into N parity sub-matrices based on the length of the codeword. When N > 1, the first sub-data corresponding to the j-th parity sub-matrix and the stored data of the M pre-defined first registers at time (j+1) can be used to update the stored data at time j. Iterative updates based on the current input and the stored data at the previous time can obtain the stored data of the M first registers at time 1, thereby determining the second corrector, calculating the failed data, and completing the decoding. This iterative update of the stored data of the M first registers in units of parity sub-matrices is equivalent to dividing the decoding execution logic in units of parity sub-matrices. Compared with the calculation scheme using the entire parity matrix and all codewords, the number of elements of the parity matrix and the amount of codeword data involved in a single calculation are reduced, thereby reducing the computational scale of decoding and thus helping to reduce the computational complexity of decoding.

[0430] Please refer to Figure 16, which is a flowchart illustrating another decoding method provided in an embodiment of this application. As shown in Figure 16, it may include steps 1601-1604:

[0431] 1601: Read data from a non-failed disk;

[0432] 1602: The corrector is calculated and updated using an improved RM transform algorithm;

[0433] 1603: Using LU decomposition to solve the encoded linear equation to obtain the recovered data;

[0434] 1604: Write the recovered data to the failed disk.

[0435] The specific implementation of steps 1601-1603 can be referred to the corresponding description in the embodiment shown in Figure 15, and can achieve the same or similar beneficial effects.

[0436] Under the parameters of Example 1.1 of this application, the encoding requires a total of 782 XOR operations, and the number of XOR operations required for decoding depends on the location and number of failures. The computational complexity of decoding 4-bit failures is slightly higher than that of the encoding process. Meanwhile, both the encoding and decoding processes only require the introduction of 5 additional registers, resulting in low computational space complexity. Table 1 shows the average time taken to encode and decode 1 gigabyte (GB) of data 100 times on the test platform. The data block size was chosen to be 4 kilobytes (kB), and the failure locations for the decoding tests were: 16, 18, 20, and 22.

[0437] Table 1

[0438] As can be seen from Table 1, the encoding and decoding algorithm provided in this application embodiment can effectively reduce the space complexity based on the RM transform method and reduce the computational complexity of the encoding and decoding process. The encoding and decoding speed is fast and the computational efficiency is high.

[0439] Under the parameters of Example 1.3 of this application, the number of additional registers required by the proposed encoding / decoding algorithm, optimization method and existing encoding / decoding methods based on the original RM transform algorithm under different code lengths was statistically analyzed. The statistical results are shown in Table 2.

[0440] Table 2

[0441] As can be seen from Table 2, the encoding and decoding algorithm provided in this application embodiment can achieve a space complexity that is much smaller than that of existing encoding and decoding algorithms based on RM transform. Although the optimization method increases the space complexity to some extent, it is still better than the existing methods.

[0442] This application also evaluates the computational complexity of the proposed encoding / decoding algorithm and optimization method, as well as existing encoding / decoding algorithms based on the RM transform method, when the redundancy check data has 4 bits and a full XOR operation. The evaluation results are shown in Figure 17. Based on Figure 17, it can be seen that the encoding / decoding method provided by this application can provide similar computational complexity while having a much lower space complexity than the original RM transform method, and its computational complexity is even better when the code length is short.

[0443] Please refer to Figure 18, which is a schematic diagram of an encoding device provided in an embodiment of this application. This device can be applied to an electronic device or a chip in an electronic device. As shown in Figure 18, the device may include a first acquisition unit 1801 and a first processing unit 1802; wherein:

[0444] The first acquisition unit 1801 is used to acquire the data to be encoded and the codeword length;

[0445] The first processing unit 1802 is used to determine N parity sub-matrices from a pre-constructed parity matrix based on the codeword length; when N>1, for the j-th parity sub-matrice among the N parity sub-matrices, based on the first sub-data corresponding to the j-th parity sub-matrice in the data to be encoded and the stored data of the M first registers at time (j+1), the stored data of the M first registers at time j is determined to obtain the stored data of the M first registers at time 1; the stored data of the M first registers at time N is determined based on the second sub-data corresponding to the N-th parity sub-matrice in the data to be encoded and the initial values ​​of the M first registers; based on the stored data of the M first registers at time 1, a first corrector is determined; based on the first corrector, redundant parity data is determined to obtain the encoded codeword; where 0≤j≤N-1.

[0446] In one possible implementation, regarding determining the stored data of the M first registers at time j based on the first sub-data corresponding to the j-th parity sub-matrix in the data to be encoded and the stored data of the M first registers at time (j+1), the first processing unit 1802 is specifically used for:

[0447] The first sub-data is grouped to obtain multiple first sub-data groups;

[0448] Based on a preset set of T second registers, the Reid-Muller RM transform algorithm is used to register multiple first sub-data groups to obtain the stored data of T1 second registers at time j; where T1≤T;

[0449] Based on the stored data of T1 second registers at time j and the stored data of M first registers at time (j+1), determine the stored data of M first registers at time j.

[0450] In one possible implementation, the M first registers include M1 registers A; the M1 registers A store the corrector at time (j+1); the T1 second registers include multiple target registers C;

[0451] In determining the stored data of the M first registers at time j based on the stored data of the T1 second registers at time j and the stored data of the M first registers at time (j+1), the first processing unit 1802 is specifically used for:

[0452] Based on the stored data of multiple target registers C at time j, the coefficients corresponding to the j-th check matrix, and the corrector at time (j+1), the first target bit corrector in the corrector at time j is determined;

[0453] Based on the first target bit corrector, the corrector at time j is determined; the data stored in registers A of M1 at time j is the corrector at time j.

[0454] In one possible implementation, the data stored in M1 registers A at time 1 is the corrector at time 1; the first corrector is the corrector at time 1.

[0455] In one possible implementation, the M first registers include M2 ​​registers B; the T1 second registers include multiple destination registers C;

[0456] In determining the stored data of the M first registers at time j based on the stored data of the T1 second registers at time j and the stored data of the M first registers at time (j+1), the first processing unit 1802 is specifically used for:

[0457] Based on M2 registers B, the RM transformation algorithm is used to register the stored data of multiple target registers C at time j, resulting in multiple sets of stored data of M2 registers B at time j. The stored data of multiple target registers C at time j corresponds one-to-one with the stored data of multiple sets of M2 registers B at time j. The stored data of each set of M2 registers B at time j is obtained based on the stored data of M2 registers B at time (j+1) and the corresponding stored data of target register C at time j.

[0458] In one possible implementation, regarding determining the first corrector based on the stored data in the M first registers at time 1, the first processing unit 1802 is specifically used for:

[0459] Based on the stored data of multiple sets of M2 registers B at time 1, the first target bit corrector in the first corrector is determined;

[0460] The first corrector is determined based on the first target position corrector.

[0461] In one possible implementation, when the length t of the redundancy check data is within a first preset range, the T1 second registers also include a target register D. The data stored in the target register D at time j is used to calculate the second target bit corrector in the corrector at time j or to calculate the second target bit corrector in the first corrector; t is determined based on the length of the data to be encoded and the codeword length.

[0462] In one possible implementation, the first processing unit 1802 is further configured to:

[0463] The parity check matrix is ​​divided into a first submatrix and a second submatrix; the first submatrix is ​​the matrix composed of columns 1 to t of the parity check matrix; the second submatrix is ​​the matrix composed of the remaining columns of the parity check matrix.

[0464] In determining the redundancy check data based on the first corrector, the first processing unit 1802 is specifically used for:

[0465] Based on the data to be encoded, the first corrector, the first submatrix, and the second submatrix, the redundant check data is determined.

[0466] In one possible implementation, in registering multiple first sub-data sets using the Reid-Muller RM transform algorithm, the first processing unit 1802 is specifically used for:

[0467] The RM transformation algorithm is used to register multiple first sub-data groups in reverse or partial reverse order; or,

[0468] When the codeword length is within the second preset range, the RM transformation algorithm is used to register multiple first sub-data groups in a group synchronization manner.

[0469] In one possible implementation, the parity-check matrix is ​​over a finite field F. 16 [x] / (1+αx+x 2 The Vandermonde matrix constructed on α; where / denotes the modular operation, and α is the annular domain F. 16 =F2[α] / (1+α+α) 2 +α 3 +α 4 The elements in ) are variables, where x is a variable.

[0470] It should be noted that the implementation of each unit described in FIG18 can also refer to the corresponding description of the embodiments shown in FIG4 to FIG14. Furthermore, the beneficial effects of the device described in FIG18 can be described with reference to the corresponding description of the embodiments shown in FIG4 to FIG14, and will not be repeated here.

[0471] Please refer to Figure 19, which is a schematic diagram of a decoding device provided in an embodiment of this application. This device can be applied to an electronic device or a chip in an electronic device. As shown in Figure 19, the device may include a second acquisition unit 1901 and a second processing unit 1902; wherein:

[0472] The second acquisition unit 1901 is used to acquire the codeword to be decoded;

[0473] The second processing unit 1902 is used to determine N parity sub-matrices from a pre-constructed parity matrix based on the length of the codeword; when N>1, for the j-th parity sub-matrice among the N parity sub-matrices, based on the fourth sub-data corresponding to the j-th parity sub-matrice in the codeword and the stored data of the M first registers at time (j+1), the stored data of the M first registers at time j is determined, so as to obtain the stored data of the M first registers at time 1; the stored data of the M first registers at time N is determined based on the fifth sub-data corresponding to the N-th parity sub-matrice in the codeword and the initial values ​​of the M first registers; based on the stored data of the M first registers at time 1, a second corrector is determined; and the failed data is recovered based on the second corrector; where 0≤j≤N-1.

[0474] In one possible implementation, regarding determining the stored data of the M first registers at time j based on the fourth sub-data corresponding to the j-th parity sub-matrix in the codeword and the stored data of the preset M first registers at time (j+1), the second processing unit 1902 is specifically used for:

[0475] The fourth sub-data is grouped to obtain multiple fourth sub-data groups;

[0476] Based on a preset set of T second registers, the Reid-Muller RM transform algorithm is used to register multiple fourth sub-data groups to obtain the stored data of T1 second registers at time j; where T1≤T;

[0477] Based on the stored data of T1 second registers at time j and the stored data of M first registers at time (j+1), determine the stored data of M first registers at time j.

[0478] In one possible implementation, the M first registers include M1 registers A; the M1 registers A store the corrector at time (j+1); the T1 second registers include multiple target registers C;

[0479] In determining the stored data of the M first registers at time j based on the stored data of the T1 second registers at time j and the stored data of the M first registers at time (j+1), the second processing unit 1902 is specifically used for:

[0480] Based on the stored data of multiple target registers C at time j, the coefficients corresponding to the j-th check matrix, and the corrector at time (j+1), the first target bit corrector in the corrector at time j is determined;

[0481] Based on the first target bit corrector, the corrector at time j is determined; the data stored in registers A of M1 at time j is the corrector at time j.

[0482] In one possible implementation, the data stored in registers A at time 1 is the corrector at time 1; the second corrector is the corrector at time 1.

[0483] In one possible implementation, the M first registers include M2 ​​registers B; the T1 second registers include multiple destination registers C;

[0484] In determining the stored data of the M first registers at time j based on the stored data of the T1 second registers at time j and the stored data of the M first registers at time (j+1), the second processing unit 1902 is specifically used for:

[0485] Based on M2 registers B, the RM transformation algorithm is used to register the stored data of multiple target registers C at time j, resulting in multiple sets of stored data of M2 registers B at time j. The stored data of multiple target registers C at time j corresponds one-to-one with the stored data of multiple sets of M2 registers B at time j. The stored data of each set of M2 registers B at time j is obtained based on the stored data of M2 registers B at time (j+1) and the corresponding stored data of target register C at time j.

[0486] In one possible implementation, regarding the determination of the second corrector based on the stored data of the M first registers at time 1, the second processing unit 1902 is specifically used for:

[0487] Based on the stored data of multiple sets of M2 registers B at time 1, the first target bit corrector in the second corrector is determined;

[0488] The second corrector is determined based on the first target position corrector.

[0489] In one possible implementation, when the length t of the redundancy check data is within a first preset range, the T1 second registers also include a target register D. The data stored in the target register D at time j is used to calculate the second target bit corrector in the corrector at time j or to calculate the second target bit corrector in the second corrector; t is determined based on the length of the data to be encoded and the length of the codeword.

[0490] In one possible implementation, the second processing unit 1902 is further configured to:

[0491] The check matrix is ​​divided into a third submatrix and a fourth submatrix; the third submatrix is ​​a matrix composed of the columns corresponding to the invalid data in the check matrix; the fourth submatrix is ​​a matrix composed of the remaining columns in the check matrix.

[0492] Regarding the recovery of failed data based on the second corrector, the second processing unit 1902 is specifically used for:

[0493] Based on the codeword, the second corrector, the third submatrix, and the fourth submatrix, recover the invalid data.

[0494] In one possible implementation, if the number of bits of the invalid data is less than or equal to t, the third submatrix is ​​a Vandermonde square matrix, and the number of bits of the second corrector is equal to the number of bits of the invalid data.

[0495] In one possible implementation, the second processing unit 1902 is specifically used for registering multiple fourth sub-data sets using the Reid-Muller RM transform algorithm:

[0496] The RM transformation algorithm is used to register multiple fourth sub-data groups in reverse or partial reverse order; or,

[0497] When the length of the codeword is within the second preset range, the RM transformation algorithm is used to register multiple fourth sub-data groups in a group synchronization manner.

[0498] In one possible implementation, the parity-check matrix is ​​over a finite field F. 16 [x] / (1+αx+x 2 The Vandermonde matrix constructed on ); where / denotes the modular operation, and α is the annular domain F16=F2[α] / (1+α+α) 2 +α 3 +α 4 The elements in ) are variables, where x is a variable.

[0499] It should be noted that the implementation of each unit described in FIG19 can also correspond to the description of the embodiments shown in FIG15 and FIG16. Furthermore, the beneficial effects of the device described in FIG19 can be described in the corresponding descriptions of the embodiments shown in FIG15 and FIG16, and will not be repeated here.

[0500] Based on the description of the above method and device embodiments, this application also provides an electronic device. Please refer to FIG20, which is a schematic diagram of the structure of an electronic device provided in this application embodiment. The electronic device includes at least one processor 2001. Optionally, the electronic device may further include an interface circuit 2002 (shown as dashed lines in the figure), with the processor 2001 and the interface circuit 2002 coupled to each other. It is understood that the interface circuit 2002 can be a transceiver or an input / output interface. Optionally, the electronic device may further include at least one memory 2003 (shown as dashed lines in the figure), which stores instructions (such as one or more computer programs) executed by at least one processor 2001, or input data required for at least one processor 2001 to execute instructions, or data generated after at least one processor 2001 executes instructions. This electronic device can be used to perform related steps of an encoding or decoding method; for example, the electronic device can be a computer, server, cloud server, etc. At least one processor 2001 in the electronic device is used to read computer program code stored in at least one memory 2003 and execute the method of any one of the embodiments shown in FIG4 to FIG14 or FIG15 to FIG16.

[0501] At least one memory 2003 includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or compact disc read-only memory (CD-ROM).

[0502] At least one processor 2001 may be one or more central processing units (CPUs). If the processor 2001 is a CPU, the CPU may be a single-core CPU or a multi-core CPU.

[0503] For example, when an electronic device is used to implement the function of an encoding method, at least one processor 2001 in the electronic device can be used to read one or more programs stored in at least one memory 2003 and perform the following operations:

[0504] Get the data to be encoded and the codeword length;

[0505] N check submatrices are determined from the pre-constructed check matrix based on the codeword length;

[0506] When N > 1, for the j-th parity submatrix among the N parity submatrixes, the storage data of the M first registers at time j is determined based on the first sub-data corresponding to the j-th parity submatrix in the data to be encoded and the storage data of the M first registers at time (j+1), so as to obtain the storage data of the M first registers at time 1; the storage data of the M first registers at time N is determined based on the second sub-data corresponding to the N-th parity submatrix in the data to be encoded and the initial values ​​of the M first registers; where 0 ≤ j ≤ N-1;

[0507] The first corrector is determined based on the stored data of the M first registers at time 1.

[0508] Redundancy check data is determined based on the first corrector to obtain the encoded codeword.

[0509] In one possible implementation, at least one processor 2001 executes the storage data of the M first registers at time (j+1) based on the first sub-data corresponding to the j-th parity sub-matrix in the data to be encoded and the stored data of the M first registers at time (j+1), including:

[0510] The first sub-data is grouped to obtain multiple first sub-data groups;

[0511] Based on a preset set of T second registers, the Reid-Muller RM transform algorithm is used to register multiple first sub-data groups to obtain the stored data of T1 second registers at time j; where T1≤T;

[0512] Based on the stored data of T1 second registers at time j and the stored data of M first registers at time (j+1), determine the stored data of M first registers at time j.

[0513] In one possible implementation, the M first registers include M1 registers A; the M1 registers A store the corrector at time (j+1); the T1 second registers include multiple target registers C;

[0514] At least one processor 2001 executes the storage data of T1 second registers at time j and the storage data of M first registers at time (j+1), determining the storage data of the M first registers at time j, including:

[0515] Based on the stored data of multiple target registers C at time j, the coefficients corresponding to the j-th check matrix, and the corrector at time (j+1), the first target bit corrector in the corrector at time j is determined;

[0516] Based on the first target bit corrector, the corrector at time j is determined; the data stored in registers A of M1 at time j is the corrector at time j.

[0517] In one possible implementation, the data stored in M1 registers A at time 1 is the corrector at time 1; the first corrector is the corrector at time 1.

[0518] In one possible implementation, the M first registers include M2 ​​registers B; the T1 second registers include multiple destination registers C;

[0519] At least one processor 2001 executes the storage data of T1 second registers at time j and the storage data of M first registers at time (j+1), determining the storage data of the M first registers at time j, including:

[0520] Based on M2 registers B, the RM transformation algorithm is used to register the stored data of multiple target registers C at time j, resulting in multiple sets of stored data of M2 registers B at time j. The stored data of multiple target registers C at time j corresponds one-to-one with the stored data of multiple sets of M2 registers B at time j. The stored data of each set of M2 registers B at time j is obtained based on the stored data of M2 registers B at time (j+1) and the corresponding stored data of target register C at time j.

[0521] In one possible implementation, at least one processor 2001 executes a determination of a first corrector based on stored data in M ​​first registers at time 1, including:

[0522] Based on the stored data of multiple sets of M2 registers B at time 1, the first target bit corrector in the first corrector is determined;

[0523] The first corrector is determined based on the first target position corrector.

[0524] In one possible implementation, when the length t of the redundancy check data is within a first preset range, the T1 second registers also include a target register D. The data stored in the target register D at time j is used to calculate the second target bit corrector in the corrector at time j or to calculate the second target bit corrector in the first corrector; t is determined based on the length of the data to be encoded and the codeword length.

[0525] In one possible implementation, before determining the first corrector based on the stored data in the M first registers at time 1, at least one processor 2001 is also used to perform:

[0526] The parity check matrix is ​​divided into a first submatrix and a second submatrix; the first submatrix is ​​the matrix composed of columns 1 to t of the parity check matrix; the second submatrix is ​​the matrix composed of the remaining columns of the parity check matrix.

[0527] At least one processor 2001 performs a redundancy check based on a first corrector to determine redundancy check data, including:

[0528] Based on the data to be encoded, the first corrector, the first submatrix, and the second submatrix, the redundant check data is determined.

[0529] In one possible implementation, at least one processor 2001 performs registering of multiple first sub-data blocks using the Reid-Muller RM transform algorithm, including:

[0530] The RM transformation algorithm is used to register multiple first sub-data groups in reverse or partial reverse order; or,

[0531] When the codeword length is within the second preset range, the RM transformation algorithm is used to register multiple first sub-data groups in a group synchronization manner.

[0532] In one possible implementation, the parity-check matrix is ​​over a finite field F. 16 [x] / (1+αx+x 2 The Vandermonde matrix constructed on α; where / denotes the modular operation, and α is the annular domain F. 16 =F2[α] / (1+α+α) 2 +α 3 +α 4 The elements in ) are variables, where x is a variable.

[0533] It should be noted that the implementation of each operation can also correspond to the description of the method in any of the embodiments shown in Figures 4 to 14.

[0534] For example, when an electronic device is used to implement the function of a decoding method, at least one processor 2001 in the electronic device can be used to read one or more programs stored in at least one memory 2003 and perform the following operations:

[0535] Obtain the codeword to be decoded;

[0536] Based on the length of the codeword, N check sub-matrices are determined from the pre-constructed check matrix;

[0537] When N > 1, for the j-th parity submatrix among the N parity submatrixes, the storage data of the M first registers at time j is determined based on the fourth sub-data corresponding to the j-th parity submatrix in the codeword and the preset storage data of the M first registers at time (j+1), so as to obtain the storage data of the M first registers at time 1; the storage data of the M first registers at time N is determined based on the fifth sub-data corresponding to the N-th parity submatrix in the codeword and the initial values ​​of the M first registers; where 0 ≤ j ≤ N-1;

[0538] The second corrector is determined based on the stored data of the M first registers at time 1;

[0539] Data failures were recovered based on the second corrector.

[0540] In one possible implementation, at least one processor 2001 executes the storage data of the M first registers at time (j+1) based on the fourth sub-data corresponding to the j-th parity sub-matrix in the codeword and the stored data of the M first registers at time (j+1), including:

[0541] The fourth sub-data is grouped based on the length t of the redundancy check data to obtain multiple fourth sub-data groups; where t is determined based on the length of the encoded data and the length of the codeword.

[0542] Based on a preset set of T second registers, the Reid-Muller RM transform algorithm is used to register multiple fourth sub-data groups to obtain the stored data of T1 second registers at time j; where T1≤T;

[0543] Based on the stored data of T1 second registers at time j and the stored data of M first registers at time (j+1), determine the stored data of M first registers at time j.

[0544] In one possible implementation, the M first registers include M1 registers A; the M1 registers A store the corrector at time (j+1); the T1 second registers include multiple target registers C;

[0545] At least one processor 2001 executes the storage data of T1 second registers at time j and the storage data of M first registers at time (j+1), determining the storage data of the M first registers at time j, including:

[0546] Based on the stored data of multiple target registers C at time j, the coefficients corresponding to the j-th check matrix, and the corrector at time (j+1), the first target bit corrector in the corrector at time j is determined;

[0547] Based on the first target bit corrector, the corrector at time j is determined; the data stored in registers A of M1 at time j is the corrector at time j.

[0548] In one possible implementation, the data stored in registers A at time 1 is the corrector at time 1; the second corrector is the corrector at time 1.

[0549] In one possible implementation, the M first registers include M2 ​​registers B; the T1 second registers include multiple destination registers C;

[0550] At least one processor 2001 executes the storage data of T1 second registers at time j and the storage data of M first registers at time (j+1), determining the storage data of the M first registers at time j, including:

[0551] Based on M2 registers B, the RM transformation algorithm is used to register the stored data of multiple target registers C at time j, resulting in multiple sets of stored data of M2 registers B at time j. The stored data of multiple target registers C at time j corresponds one-to-one with the stored data of multiple sets of M2 registers B at time j. The stored data of each set of M2 registers B at time j is obtained based on the stored data of M2 registers B at time (j+1) and the corresponding stored data of target register C at time j.

[0552] In one possible implementation, at least one processor 2001 executes a determination of a second corrector based on stored data in M ​​first registers at time 1, including:

[0553] Based on the stored data of multiple sets of M2 registers B at time 1, the first target bit corrector in the second corrector is determined;

[0554] The second corrector is determined based on the first target position corrector.

[0555] In one possible implementation, when the length t of the redundancy check data is within a first preset range, the T1 second registers also include a target register D. The data stored in the target register D at time j is used to calculate the second target bit corrector in the corrector at time j or to calculate the second target bit corrector in the second corrector; t is determined based on the length of the data to be encoded and the length of the codeword.

[0556] In one possible implementation, before determining the second corrector based on the stored data in the M first registers at time 1, at least one processor 2001 is also used to perform:

[0557] The check matrix is ​​divided into a third submatrix and a fourth submatrix; the third submatrix is ​​a matrix composed of the columns corresponding to the invalid data in the check matrix; the fourth submatrix is ​​a matrix composed of the remaining columns in the check matrix.

[0558] At least one processor 2001 executes data recovery based on the second corrector, including:

[0559] Based on the codeword, the second corrector, the third submatrix, and the fourth submatrix, recover the invalid data.

[0560] In one possible implementation, if the number of bits of the invalid data is less than or equal to t, the third submatrix is ​​a Vandermonde square matrix, and the number of bits of the second corrector is equal to the number of bits of the invalid data.

[0561] In one possible implementation, at least one processor 2001 performs registering of multiple fourth sub-data blocks using the Reid-Muller RM transform algorithm, including:

[0562] The RM transformation algorithm is used to register multiple fourth sub-data groups in reverse or partial reverse order; or,

[0563] When the length of the codeword is within the second preset range, the RM transformation algorithm is used to register multiple fourth sub-data groups in a group synchronization manner.

[0564] In one possible implementation, the parity-check matrix is ​​over a finite field F. 16 [x] / (1+αx+x 2 The Vandermonde matrix constructed on α; where / denotes the modular operation, and α is the annular domain F. 16 =F2[α] / (1+α+α) 2 +α 3 +α 4 The elements in ) are variables, where x is a variable.

[0565] It should be noted that the implementation of each operation can also correspond to the description of the method in any of the embodiments shown in Figures 15 and 16.

[0566] It should be noted that although the electronic device shown in FIG20 only illustrates at least one processor 2001, at least one memory 2003, and interface circuit 2002, those skilled in the art should understand that in specific implementations, the electronic device may also include other devices necessary for normal operation. Furthermore, depending on specific needs, those skilled in the art should understand that the electronic device may also include hardware devices for implementing other additional functions. Moreover, those skilled in the art should understand that the electronic device may only include the devices necessary for implementing the embodiments of this application, and not necessarily all the devices shown in FIG20.

[0567] This application also provides a chip, including: a processor for calling and running a computer program from a memory, causing a device with the chip installed to perform the method described in any of the embodiments shown in Figures 14 to 16 above. This chip can be a chip in an electronic device.

[0568] This application also provides a computer-readable storage medium (memory) storing a computer program that, when executed, implements the method described in any of the embodiments shown in Figures 14 to 16. It is understood that the computer-readable storage medium here may include built-in storage media in a device, or it may include extended storage media supported by the device. The computer-readable storage medium provides storage space containing the device's operating system. Furthermore, one or more computer programs suitable for loading and execution by the device's processor are also stored in this storage space. It should be noted that the computer-readable storage medium here may be high-speed RAM, or non-volatile memory, such as at least one disk storage device; optionally, it may also be at least one computer-readable storage medium located remotely from the aforementioned processor.

[0569] This application also provides a computer program product, which includes computer program code. When the computer program code is run by an electronic device, the method flow described in any one of the embodiments in Figures 14 to 16 is implemented.

[0570] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0571] It should be understood that the processor mentioned in the embodiments of this application can be a CPU, or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0572] It should also be understood that the memory mentioned in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory can be ROM, Programmable Read-Only Memory (PROM), EPROM, Electrically Erasable Programmable Read-Only Memory (EEPROM), or flash memory. Volatile memory can be RAM, which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), Synchlink Dynamic Random Access Memory (SLDRAM), and Direct Rambus RAM (DR RAM).

[0573] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory (storage module) is integrated into the processor.

[0574] It should be noted that the memories described herein are intended to include, but are not limited to, these and any other suitable types of memories.

[0575] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0576] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely exemplary. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0577] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0578] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium.

[0579] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. In the textual description of this application, the character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0580] The steps in the method of this application embodiment can be adjusted, combined, or deleted according to actual needs.

[0581] The modules in the device of this application embodiment can be merged, divided, and deleted according to actual needs.

[0582] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An encoding method, characterized in that, The method includes: Get the codeword length and the data to be encoded; Based on the codeword length, N parity submatrices are determined from the pre-constructed parity matrix; When N > 1, for the j-th parity submatrix among the N parity submatrixes, based on the first sub-data corresponding to the j-th parity submatrix in the data to be encoded and the stored data of the M first registers at time (j+1), the stored data of the M first registers at time j is determined to obtain the stored data of the M first registers at time 1; the stored data of the M first registers at time N is determined based on the second sub-data corresponding to the N-th parity submatrix in the data to be encoded and the initial values ​​of the M first registers; where 0 ≤ j ≤ N-1; Based on the stored data of the M first registers at time 1, the first corrector is determined; Redundancy check data is determined based on the first corrector to obtain the encoded codeword.

2. The method according to claim 1, characterized in that, The step of determining the stored data of the M first registers at time j based on the first sub-data corresponding to the j-th parity sub-matrix in the data to be encoded and the stored data of the M first registers at time (j+1) includes: The first sub-data is grouped to obtain multiple first sub-data groups; Based on a preset set of T second registers, the Reid-Muller RM transform algorithm is used to register the multiple first sub-data groups to obtain the stored data of T1 second registers at time j; where T1≤T; Based on the stored data of the T1 second registers at time j and the stored data of the M first registers at time (j+1), the stored data of the M first registers at time j is determined.

3. The method according to claim 2, characterized in that, The M first registers include M1 registers A; the data stored in the M1 registers A at time (j+1) is the corrector at time (j+1); the T1 second registers include multiple target registers C; The step of determining the stored data of the M first registers at time j based on the stored data of the T1 second registers at time j and the stored data of the M first registers at time (j+1) includes: Based on the stored data of the plurality of target registers C at time j, the coefficients corresponding to the j-th check matrix, and the corrector at time (j+1), the first target bit corrector in the corrector at time j is determined; Based on the first target bit corrector, the corrector at time j is determined; the stored data of the M1 registers A at time j is the corrector at time j.

4. The method according to claim 3, characterized in that, The data stored in registers A of the M1 at time 1 is the corrector at time 1; the first corrector is the corrector at time 1.

5. The method according to claim 2, characterized in that, The M first registers include M2 ​​registers B; the T1 second registers include multiple target registers C; The step of determining the stored data of the M first registers at time j based on the stored data of the T1 second registers at time j and the stored data of the M first registers at time (j+1) includes: Based on the M2 registers B, the RM transformation algorithm is used to register the stored data of the multiple target registers C at time j, resulting in multiple sets of stored data of the M2 registers B at time j; the stored data of the multiple target registers C at time j corresponds one-to-one with the stored data of the multiple sets of stored data of the M2 registers B at time j; each set of stored data of the M2 registers B at time j is obtained based on the stored data of the M2 registers B at time (j+1) and the corresponding stored data of the target register C at time j.

6. The method according to claim 5, characterized in that, The determination of the first corrector based on the stored data of the M first registers at time 1 includes: Based on the stored data of the M2 registers B in the first time step, the first target bit corrector in the first corrector is determined; The first corrector is determined based on the first target position corrector.

7. The method according to any one of claims 3-6, characterized in that, When the length t of the redundant check data is within a first preset range, the T1 second registers also include a target register D. The data stored in the target register D at time j is used to calculate the second target bit corrector in the corrector at time j or to calculate the second target bit corrector in the first corrector. t is determined based on the length of the data to be encoded and the codeword length.

8. The method according to any one of claims 1-7, characterized in that, Before determining the first corrector based on the stored data of the M first registers at time 1, the method further includes: The verification matrix is ​​divided into a first submatrix and a second submatrix; the first submatrix is ​​a matrix composed of the 1st to the tth columns of the verification matrix; the second submatrix is ​​a matrix composed of the remaining columns of the verification matrix. The step of determining redundant check data based on the first corrector includes: The redundancy check data is determined based on the data to be encoded, the first corrector, the first sub-matrix, and the second sub-matrix.

9. The method according to claim 2, characterized in that, The process of registering the multiple first sub-data groups using the Reid-Muller RM transform algorithm includes: The RM transformation algorithm is used to register the multiple first sub-data groups in reverse or partial reverse order; or... When the codeword length is within the second preset range, the RM transformation algorithm is used to register the multiple first sub-data groups in an inter-group synchronization manner.

10. The method according to any one of claims 1-9, characterized in that, The verification matrix is ​​in the finite field F 16 [x] / (1+αx+x 2 The Vandermonde matrix constructed on α; where / denotes the modular operation, and α is the annular domain F. 16 =F2[α] / (1+α+α) 2 +α 3 +α 4 The elements in ) are variables, where x is a variable.

11. A decoding method, characterized in that, The method includes: Obtain the codeword to be decoded; Based on the length of the codeword, N check sub-matrices are determined from the pre-constructed check matrix; When N > 1, for the j-th parity submatrix among the N parity submatrixes, based on the fourth sub-data corresponding to the j-th parity submatrix in the codeword and the preset stored data of the M first registers at time (j+1), the stored data of the M first registers at time j is determined, so as to obtain the stored data of the M first registers at time 1; the stored data of the M first registers at time N is determined based on the fifth sub-data corresponding to the N-th parity submatrix in the codeword and the initial values ​​of the M first registers; where 0 ≤ j ≤ N-1; The second corrector is determined based on the stored data of the M first registers at time 1; The failed data is recovered based on the second corrector.

12. The method according to claim 11, characterized in that, The step of determining the stored data of the M first registers at time j based on the fourth sub-data corresponding to the j-th parity sub-matrix in the codeword and the stored data of the M first registers at time (j+1) includes: The fourth sub-data is grouped to obtain multiple fourth sub-data groups; Based on the preset T second registers, the Reid-Muller RM transform algorithm is used to register the multiple fourth sub-data groups to obtain the stored data of the T1 second registers at time j; where T1≤T; Based on the stored data of the T1 second registers at time j and the stored data of the M first registers at time (j+1), the stored data of the M first registers at time j is determined.

13. The method according to claim 12, characterized in that, The M first registers include M1 registers A; the data stored in the M1 registers A at time (j+1) is the corrector at time (j+1); the T1 second registers include multiple target registers C; The step of determining the stored data of the M first registers at time j based on the stored data of the T1 second registers at time j and the stored data of the M first registers at time (j+1) includes: Based on the stored data of the plurality of target registers C at time j, the coefficients corresponding to the j-th check matrix, and the corrector at time (j+1), the first target bit corrector in the corrector at time j is determined; Based on the first target bit corrector, the corrector at time j is determined; the stored data of the M1 registers A at time j is the corrector at time j.

14. The method according to claim 13, characterized in that, The data stored in registers A of the M1 at time 1 is the corrector at time 1; the second corrector is the corrector at time 1.

15. The method according to claim 12, characterized in that, The M first registers include M2 ​​registers B; the T1 second registers include multiple target registers C; The step of determining the stored data of the M first registers at time j based on the stored data of the T1 second registers at time j and the stored data of the M first registers at time (j+1) includes: Based on the M2 registers B, the RM transformation algorithm is used to register the stored data of the multiple target registers C at time j, resulting in multiple sets of stored data of the M2 registers B at time j; the stored data of the multiple target registers C at time j corresponds one-to-one with the stored data of the multiple sets of stored data of the M2 registers B at time j; each set of stored data of the M2 registers B at time j is obtained based on the stored data of the M2 registers B at time (j+1) and the corresponding stored data of the target register C at time j.

16. The method according to claim 15, characterized in that, The determination of the second corrector based on the stored data of the M first registers at time 1 includes: Based on the stored data of the M2 registers B in the first time step, the first target bit corrector in the second corrector is determined; The second corrector is determined based on the first target position corrector.

17. The method according to any one of claims 13-16, characterized in that, When the length t of the redundant check data is within a first preset range, the T1 second registers also include a target register D. The data stored in the target register D at time j is used to calculate the second target bit corrector in the corrector at time j or to calculate the second target bit corrector in the second corrector; t is determined based on the length of the data to be encoded and the length of the codeword.

18. The method according to any one of claims 2-17, characterized in that, Before determining the second corrector based on the stored data of the M first registers at time 1, the method further includes: The verification matrix is ​​divided into a third sub-matrix and a fourth sub-matrix; the third sub-matrix is ​​a matrix composed of the columns corresponding to the invalid data in the verification matrix; the fourth sub-matrix is ​​a matrix composed of the remaining columns in the verification matrix. The data for recovering from failure based on the second corrector includes: Based on the codeword, the second corrector, the third submatrix, and the fourth submatrix, the failed data is recovered.

19. The method according to claim 18, characterized in that, When the number of bits of the invalid data is less than or equal to t, the third submatrix is ​​a Vandermonde matrix, and the number of bits of the second corrector is equal to the number of bits of the invalid data.

20. The method according to claim 12, characterized in that, The process of registering the multiple fourth sub-data groups using the Reid-Muller RM transform algorithm includes: The RM transformation algorithm is used to register the multiple fourth sub-data groups in reverse or partial reverse order; or, When the length of the codeword is within the second preset range, the RM transformation algorithm is used to register the multiple fourth sub-data groups in an inter-group synchronization manner.

21. The method according to any one of claims 1-20, characterized in that, The verification matrix is ​​in the finite field F 16 [x] / (1+αx+x 2 The Vandermonde matrix constructed on α; where / denotes the modular operation, and α is the annular domain F. 16 =F2[α] / (1+α+α) 2 +α 3 +α 4 The elements in ) are variables, where x is a variable.

22. An encoding device, characterized in that, The device includes a first acquisition unit and a first processing unit; The first acquisition unit is used to acquire the data to be encoded and the codeword length; The first processing unit is configured to determine N parity sub-matrices from a pre-constructed parity matrix based on the codeword length; when N > 1, for the j-th parity sub-matrice among the N parity sub-matrices, based on the first sub-data corresponding to the j-th parity sub-matrice in the data to be encoded and the stored data of the M first registers at time (j+1), determine the stored data of the M first registers at time j, so as to obtain the stored data of the M first registers at time 1; the stored data of the M first registers at time N is determined based on the second sub-data corresponding to the N-th parity sub-matrice in the data to be encoded and the initial values ​​of the M first registers; and a first corrector is determined based on the stored data of the M first registers at time 1. Based on the first corrector, redundant check data is determined to obtain the encoded codeword; where 0≤j≤N-1.

23. A decoding device, characterized in that, The device includes a second acquisition unit and a second processing unit; The second acquisition unit is used to acquire the codeword to be decoded; The second processing unit is configured to determine N parity sub-matrices from a pre-constructed parity matrix based on the length of the codeword; when N > 1, for the j-th parity sub-matrice among the N parity sub-matrices, based on the fourth sub-data corresponding to the j-th parity sub-matrice in the codeword and the stored data of the M first registers at time (j+1), determine the stored data of the M first registers at time j, so as to obtain the stored data of the M first registers at time 1; the stored data of the M first registers at time N is determined based on the fifth sub-data corresponding to the N-th parity sub-matrice in the codeword and the initial values ​​of the M first registers; and a second corrector is determined based on the stored data of the M first registers at time 1. The failed data is recovered based on the second corrector; where 0 ≤ j ≤ N-1.

24. An electronic device, characterized in that, The device includes at least one processor coupled to at least one memory for storing one or more computer programs; the at least one processor is configured such that when the electronic device executes the one or more computer programs, it implements the method as claimed in any one of claims 1-10 or 11-21.

25. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program for execution by the device, which, when executed, implements the method of any one of claims 1-10 or 11-21.

26. A computer program product, characterized in that, When the computer program product is run by the device, the device performs the method as claimed in any one of claims 1-10 or 11-21.

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