Framing reuse method and apparatus, and terminal device

Abstract

The present disclosure relates to the technical field of data communications, and in particular to a framing reuse method and apparatus, and a terminal device. The apparatus comprises: receiving, by means of a depth and bit width configuration interface, the depth and the bit width of a cache space configured according to requirements, and receiving, by means of a check mode configuration interface, a check calculation mode configured according to requirements; correspondingly receiving frame header information, frame data information, and frame trailer information by means of input interfaces respectively corresponding to a frame header, frame data, and a frame trailer, adding a frame identifier, and then respectively storing the frame header information, the frame data information, the frame trailer information, and the frame identifier in the cache space; performing framing on the basis of the frame header information, the frame data information, the frame trailer information, and the frame identifier, and calculating a check value of a current frame on the basis of the check calculation mode during framing, the check value being incorporated into the current frame; and storing, in a storage space, the current frame having undergone framing. In this way, the problems of high difficulty, long cycle and high costs in framing and caching development in complex application scenarios are solved.

Description

A multiplexing framing method, apparatus and terminal equipment

[0001] Cross-reference to related applications

[0002] This disclosure claims priority to Chinese Patent Application No. 2024109117071, filed on July 9, 2024, entitled "A Multiplexing Framing Method, Apparatus and Terminal Equipment", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of data communication technology, and in particular to a multiplexing framing method, apparatus and terminal equipment. Background Technology

[0004] In digital logic development, when application scenarios involve communication and interaction, frame assembly and storage functionalities are required to meet protocol requirements. During development, when encountering scenarios requiring frame assembly and caching operations, the common approach is to directly design the frame assembly, caching, and reading logic based on the application's needs. This approach is feasible for simple applications. However, if the application's functionalities are diverse and numerous, this method obviously requires significant effort and time, increasing development difficulty and extending the development cycle. Therefore, in complex scenarios, a customizable, depth- and content-based reusable frame assembly and caching design is crucial. This design can reduce development difficulty and costs, and shorten the product development process.

[0005] Application content

[0006] In view of this, the present disclosure provides a method, apparatus and terminal device for reusing frames, which can effectively solve the problems of high difficulty, long development cycle and high cost in the design and development of frame buffers in existing complex application scenarios.

[0007] This disclosure provides a multiplexing frame method, including the following steps:

[0008] The interface for configuring the depth and bit width of the cache space according to requirements is used to receive the depth and bit width of the cache space according to requirements, and the interface for configuring the verification method is used to receive the verification calculation method according to requirements.

[0009] The frame header information, frame data information, and frame tail information are received through the corresponding input interfaces of the frame header, frame data, and frame tail, and a frame identifier is added. Then, the frame header information, frame data information, frame tail information, and frame identifier are stored in the cache space respectively.

[0010] Frames are assembled based on the frame header information, frame data information, frame tail information, and frame identifier. During frame assembly, the check value of the current frame is calculated according to the check calculation method. The check value is used to assemble the current frame.

[0011] Store the current frame, after it has been assembled, into the storage space.

[0012] In some embodiments, the method further includes reading and outputting a frame from the buffer space according to the frame identifier via a read interface; the frame includes frame header information, frame data information, checksum, frame tail information, and frame identifier.

[0013] In some embodiments, when storing the frame header information, frame data information, frame tail information, and frame identifier into the cache space, the method further includes:

[0014] Record the total length of the input frames;

[0015] The method further includes receiving a configured read buffer threshold and determining, based on the read buffer threshold and the total length of the input frames, to output a read signal through the read-ready interface; the read signal is used by an external module to determine whether to read a frame.

[0016] Driven by the external module, the frame is read from the buffer space according to the frame identifier through the read interface and output to the external module.

[0017] In some embodiments, the frame identifier includes a frame header identifier and a frame tail identifier; the frame tail information includes an initial frame tail marker, and the frame tail identifier is determined based on the initial frame tail marker; when outputting the frame tail to the external module, a frame tail indication signal is output.

[0018] This disclosure also provides a multiplexing framing device, which includes: a framing logic module, a verification calculation logic module, a write cache logic module, and a cache management module; the framing logic module is provided with an input interface.

[0019] The cache management module includes a depth and bit width configuration interface; the cache management module is configured to receive the configured depth and bit width through the depth and bit width configuration interface, and configure the size of the cache space and the bit width of each frame according to the depth and bit width.

[0020] The framing logic module is configured to receive frame header information, frame data information, and frame tail information through the corresponding input interfaces of the frame header, frame data, and frame tail, respectively, add a frame identifier, and then store the frame header information, frame data information, frame tail information, and frame identifier into the cache space respectively.

[0021] The verification calculation logic module includes a verification method configuration interface; the verification calculation logic module is configured to receive a verification calculation method configured through the verification method configuration interface, and calculate the verification value of the current frame according to the verification calculation method when the framing logic module performs framing, and the verification value is configured to encapsulate the current frame;

[0022] The write cache logic module is configured to store the current frame after it has been assembled into a storage space; the current frame after it has been assembled includes the frame header information, frame data information, frame tail information, check value and frame identifier.

[0023] In some embodiments, the apparatus further includes a read cache logic module; the read cache logic module includes a read interface;

[0024] The read cache logic module is configured to read and output a frame from the cache space according to the frame identifier through the read interface; the frame includes frame header information, frame data information, check value, frame tail information and frame identifier.

[0025] In some embodiments, the write cache logic module is further configured to record the total length of the input frames; the read cache logic module further includes a read-ready interface and a read cache threshold configuration interface;

[0026] The read buffer logic module is specifically configured to receive a configured read buffer threshold, and determine the output of a read signal through the read-ready interface based on the read buffer threshold and the total length of the input frames; the read signal is configured to allow external modules to determine whether to read frames.

[0027] The read cache logic module is configured to read frames from the cache space according to the frame identifier through the read interface and output them to the external module under the drive of the read frame task of the external module.

[0028] In some embodiments, the frame identifier includes a frame header identifier and a frame tail identifier; the frame tail information includes an initial frame tail marker, and the frame tail identifier is determined based on the initial frame tail marker; the read buffer logic module outputs a frame tail indication signal when outputting the frame tail.

[0029] In some embodiments, the verification calculation method in the verification calculation logic module includes at least one of the following: cumulative sum, cumulative difference, parity check, and bitwise XOR.

[0030] This disclosure also provides a terminal device, which includes a processor and a memory. The memory stores a computer program, and the processor is configured to execute the computer program to implement the above-described multiplexing framing method.

[0031] The embodiments disclosed herein have the following beneficial effects:

[0032] To meet the diverse functional requirements of complex engineering scenarios, this disclosure provides a customizable and reusable design for frame assembly and caching functions. For external modules, it offers depth and bit width configuration interfaces, as well as verification method configuration interfaces, allowing for customization of cache depth and bit width, and the chosen verification calculation method based on business needs. This disclosure also provides frame header input interfaces, frame data input interfaces, and frame tail input interfaces, enabling external modules to customize frame assembly parameters and content as required. Then, a frame assembly logic module assembles frames and stores them in the cache space. A cache management module manages the cache based on depth and bit width. A verification calculation logic module performs verification and stores the verification results. A write cache logic module stores the frame header, frame data, frame tail, verification value, and frame identifier. The content of the depth and bit width configuration interfaces, verification method configuration interfaces, frame header input interfaces, frame data input interfaces, and frame tail input interfaces can all be customized according to requirements, satisfying various application scenarios. Therefore, this disclosure effectively solves the problems of high difficulty, long development cycle, and high cost in the design and development of frame caching in complex application scenarios. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this disclosure and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 shows a structural block diagram of a multiplexing framing device according to an embodiment of the present disclosure;

[0035] Figure 2 shows another structural block diagram of the multiplexing framing device according to an embodiment of the present disclosure;

[0036] Figure 3 shows a flowchart of a multiplexing framing method according to an embodiment of the present disclosure.

[0037] Key component symbols: 110 - Cache management module; 120 - Frame assembly logic module; 130 - Verification calculation logic module; 140 - Write cache logic module; 150 - Cache space; 160 - Read cache logic module. Detailed Implementation

[0038] The technical solutions of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present disclosure, and not all embodiments.

[0039] The components of the embodiments of this disclosure, typically described and illustrated in the accompanying drawings, can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the drawings is not intended to limit the scope of the claimed disclosure, but merely to illustrate selected embodiments of the disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of this disclosure.

[0040] In the following, the terms “comprising,” “having,” and their cognates, which may be used in the various embodiments of this disclosure, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more combinations thereof. Furthermore, the terms “first,” “second,” “third,” etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0041] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this disclosure pertain. Terms (such as those defined in a generally used dictionary) shall be interpreted as having the same meaning as in the context of the relevant technical field and shall not be interpreted as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this disclosure.

[0042] The following detailed description of some embodiments of this disclosure is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0043] In existing technologies, frame assembly and buffer design is performed directly based on the application scenario requirements, involving logic designs related to frame assembly, frame caching, and frame reading. However, complex scenarios with numerous and diverse functionalities require multiple frame assembly logic designs and frame buffer designs, leading to high development difficulty, long development cycles, and high costs. Therefore, this disclosure provides a reusable frame assembly method, apparatus, and terminal device, which effectively solves the problems of high development difficulty, long development cycles, and high costs associated with multiple frame assembly logic designs and frame buffer designs required for multifunctional external output in complex scenarios.

[0044] To meet the diverse application needs of complex scenarios in engineering, this disclosure presents a custom reusable design for functions such as framing and caching. The main idea of ​​this disclosure is to utilize the control of the chip's internal storage space and the configurable framing logic design to customize the cache space size and framing content of use cases, providing a reusable framing cache design that can adapt to different functional scenarios.

[0045] The following describes the multiplexing and framing device with reference to some specific embodiments.

[0046] Figure 1 shows a structural block diagram of a multiplexing and framing apparatus according to an embodiment of the present disclosure. Exemplarily, the multiplexing and framing apparatus includes: a cache management module 110, a framing logic module 120, a verification calculation logic module 130, and a write cache logic module 140.

[0047] The cache management module 110 includes a depth and bit width configuration interface; the cache management module 110 is configured to receive the configured depth and bit width through the depth and bit width configuration interface, and configure the size of the cache space 150 and the bit width of each frame according to the depth and bit width.

[0048] Optionally, when designing the cache management module 110, a depth and bit width configuration interface is provided to set the size of the frame cache space 150 and the bit width of the content of each base frame unit. The depth and bit width can be customized according to requirements to be applied to different functional scenarios.

[0049] The framing logic module 120 is equipped with input interfaces. The framing logic module 120 is configured to receive frame header information, frame data information, and frame trailer information through the corresponding input interfaces for the frame header, frame data, and frame trailer, respectively, and add a frame identifier. Then, it stores the frame header information, frame data information, frame trailer information, and frame identifier into the buffer space 150. Framing involves adding a frame header and frame trailer to the beginning and end of the frame data information. The frame header and frame trailer contain a lot of control information, such as frame delimitation to determine the frame boundaries, and frame synchronization, meaning the receiver should be able to distinguish the start and end of the frame from the received binary bit stream (frame synchronization is from the receiver's perspective). In addition, a frame identifier needs to be added for identification when reading the frame.

[0050] Optionally, the framing logic module 120 provides external input interfaces, including a frame header input interface, a frame data input interface, and a frame trailer input interface. Frame header information, frame data information, and frame trailer information are input through the corresponding input interfaces. The framing logic module 120 receives the frame header information, frame data information, and frame trailer information respectively, performs framing, and then stores them in the buffer space 150, adding their respective start markers (frame header identifier) ​​and end markers (frame trailer identifier) ​​for differentiation when reading frames. The framing logic module 120 can execute multiple times to buffer multiple frames. The content input from the frame header input interface, frame data input interface, and frame trailer input interface can be customized according to requirements to be applied to different functional scenarios. For example, different frame header information, frame data information, and frame trailer information input from external functions will result in different frame formats, completely customized by the external application.

[0051] The verification calculation logic module 130 includes a verification method configuration interface. The module is configured to receive a verification calculation method configured through this interface, calculate the verification value of the current frame according to the verification calculation method during framing by the framing logic module 120, and cache the verification value. The verification value is configured to encapsulate the current frame. In other words, the verification calculation logic module 130 can be configured with a verification calculation method. During the framing process, it calculates the verification value of the current frame simultaneously, continuing until the end of the frame data, and caching the result. The verification calculation methods in the module 130 include at least one of cumulative summation, cumulative difference, parity check, and bitwise XOR. The verification calculation method can be configured through the verification method configuration interface.

[0052] The write cache logic module 140 is configured to store frame header information, frame data information, checksum, frame trailer information, and frame identifier into the storage space. The frame identifier includes a frame header identifier and a frame trailer identifier, configured to mark the start and end positions of the current frame.

[0053] The write cache logic module 140 stores the frame, which includes frame header information, frame data information, frame tail information and frame identifier, obtained by the frame assembly logic module 120 into the chip storage space, and stores the start and end positions of the verification value obtained by the frame assembly logic module verification calculation logic module 130 into the chip storage space.

[0054] In one embodiment, to facilitate frame reading by external modules, as shown in FIG2, the device further includes a read cache logic module 160; the read cache logic module 160 includes a read interface. The read cache logic module 160 is configured to read and output frames from the cache space 150 according to the frame identifier through the read interface; the frame includes frame header information, frame data information, checksum, frame trailer information, and frame identifier.

[0055] Furthermore, the write cache logic module 140 is also configured to record the total length of the input frames; the read cache logic module 160 also includes a read-ready interface and a read cache threshold configuration interface.

[0056] The read buffer logic module 160 is specifically configured to receive a configured read buffer threshold and, based on the read buffer threshold and the total length of the input frames, determine the output of a read signal through the read-ready interface. The read signal is configured to allow external modules to determine when to read frames. Driven by the external module's frame reading task, the read buffer logic module 160 reads frames from the buffer space 150 via the read interface based on the frame identifier and outputs them to the external module. The customizable read buffer threshold described above can adapt to special application scenarios such as early reading and preventing buffer overflows.

[0057] Furthermore, the frame identifier includes a frame header identifier and a frame tail identifier; the frame tail information includes an initial frame tail mark, and the frame tail identifier is determined based on the initial frame tail mark; the initial frame tail mark contains a 1-bit signal to indicate that the data is valid, and this 1-bit signal data needs to be removed first to obtain the frame tail identifier, and then the frame tail identifier is re-added. The read buffer logic module 160 outputs a frame tail indicator signal when outputting the frame tail to indicate that a complete frame has been output. For example, the frame tail indicator signal can be a pulse signal, and this disclosure does not limit it.

[0058] For example, the storage space is the chip storage space. The read buffer logic module 160 is configured to determine the relationship between the total length of the input frames in the previous frame step and the size of the read buffer threshold, and set the read ready interface level high when the total length of the input frames is greater than the read buffer threshold; otherwise, it keeps the read ready interface low. The read buffer logic module 160 outputs a pulse signal and sets the read ready signal low when outputting the end of the frame according to the frame end mark.

[0059] Figure 3 illustrates a flowchart of a multiplexing framing method according to an embodiment of the present disclosure. Exemplarily, the multiplexing framing method includes:

[0060] S10 receives the depth and bit width of the cache space of 150 configured according to requirements through the depth and bit width configuration interface, and receives the verification calculation method configured according to requirements through the verification method configuration interface.

[0061] This embodiment provides a depth and bit width configuration interface for external modules, allowing them to customize the depth and bit width of the 150-bit cache space according to their needs. For example, the cache depth configuration in this use case is at least greater than the maximum length of the complete frame, and the cache bit width configuration is equal to the data bit width of each base frame unit. This embodiment also provides a verification method configuration interface for external modules, allowing them to set the verification calculation method according to their needs. Verification calculation methods include one of the following: summation, difference, parity check, and bitwise XOR. Only after defining the configuration interface can the method disclosed herein be adapted to the specified functional scenario. Exemplarily, the aforementioned depth and bit width configuration interface and verification method configuration interface can be chip ports.

[0062] S20: Receive frame header information, frame data information, and frame tail information through the corresponding input interfaces of frame header, frame data, and frame tail, respectively, add frame identifier, and then store the frame header information, frame data information, frame tail information, and frame identifier into the buffer space 150 respectively.

[0063] When the frame assembly logic starts working, it receives the frame header information, frame data information, frame tail information, length, and valid signal from each input interface. The information is cached according to the content. The above information is entirely determined by the application scenario input, which determines the required frame format. For example, the specific content of each part of the frame and its continuous cache length are all customized according to the application scenario.

[0064] During the framing process, each input base frame unit is stored in the buffer space 150 through write buffer logic, and frame header and frame tail identifiers are added to determine their respective start and end positions and record the total length of the input frames.

[0065] S30: Frames are assembled based on the frame header, frame data, frame trailer, and frame identifier. During frame assembly, the checksum of the current frame is calculated according to the checksum calculation method. The checksum is used to assemble the current frame. While writing to the buffer, the checksum logic calculates the result according to the configured checksum calculation method and records it, waiting to continue calculation when the next base frame unit is written, until the frame data ends and the calculation result is cached.

[0066] The input of information for each part of a frame is a continuous process. The verification logic, framing logic, and write buffer logic are performed synchronously. While framing, the verification value is also being accumulated and calculated until the end of the frame. The write buffer logic caches the result of the framing logic before the end of the frame and caches the verification result of the current frame at the end of the frame.

[0067] S40: Store the current frame, which has been assembled, into the storage space.

[0068] The current frame, once assembled, includes a frame header identifier, frame header information, frame data information, a checksum, frame trailer information, and a frame trailer identifier. For example, the storage space can be the chip's storage space. When reading a frame, it is necessary to first read the frame from the buffer space within the chip's storage space based on the frame header identifier and frame trailer identifier.

[0069] In one embodiment, the method further includes step S50.

[0070] S50 reads and outputs frames from buffer space 150 based on the frame identifier through the read interface; the frame includes frame header information, frame data information, checksum, and frame trailer information. A read interface is provided to external modules for reading frames.

[0071] Furthermore, when storing the frame header information, frame data information, frame tail information and frame identifier into the buffer space 150 respectively, it also includes: recording the total length of the input frames;

[0072] The method also includes receiving a configured read buffer threshold and determining, based on the read buffer threshold and the total length of the input frames, to output a read-ready signal through the read-ready interface provided to the external module. The read signal is used by the external module to determine whether to read a frame. Under the drive of the external module, the frame is read from the buffer space 150 according to the corresponding storage location through the read interface and output to the external module. The frame tail includes a frame tail marker; when outputting the frame tail to the external module, a frame tail indication signal is also output.

[0073] Optionally, the relationship between the total length of the input frames recorded in the previous step and the configured read buffer threshold is determined. If the total length of the input frames is greater than the read buffer threshold, the read-ready interface signal is set high; otherwise, the read-ready interface remains low. After the external module determines that the read-ready interface signal is high, it can read the buffered frames. When the end of the frame is read, a pulse signal indicating the end of frame reading is output, and the read-ready interface signal is set low. The module then continues to determine the relationship between the total length of the input frames recorded in the previous two steps and the set read buffer threshold to continue reading frames.

[0074] After completing one frame assembly and caching operation, multiple frame assemblies and caching operations can be supported based on the set cache depth. When a full frame or more is completed, the read-ready interface signal will remain high, and the read interface supports continuous reading of multiple full frames. The specific number of cached full frames and the required cache depth can be defined by the application scenario.

[0075] It is understood that the apparatus in this embodiment corresponds to the multiplexing framing method in the above embodiments, and the options in the above embodiments are also applicable to this embodiment, so they will not be described again here.

[0076] To meet the diverse functional requirements of complex engineering scenarios, this disclosure provides a customized, reusable design for frame assembly and caching functions. For external modules, this disclosure includes interfaces for depth and bit width configuration, verification method configuration, and read cache thresholds, allowing for customization of cache depth and bit width, verification calculation methods, and read cache thresholds according to business needs. This disclosure also includes frame header input interfaces, frame data input interfaces, and frame tail input interfaces, enabling external modules to customize frame assembly parameters and content as required. Then, the frame assembly logic module 120 assembles the frames and stores them in the cache space 150. The cache management module 110 manages the cache according to the depth and bit width. The verification calculation logic module 130 performs verification and stores the verification results. The write cache logic module 140 stores the frame header, frame data, frame tail, verification value, and frame identifier. This disclosure also includes read-ready interfaces and a read interface, configured to output read-ready signals and read frames. Therefore, this disclosure effectively solves the problems of high difficulty, long development cycle, and high cost in the design and development of frame caching in complex application scenarios.

[0077] This disclosure also provides a terminal device, exemplary of which includes a processor and a memory, wherein the memory stores a computer program, and the processor executes the computer program to enable the terminal device to perform the functions of the various modules in the above-described multiplexing framing method or multiplexing framing apparatus.

[0078] The processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including at least one of a Central Processing Unit (CPU), Graphics Processing Unit (GPU), Network Processor (NP), Digital Signal Processor (DSP), Application-Specific Integrated Circuit (ASIC), Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor or any conventional processor, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure.

[0079] The memory can be, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), and Electrically Erasable Programmable Read-Only Memory (EEPROM). The memory is configured to store computer programs, and the processor can execute these programs upon receiving execution instructions.

[0080] This disclosure also provides a readable storage medium configured to store computer programs used in the aforementioned terminal devices.

[0081] In the several embodiments provided in this disclosure, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that, as an alternative implementation, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0082] In addition, the functional modules or units in the various embodiments of this disclosure can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0083] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0084] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Industrial applicability

[0085] This disclosure provides a method, apparatus, and terminal device for reusing frames, which can effectively solve the problems of high difficulty, long development cycle, and high cost in the design and development of frame buffers in existing complex application scenarios.

Claims

1. A multiplexing framing method, characterized in that, include: The interface for configuring the depth and bit width of the cache space according to requirements is used to receive the depth and bit width of the cache space according to requirements, and the interface for configuring the verification method is used to receive the verification calculation method according to requirements. The frame header information, frame data information, and frame tail information are received through the corresponding input interfaces of the frame header, frame data, and frame tail, and a frame identifier is added. Then, the frame header information, frame data information, frame tail information, and frame identifier are stored in the cache space respectively. Frames are assembled based on the frame header information, frame data information, frame tail information, and frame identifier. During frame assembly, the check value of the current frame is calculated according to the check calculation method. The check value is used to assemble the current frame. Store the current frame, after it has been assembled, into the storage space.

2. The multiplexing and framing method according to claim 1, characterized in that, The method further includes reading and outputting a frame from the cache space according to the frame identifier through a read interface; the frame includes frame header information, frame data information, checksum, frame tail information, and frame identifier.

3. The multiplexing and framing method according to claim 2, characterized in that, When storing the frame header information, frame data information, frame tail information, and frame identifier into the cache space, the method further includes: Record the total length of the input frames; The method further includes: receiving a configured read buffer threshold, and determining, based on the read buffer threshold and the total length of the input frames, to output a read signal through the read-ready interface; the read signal is used by an external module to determine whether to read a frame. Driven by the external module, the frame is read from the buffer space according to the frame identifier through the read interface and output to the external module.

4. The multiplexing and framing method according to claim 3, characterized in that, The frame identifier includes a frame header identifier and a frame tail identifier; the frame tail information includes an initial frame tail marker, and the frame tail identifier is determined based on the initial frame tail marker; when outputting the frame tail to the external module, a frame tail indication signal is output.

5. The multiplexing and framing method according to any one of claims 1-4, characterized in that, The verification calculation method includes at least one of the following: cumulative sum, cumulative difference, parity check, and bitwise XOR.

6. A multiplexing and framing device, characterized in that, The device includes: a framing logic module, a verification calculation logic module, a write cache logic module, and a cache management module; the framing logic module is provided with an input interface. The cache management module includes a depth and bit width configuration interface; the cache management module is configured to receive the configured depth and bit width through the depth and bit width configuration interface, and configure the size of the cache space and the bit width of each frame according to the depth and bit width. The framing logic module is configured to receive frame header information, frame data information, and frame tail information through the corresponding input interfaces of the frame header, frame data, and frame tail, respectively, add a frame identifier, and then store the frame header information, frame data information, frame tail information, and frame identifier into the cache space respectively. The verification calculation logic module includes a verification method configuration interface; the verification calculation logic module is configured to receive a verification calculation method configured through the verification method configuration interface, calculate the verification value of the current frame according to the verification calculation method when the framing logic module performs framing, and configure the verification value to be assembled into the current frame; The write cache logic module is configured to store the current frame after it has been assembled into a storage space; the current frame after it has been assembled includes the frame header information, frame data information, frame tail information, check value and frame identifier.

7. The multiplexing and framing apparatus according to claim 6, characterized in that, The device further includes a read cache logic module; the read cache logic module includes a read interface; The read cache logic module is configured to read and output a frame from the cache space according to the frame identifier through the read interface; the frame includes frame header information, frame data information, check value, frame tail information and frame identifier.

8. The multiplexing and framing apparatus according to claim 7, characterized in that, The write cache logic module is also configured to record the total length of the input frames; the read cache logic module further includes a read-ready interface and a read cache threshold configuration interface. The read buffer logic module is specifically configured to receive a configured read buffer threshold, and determine the output of a read signal through the read-ready interface based on the read buffer threshold and the total length of the input frames; the read signal is configured to allow external modules to determine whether to read frames. The read cache logic module is configured to read frames from the cache space according to the frame identifier through the read interface and output them to the external module under the drive of the read frame task of the external module.

9. The multiplexing and framing apparatus according to claim 8, characterized in that, The frame identifier includes a frame header identifier and a frame tail identifier; the frame tail information includes an initial frame tail marker, and the frame tail identifier is determined based on the initial frame tail marker; the read buffer logic module outputs a frame tail indicator signal when outputting the frame tail.

10. The multiplexing and framing apparatus according to any one of claims 6-9, characterized in that, The verification calculation logic module includes at least one of the following verification calculation methods: cumulative sum, cumulative difference, parity check, and bitwise XOR.

11. The multiplexing and framing apparatus according to any one of claims 6-10, characterized in that, The input interface includes a frame header input interface, a frame data input interface, and a frame tail input interface.

12. A terminal device, characterized in that, The terminal device includes a processor and a memory, the memory storing a computer program, and the processor being configured to execute the computer program to implement the multiplexing framing method according to any one of claims 1-4.

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