Photon stream detector having high image acquisition performance and CT device

Abstract

A photon stream detector having high image acquisition performance and a CT device. The photon stream detector comprises a scintillator (100), a photon stream sensor (200), a main control board (400), and a substrate (300), wherein the scintillator (100) is coupled to the photon stream sensor (200), and an output end of the photon stream sensor (200) is connected to the main control board (400). The scintillator (100) is configured for converting an incident X-ray into visible light. The photon stream sensor (200) is configured for converting the visible light into an electrical signal, then amplifying, shaping, integrating and counting same to generate an integration signal and a counting signal, and outputting image data after data conversion and processing. The main control board (400) is configured for providing a clock signal, a working power supply, and data analysis and transmission. When the photon stream detector performs detection, the photon stream sensor (200) simultaneously generates an integration signal and a counting signal, forms image data after data conversion and processing, and uploads the image data to an image acquisition device, thereby achieving good image acquisition performance in the entire dose range.

Description

A photon flow detector and CT device with high image acquisition performance Technical Field

[0001] This invention relates to a photon flow detector with high image acquisition performance, and also to a CT device including the photon flow detector, belonging to the field of medical device technology. Background Technology

[0002] The core component of a CT scanner is the CT detector, and its image acquisition performance plays a decisive role in the quality of CT imaging. Currently, two types of CT detectors are commonly used: energy integration detectors and photon counting detectors. Energy integration detectors typically consist of a scintillation crystal-coupled photodiode array, along with an external analog front-end (AFE) and analog-to-digital converter (ADC) to form the detector system. Photon counting detectors, on the other hand, typically use semiconductor materials directly integrated with an external analog front-end and counter to form the detector system.

[0003] Regarding the performance of the detector output signal, the response curves of the energy integration detector and the photon counting detector under the same operating conditions but different photon illuminances are shown in Figure 1. The coordinate axes in Figure 1 are logarithmic, with the horizontal axis representing the dose rate expressed in photon flux illuminance and the vertical axis representing the pixel signal quantity output by the detector. As can be seen from Figure 1, the energy integration detector, due to the influence of dark field noise and leakage current noise, exhibits a significant performance degradation when the dose rate is less than 10... 5 photons / s / mm 2 At low doses, the integrated signal is submerged in electronic noise, failing to obtain accurate X-ray photon information. However, as the X-ray photon dose rate increases, the detector's energy integrated signal increases accordingly, exhibiting a good linear relationship and achieving an excellent signal-to-noise ratio, resulting in good CT imaging quality. Photon counting detectors, due to their immunity to dark field noise and leakage current noise, exhibit excellent signal quality at low and medium doses. However, when the dose rate increases to 10... 8 photons / s / mm 2 At this point, the photon counting detector begins to enter the nonlinear region. As the photon flux illuminance further increases, the photon counting detector reaches saturation, resulting in pulse stacking and an inability to obtain accurate X-ray photon information. Therefore, improving the image acquisition performance of CT detectors to meet the high requirements of CT imaging across the entire dose range remains a very important technical research topic in this field. Summary of the Invention

[0004] The primary technical problem to be solved by this invention is to provide a photon flow detector with high image acquisition performance.

[0005] Another technical problem to be solved by the present invention is to provide a CT device including the photon flow detector.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] According to a first aspect of the present invention, a photon flow detector with high image acquisition performance is provided, comprising a scintillator, a photon flow sensor, a main control board, and a substrate; wherein,

[0008] The scintillator is coupled to the photon flow sensor, the output terminal of the photon flow sensor is connected to the main control board, and the photon flow sensor is mounted on the substrate;

[0009] The scintillator is used to convert incident X-ray photons into visible light photons;

[0010] The photon flow sensor is used to convert visible light into electrical signals, which are then amplified, shaped, integrated, and counted to generate integrated and counted signals. After data conversion and processing, image data is output.

[0011] The main control board is used to provide the photon flow sensor with a working clock, a working power supply, and to parse and transmit input and output data.

[0012] When the photon flow detector performs detection, the photon flow sensor simultaneously generates the integral signal and the counting signal. After data conversion and processing, the image data is formed and uploaded to the image acquisition device, thereby achieving high image acquisition performance throughout the entire dose range.

[0013] Preferably, the photon flow sensor includes a photodiode array, a sampling and counting clock unit, a row transfer register unit, an ADC array, a serial link unit, and an auxiliary circuit unit; wherein...

[0014] The sampling counting clock unit, the row transfer register unit, the ADC array, and the serial link unit are respectively coupled to the photodiode array, and the output terminal of the ADC array is connected to the serial link unit;

[0015] The photodiode array is composed of a matrix of photodiode pixel units, which is used to convert visible light into electrical signals and generate the integrated signal and the count signal after amplification, shaping, integration and counting processing.

[0016] The sampling and counting clock unit is used to provide a working clock signal for the photodiode array;

[0017] The row transfer register unit is used to enable the output of the integral signal generated by each row of the photodiode pixel unit in the photodiode array;

[0018] The ADC array is used to convert the integrated signal output by the photodiode array into a digital signal;

[0019] The serial link unit is used to convert parallel data signals into serial data signals and output them to the outside on a serial link.

[0020] The auxiliary circuit unit is used to provide operating power, clock signals, and operating parameter settings for each functional unit.

[0021] Preferably, the photodiode pixel unit includes a photodiode, a pre-amplification and shaping circuit, an integrating circuit, a first comparator, a counter, a serializer, a feedback capacitor, and a reset switch; wherein the first comparator and the counter constitute a counting circuit;

[0022] The negative terminal of the photodiode is connected to the input terminal of the pre-amplification and shaping circuit. The output terminal of the pre-amplification and shaping circuit is connected to the input terminal of the integrating circuit and the second input terminal of the first comparator. A feedback capacitor and a reset switch are connected in parallel between the input and output terminals of the integrating circuit. The output terminal of the integrating circuit is the first output terminal of the photodiode pixel unit. The first input terminal of the first comparator is connected to the first threshold voltage signal terminal. The output terminal of the first comparator is connected to the input terminal of the counter. The output terminal of the counter is connected to the input terminal of the serializer. The output terminal of the serializer is the second output terminal of the photodiode pixel unit.

[0023] Preferably, the photodiode pixel unit includes a photodiode, a pre-amplification and shaping circuit, an integrating circuit, a first comparator, a second comparator, a counter, a serializer, a feedback capacitor, and a reset switch; wherein the first comparator and the counter constitute a counting circuit;

[0024] The output of the integrating circuit is the first output of the photodiode pixel unit, and the output of the serializer is the second output of the photodiode pixel unit.

[0025] The first input terminal of the second comparator is connected to the second threshold voltage signal terminal, the second input terminal is connected to the third threshold voltage signal terminal, the third input terminal is connected to the output terminal of the integrator circuit, and the output terminal of the second comparator is connected to the input terminal of the serializer.

[0026] Preferably, the counting circuit further includes two or more comparators, each comparator's first input terminal is connected to a first threshold voltage signal terminal, each comparator's second input terminal is connected to the output terminal of the pre-amplification and shaping circuit, and each comparator's output terminal is connected to the input terminal of the counter, so as to realize multi-level distinguishable counting.

[0027] Preferably, the first output terminal of the photodiode pixel unit is connected to the ADC bus through a control switch, and the photodiode pixel units in the same column of the photodiode array share one ADC bus and are connected to the ADC module of the corresponding column in the ADC array through the ADC bus.

[0028] The second output terminal of the photodiode pixel unit is connected to a serial link. The photodiode pixel units in the same column of the photodiode array share a serial link and are connected to the horizontal serializer corresponding to that column in the serial link unit through the serial link.

[0029] Preferably, for the photodiode array composed of (m+1)*(n+1) photodiode pixel units, where m and n are both positive integers; the serial link unit includes n+1 serial links and n+1 serializers; wherein the n+1 serial links are respectively connected to the first input terminals of the n+1 serializers, and the output terminals of the n+1 ADC modules in the ADC array are respectively connected to the second input terminals of the n+1 serializers; the output terminals of the n+1 serializers are cascaded sequentially to form a horizontal serializer link.

[0030] Preferably, the photon flow sensor includes a photodiode array, a sampling and counting clock unit, a row transfer register unit, an ADC array, a serial link unit, and an auxiliary circuit unit; wherein...

[0031] The sampling counting clock unit, the row transfer register unit, and the ADC array are respectively coupled to the photodiode array, and the output terminal of the ADC array is connected to the serial link unit;

[0032] The photodiode array is composed of a matrix of photodiode pixel units, which is used to convert visible light into electrical signals and generate the integrated signal and the count signal after amplification, shaping, integration and counting processing.

[0033] The sampling and counting clock unit is used to provide a working clock signal for the photodiode array;

[0034] The row transfer register unit is used to enable the output of the integral signal and the counting signal generated by each row of the photodiode pixel unit in the photodiode array;

[0035] The ADC array is used to convert the integral signal and the counting signal output by the photodiode array into digital signals;

[0036] The serial link unit is used to convert parallel data signals into serial data signals and output them to the outside on a serial link.

[0037] The auxiliary circuit unit is used to provide operating power, clock signals, and operating parameter settings for each functional unit.

[0038] Preferably, the photodiode pixel unit includes a photodiode, a pre-amplification and shaping circuit, an integrating circuit, a first comparator, an analog counter, a feedback capacitor, and a reset switch; wherein the first comparator and the analog counter constitute a counting circuit;

[0039] The negative terminal of the photodiode is connected to the input terminal of the pre-amplification and shaping circuit. The output terminal of the pre-amplification and shaping circuit is connected to the input terminal of the integrating circuit and the second input terminal of the first comparator. A feedback capacitor and a reset switch are connected in parallel between the input and output terminals of the integrating circuit. The output terminal of the integrating circuit is the first output terminal of the photodiode pixel unit. The first input terminal of the first comparator is connected to the first threshold voltage signal terminal. The output terminal of the first comparator is connected to the input terminal of the analog counter. The output terminal of the analog counter is the second output terminal of the photodiode pixel unit.

[0040] Preferably, the first output terminal and the second output terminal of the photodiode pixel unit are connected to the ADC bus via a first control switch and a second control switch, respectively.

[0041] The photodiode pixel units in the same column of the photodiode array share a single ADC bus and are connected to the ADC module of the corresponding column in the ADC array through this ADC bus.

[0042] The output of each column of ADC modules in the ADC array is connected to the horizontal serializer corresponding to that column in the serial link unit.

[0043] Preferably, the photon flow image data P generated by the data collected by the photon flow detector satisfies the following formula:

[0044] Among them, P c P represents the photon count data for a photodiode pixel unit. i P represents the energy integral data of a photodiode pixel unit. i =a*P c +b, where a and b are fitting coefficients; P c-nl Data for the entry point of the nonlinear region of photon counting in the response curve; P lsnr The integral data is 350 times the standard deviation of the dark field.

[0045] According to a second aspect of the present invention, a CT device is provided, including the aforementioned photon flow detector with high image acquisition performance.

[0046] Compared with existing technologies, the photon flow detector with high image acquisition performance provided by this invention achieves excellent image acquisition performance across the entire dose range by employing a photon flow sensor that simultaneously integrates energy and counts photons. It also boasts higher signal detection and resolution, and a wider dynamic range. This solves the problem of insufficient signal-to-noise ratio in energy-integrating detectors at low doses, and the signal nonlinearity caused by insufficient count rate in photon-counting detectors at high doses. Therefore, the photon flow detector provided by this invention offers advantages such as ingenious and reasonable structural design, low design cost, large dynamic range, and high image acquisition performance. Attached Figure Description

[0047] Figure 1 shows the response curves of the energy integration detector and the photon counting detector under different photon flux illuminance in the prior art.

[0048] Figure 2 is a structural block diagram of a photon flow detector with high image acquisition performance provided by the present invention;

[0049] Figure 3 is a schematic diagram of the photon flow sensor in the first embodiment of the present invention;

[0050] Figure 4 is a circuit diagram of the first technical solution of the photodiode pixel unit in the first embodiment of the present invention;

[0051] Figure 5 is a circuit diagram of the second technical solution of the photodiode pixel unit in the first embodiment of the present invention;

[0052] Figure 6 is a circuit diagram of the third technical solution of the photodiode pixel unit in the first embodiment of the present invention;

[0053] Figure 7 is a circuit schematic diagram of the serial link unit in the first embodiment of the present invention;

[0054] Figure 8 is a schematic diagram of the main control board in the first embodiment of the present invention;

[0055] Figure 9 shows the response curves of the photon flow detector provided by the present invention under different photon flow illuminance.

[0056] Figure 10 is a schematic diagram of the photon flow sensor in the second embodiment of the present invention;

[0057] Figure 11 is a circuit diagram of the photodiode pixel unit in the second embodiment of the present invention;

[0058] Figure 12 is a circuit diagram of the serial link unit in the second embodiment of the present invention. Detailed Implementation

[0059] The technical content of the present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0060] As shown in Figure 2, the photon flow detector with high image acquisition performance provided by the present invention includes a scintillator 100, a photon flow sensor 200, a main control board 400, and a substrate 300. The scintillator 100 is coupled to the photon flow sensor 200, the output terminal of the photon flow sensor 200 is connected to the main control board 400, and the photon flow sensor 200 is mounted on the substrate 300.

[0061] The scintillator 100 is used to convert incident X-ray photons into visible light photons. The scintillator can be a mainstream crystal such as GOS, CsI, or LYSO, and pixelating it to correspond one-to-one with the photodiode (PD) array in the photon flow sensor 200 is the optimal choice. Alternatively, the scintillator can be a micro-columnar CsI crystal, where the diameter of the columnar crystal is much smaller than the size of the PD pixel structure, and pixelation may not be required. The scintillator is coupled to the photon flow sensor using optical adhesive.

[0062] The photon flow sensor 200 converts visible light into electrical signals, which are then amplified, shaped, integrated, and counted to generate integrated and counted signals. After data conversion and processing, image data is output. The photon flow sensor 200 includes a photodiode array, a sampling and counting clock unit, a row transfer register unit, an ADC array, a serial link unit, and auxiliary circuit units. Each photodiode pixel unit in the photodiode array has energy integration and photon counting functions. The photon flow sensor is fabricated as a chip using CMOS integrated circuit technology and mounted on a substrate 300.

[0063] The main control board 400 provides the photon flow sensor 200 with a working clock, power supply, and handles the parsing and transmission of input and output data. Specifically, the image data output by the photon flow sensor is parsed and uploaded to an image acquisition device, such as an image acquisition card, to a host computer or other data processing and imaging equipment.

[0064] The substrate 300 serves as the carrier for the photon flow sensor chip, and the photon flow detector is fixed to the CT equipment via the substrate.

[0065] When the photon flow detector performs detection, the photon flow sensor simultaneously generates an integral signal and a counting signal. After data conversion and processing, image data is formed and uploaded to the image acquisition device, ultimately forming a high-quality CT image. The photon flow detector achieves high image acquisition performance across the entire dose range.

[0066] In the first embodiment of the present invention, as shown in FIG3, the photon flow sensor 200 includes a photodiode array, a sample and counting clock unit, a row shift register unit, an ADC array, a serial link unit, and an auxiliary circuit unit (not shown in FIG3). The sample and counting clock unit, the row shift register unit, the ADC array, and the serial link unit are respectively coupled to the photodiode array, and the output terminal of the ADC array is connected to the serial link unit.

[0067] A photodiode array is an m*n matrix (where m and n are both positive integers, such as 256*288) composed of photodiode pixel units. It is used to convert visible light into electrical signals, which are then amplified, shaped, integrated, and counted to generate integrated and counted signals. Each photodiode pixel unit includes a photodiode, a pre-amplification and shaping circuit, an integration circuit, and a counting circuit.

[0068] The sampling and counting clock unit is used to provide the working clock signal for the photodiode array, enabling the integrator circuit in each photodiode pixel unit to perform operations such as reset, integration, and hold, and the counting circuit to perform operations such as clearing, counting, and hold.

[0069] The row transfer register unit is used to enable the output of the integral signal generated by each row of photodiode pixel units in the photodiode array. At any given time, only the integral signal of a certain row of photodiode pixel units is enabled for output. Typically, the enable control of each row of photodiode pixel units in the photodiode array can be performed sequentially from top to bottom or bottom to top, thereby obtaining vertically mirrored image data.

[0070] An ADC array is used to convert the integrated signal output from a photodiode array into a digital signal. ADC arrays have multiple resolutions, such as at least 19 bits, and the number of bits can be specifically designed according to system requirements. It should be noted that each column of photodiode pixels in the photodiode array shares one ADC module. Through the enable control of the row transfer register unit, the ADC module sequentially converts the integrated signal of each row of photodiode pixels in that column into a digital signal, and then outputs it to the serial link unit.

[0071] The serial link unit is used to convert parallel data signals into serial data signals and output the serial data signals of multiple nodes on a single serial link.

[0072] The auxiliary circuit unit is used to provide operating power, clock signals, and operating parameter settings for each functional unit.

[0073] In the first embodiment of the present invention, three technical solutions are provided for the circuit structure of the photodiode pixel unit in the photodiode array. The circuit structure and working principle of each technical solution are described below.

[0074] The circuit structure of the photodiode pixel unit in the first technical solution is shown in Figure 4. The photodiode pixel unit includes a photodiode (PD), a pre-amplifier and shaper circuit, an integrator circuit, a first comparator (Comparator1), a counter, a serializer (Serdes), a feedback capacitor C, and a reset switch (Reset). The negative terminal of the photodiode is connected to the input terminal of the pre-amplifier and shaper circuit. The output terminal of the pre-amplifier and shaper circuit is connected to the input terminal of the integrator circuit and the second input terminal of the first comparator. The feedback capacitor C and the reset switch (Reset) are connected in parallel between the input and output terminals of the integrator circuit. The output terminal of the integrator circuit is the first output terminal of the photodiode pixel unit. The first input terminal of the first comparator is connected to the first threshold voltage Vth1 signal terminal. The output terminal of the first comparator is connected to the input terminal of the counter. The output terminal of the counter is connected to the input terminal of the serializer. The output terminal of the serializer is the second output terminal of the photodiode pixel unit. The first comparator and the counter form a counting circuit.

[0075] When the scintillator generates visible light output, the photodiode converts the visible light signal into an electrical signal and outputs it to the pre-amplification and shaping circuit. The pre-amplification and shaping circuit amplifies and shapes this electrical signal and outputs a pulse signal, which is then sent to the integrator circuit and the counting circuit. The integrator circuit integrates the input pulse signal and outputs a corresponding analog voltage signal, called the integrated signal. This integrated signal (output from the first output terminal of the photodiode pixel unit) is connected to the ADC bus via the control switch Mux. In the counting circuit, the first comparator compares the input pulse signal with a set first threshold voltage V. th1 In comparison, the filtration amplitude is lower than V th1 After the pulse is generated, a digital pulse is output to the counter. The counter counts the digital pulses and outputs a counting signal. The serializer converts the counting signal into a serial data signal (output from the second output terminal of the photodiode pixel unit) and then connects it to the serial link (Serdes Chain).

[0076] It should be noted that the control switch Mux, which controls the output of the integral signal to the ADC bus, is uniformly controlled by the row transfer register unit. Photodiode pixel units in the same column of the photodiode array share a single ADC bus and are connected to the corresponding ADC module in the ADC array via this bus. The counting signal output by each photodiode pixel unit is connected to a serial link. Photodiode pixel units in the same column of the photodiode array share a single serial link and are connected to the corresponding horizontal serializer in the serial link unit via this serial link.

[0077] The circuit structure of the photodiode pixel unit in the second technical solution is shown in Figure 5. The photodiode pixel unit includes a photodiode (PD), a pre-amplifier and shaper circuit, an integrator circuit, a first comparator (Comparator1), a second comparator (Comparator2), a counter, a serializer (Serdes), a feedback capacitor C, and a reset switch (Reset). The output of the integrator circuit is the first output of the photodiode pixel unit, and the output of the serializer is the second output of the photodiode pixel unit. The first input of the second comparator is connected to the second threshold voltage V. th21 The signal terminal and the second input terminal are connected to the third threshold voltage V. th22 The signal terminal and the third input terminal are connected to the output terminal of the integrator circuit, and the output terminal of the second comparator is connected to the input terminal of the serializer. The first comparator and the counter together form a counting circuit.

[0078] Based on the first technical solution, the second technical solution adds a second comparator after the integrating circuit in the circuit structure of the photodiode pixel unit, simultaneously comparing the integrated signal output from the integrating circuit with the second threshold voltage V. th21 and the third threshold voltage V th22 In comparison, a corresponding dose signal is output to the serializer, which converts the dose signal into a serial data signal and then connects it to the serial link (Serdes Chain). The second threshold voltage V... th21 <Third threshold voltage V th22 Second threshold voltage V th21 and the third threshold voltage V th22 The setting is related to the dose rate (i.e., X-ray photon flux irradiance) and the performance change point of the detector in the response curve.

[0079] When the integrated signal voltage output by the integrating circuit is less than the second threshold voltage V th21 When the dose rate is low, the counting signal output by the counting circuit is more reliable; when the voltage of the integrated signal output by the integrating circuit is greater than or equal to the second threshold voltage V... th21And less than or equal to the third threshold voltage V th22 When the dose rate is moderate, both the integral signal and the counting signal are relatively reliable; when the voltage of the integral signal output by the integrating circuit is greater than the third threshold voltage V... th22 When the dose rate is high, the counting signal output by the counting circuit is unreliable, while the integral signal output by the integrating circuit is more reliable. Therefore, the dose signal output by the photodiode pixel unit can provide a direct basis for subsequent image data processing.

[0080] Compared with the second technical solution, the first technical solution of the photodiode pixel unit circuit structure can improve the fill rate of PD pixels because it does not have a second comparator and its corresponding circuit. The subsequent image data processing is determined by the acquisition software based on the integrator acquisition result to determine the reliability of the counter acquisition result and the corresponding image data processing.

[0081] The circuit structure of the photodiode pixel unit in the third technical solution is shown in Figure 6. The photodiode pixel unit includes a photodiode (PD), a pre-amplifier and shaper circuit, an integrator circuit, an eleventh comparator (Comparator11), a twelfth comparator (Comparator12), a counter, a serializer (Serdes), a feedback capacitor C, and a reset switch (Reset). Compared to the first technical solution, the counting circuit includes two or more comparators, and the first input terminal of each comparator is connected to a first threshold voltage signal terminal (V). th11 or V th12 Each comparator's second input is connected to the output of the pre-amplifier and shaping circuit, and each comparator's output is connected to the input of the counter.

[0082] In the counting circuit shown in Figure 6, the eleventh comparator and the twelfth comparator respectively compare the input pulse signal with two set first threshold voltages V. th11 V th12 After comparison, digital pulses are output to the counters respectively. The counters count the digital pulses and output two counting signals to the serializer. The third technical solution, as an optional approach, adds more comparators to the counting circuit, thereby enabling counting at more energy levels and obtaining counting signals for multiple energy levels.

[0083] It should be noted that the circuit structure of the photodiode pixel unit in the second technical solution can also be achieved by adding two or more comparators to the counting circuit to realize more energy level differentiation and counting.

[0084] In the first embodiment of the present invention, the circuit structure of the serial link unit is shown in Figure 7. In Figure 7, Pixel(0,0) to Pixel(m,n) represent (m+1)*(n+1) photodiode pixel units in the photodiode array. The photodiode pixel units in the same column share a serial link and an ADC bus. The ADC array includes n+1 ADC modules (ADC0 to ADCn), and the input terminals of the n+1 ADC modules are respectively connected to the n+1 ADC buses.

[0085] The serial link unit includes n+1 serial links and n+1 serializers (Serdes0 to Serdesn); wherein, the n+1 serial links are respectively connected to the first input terminal of the n+1 serializers, and the output terminals of the n+1 ADC modules in the ADC array are respectively connected to the second input terminals of the n+1 serializers. The output terminals of the n+1 serializers are cascaded sequentially to form a horizontal serializer link.

[0086] The serial link unit is arranged according to the column distribution of photodiode pixel units. The counting signal data of the same column is transmitted down to the corresponding horizontal serializer via a shared serial link. Simultaneously, the integration signal data of the same column is transmitted down to the corresponding ADC module via a shared ADC bus for analog-to-digital conversion, and then also transmitted to the corresponding horizontal serializer. The counting and integration signal data are then output as image data (to the main control board 400) through the horizontal serializer link. This serial link unit design effectively saves on the number of data lines, simplifies interconnection, and improves the reliability of data transmission.

[0087] In the first embodiment of the present invention, the structure of the main control board 400 is shown in Figure 8. The main control board includes a main controller module, a clock module, a power supply module, and an input / output module. One end of the main controller module, as well as the outputs of the clock module and the power supply module, are connected to the photon flow sensor. The other end of the main controller module is connected to the input / output module.

[0088] The main controller module is used for parsing and transmitting image data and operating parameters. Specifically, it parses the image data output by the photon flow sensor and uploads it to the image acquisition device through the input / output module; it also parses the operating parameters sent by the image acquisition device through the input / output module and transmits them to the photon flow sensor.

[0089] The clock module generates and provides the operating clock for the photon flow sensor, main controller module, and input / output modules after clock modulation of the base clock. The photon flow sensor clock includes the SerDes clock, ADC clock, and photodiode pixel unit operating clock.

[0090] The power module is used to generate and provide the operating power for the photon flow sensor, main controller module and input / output module after secondary conversion of the power supply.

[0091] The input / output module is used to transmit uploaded image data and sent operating parameters via network protocols. Image data is output from the photon flow sensor and uploaded to the image acquisition device through the input / output module, while operating parameters are sent from the image acquisition device and transmitted back to the photon flow sensor through the input / output module. The input / output module also has a detector synchronization interface to enable time synchronization between multiple detectors. The image acquisition device typically includes an image acquisition card and a host computer.

[0092] The structure and working principle of the photon flow detector with high image acquisition performance provided in the first embodiment of the present invention have been described in detail above. The data processing after image data acquisition in this embodiment will be described in detail below. The photon flow detector can simultaneously acquire integrated signal data (i.e., energy integrated data) and counting signal data (i.e., photon count data) in a single data acquisition. During data use, the two types of data need to be normalized to the same measurement scale to generate photon flow image data, thereby obtaining high-performance data information across the entire measurement range. Assume the photon count data of a pixel unit is P. c The energy integral data is P i The final generated photon stream image data is P.

[0093] First, within a dose range where both energy integral data and photon count data exhibit linear distributions (between low and medium doses), different dose rates were adjusted to obtain a set of energy integral data and photon count data. The relationship between the two types of data was then established through data fitting as follows: P i =a*P c +b (1)

[0094] Where a and b are both fitting coefficients.

[0095] Secondly, by adjusting different dose rates across the entire dose range, a set of energy integral data and photon count data were obtained, and their respective response curves were established. Based on the response curves, the entry point P of the photon counting nonlinear region was found. c-nl And the point P where the integral data is 350 times the standard deviation of the dark field (i.e., the location with a dynamic range of 51 dB). lsnr The final generated photon stream image data P satisfies the following formula:

[0096] Among them, P c-nl Data for the entry point of the nonlinear region of photon counting in the response curve; P lsnrThe integral data is 350 times the standard deviation of the dark field.

[0097] Furthermore, when the photodiode pixel unit in the photodiode array adopts the second technical solution, the photon flow sensor can generate energy integration data, photon count data, and dose data. The data P at the entry point of the photon counting nonlinear region in the above formula (2) is... c-nl And the integral data P, which is 350 times the standard deviation of the dark field. lsnr It can be obtained directly from the dose data through data processing, without the need to establish individual response curves. For example, in the low, medium, and high regions of the set dose range, the dose data are 0, 1, and 2, respectively. These data values ​​correspond to (P) in formula (2). i <P lsnr ), (P c ≤P c-nl ), (P c >P c-nl The three conditions.

[0098] Through the image data processing described above, the response curve of the photon flow detector provided by this invention, as shown in Figure 9, exhibits a linear distribution across the entire dose range, from low to high dose rates. This ensures excellent image acquisition performance throughout the entire dose range, thereby improving CT imaging quality. Therefore, the photon flow detector provided by this invention improves the signal detection limit, achieving higher signal detection and resolution, while also possessing a larger dynamic range.

[0099] In the second embodiment of the present invention, as shown in FIG10, the photon flow sensor 200 still includes a photodiode (PD) array, a sample and counting clock unit, a row shift register unit, an ADC array, a serial link unit, and an auxiliary circuit unit (not shown in FIG10). The sample and counting clock unit, the row shift register unit, and the ADC array are respectively coupled to the photodiode array, and the output of the ADC array is connected to the serial link unit.

[0100] A photodiode array is a matrix composed of photodiode pixel units, used to convert visible light into electrical signals and generate integrated and counted signals after amplification, shaping, integration and counting.

[0101] The sampling and counting clock unit is used to provide the operating clock signal for the photodiode array;

[0102] The row transfer register unit is used to enable the output of the integral signal and the counting signal generated by each row of photodiode pixel units in the photodiode array;

[0103] An ADC array is used to convert the integration and counting signals output by a photodiode array into digital signals.

[0104] The serial link unit is used to convert parallel data signals into serial data signals and output them to the outside on a serial link;

[0105] The auxiliary circuit unit is used to provide operating power, clock signals, and operating parameter settings for each functional unit.

[0106] The second embodiment differs from the first embodiment in that the counting signal output by the photodiode array is an analog signal. Therefore, the photodiode array does not need to be directly coupled to the serial link unit. Furthermore, the row transfer register needs to enable control of the photodiode array output signal, which includes both the integration and counting signals. Similarly, the ADC array needs to convert the photodiode array output signal, which also includes both the integration and counting signals. In addition, all other functional modules and operating principles are basically the same as or similar to those in the first embodiment.

[0107] In the second embodiment of the present invention, the circuit structure of the photodiode pixel unit in the photodiode array is shown in Figure 11. The photodiode pixel unit includes a photodiode (PD), a pre-amplifier and shaper circuit, an integrator circuit, a first comparator, an analog counter (pulse to voltage), a feedback capacitor C, and a reset switch. The negative terminal of the photodiode is connected to the input terminal of the pre-amplifier and shaper circuit. The output terminal of the pre-amplifier and shaper circuit is connected to the input terminal of the integrator circuit and the second input terminal of the first comparator. The feedback capacitor C and the reset switch Reset are connected in parallel between the input and output terminals of the integrator circuit. The output terminal of the integrator circuit is the first output terminal of the photodiode pixel unit. The first input terminal of the first comparator is connected to a first threshold voltage V. th1 At the signal terminal, the output terminal of the first comparator is connected to the input terminal of the analog counter, and the output terminal of the analog counter is the second output terminal of the photodiode pixel unit. The first comparator and the analog counter together form a counting circuit.

[0108] The first and second output terminals of the photodiode pixel unit are connected to the ADC bus via the first control switch Mux1 and the second control switch Mux2, respectively. The first and second control switches are uniformly controlled by the row transfer register unit. Photodiode pixel units in the same column of the photodiode array share a single ADC bus and are connected to the corresponding ADC module in the ADC array via this ADC bus. The output terminal of each column of the ADC module in the ADC array is connected to the corresponding horizontal serializer in the serial link unit.

[0109] Compared to the first technical solution of the photodiode pixel unit in the first embodiment, the counter in the counting circuit of this embodiment is implemented using a pulse-to-voltage circuit, that is, it realizes the function of an "analog counter". Therefore, in this embodiment, the integration signal and the counting signal (in analog form) output by the photodiode pixel unit can share the ADC bus.

[0110] It should be noted that the circuit structure of the photodiode pixel unit in the second embodiment can also adopt the three technical solutions provided in the first embodiment, only the counter in the counting circuit needs to be replaced with an analog counter.

[0111] Regarding the matching of the number of bits between the analog counter and the ADC conversion, if the analog counter is an equivalent 8-bit counter, then the ADC output corresponds to 256 steps. The number of bits of the ADC can be determined based on the relationship between the number of pulses of the analog counter and the output voltage (e.g., linear, exponential, etc.). For the 19-bit ADC in this embodiment, it has sufficient resolution to handle the signal resolution of an equivalent 8-bit analog counter.

[0112] Furthermore, in the prior art, there are many circuits that realize the function of a "simulation counter" to convert pulses into voltages, such as the common inverting S / H circuit, and the present invention does not limit the form of this circuit.

[0113] Since the integration and counting signals share the ADC bus, the photon flow sensor chip can be designed with row transfer register units in a configuration twice the number of physical rows of the photodiode array, effectively outputting the integration and counting signals alternately. Therefore, the structure of the serial link unit is also simplified accordingly, requiring only the output of the ADC data from each column on a horizontal serializer link.

[0114] In the second embodiment of the present invention, the circuit structure of the serial link unit is shown in Figure 12. The serial link unit includes n+1 serializers (Serdes0 to Serdesn); wherein, the output terminals of the n+1 ADC modules in the ADC array are respectively connected to the input terminals of the n+1 serializers, and the output terminals of the n+1 serializers are cascaded to form a horizontal serializer link.

[0115] In the photodiode array, the pixel units of the photodiodes are arranged in columns. The counting signal data and integration signal data of the same column are serially transmitted to the ADC module corresponding to that column through a shared ADC bus for analog-to-digital conversion. After conversion, the data is also transmitted to the horizontal serializer corresponding to that column. Then, the image data is output to the main control board 400 through the horizontal serializer link.

[0116] In the second embodiment, since the photodiode pixel unit does not have a digital signal output, there is no need for a serializer link, which reduces the area occupied by the CMOS integrated circuit chip and thus improves the fill rate of the PD pixel.

[0117] The structure and working principle of a photon stream detector with high image acquisition performance provided by the present invention have been described in detail above. In the implementation of the technical solutions of each embodiment, the parameter design and device selection of each technical link can be appropriately optimized and balanced to achieve a balance in terms of performance and cost. For example, assuming the light yield of the scintillator is ω... x The conversion efficiency is η x The conversion efficiency of PD is η v Then the number of electrons produced by an X-ray photon with energy E is n = E * ω. x *η x *η v When the number of electron noise electrons is less than n, the sensor can detect the X-ray photon with energy E. For example, photon flow detectors use scintillation crystals from traditional X-ray detectors instead of newer semiconductor detectors such as CZT, which can greatly reduce detector costs.

[0118] Based on the aforementioned photon flow detector with high image acquisition performance, this embodiment of the invention further provides a CT device. In addition to an X-ray generator, a mechanical motion device, and an image acquisition device, this CT device also includes multiple photon flow detectors with high image acquisition performance. These detectors detect X-ray photons and, after conversion processing, output image data, achieving good image acquisition performance across the entire dose range and obtaining high-quality CT images. The specific structure of this photon flow detector will not be described in detail here.

[0119] In summary, compared with existing technologies, the photon flow detector with high image acquisition performance provided by this invention, through the adoption of a photon flow sensor with both energy integration and photon counting functions, achieves excellent image acquisition performance across the entire usable dose range. Simultaneously, it boasts higher signal detection and resolution, and a wider dynamic range. It solves the problem of insufficient image signal-to-noise ratio in energy integration detectors at low doses, and the signal nonlinearity problem caused by insufficient count rate in photon counting detectors at high doses. Therefore, the photon flow detector provided by this invention has the advantages of ingenious and reasonable structural design, low design cost, large dynamic range, and high image acquisition performance.

[0120] It should be noted that the above embodiments are merely illustrative examples. The technical solutions of each embodiment can be combined, and all are within the protection scope of this invention.

[0121] It should be understood that the terms "upper," "lower," "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting the present invention.

[0122] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0123] The photon flow detector and CT device with high image acquisition performance provided by this invention have been described in detail above. Any obvious modifications made by those skilled in the art without departing from the essence of this invention will constitute an infringement of the patent rights of this invention and will incur corresponding legal liability.

Claims

1. A photon stream detector with high image acquisition performance, characterized in that... It includes a scintillator, a photon flow sensor, a main control board, and a substrate; among which, The scintillator is coupled to the photon flow sensor, the output terminal of the photon flow sensor is connected to the main control board, and the photon flow sensor is mounted on the substrate; The scintillator is used to convert incident X-ray photons into visible light photons; The photon flow sensor is used to convert visible light into electrical signals, which are then amplified, shaped, integrated, and counted to generate integrated and counted signals. After data conversion and processing, image data is output. The main control board is used to provide the photon flow sensor with a working clock, a working power supply, and to parse and transmit input and output data. When the photon flow detector performs detection, the photon flow sensor simultaneously generates the integral signal and the counting signal. After data conversion and processing, the image data is formed and uploaded to the image acquisition device, thereby achieving high image acquisition performance throughout the entire dose range.

2. The photon stream detector with high image acquisition performance as described in claim 1, characterized in that: The photon flow sensor includes a photodiode array, a sampling and counting clock unit, a row transfer register unit, an ADC array, a serial link unit, and an auxiliary circuit unit; wherein... The sampling counting clock unit, the row transfer register unit, the ADC array, and the serial link unit are respectively coupled to the photodiode array, and the output terminal of the ADC array is connected to the serial link unit; The photodiode array is composed of a matrix of photodiode pixel units, which is used to convert visible light into electrical signals and generate the integrated signal and the count signal after amplification, shaping, integration and counting processing. The sampling and counting clock unit is used to provide a working clock signal for the photodiode array; The row transfer register unit is used to enable the output of the integral signal generated by each row of the photodiode pixel unit in the photodiode array; The ADC array is used to convert the integrated signal output by the photodiode array into a digital signal; The serial link unit is used to convert parallel data signals into serial data signals and output them to the outside on a serial link. The auxiliary circuit unit is used to provide operating power, clock signals, and operating parameter settings for each functional unit.

3. The photon stream detector with high image acquisition performance as described in claim 2, characterized in that: The photodiode pixel unit includes a photodiode, a pre-amplification and shaping circuit, an integrating circuit, a first comparator, a counter, a serializer, a feedback capacitor, and a reset switch; wherein, the first comparator and the counter constitute a counting circuit; The negative terminal of the photodiode is connected to the input terminal of the pre-amplification and shaping circuit. The output terminal of the pre-amplification and shaping circuit is connected to the input terminal of the integrating circuit and the second input terminal of the first comparator. A feedback capacitor and a reset switch are connected in parallel between the input and output terminals of the integrating circuit. The output terminal of the integrating circuit is the first output terminal of the photodiode pixel unit. The first input terminal of the first comparator is connected to the first threshold voltage signal terminal. The output terminal of the first comparator is connected to the input terminal of the counter. The output terminal of the counter is connected to the input terminal of the serializer. The output terminal of the serializer is the second output terminal of the photodiode pixel unit.

4. The photon stream detector with high image acquisition performance as described in claim 2, characterized in that: The photodiode pixel unit includes a photodiode, a pre-amplification and shaping circuit, an integrating circuit, a first comparator, a second comparator, a counter, a serializer, a feedback capacitor, and a reset switch; wherein, the first comparator and the counter constitute a counting circuit; The output of the integrating circuit is the first output of the photodiode pixel unit, and the output of the serializer is the second output of the photodiode pixel unit. The first input terminal of the second comparator is connected to the second threshold voltage signal terminal, the second input terminal is connected to the third threshold voltage signal terminal, the third input terminal is connected to the output terminal of the integrator circuit, and the output terminal of the second comparator is connected to the input terminal of the serializer.

5. The photon stream detector with high image acquisition performance as described in claim 3 or 4, characterized in that: The counting circuit also includes two or more comparators. The first input terminal of each comparator is connected to a first threshold voltage signal terminal, the second input terminal of each comparator is connected to the output terminal of the pre-amplification and shaping circuit, and the output terminal of each comparator is connected to the input terminal of the counter to achieve multi-level distinguishing counting.

6. The photon stream detector with high image acquisition performance as described in claim 3 or 4, characterized in that: The first output terminal of the photodiode pixel unit is connected to the ADC bus through a control switch. The photodiode pixel units in the same column of the photodiode array share one ADC bus and are connected to the ADC module of the corresponding column in the ADC array through the ADC bus. The second output terminal of the photodiode pixel unit is connected to a serial link. The photodiode pixel units in the same column of the photodiode array share a serial link and are connected to the horizontal serializer corresponding to that column in the serial link unit through the serial link.

7. The photon stream detector with high image acquisition performance as described in claim 2, characterized in that: For the photodiode array composed of (m+1)*(n+1) photodiode pixel units, where m and n are both positive integers; the serial link unit includes n+1 serial links and n+1 serializers; wherein, the n+1 serial links are respectively connected to the first input terminals of the n+1 serializers, and the output terminals of the n+1 ADC modules in the ADC array are respectively connected to the second input terminals of the n+1 serializers; the output terminals of the n+1 serializers are cascaded to form a horizontal serializer link.

8. The photon stream detector with high image acquisition performance as described in claim 1, characterized in that: The photon flow sensor includes a photodiode array, a sampling and counting clock unit, a row transfer register unit, an ADC array, a serial link unit, and an auxiliary circuit unit; wherein... The sampling counting clock unit, the row transfer register unit, and the ADC array are respectively coupled to the photodiode array, and the output terminal of the ADC array is connected to the serial link unit; The photodiode array is composed of a matrix of photodiode pixel units, which is used to convert visible light into electrical signals and generate the integrated signal and the count signal after amplification, shaping, integration and counting processing. The sampling and counting clock unit is used to provide a working clock signal for the photodiode array; The row transfer register unit is used to enable the output of the integral signal and the counting signal generated by each row of the photodiode pixel unit in the photodiode array; The ADC array is used to convert the integral signal and the counting signal output by the photodiode array into digital signals; The serial link unit is used to convert parallel data signals into serial data signals and output them to the outside on a serial link. The auxiliary circuit unit is used to provide operating power, clock signals, and operating parameter settings for each functional unit.

9. The photon stream detector with high image acquisition performance as described in claim 8, characterized in that: The photodiode pixel unit includes a photodiode, a pre-amplification and shaping circuit, an integrating circuit, a first comparator, an analog counter, a feedback capacitor, and a reset switch; wherein, the first comparator and the analog counter constitute a counting circuit; The negative terminal of the photodiode is connected to the input terminal of the pre-amplification and shaping circuit. The output terminal of the pre-amplification and shaping circuit is connected to the input terminal of the integrating circuit and the second input terminal of the first comparator. A feedback capacitor and a reset switch are connected in parallel between the input and output terminals of the integrating circuit. The output terminal of the integrating circuit is the first output terminal of the photodiode pixel unit. The first input terminal of the first comparator is connected to the first threshold voltage signal terminal. The output terminal of the first comparator is connected to the input terminal of the analog counter. The output terminal of the analog counter is the second output terminal of the photodiode pixel unit.

10. The photon stream detector with high image acquisition performance as described in claim 9, characterized in that: The first output terminal and the second output terminal of the photodiode pixel unit are respectively connected to the ADC bus via a first control switch and a second control switch. The photodiode pixel units in the same column of the photodiode array share a single ADC bus and are connected to the ADC module of the corresponding column in the ADC array through this ADC bus. The output of each column of ADC modules in the ADC array is connected to the horizontal serializer corresponding to that column in the serial link unit.

11. The photon stream detector with high image acquisition performance as described in claim 1, characterized in that: The photon flow image data P generated by the data collected by the photon flow detector satisfies the following formula: Among them, P c P represents the photon count data for a photodiode pixel unit. i P represents the energy integral data of a photodiode pixel unit. i =a*P c +b, where a and b are fitting coefficients; P c-nl Data for the entry point of the nonlinear region of photon counting in the response curve; P lsnr The integral data is 350 times the standard deviation of the dark field.

12. A CT scanner, characterized in that... Including the photon stream detector with high image acquisition performance as described in any one of claims 1 to 11.

Images