Semiconductor device and method for fabricating semiconductor device

Abstract

The present invention provides a transistor that can handle large currents. The present invention provides a storage device in which transistors can be densely arranged. This semiconductor device has first and second semiconductor layers, first to third conductive layers, and a first insulating layer. The first conductive layer and the second conductive layer are provided apart from each other. A first lateral surface of the first conductive layer and a second lateral surface of the second conductive layer have first groove parts and second groove parts, respectively. The first semiconductor layer fits into a pair of the first groove parts, and the second semiconductor layer fits into a pair of the second groove parts. Between the first conductive layer and the second conductive layer, the third conductive layer surrounds the upper surface, the lower surface, and the pair of lateral surfaces of each of the first semiconductor layer and the second semiconductor layer. The first insulating layer has a portion located between the first semiconductor layer and the third conductive layer and a portion located between the second semiconductor layer and the third conductive layer.

Description

Semiconductor device and method for manufacturing the same

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a transistor, or a memory device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0003] In recent years, the development of semiconductor devices has progressed, and CPUs, memories, and other large-scale integrated circuits (LSIs) are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0004] 2. Description of the Related Art A CPU, a memory, or other LSI semiconductor circuit (IC chip) is mounted on a circuit board, such as a printed wiring board, and is used as one of the components of various electronic devices.

[0005] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0006] Furthermore, it is known that a transistor including an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the property of a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time.

[0007] JP 2012-257187 A JP 2011-151383 A

[0008] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0009] An object of one embodiment of the present invention is to provide a transistor capable of passing a large current. Another object is to provide a transistor with favorable electrical characteristics. Another object is to provide a transistor that can be miniaturized. Another object is to provide a transistor that occupies a small area. Another object is to provide a transistor that combines miniaturization with high reliability. Another object is to provide a memory device in which transistors can be arranged at high density.

[0010] An object of one embodiment of the present invention is to provide a semiconductor device, a memory device, or an electronic device having a novel structure. An object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0012] One embodiment of the present invention is a semiconductor device including first and second semiconductor layers, first to third conductive layers, and a first insulating layer. The first conductive layer and the second conductive layer are provided separately. The first conductive layer has a first side surface facing the second conductive layer. The second conductive layer has a second side surface facing the first side surface. The first side surface and the second side surface each have a first groove and a second groove located above the first groove. The first semiconductor layer is provided to fit into a pair of first grooves formed in the first side surface and the second side surface, respectively. The second semiconductor layer is provided to fit into a pair of second grooves formed in the first side surface and the second side surface, respectively. Between the first conductive layer and the second conductive layer, a third conductive layer has portions surrounding the top surface, the bottom surface, and a pair of side surfaces of the first semiconductor layer and the second semiconductor layer. The first insulating layer has portions located between the first conductive layer and the third conductive layer, between the second conductive layer and the third conductive layer, between the first semiconductor layer and the third conductive layer, and between the second semiconductor layer and the third conductive layer, respectively.

[0013] Another embodiment of the present invention is a semiconductor device including first to n-th (n is 2 or more) semiconductor layers, first to third conductive layers, and a first insulating layer. The first conductive layer and the second conductive layer are spaced apart from each other. The first conductive layer has a first side surface facing the second conductive layer. The second conductive layer has a second side surface facing the first side surface. The first side surface and the second side surface each have first to n-th grooves spaced apart in the height direction. The k-th (k is an integer greater than or equal to 1 and less than or equal to n) semiconductor layer is provided to fit into a pair of k-th grooves formed in the first side surface and the second side surface, respectively. Between the first conductive layer and the second conductive layer, the third conductive layer has portions surrounding the top surface, the bottom surface, and a pair of side surfaces of each of the first to n-th semiconductor layers. The first insulating layer has portions located between the first conductive layer and the third conductive layer, between the second conductive layer and the third conductive layer, and between the first to n-th semiconductor layers and the third conductive layer, respectively.

[0014] In the above, the first semiconductor layer and the second semiconductor layer preferably overlap each other.

[0015] In the above, it is preferable that the semiconductor device further includes a fourth conductive layer and a first connection electrode. The fourth conductive layer is preferably located on the second conductive layer, and the fourth conductive layer and the second conductive layer are preferably connected via the first connection electrode. The fourth conductive layer preferably extends in a first direction. The third conductive layer preferably extends in a second direction perpendicular to the first direction.

[0016] In the above, it is preferable that the semiconductor device further includes a capacitor and a second connection electrode. The capacitor is preferably located above the fourth conductive layer. One electrode of the capacitor and the first conductive layer are preferably connected via the second connection electrode. Furthermore, it is preferable that the second connection electrode is provided at a position that overlaps with the first conductive layer but does not overlap with the fourth conductive layer in a plan view.

[0017] In the above, the first semiconductor layer and the second semiconductor layer preferably contain a metal oxide.

[0018] In the above, the first semiconductor layer and the second semiconductor layer preferably contain indium oxide.

[0019] Another embodiment of the present invention is a method for manufacturing a semiconductor device, the method including: forming a first sacrificial layer, a first semiconductor film, a second sacrificial layer, a second semiconductor film, and a third sacrificial layer in this order; forming a mask layer over the third sacrificial layer; removing portions of the first sacrificial layer, the first semiconductor film, the second sacrificial layer, the second semiconductor film, and the third sacrificial layer that are not covered with the mask layer; recessing side surfaces of the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer to form a first semiconductor layer and a second semiconductor layer, each having a pair of protrusions; The method includes the steps of forming a first conductive layer in contact with one of a pair of protrusions of each of the second semiconductor layers and a second conductive layer in contact with the other of the protrusions; removing the mask layer and the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer; forming a first insulating layer between the first conductive layer and the second conductive layer to cover the upper surface, lower surface, and side surface of each of the first semiconductor layer and the second semiconductor layer; and forming a third conductive layer that surrounds the upper surface, lower surface, and side surface of each of the first semiconductor layer and the second semiconductor layer via the first insulating layer.

[0020] According to one embodiment of the present invention, a transistor capable of passing a large current can be provided. Alternatively, a transistor with favorable electrical characteristics can be provided. Alternatively, a transistor that can be miniaturized can be provided. Alternatively, a transistor that occupies a small area can be provided. Alternatively, a transistor that can be miniaturized and has high reliability can be provided. Alternatively, a memory device in which transistors can be arranged at high density can be provided.

[0021] According to one aspect of the present invention, it is possible to provide a semiconductor device, a memory device, or an electronic device having a novel configuration. According to one aspect of the present invention, it is possible to at least alleviate at least one of the problems of the prior art.

[0022] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0023] FIGS. 1A and 1B are structural examples of a semiconductor device. FIGS. 2A and 2B are structural examples of a semiconductor device. FIG. 3 is a structural example of a semiconductor device. FIG. 4 is a structural example of a semiconductor device. FIGS. 5A to 5C are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 6A to 6C are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 7A to 7C are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 8A to 8C are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 9A to 9C are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 10A to 10C are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 11A to 11C are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 12A to 12C are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 13A to 13C are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 14A to 14C are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 15A to 15C are diagrams illustrating an example of a method for manufacturing a semiconductor device. 16A to 16C are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 17A and 17B are diagrams illustrating carrier concentration dependence of Hall mobility. FIG. 17C is a cross-sectional view illustrating an indium oxide film. FIG. 18 is a block diagram illustrating a configuration example of a semiconductor device. FIGS. 19A to 19H are diagrams illustrating an example of a circuit configuration of a memory cell. FIGS. 20A and 20B are perspective views illustrating an example of a configuration of a semiconductor device. FIG. 21 is a block diagram illustrating a CPU. FIGS. 22A and 22B are perspective views of a semiconductor device. FIGS. 23A and 23B are perspective views of a semiconductor device. FIGS. 24A and 24B are configuration examples of electronic components. FIGS. 25A to 25C are configuration examples of a mainframe computer. FIG. 26A is a configuration example of space equipment. FIG. 26B is a configuration example of a storage system.

[0024] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0025] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0026] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0027] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0028] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0029] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0030] In this specification and the like, either the source or the drain of a transistor may be referred to as a “first electrode,” and the other of the source or the drain may be referred to as a “second electrode.” The gate may also be referred to as a “gate” or a “gate electrode.”

[0031] In this specification, "connection" includes "electrical connection." "A and B are electrically connected" means that, among the cases where A and B are connected without an insulator (where A and B are connected via a conductor or semiconductor, or where A and B are in contact), there is a time when an exchange of electrical signals or an interaction of potentials occurs between A and B during circuit operation. In other words, even if there is a time during circuit operation when an exchange of electrical signals or an interaction of potentials does not occur between A and B, it can be said that "A and B are electrically connected" as long as there is a time when an exchange of electrical signals or an interaction of potentials occurs between A and B.

[0032] An "electrical connection" includes a connection (direct connection) that does not involve a circuit element (for example, a transistor, but excluding wiring), and a connection (indirect connection) that involves one or more circuit elements.

[0033] In this specification, the phrase "top surface shapes generally match" refers to the overlap of at least a portion of the contours between stacked layers. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" may also be used.

[0034] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. The plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0035] In the following, expressions indicating directions such as "up" and "down" will basically be used in accordance with the directions in the drawings. However, for purposes such as facilitating explanation, the directions indicated by "up" or "down" in the specification may not match those in the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided (such as a forming surface, a support surface, an adhesive surface, or a flat surface) is located above the laminate in the drawings, the forming surface side may be expressed as "down" and the direction opposite to the forming surface as "up."

[0036] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the line connecting the source region and the drain region at the shortest distance. In other words, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in an on-state. The channel width direction refers to a direction perpendicular to the channel length direction. Depending on the structure or shape of the transistor, the channel length direction and the channel width direction may not be defined as a single direction.

[0037] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0038] Unless otherwise specified, in this specification and the like, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the gate-source voltage Vgs is lower than the threshold voltage Vth for an n-channel transistor (higher than Vth for a p-channel transistor).

[0039] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by adding a superscript bar to the numbers. However, due to formatting restrictions, in this specification, instead of adding a bar above the numbers, they may be expressed by adding a minus sign (-) before the numbers. Furthermore, individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent orientations are expressed with < >, individual planes indicating crystal planes are expressed with ( ), and collective planes with equivalent symmetry are expressed with {}.

[0040] In this specification, "two lines parallel" refers to a state in which the two lines are arranged at an angle of -10 degrees or more and 10 degrees or less. "Two lines approximately parallel" refers to a state in which the two lines are arranged at an angle of -30 degrees or more and 30 degrees or less (including parallel). "Two lines perpendicular" refers to a state in which the two lines are arranged at an angle of 80 degrees or more and 100 degrees or less. "Two lines approximately perpendicular" refers to a state in which the two lines are arranged at an angle of 60 degrees or more and 120 degrees or less (including perpendicular).

[0041] In this specification, "two surfaces are parallel" refers to a state in which their interior angle is between -10 degrees and 10 degrees. "Two surfaces are approximately parallel" refers to a state in which their interior angle is between -30 degrees and 30 degrees (including parallel). "Two surfaces are perpendicular" refers to a state in which their interior angle is between 80 degrees and 100 degrees (including perpendicular). "Two surfaces are approximately perpendicular" refers to a state in which their interior angle is between 60 degrees and 120 degrees (including perpendicular).

[0042] Embodiment 1 In this embodiment, a structural example of a transistor according to one embodiment of the present invention, a structural example of a memory device including the transistor, and a manufacturing method thereof will be described.

[0043] One embodiment of the present invention is a transistor including a sheet-shaped semiconductor layer. The transistor includes a gate electrode surrounding a part of an upper surface, a side surface, and a lower surface of the sheet-shaped semiconductor layer, and a gate insulating layer located between the semiconductor layer and the gate electrode. A region of the semiconductor layer covered by the gate electrode via the gate insulating layer functions as a channel formation region. With this structure, a gate electric field is applied so as to surround the semiconductor layer, thereby improving the controllability of turning the transistor on and off. Specifically, the transistor can have an increased source-drain current (on current) in an on state and a reduced leakage current (off current) in an off state.

[0044] The sheet-like semiconductor layer is preferably not only one layer but two or more layers. When multiple semiconductor layers are used, the semiconductor layers are preferably stacked with a gap between them in the vertical direction (height direction). In this case, the gate insulating layer is provided to cover the channel formation regions of all the semiconductor layers. The gate electrode has a portion located below the lowest semiconductor layer, above the highest semiconductor layer, and between the two semiconductor layers. With this configuration, a gate electric field can be applied to all the semiconductor layers in a surrounding manner, thereby obtaining a larger on-current than simply stacking semiconductor layers and increasing the effective channel width.

[0045] The transistor has a pair of conductive layers in contact with a semiconductor layer. One of the pair of conductive layers functions as a source electrode, and the other functions as a drain electrode. The conductive layer has multiple recesses spaced apart in the height direction in part of its side surface. The edge of the semiconductor layer is provided to fit snugly into the recess, and the top, side, and bottom surfaces of the edge of the semiconductor layer are in contact with the conductive layer. With this structure, the semiconductor layer is fixed to the pair of conductive layers, which prevents the semiconductor layer from being damaged during the manufacturing process and improves yield. Furthermore, the contact area between the semiconductor layer and the conductive layer can be increased, thereby increasing the current in the on state of the transistor (also referred to as on-current).

[0046] The transistor can be used in a memory device. For example, by connecting one of a pair of conductive layers of the transistor to a capacitor and connecting the other to a signal line (bit line), the transistor can be used as a memory cell of a dynamic random access memory (DRAM). In this case, the gate electrode of the transistor can be used as a word line. Furthermore, by providing two transistors adjacent to each other and sharing a conductive layer connected to the bit line, a highly integrated memory device can be realized.

[0047] When a transistor is used in a memory device, a capacitor is preferably provided above a bit line. The capacitor can have a structure including a pair of electrodes and an insulating layer positioned between the electrodes and functioning as a dielectric. One of the pair of conductive layers of the transistor can be connected to one electrode of the capacitor located above the bit line through a connection electrode (also referred to as a plug). In this case, the bit line and the word line are provided orthogonal to each other, and the connection electrode is provided at a position that does not overlap with the bit line in a plan view, thereby preventing the connection electrode from contacting the bit line.

[0048] As a semiconductor material used for the semiconductor layer, a metal oxide (also referred to as an oxide semiconductor) that exhibits semiconductor properties is preferably used. A transistor using an oxide semiconductor has significantly lower leakage current in an off state than a transistor using silicon, and therefore a memory device that can retain data for a long period of time and has low power consumption can be realized.

[0049] A more specific example will be described below with reference to the drawings.

[0050] [Configuration Example] Fig. 1A is a schematic top view of a memory device exemplified below. Fig. 1B is a schematic cross-sectional view taken along the line A-B in Fig. 1A. Some components (such as insulating layers and conductive layer 53) are omitted in Fig. 1A.

[0051] 1A, a coordinate system having orthogonal X, Y, and Z directions is indicated by arrows. Arrows also indicate a coordinate system having X' and Y' directions obtained by rotating the X and Y directions around the Z axis. The cutting line A-B is a line parallel to the X' direction. The angle between the X and X' directions is preferably in the range of 20 degrees to 30 degrees.

[0052] As shown in FIGS. 1A and 1B , the memory device includes a pair of transistors 10 (transistor 10a and transistor 10b), a pair of capacitors 50 (capacitors 50a and 50b), a conductive layer 26 functioning as a bit line, a connection electrode 32, a pair of connection electrodes 33 (connection electrode 33a and connection electrode 33b), and a pair of connection electrodes 31 (connection electrode 31a and connection electrode 31b). The capacitor 50a is connected to the transistor 10a, and the capacitor 50b is connected to the transistor 10b. The conductive layer 26 extends in the X direction. A portion of the conductive layer 23 shown in FIG. 1B functions as the gate electrode of the transistor 10 and also functions as a word line. The conductive layer 23 extends in the Y direction, which is perpendicular to the X direction. The connection electrode 31 and the connection electrode 33 connect the transistor 10 and the capacitor 50. As shown in FIG. 1A, the connection electrode 33 (and the connection electrode 31 connected thereto) is provided at a position that does not overlap the conductive layer 26 in a plan view.

[0053] The connection electrodes 33a and 33b connected to the capacitance element 50 are arranged in a region surrounded by the conductive layers 23 functioning as a pair of word lines and the conductive layers 26 functioning as a pair of bit lines in a plan view. By using such an arrangement method, the area occupied by each memory cell (i.e., a configuration including one transistor 10 and one capacitance element 50) can be reduced to 6F. ２ (F is the minimum processing dimension) This makes it possible to realize a memory device in which memory cells are arranged at high density.

[0054] In this embodiment, when describing matters common to components distinguished by alphabets attached to their reference symbols (transistor 10a, transistor 10b, etc.) and components distinguished by numbers attached to their reference symbols (semiconductor layer 21_1, semiconductor layer 21_2, etc.), the description may be made using reference symbols (transistor 10, semiconductor layer 21, etc.) with the alphabets or numbers omitted, unless otherwise specified.

[0055] The transistor 10a and the transistor 10b are provided over an insulating layer 11 provided over a substrate (not shown). The insulating layer 11 functions as a base insulating layer.

[0056] 1B , in a cross-sectional view parallel to the X′ direction, the transistors 10a and 10b are provided symmetrically with respect to the conductive layer 26. Each transistor 10 includes a conductive layer 24, a conductive layer 25, a plurality of semiconductor layers 21 (semiconductor layer 21_1, semiconductor layer 21_2, and semiconductor layer 21_3), an insulating layer 22, and a conductive layer 23. A portion of the conductive layer 24 functions as one of a source electrode and a drain electrode, and a portion of the conductive layer 25 functions as the other. The insulating layer 22 functions as a gate insulating layer, and a portion of the conductive layer 23 functions as a gate electrode.

[0057] The transistors 10a and 10b share the conductive layer 25. This makes it possible to realize a highly integrated memory device.

[0058] Conductive layers 24 and 25 are provided on the insulating layer 11. The conductive layers 24 and 25 are provided separately. A side surface of the conductive layer 24 facing the conductive layer 25 (also referred to as a first side surface) and a side surface of the conductive layer 25 facing the conductive layer 24 (a second side surface) are provided opposite each other. A plurality of grooves are provided on the first side surface and the second side surface at intervals in the height direction. The grooves are preferably parallel to the substrate surface.

[0059] The semiconductor layer 21 is provided so as to fit snugly (to fit) into the respective grooves of the conductive layer 24 and the conductive layer 25. That is, the top surface, side surface, and bottom surface of a pair of ends of the semiconductor layer 21 are in contact with the conductive layer 24 or the conductive layer 25. This allows the semiconductor layer 21 to be held by the conductive layer 24 and the conductive layer 25, and prevents the semiconductor layer 21 from being lost during the manufacturing process. Furthermore, the contact area between the conductive layer 24 or the conductive layer 25 and the semiconductor layer 21 can be increased, thereby increasing the on-state current of the transistor 10.

[0060] 2A shows a schematic perspective view in which some components (such as insulating layers and the capacitance element 50) are omitted. Also, FIG. 2B shows a schematic perspective view in which only the outlines of the conductive layer 23 and the insulating layer 22 are indicated by dashed lines. As shown in FIG. 2B, the three semiconductor layers 21 are provided so as to overlap one another and are arranged at approximately equal intervals in the Z direction. Furthermore, the upper, side, and lower surfaces of both ends of the semiconductor layer 21 in the X' direction are in contact with the conductive layer 24 or the conductive layer 25 and are arranged so as to fit into the grooves formed therein.

[0061] 1B, an insulating layer 41 is provided on the conductive layer 24 and the conductive layer 25. The insulating layer 41 functions as an interlayer insulating layer.

[0062] An insulating layer 22 is provided to cover the exposed surfaces of the conductive layer 24, the conductive layer 25, the semiconductor layer 21, and the insulating layer 41. The insulating layer 22 is provided in the region between the conductive layer 24 and the conductive layer 25 to cover the top surface, bottom surface, and both side surfaces of the semiconductor layer 21.

[0063] Furthermore, a conductive layer 23 is provided on the insulating layer 22 so as to fill the region between the conductive layer 24 and the conductive layer 25. The conductive layer 23 is provided in the region between the conductive layer 24 and the conductive layer 25, covering the top surface, bottom surface, and both side surfaces of the semiconductor layer 21 via the insulating layer 22. This allows a gate electric field from the conductive layer 23 to be efficiently applied to the semiconductor layer 21, thereby improving the on / off controllability of the transistor 10. For example, the on-current of the transistor 10 can be increased and the off-current can be reduced.

[0064] The planar shapes of the conductive layer 23, the conductive layer 24, the conductive layer 25, and the semiconductor layer 21 will be described using FIG. 3 . FIG. 3 is a top view schematic diagram illustrating the conductive layer 24, the conductive layer 25, and the semiconductor layer 21. In FIG. 3 , the conductive layer 23 is indicated by a dashed line. Here, a structure 10S is defined as a configuration including the conductive layer 24a, the conductive layer 24b, the conductive layer 25, and the semiconductor layer 21 in two transistors 10 (transistor 10a, transistor 10b) that share the conductive layer 25. A conductive layer 23 extending in the Y direction is provided between two structures 10S adjacent in the X′ direction. Furthermore, the structures 10S are not simply repeatedly arranged in the Y direction; rather, the structures 10S arranged in the Y direction are arranged so as to be offset in the X′ direction by the arrangement interval of the conductive layer 23.

[0065] 3, the conductive layer 24, the conductive layer 25, and the semiconductor layer 21 each have an outer shape in a plan view that is a parallelogram or a shape close to a parallelogram. Of the four sides of the parallelogram, two sides are parallel to the Y direction, and the other two sides are parallel to the X' direction.

[0066] 1B , insulating layer 22 is disposed between conductive layer 23 and conductive layer 24 and between conductive layer 23 and conductive layer 25, and has the function of insulating them. In addition, insulating layer 22 is also provided between conductive layer 23 and conductive layer 24 between two structures 10S described later, so that an electrical short circuit between them can be prevented.

[0067] It is preferable to use a metal oxide (oxide semiconductor) that exhibits semiconductor properties for the semiconductor layer 21. In this case, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductive material for the conductive layers 24 and 25 that are in contact with the semiconductor layer 21. This can prevent high-resistance oxides from being generated at the interface between the semiconductor layer 21 and the conductive layer 24 or 25, and can suppress an increase in contact resistance between the semiconductor layer 21 and the conductive layer 24 or 25.

[0068] In particular, it is preferable to use a conductive metal oxide (oxide conductor) for at least the portions of the conductive layer 24 and the conductive layer 25 that are in contact with the semiconductor layer 21. By using a metal oxide for the conductive layer that is in contact with the metal oxide-containing semiconductor layer 21, the contact resistance therebetween can be reduced, and the load on the wiring can be reduced, thereby increasing the on-state current of the transistor 10.

[0069] The conductive layer 24 and the conductive layer 25 preferably contain a metal oxide containing the same metal element as the semiconductor layer 21. In particular, the conductive layer 24, the conductive layer 25, and the semiconductor layer 21 each preferably contain a metal oxide containing indium. This makes it possible to effectively reduce the contact resistance between the semiconductor layer 21 and the conductive layer 24, and between the semiconductor layer 21 and the conductive layer 25. It is preferable to use a metal oxide containing indium and tin for the conductive layer 24 and the conductive layer 25, as this can increase the conductivity.

[0070] Here, the conductive layer 24 and the conductive layer 25 may have a two-layer structure. FIG. 4 shows an example in which the conductive layer 24a and the conductive layer 24b each have a stacked structure of a conductive layer 24_1 and a conductive layer 24_2, and the conductive layer 25 has a stacked structure of a conductive layer 25_1 and a conductive layer 25_2. The conductive layer 24_1 and the conductive layer 25_1 are provided in contact with the top surface, bottom surface, and side surface of the end portion of each semiconductor layer 21, respectively. The conductive layer 24_1 and the conductive layer 25_1 are provided in contact with the top surface of the insulating layer 11, respectively. The conductive layer 24_2 and the conductive layer 25_2 are provided to cover the conductive layer 24_1 or the conductive layer 25_1.

[0071] The conductive layers 24_1 and 25_1 can be formed using the above-mentioned conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material. The conductive layers 24_2 and 25_2 can be formed using a conductive material that has lower resistance than the conductive layers 24_1 and 25_1, such as a metal or an alloy. This reduces the wiring resistance of the conductive layers 24 and 25. The conductive layers 24_1 and 25_1 are not provided on the conductive layers 24_2 and 25_2, and the connection electrodes 31a, 31b, and 32 are directly connected to the conductive layers 24_2 and 25_2. This reduces the contact resistance between the conductive layers 24 and 25 and the respective connection electrodes.

[0072] 1B , an insulating layer 42 is provided to cover the insulating layer 22 and the conductive layer 23. The insulating layer 42 functions as an interlayer insulating layer. Furthermore, a connection electrode 31 a, a connection electrode 31 b, and a connection electrode 32 are provided in the insulating layer 42, the insulating layer 22, and the insulating layer 41, respectively, so as to fill openings provided to reach the conductive layer 24 or the conductive layer 25. The connection electrode 31 a is connected to the conductive layer 24 a, the connection electrode 31 b is connected to the conductive layer 24 b, and the connection electrode 32 is connected to the conductive layer 25.

[0073] A conductive layer 26 is provided on the insulating layer 42. The conductive layer 26 is connected to the conductive layer 25 via a connection electrode 32. The conductive layer 26 functions as a bit line. An insulating layer 43 is provided to cover the conductive layer 26 and the insulating layer 42. The insulating layer 43 functions as an interlayer insulating layer.

[0074] Furthermore, openings reaching the connection electrodes 31a and 31b are provided in the insulating layer 43, and the connection electrodes 33a and 33b are provided so as to fill the openings.

[0075] The capacitance elements 50a and 50b are provided on the insulating layer 43. This allows the physical distance between the conductive layer 26 and the conductive layer 25 (i.e., the height of the connection electrode 32) to be smaller than when the conductive layer 26 is provided above the capacitance element 50, thereby reducing the wiring resistance therebetween.

[0076] The capacitor 50 includes a conductive layer 51 and a conductive layer 53 that function as a pair of electrodes, and an insulating layer 52 that functions as a dielectric and is located between the conductive layers 51 and 53. The capacitor 50 may be a so-called MIM (Metal-Insulator-Metal) capacitor.

[0077] The conductive layer 51 is provided on the insulating layer 43 and connected to the connection electrode 33a. The conductive layer 51 has a flat portion in contact with the connection electrode 33a and an annular (cylindrical) portion above the flat portion. The conductive layer 51 can also be said to have a tall cup-like shape. An insulating layer 52 is provided covering the conductive layer 51, and a conductive layer 53 is provided on the insulating layer 52. By forming the conductive layer 51 in this shape, the area of ​​the region where the conductive layer 51 and the conductive layer 53 face each other via the insulating layer 52 can be increased, thereby increasing the capacitance of the capacitive element 50. Note that the shape of the conductive layer 51 is not limited to this, and it may also be columnar. Forming the conductive layer 51 in a columnar shape allows the diameter of the conductive layer 51 to be narrowed, making it suitable for high integration.

[0078] The higher the height of the conductive layer 51, the larger the capacitance of the capacitance element 50 can be. On the other hand, the smaller the diameter of the conductive layer 51, the higher the integration density of the memory device. Furthermore, the higher the height of the conductive layer 51 and the smaller the diameter of the conductive layer 51, the more difficult it is to process the conductive layer 51, leading to a decrease in yield. The shape of the conductive layer 51 can be appropriately set taking into consideration the magnitude of the capacitance required for the capacitance element 50, the manufacturing yield, and the like. The height of the conductive layer 51 can be, for example, 100 nm or more and 10 μm or less, preferably 200 nm or more and 8 μm or less, and more preferably 500 nm or more and 5 μm or less.

[0079] It is preferable to use a low-resistance conductive material for the conductive layers 51 and 53. For example, it is preferable to use the same material as the conductive layer 23.

[0080] The insulating layer 52 functions as a dielectric for the capacitive element 50. In particular, it is preferable to use a high-k material for the insulating layer 52. Furthermore, by using a material exhibiting ferroelectricity for the insulating layer 52, the capacitive element 50 can be made into a ferroelectric capacitor, thereby realizing a nonvolatile memory device. Note that a resistance change type memory element utilizing the electric field induced giant resistance change (CER: Colossal Electro-Resistance) effect can also be used as the capacitive element 50.

[0081] Although the description has been given here of a structure in which three semiconductor layers 21 are stacked, the number of semiconductor layers 21 included in the transistor 10 is not limited to this. A larger number of semiconductor layers 21 is preferable because the on-state current of the transistor 10 can be increased. On the other hand, a smaller number of semiconductor layers 21 can simplify the manufacturing process of the transistor 10 and improve yield. The semiconductor layer 21 may be a single layer.

[0082] When n semiconductor layers 21 (n is an integer of 2 or more) are stacked, the number of grooves provided on the opposing surfaces of conductive layer 24 and conductive layer 25 is also n. The kth (k is an integer of 1 to n) semiconductor layer 21 from the bottom can be provided so as to fit into the kth groove from the bottom, among the grooves provided in conductive layer 24 and conductive layer 25.

[0083] The above is a description of an example of the configuration of the semiconductor device.

[0084] [Regarding Components] <Substrate> The substrate on which a transistor is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Examples of semiconductor substrates include those having an insulating region within the aforementioned semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides may also be used. Further, there are substrates in which a conductive layer or a semiconductor layer is provided on an insulating substrate, substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or an insulating layer is provided on a conductive substrate. Alternatively, any of these substrates may be provided with elements. The elements provided on the substrate include capacitor elements, resistor elements, switch elements (including transistors), light-emitting elements, memory elements, and the like.

[0085] <Semiconductor Layer> The semiconductor layer 21 preferably contains a metal oxide (oxide semiconductor).

[0086] The semiconductor layer 21 is preferably made of indium oxide.

[0087] Indium oxide may contain a metal element (also called a cation) that can become a positive ion. For example, indium oxide doped with an oxide of a metal such as Ge, W, Ga, Sb, Bi, Sn, or Ti can be used. Doping an indium oxide film with such an oxide can reduce oxygen vacancies, indium vacancies, or both in the indium oxide, thereby improving reliability.

[0088] Examples of metal oxides that can be used for the semiconductor layer 21 include Ga oxide and Zn oxide. The metal oxide preferably contains at least In or Zn. The metal oxide preferably contains two or three elements selected from In, element M, and Zn. The element M is a metal element or semimetal element with a high bond energy with oxygen, such as a metal element or semimetal element with a bond energy with oxygen higher than that of indium. Specific examples of the element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The element M contained in the metal oxide is preferably one or more of the above elements, and is particularly preferably one or more selected from Al, Ga, Y, and Sn, with Ga being more preferred. Hereinafter, a metal oxide having In, M, and Zn may be referred to as an In-M-Zn oxide. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0089] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. For example, the atomic ratios of metal elements in such an In-M-Zn oxide may be In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, or compositions in the vicinity thereof. Note that the term "composition in the vicinity" refers to a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current, field-effect mobility, and the like of a transistor can be increased.

[0090] Furthermore, the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M. For example, the atomic ratio of metal elements in such an In-M-Zn oxide may be In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or a composition close to these. By increasing the atomic ratio of M in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0091] The semiconductor layer 21 can be made of, for example, In—Zn oxide, In—Ga oxide, In—Sn oxide, In—Ti oxide, In—Ga—Al oxide, In—Ga—Sn oxide, In—Ga—Zn oxide, In—Sn—Zn oxide, In—Al—Zn oxide, In—Ti—Zn oxide, In—Ga—Sn—Zn oxide, or In—Ga—Al—Zn oxide. Ga—Zn oxide may also be used. On the other hand, a material containing Zn is preferred because it is easy to increase crystallinity.

[0092] Note that the metal oxide may contain one or more metal elements with higher period numbers in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element with a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements with higher period numbers include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu. Note that La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.

[0093] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0094] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). In particular, it is preferable to form the metal oxide film by the ALD method, which has excellent coating properties. When forming the metal oxide by the sputtering method, the composition of the metal oxide film may differ from that of the target. In particular, the zinc content in the metal oxide film may decrease to about 50% of that of the target.

[0095] In this specification, the content of a metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide. For example, if a metal oxide contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide is A, then Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ ) In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the metal oxide (atomic number ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0096] For example, in the case of a metal oxide containing In, a transistor with a large on-current can be realized by increasing the In content.

[0097] By using a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 21, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of threshold voltage fluctuation in a PBTS (Positive Bias Temperature Stress) test can be obtained. Furthermore, when using a metal oxide that contains Ga, it is preferable to make the Ga content lower than the In content. This makes it possible to realize a transistor with high mobility and high reliability.

[0098] On the other hand, by increasing the Ga content, a transistor with high reliability against light can be obtained. That is, a transistor with a small amount of variation in threshold voltage in a Negative Bias Temperature Illumination Stress (NBTIS) test can be obtained. Specifically, a metal oxide in which the atomic ratio of Ga is equal to or greater than the atomic ratio of In has a larger band gap, and the amount of variation in threshold voltage of the transistor in the NBTIS test can be reduced.

[0099] Furthermore, by increasing the zinc content, the metal oxide becomes highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0100] The semiconductor layer 21 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 21 may have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. A stacked structure in which two or more oxide semiconductor layers with different compositions are stacked may also be used. Furthermore, by using the ALD method, it is possible to form a metal oxide layer whose composition varies continuously in the thickness direction. This not only broadens the range of design options compared to using a film with a fixed composition, but also prevents the generation of interface states between two layers with different compositions, thereby improving electrical characteristics and reliability. Furthermore, a metal oxide layer having a stacked structure may be formed using both the sputtering method and the ALD method.

[0101] When the semiconductor layer 21 has a two-layer structure, it is preferable to use a material with higher mobility (higher conductivity) in the second layer, i.e., the side closer to the gate electrode, than in the first layer. This allows for a normally-off transistor with a large on-current. This makes it possible to achieve both low power consumption and high performance. Alternatively, a material with higher mobility than in the second layer may be used in the first layer, i.e., the side in contact with the source electrode and drain electrode. This reduces the contact resistance between the semiconductor layer 21 and the source electrode or drain electrode, thereby reducing parasitic resistance and enabling a transistor with a large on-current.

[0102] Furthermore, when the semiconductor layer 21 has a three-layer structure, it is preferable to use a material for the second layer that has a higher mobility than the first and third layers, thereby realizing a transistor with a high on-current and high reliability.

[0103] The difference in the mobility and conductivity described above can be expressed, for example, by the indium content. In addition, whether or not an element other than indium that contributes to improving conductivity is included, and the content of that element, also affect the mobility and conductivity. Examples of high-mobility materials include In:Ga:Zn = 4:2:3, In:Zn = 1:1, In:Zn = 2:1, In:Zn = 4:1, In:Sn:Zn = 40:X:10 (where X is 0.1 or more and 5 or less, typically X = 1), or materials with compositions similar to these. On the other hand, materials with lower mobility or conductivity than the above-mentioned materials include In:Ga:Zn = 1:3:2, In:Ga:Zn = 1:3:4, In:Ga:Zn = 2:2:1, In:Ga:Zn = 1:1:1, In:Ga:Zn = 1:1:2, or materials with compositions similar to these.

[0104] It is preferable to use a crystalline metal oxide layer for the semiconductor layer 21. For example, a metal oxide layer having a single crystal structure, a CAAC structure, a polycrystalline structure, a nano-crystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 21, the density of defect states in the semiconductor layer 21 can be reduced, and a highly reliable semiconductor device can be realized.

[0105] The higher the crystallinity of the metal oxide layer used in the semiconductor layer 21, the more the density of defect states in the semiconductor layer 21 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0106] In particular, it is preferable to use indium oxide for the semiconductor layer 21. In particular, it is preferable to use a single-crystal indium oxide film. Note that it is preferable to use a crystalline film for the semiconductor layer 21, and it is particularly preferable to use indium oxide with a single-crystal structure. However, indium oxide with a polycrystalline structure or a microcrystalline structure can also be used. By using indium oxide with a single-crystal structure, carrier scattering at crystal grain boundaries can be suppressed, and a transistor with high field-effect mobility can be realized. Furthermore, a highly reliable transistor can be realized. When indium oxide with a polycrystalline structure is used, it is preferable that crystal grain boundaries are not observed at least in the channel formation region (the region overlapping with the conductive layer 23). As a result, even indium oxide with a polycrystalline structure can achieve the same effects as indium oxide with a single-crystal structure.

[0107] The thickness of the semiconductor layer 21 is preferably 2 nm to 50 nm, more preferably 2.5 nm to 30 nm, more preferably 2.5 nm to 20 nm, more preferably 5 nm to 20 nm, and even more preferably 5 nm to 10 nm. By setting the thickness of the semiconductor layer 21 within the above range, the crystallinity of the semiconductor layer 21 can be improved.

[0108] Among oxide semiconductors with high crystallinity, indium oxide is a film through which one or both of hydrogen and oxygen move more easily than, for example, an IGZO (In—Ga—Zn—O-based oxide) film. Therefore, indium oxide is a film through which one or both of hydrogen and oxygen are more easily supplied and discharged than, for example, an IGZO film. This means that excess oxygen or excess hydrogen, which can become carriers or fixed charges, is less likely to accumulate in the semiconductor layer 21, thereby making it possible to provide a transistor with good electrical characteristics and reliability.

[0109] The semiconductor layer 21 preferably has a reduced concentration of elements that reduce crystallinity. For example, the concentration of elements such as boron and aluminum is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.

[0110] Furthermore, when indium oxide is used for the semiconductor layer 21, unintentionally mixed gallium has a tendency to easily bond with excess oxygen atoms, which may result in a large amount of fluctuation in threshold voltage in a PBTS (Positive Bias Temperature Stress) test. Therefore, when indium oxide is used for the semiconductor layer 21, the gallium concentration in the semiconductor layer 21 is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.

[0111] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has significantly lower source-drain leakage current in an off state (hereinafter also referred to as an off-state current) and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0112] The semiconductor device according to one embodiment of the present invention can be applied to, for example, a processor, a memory device, or various ICs. The transistor according to one embodiment of the present invention is capable of passing a large current and has an extremely low off-state current, and therefore, high-speed operation of a circuit and low power consumption can be achieved at the same time.

[0113] A semiconductor device according to one embodiment of the present invention can also be applied to a display device, for example. To increase the emission luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher withstand voltage between the source and drain than a transistor using silicon (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in the pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the emission luminance of the light-emitting device.

[0114] When a transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the amount of current flowing through the light-emitting device can be precisely controlled. This allows for a larger number of gray levels in the pixel circuit. Furthermore, even if the electrical characteristics (e.g., resistance) of the light-emitting device fluctuate or vary, a stable current can flow.

[0115] As described above, by using an OS transistor for a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," "suppression of the influence of manufacturing variations in light-emitting devices," and the like.

[0116] OS transistors exhibit smaller variations in electrical characteristics due to radiation exposure than Si transistors, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0117] The semiconductor material that can be used for the semiconductor layer 21 is not limited to oxide semiconductors. For example, semiconductors made of simple elements or compound semiconductors can be used. Examples of semiconductors made of simple elements include silicon (including single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon) and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. These semiconductor materials may contain impurities as dopants.

[0118] Alternatively, the semiconductor layer 21 may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0119] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0120] The crystallinity of the semiconductor material used for the semiconductor layer 21 is not particularly limited, and any of an amorphous semiconductor, a single-crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0121] <Gate Insulating Layer> The insulating layer 22 functions as a gate insulating layer of a transistor. When an oxide semiconductor is used for the semiconductor layer 21, it is preferable to use an oxide insulating film for at least the film of the insulating layer 22 that is in contact with the semiconductor layer 21. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide can be used. Alternatively, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide can also be used for the insulating layer 22. Furthermore, the insulating layer 22 may have a stacked structure, for example, a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0122] Furthermore, the insulating layer 22 is preferably formed by laminating insulating materials made of high-k materials with a high dielectric constant, and preferably by using a laminate structure of a high-k material and a material with a higher dielectric strength than the high-k material. For example, the insulating layer 22 can be formed by laminating an insulating film (also referred to as ZAZ) in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order. Alternatively, the insulating layer 22 can be formed by laminating an insulating film (also referred to as ZAZA) in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in this order. Alternatively, the insulating film can be formed by laminating hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By using a laminate of an insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved and electrostatic breakdown can be suppressed.

[0123] Furthermore, a material exhibiting ferroelectricity may be used for the insulating layer 22. Examples of the material exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ (X is a real number greater than 0).

[0124] When the insulating layer 22 has a two-layer structure, it is preferable to use an insulating film having a function of capturing or fixing hydrogen as the film in contact with the semiconductor layer 21, and to use an insulating film having a barrier property against hydrogen as the film located on the conductive layer 23 side that functions as the gate electrode. This makes it possible to suppress diffusion of hydrogen from the conductive layer 23 side to the semiconductor layer 21, thereby realizing a highly reliable transistor.

[0125] As an insulating film that captures or fixes hydrogen, it is preferable to use a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, etc. Furthermore, as an insulating film having a barrier property against hydrogen, it is preferable to use a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, a gallium oxide film, etc.

[0126] Alternatively, an insulating film that releases oxygen when heated may be used as a film in contact with the semiconductor layer 21, and an insulating film having a barrier property against hydrogen may be used as a film located on the conductive layer 23 side. Alternatively, an insulating film that releases oxygen when heated may be used as a film in contact with the semiconductor layer 21, and an insulating film that has a function of capturing or fixing hydrogen may be used as a film located on the conductive layer 23 side.

[0127] When the insulating layer 22 has a three-layer structure, it is preferable to use an insulating film made of a material that easily diffuses oxygen as the film in contact with the semiconductor layer 21, an insulating film that has barrier properties against hydrogen and oxygen as the film located on the conductive layer 23 side, and an insulating film that has the function of capturing or fixing hydrogen as the film located between them. Silicon oxide or silicon oxynitride can be used as the material that easily diffuses oxygen. With this structure, oxygen can be supplied to the semiconductor layer 21 from the film in contact with the semiconductor layer 21. Furthermore, the film located on the conductive layer 23 side prevents oxygen from diffusing toward the conductive layer 23, thereby suppressing oxidation of the conductive layer 23.

[0128] As the insulating film having a barrier property against oxygen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, a hafnium silicate film, etc. As the insulating film having a barrier property against oxygen and hydrogen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, etc.

[0129] When the insulating layer 22 has a four-layer structure, it is preferable to use an insulating film having a barrier property against oxygen as the film in contact with the semiconductor layer 21, followed by an insulating film made of a material that easily diffuses oxygen, an insulating film having a function of capturing or fixing hydrogen, and an insulating film having a barrier property against hydrogen and oxygen, from the side closer to the semiconductor layer 21. That is, in addition to the above-mentioned three-layer structure, a configuration can be obtained in which a film in contact with the semiconductor layer 21 is added. By using an insulating film having a barrier property against oxygen as the film in contact with the semiconductor layer 21, oxygen can be prevented from being desorbed from the semiconductor layer 21. In this case, it is preferable to use an aluminum oxide film as the film in contact with the semiconductor layer 21. Aluminum oxide not only has a barrier property against oxygen but also has a function of capturing or fixing hydrogen, and therefore has the effect of preventing hydrogen from diffusing into the semiconductor layer 21.

[0130] When the insulating layer 22 has a stacked structure, each insulating film is preferably a thin film. For example, the thickness of the insulating layer 22 is 1 nm to 20 nm, preferably 3 nm to 10 nm, to reduce the subthreshold swing (also referred to as the S value) of the transistor. The thickness of each insulating film is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, still more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm.

[0131] As a specific example, it is preferable to use a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 21 side, and to set the thicknesses of these films to 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer 21 side.

[0132] In this specification and the like, the barrier property refers to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that when hydrogen is described as a corresponding substance, it can refer to, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0133] Here, a transistor using a metal oxide film can have stable electrical characteristics by being surrounded by an insulating film that has a function of suppressing the permeation of impurities such as water and hydrogen and oxygen. Examples of insulating films that have a function of suppressing the permeation of impurities and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can also be used.

[0134] Examples of insulating film materials capable of capturing or adhering hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium. Metal oxides with an amorphous structure have dangling bonds in some oxygen atoms, which enhance their ability to capture or adhering hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure may be achieved by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Metal oxides may have crystalline regions and / or grain boundaries in some regions.

[0135] <Conductive Layer> The conductive layer 24 and the conductive layer 25 are in contact with the semiconductor layer 21. When an oxide semiconductor is used as the semiconductor layer 21, if an easily oxidized metal such as aluminum is used in the portion of the conductive layer 24 or the conductive layer 25 in contact with the semiconductor layer 21, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 24 or the conductive layer 25 and the semiconductor layer 21, preventing electrical conduction therebetween. Therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material for at least the portion of the conductive layer 24 and the conductive layer 25 in contact with the semiconductor layer 21.

[0136] For the conductive layer 24 and the conductive layer 25 in contact with the semiconductor layer 21, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. These are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when oxidized.

[0137] Alternatively, conductive oxides such as indium oxide, zinc oxide, In—Sn oxide, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide, and Ga—Zn oxide can be used. Conductive oxides containing indium are particularly preferred because of their high conductivity. Alternatively, oxide materials such as In—Ga—Zn oxide that can be used for the semiconductor layer 21 can also be used as a conductive layer by increasing the carrier concentration.

[0138] Furthermore, a low-resistance conductive material that can be used for the conductive layer 23 described later may be used for the conductive layer 24 and the conductive layer 25. In particular, the conductive layer 24 and the conductive layer 25 preferably have a stacked structure of a layer containing the above-mentioned conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductive material, and a layer containing a low-resistance conductive material.

[0139] It is preferable to use a low-resistance conductive material for the conductive layers 23, 26, 51, and 53. For example, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the metal element. Nitrides of the above metals or alloys, or oxides of the above metals or alloys, may also be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. It is also preferable to use semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide.

[0140] The conductive layers 23, 26, 51, and 53 may be formed using the nitride or oxide that can be used for the conductive layer 24.

[0141] The connection electrodes 31, 32, and 33 may be made of a low-resistance conductive material that can be used for the conductive layer 23 and the like.

[0142] <Insulating Layer> The insulating layer 41, the insulating layer 42, and the insulating layer 43 can be used as interlayer insulating films. For example, they are preferably formed by a film formation method such as a sputtering method or a plasma CVD method. In particular, when a sputtering method is used, hydrogen gas is not used as a film formation gas, and therefore a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the semiconductor layer 21 can be suppressed, and the electrical characteristics of the transistor 10 can be stabilized.

[0143] The insulating layers 41, 42, and 43 preferably have a low dielectric constant. By using a material with a low dielectric constant as the interlayer insulating film, the parasitic capacitance generated between wirings can be reduced. For example, it is preferable to have one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies. Silicon oxide and silicon oxynitride are preferable because they are thermally stable.

[0144] Since the insulating layers 41, 42, and 43 function as interlayer insulating layers, it is preferable to use a film formation method that allows film formation at a high film formation rate compared to other insulating layers. For example, the insulating layer 41, 42, or 43 may be formed using TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC ２ H ５ ) ４ Alternatively, a silicon oxide film formed by plasma CVD using a silicon dioxide film containing SiO 2 may be used. This can improve productivity.

[0145] The insulating layer 11, which functions as a base insulating layer, also functions as an interlayer insulating layer. The insulating layer 11 can be made of the same insulating material as can be used for the insulating layer 41 or the like.

[0146] The insulating layer 52, which functions as a dielectric of the capacitor element 50, is preferably made of a material with a high dielectric constant. Alternatively, a material exhibiting ferroelectricity can be used for the insulating layer 52. The insulating layer 52 can be made of any of the materials that can be used for the insulating layer 22.

[0147] This concludes the description of the components.

[0148] [Manufacturing Method Example] An example of a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described below, taking a memory device including the transistor 10 exemplified in the above structure example as an example.

[0149] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0150] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0151] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0152] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (photo-CVD), which uses light. CVD methods can also be further classified into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0153] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, since the thermal CVD method does not use plasma, it is possible to minimize plasma damage to the workpiece. Furthermore, since the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0154] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0155] Unlike sputtering, CVD and ALD are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which have a faster film formation rate.

[0156] In the CVD method, a film of any composition can be formed by adjusting the flow rate ratio of the source gases. For example, in the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0157] In the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors. Alternatively, when multiple different precursors are introduced, a film of any composition can be formed by controlling the number of cycles of each precursor. Furthermore, as with the CVD method, a film with a continuously changing composition can be formed.

[0158] The thin film constituting the semiconductor device can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Alternatively, the island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0159] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0160] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0161] Thin film etching can be performed using methods such as dry etching, wet etching, and sandblasting. Dry etching can be performed isotropically or anisotropically by controlling the etching conditions. Wet etching can be performed isotropically.

[0162] 5A to 16C will be used to describe an example of a manufacturing method of a memory device including the transistor 10. For example, FIG. 5A corresponds to FIG. 1A and is a schematic top view of a manufacturing process of the transistor 10, FIG. 5B corresponds to FIG. 1B, and FIG. 5C corresponds to FIG. 2A.

[0163] First, a substrate (not shown) is prepared, and an insulating layer 11 is formed on the substrate.

[0164] The substrate may be a substrate having heat resistance sufficient to withstand at least the subsequent heat treatment.

[0165] An inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used as the insulating layer 11. The insulating layer 11 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. If the surface on which the insulating layer 11 is to be formed is not flat, a planarization process may be performed after the insulating layer 11 is formed so that the upper surface of the insulating layer 11 becomes flat.

[0166] Subsequently, a sacrificial layer 61_1 is formed on the insulating layer 11, and a semiconductor film 21f_1 is formed thereon.

[0167] The sacrificial layer 61_1 is preferably made of a material having a high etching rate selectivity with respect to the semiconductor layer 21, the insulating layer 41, the conductive layer 24, the conductive layer 25, and the like to be formed later. For example, the sacrificial layer 61_1 can be made of a film that differs in at least one of constituent elements, composition, density, and crystallinity from each of the semiconductor layer 21, the insulating layer 41, the conductive layer 24, and the conductive layer 25. The sacrificial layer 61_1 can be made of various materials such as metals, alloys, semiconductors, insulators, oxides, nitrides, fluorides, or organic materials.

[0168] For example, when a crystalline indium oxide film is used for the semiconductor layer 21, it is preferable to use indium-gallium-zinc oxide (also referred to as IGZO) for the sacrificial layer 61_1. In this case, since indium oxide has a property of being more easily crystallized than IGZO, it is easy to make the crystallinity as well as the constituent elements and composition different.

[0169] Furthermore, when an IGZO film having c-axis-oriented crystalline regions (CAAC-IGZO (CAAC: c-axis aligned crystal)) is used for the sacrificial layer 61_1, the orientation of the crystalline regions of an indium oxide film formed thereon can be controlled. More specifically, an indium oxide film formed on a CAAC-IGZO film is likely to have the

[111] direction oriented perpendicular to the surface on which it is formed. Therefore, it is possible to form a uniaxially oriented crystalline indium oxide film or an indium oxide film having a single crystal structure.

[0170] The sacrificial layer 61_1 can be formed by any of the various methods described above depending on the material used. In particular, when IGZO is used for the sacrificial layer 61_1, the sacrificial layer 61_1 can be formed by a sputtering method or an ALD method. When a metal oxide film is used for the sacrificial layer 61_1, the description of a method for forming a semiconductor film that becomes the semiconductor layer 21_1, which will be described later, can be referred to.

[0171] Here, when a metal oxide film is used for the sacrificial layer 61_1, it is preferable that the film have crystallinity. When an IGZO film is formed as the sacrificial layer 61_1 by a sputtering method, a film with higher crystallinity can be formed by increasing the proportion of oxygen gas in the film formation gas and by increasing the substrate temperature during film formation. The film to be the sacrificial layer 61_1 is preferably formed to have a CAAC structure, a polycrystalline structure, a single crystal structure, or a microcrystalline structure, and particularly preferably has a CAAC structure.

[0172] Subsequently, a semiconductor film 21f_1 is formed on the sacrificial layer 61_1.

[0173] The semiconductor film 21f_1 may be a metal oxide (oxide semiconductor) film having semiconductor properties, which may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0174] The metal oxide film preferably has crystallinity. In particular, the metal oxide film according to one embodiment of the present invention preferably has a metal oxide having a single crystal structure, a polycrystalline structure, or a CAAC structure.

[0175] It is preferable to perform a treatment to enhance the crystallinity of the metal oxide film during or after the formation of the metal oxide film. Examples of treatments to enhance the crystallinity of the metal oxide film include heat treatment, plasma treatment, microwave (typically 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. A plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0176] Furthermore, it is more preferable to perform the treatment for increasing the crystallinity of the metal oxide film multiple times during the formation of the metal oxide film. For example, when forming a metal oxide film by the ALD method, it is preferable to perform a microwave plasma treatment every time an atomic layer is formed. Alternatively, it is preferable to perform a treatment for increasing the crystallinity every time a metal oxide film having a thickness within a predetermined range is formed, which can improve productivity. Specifically, it is preferable to form a first metal oxide film having a thickness of 1 nm to 10 nm, perform the first microwave plasma treatment, and then form a second metal oxide film having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment.

[0177] The deposition method for the first metal oxide film and the second metal oxide film is not particularly limited, and ALD or sputtering may be used for each. In particular, depositing the first metal oxide film by ALD is preferable because it can prevent elements from the layer constituting the surface to be formed from being mixed into the first metal oxide film and the second metal oxide film (also known as mixing). This is particularly suitable when the elements contained in the layer constituting the surface to be formed inhibit the crystallization of the metal oxide (e.g., when the layer contains silicon, carbon, or the like). The first metal oxide film and the second metal oxide film may have different compositions. Although a stacked structure of the first metal oxide film and the second metal oxide film is illustrated here, the present invention is not limited thereto. Similar processes can be applied to a single-layer or a stacked structure of three or more layers of metal oxide films.

[0178] Furthermore, a treatment for increasing the crystallinity of a metal oxide film may be performed after the metal oxide film is formed. Specifically, the treatment may be performed directly on the formed metal oxide film, or may be performed through another film, such as an insulating film, formed on the metal oxide film. For example, a microwave plasma treatment may be performed after the metal oxide film is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc.) may be formed after the metal oxide film is formed, and then a heat treatment or a microwave plasma treatment may be performed on the metal oxide film through the insulating film.

[0179] The above-described treatment for increasing the crystallinity of a metal oxide film can also serve as a treatment for removing impurities contained in the metal oxide film. For example, carbon, hydrogen, nitrogen, and the like contained in the metal oxide film can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of a metal oxide film in an oxygen gas atmosphere, oxygen vacancies in the metal oxide film can be reduced.

[0180] When performing a treatment to increase the crystallinity of a metal oxide film, it is preferable to set the temperature of the heat treatment (or the temperature of the substrate) to room temperature (e.g., 25°C) or higher, 100°C or higher and 700°C or lower, 100°C or higher and 600°C or lower, or 300°C or higher and 450°C or lower.

[0181] By increasing the crystallinity of the metal oxide film, a highly reliable transistor can be realized.

[0182] The metal oxide film can be formed by, for example, a sputtering method using a metal oxide target.

[0183] The metal oxide film is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film is preferably a high-purity film with as few impurities as possible, such as hydrogen and water, as reduced as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film.

[0184] Furthermore, when forming a metal oxide film, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). Note that the higher the ratio of oxygen gas to the total deposition gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow ratio), the higher the crystallinity of the metal oxide film can be, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film can be, and a transistor with a higher on-state current can be obtained.

[0185] When forming a metal oxide film, the higher the substrate temperature, the higher the crystallinity and density of the metal oxide film, whereas the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film.

[0186] The deposition conditions for the metal oxide film are such that the substrate temperature is from room temperature to 250° C., preferably from room temperature to 200° C., and more preferably from room temperature to 140° C. For example, a substrate temperature of from room temperature to less than 140° C. is preferred because productivity is increased. Furthermore, by depositing the metal oxide film at room temperature or without intentionally heating the substrate, the crystallinity can be reduced.

[0187] When the ALD method is used, it is preferable to use a film formation method such as thermal ALD (Atomic Layer Deposition) or PEALD (Plasma Enhanced ALD). The thermal ALD method is preferable because it exhibits extremely high step coverage. The PEALD method is also preferable because it exhibits high step coverage and allows low-temperature film formation.

[0188] For example, when a metal oxide is used for the semiconductor film, the film can be formed by an ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0189] For example, when forming an indium oxide film, a precursor containing indium can be used.

[0190] For example, when forming an In—Ga—Zn oxide film, three precursors, i.e., a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, i.e., a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0191] Examples of precursors that can be used that contain indium include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethylindium.

[0192] Furthermore, examples of precursors that can be used that contain gallium include trimethylgallium, triethylgallium, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride.

[0193] Furthermore, as a precursor containing zinc, dimethyl zinc, diethyl zinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc. can be used.

[0194] Examples of oxidizing agents include ozone (O ３ ), oxygen (O ２ ), water (H ２ O), nitrogen dioxide (NO ２ ), nitrous oxide (N ２ O), hydrogen peroxide (H ２ O ２ ) or the like can be used, and two or more of these may be used.

[0195] In order to reduce the hydrogen and nitrogen concentrations in the film, O is used as an oxidizing agent. ２ or O ３ It is preferable to use O ３ On the other hand, when forming a single crystal or a polycrystal with a large grain size, it is preferable to use an oxidizing agent containing hydrogen in order to suppress the generation of crystal nuclei in the initial stage of film formation. For example, H ２ O or H ２ O ２ After forming a film with few crystal nuclei, crystal growth can be caused by heat applied during film formation or by heat treatment after film formation, thereby forming a single crystal film or a polycrystalline film with a large grain size.

[0196] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the time for which the source gases are flowed, the order in which the source gases are flowed, etc. By adjusting these, it is also possible to form a film whose composition changes continuously. It is also possible to form two or more films with different compositions continuously.

[0197] After the metal oxide film is formed, heat treatment is preferably performed. The heat treatment may be performed within a temperature range in which the metal oxide film does not polycrystallize, such as 250° C. to 650° C., preferably 400° C. to 600° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen.

[0198] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment may be 1 ppb (0.001 ppm) or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a highly purified gas for the heat treatment, it is possible to prevent moisture and the like from being incorporated into the metal oxide film as much as possible.

[0199] In the following drawings, the semiconductor layer is shown as a single layer, but it may also have a laminated structure. For example, it may have a two-layer structure formed by the ALD method, a three-layer structure formed by the ALD method, a two-layer structure in which the first layer is formed by the ALD method and the second layer is formed by the sputtering method, or a three-layer structure in which the first layer is formed by the ALD method, the second layer is formed by the sputtering method, and the third layer is formed by the ALD method or the sputtering method. Forming the first layer by the ALD method is preferable because it can suppress mixing, but it is also possible to form the first layer by the sputtering method and the second layer by the ALD method. The semiconductor layer may also have a laminated structure of four or more layers.

[0200] During deposition of the semiconductor film 21f_1, the crystals of the sacrificial layer 61_1 can be used as seed crystals to form the semiconductor film 21f_1 having a single-crystal or polycrystalline crystal structure. When the sacrificial layer 61_1 has uniaxial orientation, such as a CAAC structure, the semiconductor film 21f_1 can be formed to have a crystal structure in which a specific orientation is aligned, reflecting the crystal structure. In particular, using the ALD method is preferable because it makes it easy to form a highly crystalline semiconductor film 21f_1 that reflects the crystal structure of the sacrificial layer 61_1.

[0201] Alternatively, heat treatment may be performed after the semiconductor film 21f_1 is formed to induce crystal growth, thereby forming the semiconductor film 21f_1 having a single crystal or polycrystalline crystal structure. The heat treatment may be performed, for example, at a temperature of 120° C. to 300° C., preferably 120° C. to 250° C., and more preferably 120° C. to 200° C. Note that the heat treatment may be performed at a temperature exceeding 300° C. (e.g., higher than 300° C. to 600° C.). The heat treatment may be performed every time one semiconductor film layer is formed, or after all semiconductor films have been formed, or thereafter. Furthermore, another process involving substrate heating (such as a film formation process) may also serve as the heat treatment.

[0202] Next, a sacrificial layer 61_2, a semiconductor film 21f_2, a sacrificial layer 61_3, a semiconductor film 21f_3, and a sacrificial layer 61_4 are formed in this order on the semiconductor film 21f_1. Each semiconductor film and each sacrificial layer can be formed in the same manner as described above.

[0203] Although the case where three semiconductor layers 21 are provided will be described here, when n semiconductor layers 21 are stacked, n+1 sacrificial layers 61 and n semiconductor films 21f may be stacked alternately.

[0204] Next, a mask layer 62 is formed on the sacrificial layer 61_4 (FIGS. 5A to 5C). The mask layer 62 functions as an etching mask when etching each sacrificial layer 61 and each semiconductor film 21f. The mask layer 62 preferably has heat resistance capable of withstanding the heat involved in subsequent processes, and is preferably made of an inorganic material. For example, a metal, alloy, oxide, nitride, inorganic semiconductor, or inorganic insulator can be used. A metal film such as tungsten is typically used. The mask layer 62 is provided at a position where a word line (conductive layer 23) will be later disposed. Therefore, the mask layer 62 can be formed in a strip shape extending in the Y direction, as shown in FIG. 5A.

[0205] The mask layer 62 can be formed by forming a thin film on the sacrificial layer 61_4, forming a resist mask on the thin film, and etching the portion not covered by the resist mask. At this time, the resist mask may be removed or may be left.

[0206] Subsequently, the regions of the laminate of the sacrificial layer 61 and the semiconductor film 21f that are not covered by the mask layer 62 are removed by etching (FIGS. 6A to 6C).

[0207] First, the stack of the sacrificial layer 61 and the semiconductor film 21f is etched by anisotropic dry etching until the insulating layer 11 is exposed, thereby forming each semiconductor layer 21. Next, the exposed side surfaces of the sacrificial layer 61 are etched by isotropic etching to recess the side surfaces (also called side etching). This allows both ends of the semiconductor layer 21 in the X direction to protrude outward beyond the side surfaces of the sacrificial layer 61.

[0208] The protruding portion of the semiconductor layer 21 will later be in contact with the conductive layer 24 and the conductive layer 25. The width of the region of the semiconductor layer 21 in contact with the sacrificial layer 61 corresponds to the channel length. Therefore, the length of the protruding portion of the semiconductor layer 21 can be set appropriately in consideration of the design value of the required channel length, the contact resistance between the semiconductor layer 21 and the conductive layer 24 or the conductive layer 25, and the like.

[0209] The isotropic etching is preferably performed under conditions where the etching rate of the sacrificial layer 61 is sufficiently higher than that of the semiconductor film 21f. Dry etching or wet etching can be used for the isotropic etching. Alternatively, atomic layer etching (ALE) may be used.

[0210] Subsequently, after forming a conductive film, a planarization process is performed until the upper surface of the mask layer 62 is exposed, thereby forming a conductive layer 63 (FIGS. 7A to 7C).

[0211] The conductive film that becomes the conductive layer 63 is formed so as to fill the gaps between the rectangular stack of the sacrificial layers 61, the semiconductor layers 21, and the mask layer 62. The conductive film is preferably formed by a film formation method that has high step coverage and embedding properties. For example, it is preferable to use a film formation method such as an ALD method or a CVD method.

[0212] The conductive layer 63 is a conductive layer that will later become the conductive layer 24 and the conductive layer 25. The conductive layer 63 is provided so as to contact the upper surface, lower surface, and side surface at both ends located in the X direction of the semiconductor layer 21. In other words, the semiconductor layer 21 is provided so as to be in contact with both ends thereof so as to fit into grooves (grooves parallel to the Y direction) of the conductive layer 63.

[0213] Here, as illustrated in FIG. 4 , when the conductive layer 24 and the conductive layer 25 have a stacked structure, this can be achieved by first depositing the conductive film by an ALD method or the like, which has high step coverage, and then depositing the subsequent film by a CVD method or the like, which has high embedding properties.

[0214] As the planarization treatment, a CMP (Chemical Mechanical Polishing) method, a dry etching method, or the like can be used.

[0215] Next, a resist mask having a rectangular shape parallel to the X' direction is formed on the mask layer 62 and the conductive layer 63, and regions of the mask layer 62, the plurality of sacrificial layers 61, the plurality of semiconductor layers 21, and the conductive layer 63 that are not covered by the resist mask are removed by etching to form structures extending in the X' direction (FIGS. 8A to 8C). Anisotropic dry etching is preferably used for the etching.

[0216] 8C, for clarity, only one of the multiple structures extending in the X' direction and arranged in the Y direction is shown. The same applies to the subsequent perspective views.

[0217] Next, an island-shaped resist mask is formed on a structure including a mask layer 62 extending in the X' direction, multiple sacrificial layers 61, multiple semiconductor layers 21, and a conductive layer 63, and portions of the structure are removed by etching to process the structure into an island shape ( FIGS. 9A to 9C ). At this time, conductive layers 24 and 25 are formed from the conductive layer 63. Each island-shaped structure extending in the X' direction has a pair of conductive layers 24 located at both ends, a central conductive layer 25, and a pair of stacked bodies having multiple sacrificial layers 61, multiple semiconductor layers 21, and a mask layer 62 between them. The structures are not simply arranged repeatedly in the Y direction, but are formed so as to be offset in the X' direction by the arrangement interval of the mask layers 62.

[0218] Next, an insulating layer 41 is formed to cover the island-shaped structures (FIGS. 10A to 10C). The insulating layer 41 is preferably formed so as to fill the gap between two adjacent structures. After the insulating layer 41 is formed, a planarization process is preferably performed so that the upper surface of the insulating layer 41 is flat.

[0219] Next, a strip-shaped resist mask extending in the Y direction is formed on the insulating layer 41, and the portions of the insulating layer 41 not covered by the resist mask are removed by etching ( FIGS. 11A to 11C ). This forms slits 64 extending in the Y direction. The slits 64 can be provided so as to overlap the mask layer 62. Within the slits 64, the mask layer 62, each sacrificial layer 61, each semiconductor layer 21, and the insulating layer 11 are exposed.

[0220] Next, the mask layer 62 and each sacrificial layer 61 are removed by etching (FIGS. 12A to 12C). It is preferable to use isotropic etching, in which the etching rate for the sacrificial layer 61 is sufficiently faster than that for the semiconductor layer 21. This makes it possible to selectively etch the sacrificial layer 61 between the multiple semiconductor layers 21 stacked in the Z direction, and to provide a gap between the two semiconductor layers 21.

[0221] Subsequently, the insulating layer 22 is formed by a film forming method with high step coverage, typically by ALD.

[0222] The insulating layer 22 is provided to cover the upper surface, the lower surface, and a pair of side surfaces located in the Y direction of the semiconductor layer 21, which are located between the conductive layers 24 and 25. The insulating layer 22 is also provided to cover the exposed surfaces of the conductive layers 24, 25, the insulating layer 41, and the insulating layer 11.

[0223] Next, a conductive film 23f is formed to cover the insulating layer 22 (FIGS. 13A to 13C). The conductive film 23f is formed by a film formation method with high step coverage. The conductive film 23f can be provided so as to fill the slits 64. For example, the conductive film 23f can be formed by the ALD method, the CVD method, or both.

[0224] 13B , the conductive film 23f is preferably formed so as to fill the region between two semiconductor layers 21 stacked in the Z direction. The conductive layer 23f is provided in contact with the insulating layer 22 between at least two semiconductor layers 21. Depending on the film formation conditions for the conductive film 23f, the conductive layer 23 may not be completely filled between the two semiconductor layers 21, resulting in the formation of a void (space).

[0225] Subsequently, the upper portion of the conductive film 23f is removed to separate the conductive film 23f, thereby forming the conductive layer 23 buried in the slit 64 (FIGS. 14A to 14C). At this stage, the transistors 10a and 10b are formed.

[0226] The conductive film 23f can be processed by removing the upper portion thereof using, for example, dry etching or wet etching. Alternatively, a planarization treatment may be performed to remove the upper portion of the conductive film 23f until the upper surface of the insulating layer 22 is exposed, thereby separating the conductive film 23f. When the planarization treatment is performed, the upper portion of the separated conductive layer 23 is further etched by dry etching or wet etching to process the upper surface of the conductive layer 23 so that the height of the upper surface of the conductive layer 23 is lower than the height of the insulating layer 41, which is preferable because the conductive layer 23 can be reliably separated.

[0227] Next, an insulating layer 42 is formed to cover the insulating layer 22 and the conductive layer 23. After that, openings reaching the conductive layer 24 or the conductive layer 25 are formed in the insulating layer 42, the insulating layer 22, and the insulating layer 41, and a conductive film is formed to fill the openings. After that, a planarization process is performed until the top surface of the insulating layer 42 is exposed, thereby forming the connection electrodes 31a, 31b, and 32 ( FIGS. 15A to 15C ).

[0228] Subsequently, a conductive film is formed on the insulating layer 42, and unnecessary portions are removed by etching to form the conductive layer 26 that connects to the connection electrode 32. The conductive layer 26 functions as a bit line, and is provided so as to extend in the X direction.

[0229] Next, an insulating layer 43 is formed to cover the insulating layer 42 and the conductive layer 26. After that, an opening reaching the connection electrode 31a or the connection electrode 31b is formed in the insulating layer 43, a conductive film is formed to fill the opening, and then a planarization process is performed until the upper surface of the insulating layer 43 is exposed, thereby forming the connection electrode 33a and the connection electrode 33b (FIGS. 16A to 16C).

[0230] 1B and other examples can be fabricated by forming a capacitor 50 on the insulating layer 43. The capacitor 50 can be fabricated, for example, by forming a conductive layer 51 on the insulating layer 43 so as to be in contact with the connection electrode 33a or the connection electrode 33b, then forming an insulating layer 52 so as to cover the conductive layer 51, and further forming a conductive layer 53 so as to cover the insulating layer 52. Note that the capacitor 50 is not limited to the configuration exemplified in FIG. 1B and other examples, and various capacitor elements such as a trench capacitor, a pillar capacitor, and a cylinder capacitor can be used.

[0231] The above is a description of an example of the manufacturing method.

[0232] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0233] Embodiment 2 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

[0234] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0235] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0236] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 17A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 17B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0237] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 17B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 17A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 17A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 17A.

[0238] 17A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility can be reduced to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0239] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0240] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0241] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0242] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 17A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0243] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0244] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0245] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0246] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0247] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0248] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0249] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0250] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0251] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0252] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 17C, Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0253] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0254] 17C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0255] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0256] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0257]

[0258] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0259] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0260] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0261] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0262] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0263] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0264] Embodiment 3 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention, which is different from the above embodiment, will be described. The semiconductor device 900 can function as a memory device.

[0265] Fig. 18 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 18 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 18 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0266] The memory cell 950 can be any of the memory devices described in the above embodiments.

[0267] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0268] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0269] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0270] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0271] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0272] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0273] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0274] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0275] The PSW 931 has a function of controlling the supply of VDD to the peripheral circuit 915. The PSW 932 has a function of controlling the supply of VHM to the row driver 923. In this example, the high power supply voltage of the semiconductor device 900 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of the PSW 931 is controlled by a signal PON1, and the on / off of the PSW 932 is controlled by a signal PON2. In FIG. 18 , the number of power domains to which VDD is supplied in the peripheral circuit 915 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0276] 19A to 19H, other examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0277] In the following, when two components are described as being connected, this includes being electrically connected via a circuit element (such as a transistor, a switch, a diode, or a resistor). Electrical connection means that a current can flow between the two components. Note that when two components are connected via a switch or a transistor, this is also included in the term "electrical connection," because a current can flow when these are in the on state.

[0278] 19A shows an example of a circuit configuration of a DRAM memory cell. In this specification and the like, a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). A memory cell 951 includes a transistor M1 and a capacitor CA.

[0279] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring that supplies a constant potential or a signal, or the front gate and the back gate may be connected to each other.

[0280] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0281] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0282] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitor CA into a conductive state (a state in which current can flow).

[0283] Furthermore, the memory cell that can be used for the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 950 may have the configuration of a memory cell 952 as shown in FIG. 19B. The memory cell 952 is an example in which the memory cell 952 does not include a capacitor CA and a wiring CAL. The first terminal of the transistor M1 is in an electrically floating state.

[0284] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0285] Note that an OS transistor is preferably used as the transistor M1. An OS transistor has a characteristic of extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be significantly reduced. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, because the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 951 and the memory cell 952.

[0286] 19C shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a storage device having a gain cell type memory cell in which the transistor M2 is an OS transistor is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0287] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0288] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0289] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0290] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0291] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in FIG. 19D. The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0292] 19E is an example in which the capacitor element CB and the wiring CAL in the memory cell 953 are omitted. Also, the memory cell 956 in Fig. 19F is an example in which the capacitor element CB and the wiring CAL in the memory cell 954 are omitted. With such a configuration, the integration degree of the memory cells can be increased.

[0293] Note that it is preferable to use an OS transistor for at least the transistor M2, and particularly for the transistors M2 and M3.

[0294] Since the OS transistor has an extremely low off-state current, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956.

[0295] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956, in which an OS transistor is used as the transistor M2, are one embodiment of an NOSRAM.

[0296] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0297] When an OS transistor is used as the transistor M3, the memory cell can be configured using only n-channel transistors.

[0298] 19G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 includes transistors M4 to M6 and a capacitor CC.

[0299] The first terminal of transistor M4 is connected to the first terminal of capacitor CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitor CC is connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0300] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0301] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0302] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0303] Note that at least the transistor M4 is preferably an OS transistor.

[0304] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0305] When OS transistors are used as the transistors M5 and M6, the memory cell can be configured using only n-channel transistors.

[0306] 19H shows an example of an SRAM (Static Random Access Memory) using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an OS-SRAM (Oxide Semiconductor-SRAM). Note that a memory cell 958 shown in FIG. 19H is a memory cell of an SRAM capable of backing up data.

[0307] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0308] A first terminal of transistor M7 is connected to wiring BIL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. A first terminal of transistor M8 is connected to wiring BILB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0309] A second terminal of the transistor MS1 is connected to the wiring VDL. A second terminal of the transistor MS2 is connected to the wiring VDL. A second terminal of the transistor MS3 is connected to the wiring GNDL. A second terminal of the transistor MS4 is connected to the wiring GNDL.

[0310] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0311] A second terminal of the capacitance element CD1 is connected to the wiring GNDL, and a second terminal of the capacitance element CD2 is connected to the wiring GNDL.

[0312] The wirings BIL and BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring that controls the on / off states of the transistors M9 and M10.

[0313] The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential.

[0314] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is on, a potential corresponding to information to be written is applied to the wiring BIL, and the potential is written to the second terminal of the transistor M10.

[0315] Since the memory cell 958 includes an inverter loop formed by the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is on, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Because the transistors M9 and M10 are on, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. Then, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0316] The following describes how data is read. First, the wirings BIL and BILB are precharged to a predetermined potential. Next, a high-level potential is applied to the wiring WOL, and a high-level potential is applied to the wiring BRL. At this time, the potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB. The potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL. Since the potentials of the wirings BIL and BILB change from the precharged potentials to the potentials of the first terminals of the capacitor CD2 and the first terminals of the capacitor CD1, respectively, the potential held in the memory cell can be read from the potential of the wiring BIL or the wiring BILB.

[0317] Note that OS transistors are preferably used as the transistors M7 to M10. This allows written data to be held by the transistors M7 to M10 for a long time, which reduces the frequency of refreshing the memory cells. Alternatively, refreshing the memory cells can be eliminated.

[0318] Note that Si transistors may be used as the transistors MS1 to MS4.

[0319] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in FIG. 20A, the driver circuit 910 and memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 20B, the memory array 920 may be provided in multiple layers on the driver circuit 910.

[0320] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0321] 21 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in FIG. 21 can be applied to, for example, a CPU (Central Processing Unit). The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), or an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0322] The arithmetic device 960 shown in FIG. 21 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be provided on separate chips.

[0323] The cache 999 is connected to a main memory provided on a separate chip via a cache interface 989. The cache interface 989 has a function of supplying part of the data held in the main memory to the cache 999. The cache interface 989 also has a function of outputting part of the data held in the cache 999 to the ALU 991, register 996, etc. via the bus interface 998.

[0324] As will be described later, a memory array 920 can be provided by stacking it on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 989 may have a function of supplying data held in the memory array 920 to the cache 999. In this case, it is preferable that a drive circuit 910 be included as part of the cache interface 989.

[0325] It is also possible to use only the memory array 920 as a cache without providing the cache 999 .

[0326] The arithmetic device 960 shown in FIG. 21 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 21 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle via its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0327] An instruction input to the arithmetic unit 960 via the bus interface 998 is input to the instruction decoder 993, decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0328] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 997 generates addresses for registers 996 and performs read and write operations on the registers 996 depending on the state of the arithmetic unit 960.

[0329] Furthermore, the timing controller 995 generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0330] 21 , the register controller 997 selects the holding operation of the register 996 in accordance with an instruction from the ALU 991. That is, it selects whether the memory cells of the register 996 will hold data using flip-flops or using capacitive elements. If holding data using flip-flops is selected, a power supply voltage is supplied to the memory cells in the register 996. If holding data using capacitive elements is selected, the data is rewritten to the capacitive elements, and the supply of power supply voltage to the memory cells in the register 996 can be stopped.

[0331] The memory array 920 and the arithmetic unit 960 can be provided overlapping each other. Perspective views of a semiconductor device 970A are shown in Figures 22A and 22B. The semiconductor device 970A has a layer 930 on which memory arrays are provided above the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic unit 960 and the layer 930 are shown separately in Figure 22B.

[0332] By stacking the layer 930 having the memory array and the arithmetic unit 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0333] As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method (also called monolithic stacking) in which the layer 930 having a memory array is stacked directly on the arithmetic device 960 may be used, or a method in which the arithmetic device 960 and the layer 930 are formed on different substrates, and the two substrates are bonded together and connected using a through-via or conductive film bonding technology (such as Cu-Cu bonding) may be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce manufacturing costs.

[0334] Here, the arithmetic unit 960 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also referred to as a level 1 cache), the memory array 920L2 can be used as an L2 cache (also referred to as a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also referred to as a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0335] When the cache 999 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0336] 22B, a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.

[0337] Although the number of memory arrays functioning as caches is three in this example, the number may be one or two, or four or more.

[0338] When the memory array 920L1 is used as a cache, the driver circuit 910L1 may function as part of the cache interface 989, or may be configured to be connected to the cache interface 989. Similarly, the driver circuits 910L2 and 910L3 may also function as part of the cache interface 989, or may be configured to be connected thereto.

[0339] Whether the memory array 920 is made to function as a cache or as a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the memory cells 950 included in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.

[0340] The semiconductor device 900 can cause some of the memory cells 950 to function as a cache and the other memory cells to function as a main memory. That is, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one embodiment of the present invention can function as, for example, a universal memory.

[0341] Furthermore, a layer 930 having one memory array 920 may be provided over the arithmetic device 960. Figure 23A shows a perspective view of a semiconductor device 970B.

[0342] In the semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for a different function. Figure 23A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0343] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. This configuration can improve the efficiency of calculation processing and increase the processing speed.

[0344] A plurality of memory arrays may be stacked. Figure 23B shows a perspective view of a semiconductor device 970C.

[0345] The semiconductor device 970C includes a layer 930L1 having a memory array 920L1, a layer 930L2 having a memory array 920L2 on top of that, and a layer 930L3 having a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory array to be increased, thereby further improving processing power.

[0346] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0347] Embodiment 4 In this embodiment, an application example of a semiconductor device of one embodiment of the present invention will be described. The semiconductor device of one embodiment of the present invention can be used for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)). Electronic components, electronic devices, mainframes, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0348] [Electronic Component] FIG. 24A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 24A has semiconductor device 710 inside mold 711. FIG. 24A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0349] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0350] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0351] It is also preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, one or both of the memory bandwidth and the memory access latency can be improved. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0352] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0353] 24B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on the interposer 731.

[0354] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), or a field programmable gate array (FPGA).

[0355] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0356] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0357] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0358] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0359] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0360] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0361] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 24B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0362] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0363] 25A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0364] 25B shows a perspective view of an example of a computer 5620. The computer 5620 has a motherboard 5630. The motherboard 5630 is provided with a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0365] Fig. 25C shows an example of a PC card 5621. The PC card 5621 is a processing board equipped with, for example, a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622 and connection terminals 5623, 5624, 5625, electronic components 5626, 5627, 5628, and 5629 mounted on the board 5622. Note that Fig. 25C illustrates components other than electronic components 5626, 5627, and 5628.

[0366] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0367] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0368] The electronic component 5626 has a terminal (not shown) for inputting and outputting signals, and the electronic component 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0369] The electronic components 5627 and 5628 have multiple terminals, and can be mounted on wiring provided on the board 5622 by, for example, reflow soldering the terminals. Examples of the electronic component 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the electronic component 5627. For example, the electronic component 5628 includes a storage device. For example, the electronic component 700 can be used as the electronic component 5628.

[0370] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0371] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

[0372] A semiconductor device according to one embodiment of the present invention includes an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space. Specifically, the OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutrons. Note that outer space refers to an altitude of 100 km or higher, but the outer space described in this specification may include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0373] Fig. 26A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 26A shows a planet 6804 in space as an example.

[0374] 26A , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0375] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0376] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0377] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0378] The control device 6807 has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0379] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0380] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0381] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0382] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. Data centers are required to perform long-term management of data, such as ensuring data immutability. Managing long-term data requires larger buildings, such as installing storage and servers for storing huge amounts of data, ensuring a stable power supply for data retention, or ensuring cooling equipment required for data retention.

[0383] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0384] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0385] Fig. 26B shows a storage system applicable to a data center. The storage system 6000 shown in Fig. 26B has multiple servers 6001sb as hosts 6001 (illustrated as Host Computers). It also has multiple storage devices 6003md as storage 6003 (illustrated as Storage). The host 6001 and storage 6003 are shown connected via a storage area network 6004 (illustrated as SAN: Storage Area Network) and a storage control circuit 6002 (illustrated as Storage Controller).

[0386] The host 6001 corresponds to a computer that accesses data stored in the storage 6003. The hosts 6001 may be connected to each other via a network.

[0387] Although the storage 6003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 6003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0388] The cache memory described above is used in the storage control circuit 6002 and the storage 6003. Data exchanged between the host 6001 and the storage 6003 is stored in the cache memory in the storage control circuit 6002 and the storage 6003, and then output to the host 6001 or the storage 6003.

[0389] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0390] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0391] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0392] 10: transistor, 10a: transistor, 10b: transistor, 10S: structure, 11: insulating layer, 21: semiconductor layer, 21_1: semiconductor layer, 21_2: semiconductor layer, 21_3: semiconductor layer, 21f: semiconductor film, 21f_1: semiconductor film, 21f_2: semiconductor film, 21f_3: semiconductor film, 22: insulating layer, 23: conductive layer, 23f: conductive film, 24: conductive layer, 24_1: conductive layer, 24_2: conductive layer, 24a: conductive layer, 24b: conductive layer, 25: conductive layer, 25_1: conductive layer, 2 5_2: conductive layer, 26: conductive layer, 31: connection electrode, 31a: connection electrode, 31b: connection electrode, 32: connection electrode, 33: connection electrode, 33a: connection electrode, 33b: connection electrode, 41: insulating layer, 42: insulating layer, 43: insulating layer, 50: capacitance element, 50a: capacitance element, 50b: capacitance element, 51: conductive layer, 52: insulating layer, 53: conductive layer, 61: sacrificial layer, 61_1: sacrificial layer, 61_2: sacrificial layer, 61_3: sacrificial layer, 61_4: sacrificial layer, 62: mask layer, 63: conductive layer, 64: slit

Claims

a first insulating layer; and a second semiconductor layer. the first conductive layer and the second conductive layer are provided apart from each other, the first conductive layer has a first side facing the second conductive layer; the second conductive layer has a second side surface opposite to the first side surface; the first side surface and the second side surface each have a first groove portion and a second groove portion located above the first groove portion, the first semiconductor layer is provided to fit into a pair of the first grooves formed in the first side surface and the second side surface, respectively; the second semiconductor layer is provided to fit into a pair of the second grooves formed in the first side surface and the second side surface, respectively; the third conductive layer has a portion surrounding an upper surface, a lower surface, and a pair of side surfaces of the first semiconductor layer and the second semiconductor layer between the first conductive layer and the second conductive layer; the first insulating layer has portions located between the first conductive layer and the third conductive layer, between the second conductive layer and the third conductive layer, between the first semiconductor layer and the third conductive layer, and between the second semiconductor layer and the third conductive layer, Semiconductor device. 　 The semiconductor device includes first to n-th (n is 2 or more) semiconductor layers, first to third conductive layers, and a first insulating layer, the first conductive layer and the second conductive layer are provided apart from each other, the first conductive layer has a first side facing the second conductive layer; the second conductive layer has a second side surface opposite to the first side surface; the first side surface and the second side surface each have first to n-th grooves arranged at intervals in a height direction, the kth (k is an integer of 1 to n) semiconductor layer is provided so as to fit into a pair of the kth grooves formed in the first side surface and the second side surface, respectively; the third conductive layer has portions that surround an upper surface, a lower surface, and a pair of side surfaces of each of the first to nth semiconductor layers between the first conductive layer and the second conductive layer, the first insulating layer has portions located between the first conductive layer and the third conductive layer, between the second conductive layer and the third conductive layer, and between the first to n-th semiconductor layers and the third conductive layer, respectively; Semiconductor device. 　 In claim 1, the first semiconductor layer and the second semiconductor layer overlap each other; Semiconductor device. 　 In claim 1, a fourth conductive layer and a first connection electrode; the fourth conductive layer is located on the second conductive layer; the fourth conductive layer and the second conductive layer are connected via the first connection electrode, the fourth conductive layer extends in a first direction; the third conductive layer extends in a second direction perpendicular to the first direction; Semiconductor device. 　 In claim 4, a capacitance element and a second connection electrode; the capacitive element is located above the fourth conductive layer, one electrode of the capacitance element and the first conductive layer are connected via the second connection electrode; the second connection electrode is provided at a position that overlaps the first conductive layer but does not overlap the fourth conductive layer in a plan view; Semiconductor device. 　 In claim 1, the first semiconductor layer and the second semiconductor layer contain a metal oxide; Semiconductor device. In claim 1, the first semiconductor layer and the second semiconductor layer contain indium oxide; Semiconductor device. 　 forming a first sacrificial layer, a first semiconductor film, a second sacrificial layer, a second semiconductor film, and a third sacrificial layer in order; forming a mask layer on the third sacrificial layer; removing portions of the first sacrificial layer, the first semiconductor film, the second sacrificial layer, the second semiconductor film, and the third sacrificial layer that are not covered by the mask layer; recessing side surfaces of the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer to form a first semiconductor layer and a second semiconductor layer each having a pair of protrusions; forming a first conductive layer in contact with one of the pair of protruding portions of each of the first semiconductor layer and the second semiconductor layer, and a second conductive layer in contact with the other of the pair of protruding portions; removing the mask layer, and the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer; forming a first insulating layer between the first conductive layer and the second conductive layer, the first insulating layer covering the upper surface, the lower surface, and the side surface of the first semiconductor layer and the second semiconductor layer; forming a third conductive layer surrounding the upper surface, the lower surface, and the side surface of each of the first semiconductor layer and the second semiconductor layer via the first insulating layer; A method for manufacturing a semiconductor device.

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