Delta-sigma modulator

Abstract

In the present invention, in a first step, a first adder generates a first addition signal by adding a signal obtained by amplifying an analog signal with a first gain and a signal obtained by amplifying a first feedback analog signal with a second gain. A first integration circuit generates and outputs a first integration signal by integrating the first addition signal, and a second integration circuit generates and outputs a second integration signal by integrating a signal obtained by amplifying the first integration signal with a third gain. In a second step, the first adder generates a second addition signal by adding a signal obtained by amplifying a second feedback analog signal with a fourth gain and a signal obtained by amplifying the second integration signal with a fifth gain. An operational amplifier is shared by the first integration circuit and the second integration circuit. When the number of quantization levels of a quantizer is three, the fourth gain / the fifth gain = the second gain × the third gain. When the number of quantization levels of the quantizer is two, the fourth gain / the fifth gain = 4 × the second gain × the third gain.

Description

Delta-Sigma Modulator

[0001] The present invention relates to a delta-sigma modulator.

[0002] Patent Document 1 below discloses a technique in which a fully differential amplifier is shared by multiple stages of integrating circuits in a ΔΣ modulator.

[0003] JP 2016-184792 A

[0004] However, the technology of Patent Document 1 cannot be applied to a ΔΣ modulator that can operate as both a second-order incremental AD converter and a first-order incremental AD converter.

[0005] Therefore, in the past, in a ΔΣ modulator that can operate as both a second-order incremental AD converter and a first-order incremental AD converter, it was necessary to provide an operational amplifier for each of the two integrating circuits, making it impossible to reduce the circuit area and power consumption.

[0006] A ΔΣ modulator according to one embodiment includes an input terminal to which an analog signal is input, an output terminal to which a digital signal is output, a first integrator circuit, a second integrator circuit provided downstream of the first integrator circuit, a first adder provided on the input side of the first integrator circuit, a second adder provided on the output side of the second integrator circuit, a quantizer, and a digital-to-analog converter. In a first step, the digital-to-analog converter converts the first digital signal output from the quantizer into a first feedback analog signal, and the first adder amplifies the analog signal by a first gain. the first integration circuit integrates the first integration signal to generate and output a first integration signal; the second integration circuit integrates the first integration signal to generate and output a second integration signal; the second adder outputs a first signal to the quantizer, the first signal being generated by amplifying the analog signal, the first integration signal, and the second integration signal, each with a predetermined gain, and then adding them together; the quantizer outputs a first signal to the quantizer; , converting the first signal into a first digital signal and outputting it to an output terminal; in a second step after the first step, the digital-to-analog converter converts the second digital signal output from the quantizer into a second feedback analog signal; the second integrator circuit outputs a fourth integrated signal; the first adder generates a second summed signal by adding a signal obtained by amplifying the second feedback analog signal with a fourth gain and a signal obtained by amplifying the fourth integrated signal with a fifth gain; and the first integrator circuit generates a third integrated signal by integrating the second summed signal. The first integration circuit and the second integration circuit have an operational amplifier shared by each of the first and second integration circuits, and the operational amplifier satisfies the following relationship: fourth gain / fifth gain=second gain×third gain when the quantizer has three quantization levels; and fourth gain / fifth gain=4×second gain×third gain when the quantizer has two quantization levels.

[0007] According to one embodiment of a ΔΣ modulator, a ΔΣ modulator that can operate as both a second-order incremental AD converter and a first-order incremental AD converter can achieve a reduced circuit area and low power consumption, and can obtain conversion results with low error.

[0008] A block diagram showing an example of the functional configuration of a ΔΣ modulator in the first step of one embodiment.A block diagram showing an example of the functional configuration of a ΔΣ modulator in the second step of one embodiment.A diagram showing an example of the circuit configuration of a ΔΣ modulator in one embodiment.A timing chart showing an example of the operation timing of each control signal in a ΔΣ modulator in one embodiment.A diagram showing an example of the circuit state during the first operation Φ1 in the first step of a ΔΣ modulator in one embodiment.A diagram showing an example of the circuit state during the second operation Φ2 in the first step of a ΔΣ modulator in one embodiment.A diagram showing an example of the circuit state during the first operation Φ1 in the second step of a ΔΣ modulator in one embodiment.A diagram showing an example of the circuit state during the second operation Φ2 in the second step of a ΔΣ modulator in one embodiment.

[0009] Hereinafter, an embodiment will be described with reference to the drawings.

[0010] (Functional Configuration of ΔΣ Modulator 100) FIG. 1 is a block diagram showing an example of the functional configuration of a ΔΣ modulator 100 according to an embodiment in the first step. FIG. 2 is a block diagram showing an example of the functional configuration of a ΔΣ modulator 100 according to an embodiment in the second step. The ΔΣ modulator 100 shown in FIGS. 1 and 2 can convert an analog signal (e.g., an output signal from a current detection resistor, a sensor, etc.) into a digital signal. As shown in FIGS. 1 and 2, the ΔΣ modulator 100 has different functional configurations in the first step and the second step.

[0011] 1 and 2, the ΔΣ modulator 100 includes input terminals Vin+ and Vin−, an output terminal Q, a first integrating circuit 10, a second integrating circuit 20, a second adder 30, a quantizer 40, and a digital-to-analog converter DAC. The first integrating circuit 10 includes a first adder 11 and a delay integrator 12. The second integrating circuit 20 includes a switch 21 and a delay-free integrator 22.

[0012] 1 and 2 show a relationship between each of the multiple gains used to amplify each signal and each capacitance in the circuit configuration shown in Fig. 3. That is, each of the multiple gains shown in Fig. 1 and 2 is determined by each capacitance in the circuit configuration shown in Fig. 3.

[0013] An analog signal U (for example, an output signal from a current detection resistor, a sensor, etc.) is input to the input terminals Vin+ and Vin-.

[0014] The output terminal Q is connected to the output side of the quantizer 40. In the first step, the output terminal Q outputs the first digital signal V1 output from the quantizer 40, and in the second step, the output terminal Q outputs the second digital signal V2 output from the quantizer 40. The output signal from the output terminal Q is output to, for example, a digital filter (not shown).

[0015] The digital-to-analog converter DAC is connected between the output side of the quantizer 40 and the output terminal Q. As shown in Fig. 1, in a first step, the digital-to-analog converter DAC converts the first digital signal V1 output from the quantizer 40 into a first feedback analog signal UF1 and outputs the first feedback analog signal UF1. As shown in Fig. 2, in a second step, the digital-to-analog converter DAC converts the second digital signal V2 output from the quantizer 40 into a second feedback analog signal UF2 and outputs the second feedback analog signal UF2.

[0016] The first adder 11 is provided on the input side of the delay integrator 12 .

[0017] As shown in FIG. 1 , in the first step, the first adder 11 generates a first sum signal X0 by adding a signal obtained by amplifying an analog signal U input from input terminals Vin+ and Vin− with a first gain b1 and a signal obtained by amplifying a first feedback analog signal UF1 output from the digital-to-analog converter DAC with a second gain c1, and outputs the first sum signal X0 to the delay integrator 12. Note that the first gain b1 is determined by the capacitance of capacitor Cs1 / capacitor Cf1 in the circuit configuration shown in FIG. 3 , and the second gain c1 is determined by the capacitance of capacitor Cdac / capacitor Cf1. The first adder 11 has an output terminal to which multiple signal lines are connected, and may be a circuit that controls signals input to the multiple signal lines using, for example, a switch.

[0018] As shown in FIG. 2 , in the second step, the first adder 11 generates a second sum signal X0′ by adding together a signal obtained by amplifying the second feedback analog signal UF2 output from the digital-to-analog converter DAC with a fourth gain c1′ and a signal obtained by amplifying the fourth integration signal X2′ output from the second integration circuit 20 with a fifth gain b1′, and outputs the second sum signal X0′ to the delay integrator 12.

[0019] The delay integrator 12 is provided at the subsequent stage of the first adder 11 .

[0020] As shown in FIG. 1, in the first step, the delay integrator 12 generates a first integrated signal X1 by integrating the first sum signal X0 output from the first adder 11, and outputs the first integrated signal X1.

[0021] Also, as shown in FIG. 2, in the second step, the first integration circuit 10 generates a third integration signal X1' by integrating the second sum signal X0' output from the first adder 11, and outputs the third integration signal X1'.

[0022] The switch 21 is provided between the delay integrator 12 and the no-delay integrator 22. As shown in Fig. 1, in a first step, the switch 21 is switched on. As shown in Fig. 2, in a second step, the switch 21 is switched off.

[0023] The non-delay integrator 22 is provided at the subsequent stage of the delay integrator 12 .

[0024] As shown in FIG. 1, in the first step, the delay-free integrator 22 receives a signal obtained by amplifying the first integrated signal X1 output from the delay integrator 12 by a third gain c2, integrates the signal, and generates a second integrated signal X2. The delay-free integrator 22 then outputs the second integrated signal X2 to the second adder 30.

[0025] 2, in the second step, the switch 21 is turned off, and therefore the non-delay integrator 22 does not receive a signal from the delay integrator 12. Instead, the non-delay integrator 22 functions as a hold amplifier that holds a signal proportional to the quantization error E of the first step (the error generated when the quantizer 40 converts the first signal S1 into the first digital signal V1 in the first step). The non-delay integrator 22 generates a fourth integrated signal X2' as the quantization error of the first step and outputs the second integrated signal X2' to the second adder 30. As will be described later in the description of FIG. 4, in the second step, M2 consecutive operations are performed. That is, in the second step, the fourth integrated signal X2' output from the second integration circuit is the same in all M2 operations performed in the second step.

[0026] The second adder 30 is provided at the subsequent stage of the delayless integrator 22. The second adder 30 outputs an output signal generated by adding a plurality of signals to the quantizer 40.

[0027] As shown in FIG. 1, in the first step, the second adder 30 generates a first signal S1 by adding the analog signal U amplified by the gain b3, the first integrated signal X1 amplified by the gain a1, and the second integrated signal X2 amplified by the gain a2, and outputs the first signal S1 to the quantizer 40.

[0028] Also, as shown in FIG. 2, in the second step, the second adder 30 generates a second signal S2 by adding the fourth integrated signal X2′ amplified by the gain a2′ and the third integrated signal X1′ amplified by the gain a1′, and outputs the second signal S2 to the quantizer 40.

[0029] 1, in the first step, a signal Sth that changes the threshold level of the first digital signal V1 output from the quantizer 40 is input to the second adder 30. The signal Sth is a signal obtained by amplifying the reference voltage VREF by a sixth gain Kth. Also, as shown in FIG. 2, in the second step, a signal Sth' that changes the threshold level of the second digital signal V2 output from the quantizer 40 is input to the second adder 30. The signal Sth' is a signal obtained by amplifying the reference voltage VREF by a seventh gain Kth'.

[0030] The quantizer 40 is provided after the second adder 30 .

[0031] 1, in the first step, the quantizer 40 converts the first signal S1 output from the second adder 30 into a first digital signal V1 of, for example, three levels (−1, 0, +1), and outputs the first digital signal V1 to an output terminal Q. The threshold value of this quantization level can be changed by a signal Sth.

[0032] 2, in the second step, the quantizer 40 converts the second signal S2 output from the second adder 30 into a second digital signal V2 of, for example, three levels (−1, 0, +1), and outputs the second digital signal V2 to the output terminal Q. The threshold value of this quantization level can be changed by the signal Sth′.

[0033] Although not shown, the ΔΣ modulator 100 further includes a control unit. For example, the control unit is configured by a digital circuit (ASIC). The control unit switches the switch 21 on and off, resets the delay integrator 12, and resets the no-delay integrator 22. The control unit may also be configured by a microcontroller (MCU).

[0034] (Circuit Configuration of the ΔΣ Modulator 100) FIG. 3 is a diagram showing an example of the circuit configuration of the ΔΣ modulator 100 according to an embodiment.

[0035] As shown in FIG. 3, in the ΔΣ modulator 100, the first integrating circuit 10, the second integrating circuit 20, the second adder 30, and the digital-to-analog converter DAC each include a plurality of switches.

[0036] Specifically, the first integrating circuit 10 includes switches SW11 to SW16, the second integrating circuit 20 includes switches SW22 to SW27, the second adder 30 includes switches SW31 to SW39, and the digital-to-analog converter DAC includes switches SW41 to SW45.

[0037] In Fig. 3, the switch marked with "Φ1" is a switch that is turned on during a first operation Φ1 in Fig. 4, which will be described later. Also, in Fig. 3, the switch marked with "Φ2" is a switch that is turned on during a second operation Φ2 in Fig. 4, which will be described later.

[0038] In addition, in Fig. 3, the switch indicated by "S1·Φ1" is a switch that is switched on during a first operation Φ1 in the first step in Fig. 4, which will be described later. In addition, in Fig. 3, the switch indicated by "S1·Φ2" is a switch that is switched on during a second operation Φ2 in the first step in Fig. 4, which will be described later.

[0039] 3, the switch marked "S2·Φ1" is a switch that is turned on during the first operation Φ1 in the second step of FIG. 4, which will be described later. Also, the switch marked "S2·Φ2" in FIG. 3 is a switch that is turned on during the second operation Φ2 in the second step of FIG. 4, which will be described later. Here, the switch SW22 in FIG. 3 corresponds to the switch 21 in FIGS. 1 and 2.

[0040] The first integrating circuit 10 has a first variable capacitor Cs1 and a third variable capacitor Cf1, and the digital-to-analog converter DAC has a second variable capacitor Cdac.

[0041] The second integrating circuit 20 also includes a capacitor Cs2 and a capacitor Cf2.

[0042] The capacitor Cf2 is an example of a configuration that holds the charge of the eighth capacitance, and can continue to hold the fourth integrated signal output from the second integration circuit 20 in the second step.

[0043] The second adder 30 also has a capacitor Cb3 and a capacitor Ca1a2. The second adder 30 also has a threshold setting circuit 31, which has a capacitor Cth and switches SW36 and SW37. The second adder 30 also has an anti-kickback circuit 32, which has a capacitor Chold and switches SW38 and SW39.

[0044] To explain each circuit configuration in detail, the first integrating circuit 10 has a capacitor Cs1, a switch SW13, a capacitor Cf1, and a switch SW14 provided in this order on the output side of a switch SW11 to which the output of the second integrating circuit 20 is input, and a switch SW12 to which the input voltage Vin is input. A switch SW15 is provided between the switches SW11 and SW12 and the capacitor Cs1. A voltage V ＩＣＭ The output of the digital-to-analog converter DAC and the input terminal of the operational amplifier OP are connected between the switch SW13 and the capacitor Cf1, and the output side of the switch SW14 is connected to the output terminal of the operational amplifier OP.

[0045] In the second integrating circuit 20, a capacitor Cs2 is connected to the output side of a switch SW22 to which the output of the first integrating circuit 10 is input. A switch SW23 to which a voltage Vcm is input is provided between the switch SW22 and the capacitor Cs2. A switch SW26, a capacitor Cf2, and a switch SW27 are provided in this order on the output side of the capacitor Cs2. A voltage Vcm is input between the capacitor Cs2 and the switch SW26. ＩＣＭAn input terminal of an operational amplifier OP is connected between the switch SW26 and the capacitor Cf2, and an output terminal of the operational amplifier OP is connected to the output side of the switch SW27.

[0046] The digital-to-analog converter DAC also uses a reference voltage V Ｒ A second variable capacitor Cdac is provided on the output side of the switches SW41 and SW42 to which a reference voltage VREF (reference voltage VREF in FIGS. 1 and 2) is input. Also, switches SW44 and SW45 are provided on the output side of the second variable capacitor Cdac. Also, a voltage VREF is provided between the second variable capacitor Cdac and the switches SW44 and SW45. ＩＣＭ A switch SW43 is provided to which the signal is input.

[0047] The second adder 30 calculates the reference voltage V Ｒ A capacitor Cth is provided on the output side of switches SW36 and SW37 to which a reference voltage VREF (see FIGS. 1 and 2) is input. A capacitor Cb3 is provided on the output side of switch SW31 to which input voltage Vin is input. A switch SW32 to which voltage Vcm is input is provided between switch SW31 and capacitor Cb3. A capacitor Ca1a2 is provided on the output side of switch SW33 to which the output of second integrating circuit 20 is input, and switch SW34 to which the output of first integrating circuit 10 is input. A kickback prevention circuit 32 is connected to the output sides of capacitors Cth, Cb3, and Ca1a2. A switch SW35 to which voltage Vcm is input is provided between capacitors Cth, Cb3, and Ca1a2 and the kickback prevention circuit 32.

[0048] 3, the delta-sigma modulator 100 has the same circuit configuration on the side where Vin+ is input (upper side in the figure) and the side where Vin- is input (lower side in the figure). That is, each of the side where Vin+ is input (upper side in the figure) and the side where Vin- is input (lower side in the figure) has the above-mentioned multiple switches and the above-mentioned multiple capacitors. Therefore, the delta-sigma modulator 100 performs the same signal processing at the same timing on the side where Vin+ is input (upper side in the figure) and the side where Vin- is input (lower side in the figure), except that the input voltage Vin is positive or negative.

[0049] As shown in FIG. 3, the ΔΣ modulator 100 according to one embodiment has an operational amplifier OP shared by the first integrating circuit 10 and the second integrating circuit 20 .

[0050] Specifically, the first integrating circuit 10 is composed of switches SW11 to SW16, a first variable capacitor Cs1, a third variable capacitor Cf1, and a shared operational amplifier OP.

[0051] The second integrating circuit 20 is composed of switches SW22 to SW27, a capacitor Cs2, a capacitor Cf2, and a shared operational amplifier OP.

[0052] As a result, the delta-sigma modulator 100 according to one embodiment can reduce the number of operational amplifiers for the integration circuits, which in conventional delta-sigma modulators must be provided for each integration circuit, to just one. Therefore, the delta-sigma modulator 100 according to one embodiment can achieve reduced circuit area and power consumption in the delta-sigma modulator 100 that can operate as both a second-order incremental AD converter and a first-order incremental AD converter.

[0053] In particular, the ΔΣ modulator 100 of one embodiment can be applied to an incremental ADC in a configuration in which the number of operational amplifiers for the integration circuit is one, thereby achieving the advantages of incremental ADCs, such as simplified digital filters and reduced conversion time, and thus enabling further reduction in current consumption in such incremental ADCs.

[0054] Furthermore, the ΔΣ modulator 100 of one embodiment is provided with a first variable capacitor Cs1, a second variable capacitor Cdac, and a third variable capacitor Cf1 so as to satisfy the mathematical formula (2) described below, and the capacitance of each of these variable capacitors can be changed between a first step and a second step.

[0055] Specifically, in the ΔΣ modulator 100 according to one embodiment, the capacitance of the first variable capacitor Cs1 is variable between a first capacitance Cs1 and a second capacitance Cs1′. The capacitance of the second variable capacitor Cdac is variable between a third capacitance Cdac and a fourth capacitance Cdac′. The capacitance of the third variable capacitor Cf1 is variable between a fifth capacitance Cf1 and a sixth capacitance Cf1′.

[0056] Furthermore, in the delta-sigma modulator 100 according to one embodiment, the second integrating circuit 20 includes a seventh capacitor Cs2 and an eighth capacitor Cf2.

[0057] In the ΔΣ modulator 100 according to one embodiment, the second gain c1 in the first step is proportional to the third capacitance Cdac / the fifth capacitance Cf1, as shown in Fig. 1. Also, the third gain c2 in the first step is proportional to the seventh capacitance Cs2 / the eighth capacitance Cf2, as shown in Fig. 1.

[0058] 2, the fourth gain c1' in the second step is proportional to the fourth capacitance Cdac' / sixth capacitance Cf1'. Also, the fifth gain b1' in the second step is proportional to the second capacitance Cs1' / sixth capacitance Cf1'.

[0059] Therefore, in the delta-sigma modulator 100 according to one embodiment, by appropriately setting each of the first capacitance Cs1, the second capacitance Cs1′, the third capacitance Cdac, the fourth capacitance Cdac′, the fifth capacitance Cf1, the sixth capacitance Cf1′, the seventh capacitance Cs2, and the eighth capacitance Cf2, it is possible to satisfy the formula (2) described below, and thus to obtain a conversion result with small error. Note that the symbols of the capacitors in the calculation formulas for each gain shown in FIGS. 1 and 2 are the same as those described above.

[0060] (Operation of the ΔΣ Modulator 100) Hereinafter, an example of the operation of the ΔΣ modulator 100 according to one embodiment will be described with reference to FIGS.

[0061] (Operation of the ΔΣ Modulator 100) FIG. 4 is a timing chart showing the operation timing of each control signal in the ΔΣ modulator 100 according to one embodiment.

[0062] As shown in Figure 4, in the first step, when the ΔΣ modulator 100 operates as a second-order incremental AD converter, it outputs one output signal with a first operation Φ1 and a second operation Φ2. Here, the first operation Φ1 and the second operation Φ2 together constitute one cycle. That is, the first step is performed M1 consecutive cycles (where M1 is a natural number). The first cycle 0 is an initial operation, in which the first integrating circuit 10 and the second integrating circuit 20 are reset, etc.

[0063] To simplify the explanation of the operation, the amplification factor for the output of each integrating circuit is omitted. In the first step, the switch 21 is turned on. Then, in the first step, in the first operation Φ1, the first integrating circuit 10 samples a signal obtained by adding the input voltage Vin of the analog signal U and the first feedback analog signal UF1 output from the digital-to-analog converter DAC. The second integrating circuit 20 performs an integration operation using the output of the first integrating circuit 10 sampled in the previous second operation Φ2. The second adder 30 then adds the input voltage Vin and the output of the second integrating circuit 20 to the output of the first integrating circuit 10 sampled in the previous second operation Φ2. Furthermore, the second adder 30 receives a signal Sth that determines the quantization level threshold, thereby generating a first signal S1, which is then output to the quantizer 40. The output of the first integrating circuit 10, which is input to the second integrating circuit 20 in cycle 1, is reset in cycle 0, and 0V is output.

[0064] In the first step, in the second operation Φ2, the first integrator circuit 10 performs an integration operation, and the second adder 30 and the second integrator circuit 20 sample the output of the first integrator circuit 10 .

[0065] As shown in FIG. 4, in the first step, the first integrating circuit 10 and the second integrating circuit 20 are reset by the first reset signal reset1 in the 0th cycle.

[0066] As described above, in the first step, in each of the M1 cycles, during the first operation Φ1, the second adder 30 outputs the first signal S1 to the quantizer 40. Therefore, in the first step, M1 digital signals V1 are obtained from the quantizer 40.

[0067] Also, as shown in Figure 4, in the second step in which the ΔΣ modulator 100 operates as a first-order incremental AD converter, it has M2 consecutive cycles (where M2 is a natural number), and each cycle includes a first operation Φ1 and a second operation Φ2.

[0068] In the second step, the switch 21 is turned off. In the first operation Φ1 of cycle 1, the second integrator circuit 20 performs an integration operation using the output of the first integrator circuit 10 in the second operation Φ2 of the first step. Then, in the second operation Φ2 of cycle 1, the second integrator circuit 20 does not perform sampling because the switch 21 is turned off. In subsequent cycles, the second integrator circuit 20 performs an integration operation without sampling, resulting in a hold operation to hold the output result. In the first operation Φ1 of the second step, the first integrator circuit 10 samples a signal obtained by adding the held output of the second integrator circuit 20 to the first feedback analog signal UF1 output from the digital-to-analog converter DAC, and the second adder 30 adds the held output of the second integrator circuit 20 to the output of the first integrator circuit 10 sampled in the previous second operation Φ2. Furthermore, a signal Sth′ that determines the threshold value of the quantization level is added to the second adder 30 to generate a second signal S 2 , which is then output to the quantizer 40 .

[0069] In the second step, in the second operation Φ2, the first integrator circuit 10 performs an integration operation, the second integrator circuit 20 does not perform sampling, and the second adder 30 samples the output of the first integrator circuit 10.

[0070] Also, as shown in FIG. 4, in the second step, the first integrating circuit 10 is reset by the second reset signal reset2 in the 0th cycle.

[0071] As described above, in the second step, during the first operation Φ1, the second adder 30 outputs the second signal S2 to the quantizer 40 in each of the M2 cycles. Therefore, in the second step, M2 second digital signals V2 are obtained from the quantizer 40.

[0072] Here, the output of the second integrating circuit 20 at the first clock in the second step is expressed by the following equation (1), and the quantization error E1 in the first step is multiplied by −c1c2 and output.

[0073]

[0074] In other words, since the input full scale in the second step is c1c2 times, the applicants have found that it is preferable to set the relationship between the fourth gain c1' and fifth gain b1' in the second step and the second gain c1 and third gain c2 in the first step so that it satisfies the following formula (2) when the quantizer has 3 quantization levels, and the following formula (3) when the quantizer has 2 quantization levels. Note that the quantization level is the number of values ​​to be output, with level 2 outputting a binary digital value of (-1, +1) and level 3 outputting a ternary digital value of (-1, 0, +1).

[0075]

[0076]

[0077] Therefore, in one embodiment of the ΔΣ modulator 100, the fourth gain c1' and fifth gain b1' of the second step and the second gain c1 and third gain c2 of the first step are each set so as to satisfy the above formula (2) or the above formula (3).

[0078] As a result, the delta-sigma modulator 100 according to one embodiment satisfies the above formula (2) or (3), and is therefore able to obtain a conversion result with a small error.

[0079] <At the Time of First Operation Φ1 in the First Step> FIG. 5 is a diagram showing an example of the state of the circuit at the time of the first operation Φ1 in the first step of the ΔΣ modulator 100 according to one embodiment.

[0080] As shown in FIG. 5, during the first operation Φ1 in the first step operating as a second-order incremental AD converter, switches SW12, SW16, SW23, SW26, SW27, SW31, SW33, SW37, SW38, SW42, and SW43 are turned on.

[0081] At this time, in the first integrating circuit 10, the switches SW12 and SW16 are turned on, and the analog signal U input from the input terminal Vin+ is sampled by the first variable capacitor Cs1.

[0082] At this time, in the second integration circuit 20, the switches SW23, SW26, and SW27 are turned on, so that the charge in the capacitor Cs2 is transferred to the capacitor Cf2 and an integration operation is performed.

[0083] <At the Time of Second Operation Φ2 in the First Step> FIG. 6 is a diagram showing an example of the state of the circuit at the time of the second operation Φ2 in the first step of the ΔΣ modulator 100 according to one embodiment.

[0084] As shown in Fig. 6, during the second operation Φ2 in the first step operating as a second-order incremental AD converter, switches SW13, SW14, SW15, SW22, SW25, SW32, SW34, SW35, SW36, SW39, and SW41 are switched on. Also, SW44 and SW45 are selectively switched on by the quantizer output Q. Specifically, as the calculation circuit 46 shows the result of calculating the quantizer output Q, the result of ANDing Q[0] and Q[1] is calculated as Q. ＋１ , the result of AND operation of barQ[0] and barQ[1] is Q －１ Let's say. ＋１ When is at high level, SW44 is turned on and Q －１is at a high level, the SW45 is turned on. Note that "bar" means negative logic.

[0085] At this time, in the first integration circuit 10, the switches SW15, SW13, and SW14 are turned on, so that the charge in the first variable capacitor Cs1 is transferred to the third variable capacitor Cf1, and an integration operation is performed.

[0086] Also, at this time, in the first integrating circuit 10, switch SW14 is turned on, and in the second integrating circuit 20, switches SW22 and SW25 are turned on, so that the output of the first integrating circuit 10 is sampled by capacitor Cs2 of the second integrating circuit 20.

[0087] <At the Time of First Operation Φ1 in the Second Step> FIG. 7 is a diagram showing an example of the state of the circuit at the time of the first operation Φ1 in the second step of the ΔΣ modulator 100 according to one embodiment.

[0088] As shown in FIG. 7, during the first operation Φ1 in the second step operating as a primary incremental AD converter, switches SW11, SW16, SW23, SW26, SW27, SW33, SW37, SW38, SW42, and SW43 are turned on.

[0089] At this time, the switch SW27 is turned on in the second integration circuit 20, and the switches SW11 and SW16 are turned on in the first integration circuit 10, so that the output of the second integration circuit 20 is sampled by the first variable capacitor Cs1. Here, the output of the second integration circuit 20 (fourth integration signal X2′) is the result of the hold operation of the second integration circuit 20, and is therefore the same in all M2 cycles of the second step.

[0090] At this time, in the second integration circuit 20, the switches SW23, SW26, and SW27 are turned on, so that the charge sampled in the capacitor Cs2 is transferred to the capacitor Cf2, and an integration operation is performed. However, as will be described later, during the second operation Φ2 in the second step, nothing is sampled in the capacitor Cs2, so no charge is transferred to Cf2, and a hold operation is performed in which the charge on Cf2 is held constant.

[0091] The second integrator circuit 20 integrates the first integrated signal X1 output by the first integrator circuit 10 in the second operation Φ2 of the M1th time in the first step, and the signal amplified by the third gain c2 in the first operation Φ1 of the second step, to generate and output a fourth integrated signal X2'. This signal is held in the capacitor Cf2. Next, the first integrator circuit 10 integrates the signal held in the capacitor Cf2 (the fourth integrated signal X2') in the first operation Φ1 after cycle 1 in the second step, and the signal amplified by the fifth gain b1' in the second operation Φ2, to generate and output a third integrated signal X1'.

[0092] In the second step, the control unit changes the capacitance of each of the first variable capacitor Cs1, the second variable capacitor Cdac, and the third variable capacitor Cf1 (the areas surrounded by dotted lines in the figure) so as to satisfy the above formula (2) or (3). As a result, according to the ΔΣ modulator 100 of one embodiment, the relationship between the fourth gain c1′ and the fifth gain b1′ used in the second step and the second gain c1 and the third gain c2 used in the first step can satisfy the above formula (2) or (3), thereby making it possible to obtain a conversion result with a small error.

[0093] <At the Time of Second Operation Φ2 in the Second Step> FIG. 8 is a diagram showing an example of the state of the circuit at the time of the second operation Φ2 in the second step of the ΔΣ modulator 100 according to one embodiment.

[0094] 8, during the second operation Φ2 in the second step operating as a primary incremental AD converter, switches SW13, SW14, SW15, SW25, SW34, SW35, SW36, SW39, and SW41 are switched on. Also, SW44 and SW45 are selectively switched on by the quantizer output Q. Specifically, as the calculation circuit 46 shows the result of calculating the quantizer output Q, the result of ANDing Q[0] and Q[1] is calculated as Q. ＋１ , the result of AND operation of barQ[0] and barQ[1] is Q －１ Let's say. ＋１ When is at high level, SW44 is turned on and Q －１ is at a high level, the SW45 is turned on. Note that "bar" means negative logic.

[0095] At this time, in the first integration circuit 10, the switches SW15, SW13, and SW14 are turned on, so that the charge in the first variable capacitor Cs1 is transferred to the third variable capacitor Cf1, and an integration operation is performed.

[0096] At this time, the switch SW22 remains off in the second integration circuit 20, and nothing is sampled onto the capacitor Cs2. Therefore, in the second step, the capacitor Cf2 continues to hold the output of the second integration circuit 20 (the fourth integration signal X2′).

[0097] As shown in Figures 6 and 8, in both the first step and the second step, during the second operation Φ2, the second adder 30 samples the output of the first integration circuit 10 by switching on the switches SW34 and SW35.

[0098] 5 , during the first operation Φ1 in the first step, the second adder 30 receives the input voltage Vin as a result of the switch SW31 being turned on, and receives the output of the second integrating circuit 20 as a result of the switch SW33 being turned on. The second adder 30 adds the output of the first integrating circuit 10, the input voltage Vin, and the output of the second integrating circuit 20, and outputs the result to the quantizer 40.

[0099] 7 , during the first operation Φ1 in the second step, the switch SW33 is turned on, and the output of the second integrating circuit 20 is input to the second adder 30. The second adder 30 then adds the output of the first integrating circuit 10 and the output of the second integrating circuit 20, and outputs the result to the quantizer 40.

[0100] Although one embodiment of the present invention has been described in detail above, the present invention is not limited to these embodiments, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims.

[0101] This international application claims priority based on Japanese Patent Application No. 2024-111310, filed on July 10, 2024, the entire contents of which are incorporated herein by reference.

[0102] 100 ΔΣ modulator Vin+, Vin− Input terminal U Analog signal Q Output terminal 10 First integrator circuit 11 First adder 12 Delay integrator 20 Second integrator circuit 21 Switch 22 Delay-free integrator 30 Second adder 40 Quantizer DAC Digital-to-analog converter V1 First digital signal UF1 First feedback analog signal V2 Second digital signal UF2 Second feedback analog signal S1 First signal S2 Second signal X0 First sum signal X0′ Second sum signal X1 First integrated signal X2 Second integrated signal X1′ Third integrated signal X2′ Fourth integrated signal b1 First gain c1 Second gain c2 Third gain c1′ Fourth gain b1′ Fifth gain Kth Sixth gain Kth′ Seventh gain Cs1 First variable capacitor Cdac Second variable capacitor Cf1 Third variable capacitor Cs2, Cf2, Cs2, Cb3, Ca1a2, Cth, Chold Capacitor Cs1 First capacitance Cs1' Second capacitance Cdac Third capacitance Cdac' Fourth capacitance Cf1 Fifth capacitance Cf1' Sixth capacitance Cs2 Seventh capacitance Cf2 Eighth capacitance

Claims

1. A digital-to-analog converter comprising: an input terminal for inputting an analog signal; an output terminal for outputting a digital signal; a first integrating circuit; a second integrating circuit provided subsequent to the first integrating circuit; a first adder provided on the input side of the first integrating circuit; a second adder provided on the output side of the second integrating circuit; a quantizer; and a digital-to-analog converter, wherein in a first step, the digital-to-analog converter converts the first digital signal output from the quantizer into a first feedback analog signal; the first adder generates a first summed signal by adding a signal obtained by amplifying the analog signal with a first gain and a signal obtained by amplifying the first feedback analog signal with a second gain; the first integrating circuit integrates the first summed signal to generate and output a first integrated signal; and the second integrating circuit integrates a signal obtained by amplifying the first integrated signal with a third gain to generate and output a second integrated signal. the second adder outputs a first signal generated by amplifying the analog signal, the first integrated signal, and the second integrated signal by a predetermined gain and then adding them to the quantizer; the quantizer converts the first signal into a first digital signal and outputs it to the output terminal; in a second step after the first step, the digital-to-analog converter converts the second digital signal output from the quantizer into a second feedback analog signal; the second integrator circuit outputs a fourth integrated signal; the first adder generates a second summed signal by adding a signal obtained by amplifying the second feedback analog signal by a fourth gain and a signal obtained by amplifying the second integrated signal by a fifth gain; and the first integrator circuit generates and outputs a third integrated signal by integrating the second summed signal. the second adder outputs a second signal generated by amplifying the fourth integrated signal and the third integrated signal by a predetermined gain and then adding them together to the quantizer; the quantizer converts the second signal into the second digital signal and outputs the second digital signal to the output terminal; and the first integrating circuit and the second integrating circuit have an operational amplifier shared by them;A delta-sigma modulator characterized in that, when the quantization level of the quantizer is three levels, the fourth gain / fifth gain = the second gain x the third gain is satisfied, and, when the quantization level of the quantizer is two levels, the fourth gain / fifth gain = 4 x the second gain x the third gain is satisfied.

2. The delta-sigma modulator of claim 1, comprising a first variable capacitor, a second variable capacitor, and a third variable capacitor, wherein the capacitances of the first variable capacitor, the second variable capacitor, and the third variable capacitor are changed in the first step and the second step so that when the quantizer has three quantization levels, the fourth gain / the fifth gain = the second gain x the third gain is satisfied, and when the quantizer has two quantization levels, the fourth gain / the fifth gain = 4 x the second gain x the third gain is satisfied.

3. The ΔΣ modulator of claim 2, further comprising: a capacitance of the first variable capacitor that is variable between a first capacitance and a second capacitance in the first step and a second step; a capacitance of the second variable capacitor that is variable between a third capacitance and a fourth capacitance in the first step and a second step; a capacitance of the third variable capacitor that is variable between a fifth capacitance and a sixth capacitance in the first step and a second step; a seventh capacitance; and an eighth capacitance; wherein the second gain is proportional to the third capacitance / the fifth capacitance; the third gain is proportional to the seventh capacitance / the eighth capacitance; the fourth gain is proportional to the fourth capacitance / the sixth capacitance; and the fifth gain is proportional to the second capacitance / the sixth capacitance.

4. The delta-sigma modulator of claim 3, characterized in that: the first step is performed consecutively M1 times (M1 is a natural number); the second step is performed consecutively M2 times (M2 is a natural number); each of the cycles of the first step and the second step includes a first operation and a second operation; in the first cycle of the second step, the second integrator circuit generates and outputs the fourth integrated signal by integrating the first integrated signal output by the first integrator circuit in the M1th second operation of the first step with a signal amplified by the third gain in the first operation of the second step; and the first integrator circuit generates and outputs the third integrated signal by integrating the fourth integrated signal output by the second integrator circuit in the first operation with a signal amplified by the fifth gain in the second operation.

5. The delta-sigma modulator according to claim 4, characterized in that the configuration for retaining the charge in the eighth capacitor continues to retain the fourth integrated signal in the second step.

6. The delta-sigma modulator according to claim 5, wherein in the second step, the fourth integrated signal output from the second integration circuit is the same in all of the M2 cycles.

7. A ΔΣ modulator as described in claim 1, characterized in that in the first step, a reference voltage after being amplified by a sixth gain that changes the threshold level of the first digital signal output from the quantizer is input to the second adder, and in the second step, a reference voltage after being amplified by a seventh gain that changes the threshold level of the second digital signal output from the quantizer is input to the second adder.

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