Semiconductor device and manufacturing method therefor

Abstract

[Problem] To provide a semiconductor device that can be easily manufactured by reducing warpage of a wafer and increasing mechanical strength to thereby make the wafer less susceptible to cracking. [Solution] The present invention relates to a semiconductor device comprising: a second conductivity-type semiconductor layer 13 that is disposed on a first first conductivity-type semiconductor layer 11 and formed further on the inner side than the first first conductivity-type semiconductor layer 11 in plan view; a second first conductivity-type semiconductor layer 12 that is disposed in contact with the bottom of the first first conductivity-type semiconductor layer 11; a groove 11a that has a mesa structure and is formed on the upper surface side of the second conductivity-type semiconductor layer 13, and formed on an outer peripheral part of the second conductivity-type semiconductor layer 13 and on the first first conductivity-type semiconductor layer 11 located outside the outer peripheral part in plan view; and a passivation layer 15 that is formed in the groove 11a and formed on a side surface on the upper surface side of the second conductivity-type semiconductor layer 13 and the upper surface side of the first first conductivity-type semiconductor layer 11. A bottom surface of the groove 11a is located on the second conductivity-type semiconductor layer 13 and the first first conductivity-type semiconductor layer 11.

Description

Semiconductor device and manufacturing method thereof

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof.

[0002] Conventional diodes are broadly divided into two types: mesa type and planar type (see Figures 4 and 5). The mesa type diode shown in Figure 4 has deep grooves separating adjacent chips, which has the advantages of reducing the number of photolithography steps and narrowing the peripheral dead zone (see, for example, Patent Document 1). However, forming deep grooves has the disadvantage of causing warping of the wafer as the wafer becomes thinner, and of reducing its mechanical strength and making it more susceptible to cracking.

[0003] The planar diode shown in Figure 5 has the advantage of having no grooves, which reduces wafer warpage and makes it easy to increase the diameter. However, it has the disadvantage of requiring many photolithography steps to introduce impurities using a resist pattern, and of having a large peripheral invalid area.

[0004] A new structure that overcomes both of the above disadvantages is desired.

[0005] JP 2014-192500 A

[0006] Various aspects of the present invention aim to provide a semiconductor device that can be easily manufactured by reducing wafer warpage and increasing mechanical strength to make the wafer less likely to crack, and a method for manufacturing the same.

[0007] Various aspects of the present invention are described below.

[0008] a second conductivity type semiconductor layer disposed on and in contact with the first conductivity type semiconductor layer and formed inside the first conductivity type semiconductor layer in a plan view; a second conductivity type semiconductor layer disposed below and in contact with the first conductivity type semiconductor layer and having a higher impurity concentration than the first conductivity type semiconductor layer; a mesa-structured groove formed in the first conductivity type semiconductor layer on an upper surface side of the second conductivity type semiconductor layer and located on an outer periphery of the second conductivity type semiconductor layer and outside the outer periphery in a plan view; and a passivation layer formed in the groove and on a side surface on an upper surface side of the second conductivity type semiconductor layer and on an upper surface side of the first conductivity type semiconductor layer, wherein a bottom surface of the groove is located on the second conductivity type semiconductor layer and the first conductivity type semiconductor layer.

[0009] According to the semiconductor device of [1] above, the bottom surface of the groove is formed to be located above the second conductivity type semiconductor layer and the first first conductivity type semiconductor layer. Therefore, the second conductivity type semiconductor layer is formed to extend below the groove, and when a reverse bias is applied, the depletion layer extends below the groove. This alleviates electric field concentration and improves surge resistance. Because such grooves can be smoothed by dicing or etching, there is no need to use expensive mirror-finished wafers as in conventional planar structures, resulting in cost reduction. Furthermore, because the grooves are shallower than in conventional mesa structures, wafer warpage is reduced, mechanical strength is increased, and wafers with diameters of 6 inches or more can be accommodated.

[0010] [2] The semiconductor device according to the above [1], wherein the side surface of the second conductivity type semiconductor layer below the bottom surface of the groove has a rounded shape.

[0011] According to the semiconductor device of [2] above relating to one aspect of the present invention, the side surface of the second conductivity type semiconductor layer below the bottom surface of the groove has a rounded shape, thereby alleviating electric field concentration and improving surge resistance.

[0012] [3] In the above [1] or [2], the semiconductor device is characterized by having a first electrode layer formed on the second conductive type semiconductor layer, and a second electrode layer formed under the second first conductive type semiconductor layer.

[0013] [4] The semiconductor device according to the above [3], wherein, in a plan view, the outer periphery of the first electrode layer is located inside the outermost periphery of the second conductivity type semiconductor layer.

[0014] [5] The semiconductor device according to the above [1] or [2], wherein the passivation layer is a glass layer.

[0015] [6] A method for manufacturing a semiconductor wafer, comprising: (a) introducing a second conductivity type impurity into an upper surface of a first conductivity type semiconductor wafer and introducing a first conductivity type impurity into a lower surface of the semiconductor wafer, thereby forming a first second conductivity type semiconductor layer on the upper surface side of the semiconductor wafer, and forming a first first conductivity type semiconductor layer on the lower surface side of the semiconductor wafer, the first second conductivity type semiconductor layer having a higher impurity concentration than the semiconductor wafer; (b) forming a mesa structure groove in the first second conductivity type semiconductor layer and the semiconductor wafer, the groove being deeper than the thickness of the first second conductivity type semiconductor layer; (c) performing a heat treatment on the first first conductivity type semiconductor layer and the first second conductivity type semiconductor layer, thereby forming a second first conductivity type semiconductor layer that is thicker than the first first conductivity type semiconductor layer and has a higher impurity concentration than the semiconductor wafer, and forming a second second conductivity type semiconductor layer that is thicker than the first second conductivity type semiconductor layer; and (d) forming a passivation layer in the groove. a bottom surface of the groove located on the second conductivity type semiconductor layer and the first first conductivity type semiconductor layer in the step (c); and a lower surface of the passivation layer located on the second second conductivity type semiconductor layer and the semiconductor wafer in the step (d).

[0016] According to one aspect of the present invention, the method for manufacturing a semiconductor device described in [6] above includes the steps of (b) forming a mesa-structured groove in a first second-conductivity-type semiconductor layer and a semiconductor wafer, the groove being deeper than the thickness of the first second-conductivity-type semiconductor layer, and (c) performing a heat treatment on the first first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer to form a second first-conductivity-type semiconductor layer having a greater thickness than the first first-conductivity-type semiconductor layer and a higher impurity concentration than the semiconductor wafer, and forming a second second-conductivity-type semiconductor layer having a greater thickness than the first second-conductivity-type semiconductor layer. By forming the second second-conductivity-type semiconductor layer having a greater thickness than the first second-conductivity-type semiconductor layer, the second second-conductivity-type semiconductor layer can be formed so as to extend below the groove. Because the depletion layer extends below the groove when a reverse bias is applied, there is no need to use an expensive mirror-finished wafer as in conventional planar structures, resulting in reduced costs. Furthermore, because the grooves are shallower than in conventional mesa structures, wafer warpage is reduced, mechanical strength is increased, and it is possible to accommodate larger diameters of 6 inches or more.

[0017] [7] The method for manufacturing a semiconductor device according to the above [6], wherein the grooves in the step (b) are formed by cutting with a dicing blade.

[0018] According to the semiconductor device manufacturing method [7] of one aspect of the present invention, in a conventional mesa diode structure in which grooves are formed by cutting with a dicing blade, corners are right-angled, and electric field concentration reduces surge resistance, whereas in the semiconductor device manufacturing method [4], the bottoms of the grooves are formed to be located above the second conductivity type semiconductor layer and the first first conductivity type semiconductor layer, so the corners of the second conductivity type semiconductor layer are rounded rather than right-angled, thereby mitigating electric field concentration and improving surge resistance.

[0019] [8] The method for manufacturing a semiconductor device according to the above [6], wherein the groove in the step (b) is formed by etching.

[0020] [9] The method for manufacturing a semiconductor device according to the above [6], wherein the grooves in the step (b) are formed by cutting with a dicing blade and then etching.

[0021]

[10] In any one of the above [6] to [9], the method for manufacturing a semiconductor device further comprises, after the step (d), a step (e) of forming a first electrode layer on the second conductive type semiconductor layer and forming a second electrode layer under the second first conductive type semiconductor layer.

[0022] According to various aspects of the present invention, it is possible to provide a semiconductor device that can be easily manufactured by reducing the warpage of the wafer and increasing the mechanical strength to make the wafer less likely to crack, and a method for manufacturing the same.

[0023] 1A to 1D are cross-sectional views illustrating a semiconductor device according to an embodiment of the present invention. (A) to (D) are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. (A) to (D) are cross-sectional views illustrating a semiconductor device according to an embodiment of the present invention. (B) is a plan view of the semiconductor device shown in FIG. 1. (C) is a cross-sectional view illustrating a conventional mesa diode. (D) is a cross-sectional view illustrating a conventional planar diode.

[0024] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0025] 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention, and FIG. 3 is a plan view of the semiconductor device shown in FIG.

[0026] The semiconductor device shown in FIG. 1 includes a first first conductivity type semiconductor layer (N － ) 11, and a first first conductivity type semiconductor layer (N － ) 11, a second conductivity type semiconductor layer (anode layer, P ＋ ) 13 is arranged in contact with the anode layer (P ＋ ) 13 is a first first conductivity type semiconductor layer (N －1, the first conductive type semiconductor layer (N － Under the first conductive type semiconductor layer (cathode layer, N ＋ ) 12, and the cathode layer (N ＋ ) 12 is a first first conductivity type semiconductor layer (N － The impurity concentration is higher than that of the first first conductivity type semiconductor layer (N － ) 11 is N － It is preferable that the layer be a silicon semiconductor layer of the same type.

[0027] The first first conductivity type semiconductor layer (N － ) 11 has a groove 11a with a mesa structure, and this groove 11a is ＋ The groove 11a is formed on the upper surface side of the anode layer (P ＋ ) 13 and located outside this outer periphery (see FIG. 3).

[0028] As shown in FIG. 1, a passivation layer 15 is formed in the groove 11a, and an anode layer (P ＋ ) 13 and the first first conductivity type semiconductor layer (N － A passivation layer 15 is formed on the upper surface of the groove 11. The bottom surface of the groove 11a is covered with an anode layer (P ＋ ) 13 and the first first conductivity type semiconductor layer (N － 1 is a diode. The passivation layer 15 is preferably a glass layer, and an underlayer is preferably present below the glass layer.

[0029] The anode layer (P ＋ The side surfaces of the anode layer (P) 13 are preferably rounded. ＋ By providing the rounded side surfaces of the insulator 13, electric field concentration is alleviated, and surge resistance can be improved.

[0030] Anode layer (P ＋ A first electrode layer 21 is formed on the cathode layer (N ＋A second electrode layer 22 is formed under the anode layer (P) 12. In plan view, the outer periphery 21a of the first electrode layer 21 is ＋ 1 and 3, the outermost periphery 13a of the outermost periphery 13 of the inner periphery 13 is located inside the outermost periphery 13a of the outer periphery 13 of the outer periphery 13 of the inner periphery 13 of the outer ...

[0031] According to this embodiment, the anode layer (P ＋ ) 13 and the first first conductivity type semiconductor layer (N － The bottom surface of the groove 11a is formed on the anode layer (P) 11. ＋ ) 13 is formed, and when a reverse bias is applied, the depletion layer extends below the groove 11a. This alleviates electric field concentration and improves surge resistance. Because the groove 11a can be smoothed by dicing or etching, there is no need to use expensive mirror-finished wafers as in conventional planar structures, resulting in cost reduction (see Figure 1). Furthermore, because the groove is shallower than in conventional mesa structures, wafer warpage is reduced, mechanical strength can be increased, and large diameters of 6 inches or more can be accommodated (see Figure 1). In other words, by reducing wafer warpage and increasing mechanical strength to make the wafer less likely to crack, a semiconductor device can be provided that can be easily manufactured.

[0032] Second Embodiment FIGS. 2A to 2D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0033] As shown in FIG. 2A, a semiconductor wafer of a first conductivity type (N － ) 11, and the second conductivity type impurity is introduced into the upper surface of the semiconductor wafer (N － The first conductivity type impurity is introduced into the lower surface of the semiconductor wafer (N － ) 11 on the upper surface side of the first second conductivity type semiconductor layer (P ＋ ) 3, and a semiconductor wafer (N － ) 11 on the underside of the semiconductor wafer (N － ) 11 has a higher impurity concentration than the first first conductivity type semiconductor layer (N ＋ 1A to 1D show the cross section of one chip, and the semiconductor wafer (N －1 are formed adjacent to each other on the substrate 11.

[0034] Next, as shown in FIG. 2B, the first second conductivity type semiconductor layer (P ＋ ) 3 and semiconductor wafer (N － ) 11, a first second conductivity type semiconductor layer (P ＋ ) 3, a groove 11a having a mesa structure is formed that is deeper than the thickness of the semiconductor substrate 3 (step (b)). The groove 11a may be formed by cutting with a dicing blade. Alternatively, the groove 11a may be formed by etching (dry etching or wet etching). Alternatively, the groove 11a may be formed by cutting with a dicing blade and then etching.

[0035] The details of forming the groove 11a by wet etching are as follows: A resist pattern (not shown) having an opening on the groove 11a is formed, and the first second conductivity type semiconductor layer (P ＋ ) 3 and semiconductor wafer (N － ) 11 is wet-etched. As a result, the first second conductivity type semiconductor layer (P ＋ ) 3 and semiconductor wafer (N － ) 11, a first second conductivity type semiconductor layer (P ＋ ) 3, a groove 11a is formed that is deeper than the thickness of the substrate 11a.

[0036] Next, as shown in FIG. 2C, a first first conductivity type semiconductor layer (N ＋ ) 12a and the first second conductivity type semiconductor layer (P ＋ ) 3 is subjected to a heat treatment. As a result, the first first conductivity type semiconductor layer (N ＋ ) 12a is thicker and the semiconductor wafer (N － A second first conductivity type semiconductor layer (cathode layer, N) 11 having a higher impurity concentration than the first conductivity type semiconductor layer (cathode layer, N) 11 ＋ ) 12 and a first second conductivity type semiconductor layer (P ＋ ) 3 is thicker than the second conductive type semiconductor layer (anode layer, P ＋ ) 13 is formed on the bottom surface of the groove 11a (step (c)). ＋ ) 13 and semiconductor wafer (N－ ) 11. That is, the anode layer (P ＋ ) 13 is formed so as to be embedded under the shallow groove 11a (see FIG. 2(C)).

[0037] Next, as shown in FIG. 2D, a passivation layer 15 is formed in the groove 11a (step (d)). The lower surface of this passivation layer 15 is covered with an anode layer (P ＋ ) 13 and semiconductor wafer (N － ) 11. The passivation layer 15 is preferably a glass layer, and an underlayer is preferably present below the glass layer.

[0038] More specifically, a glass paste is applied to the entire inner surface of the groove 11a by printing, and the glass paste is then baked to form the passivation layer 15 made of glass.

[0039] After this, the anode layer (P ＋ A first electrode layer 21 is formed on the cathode layer (N ＋ A second electrode layer 22 is formed under the insulating film 12 (step (e)).

[0040] According to this embodiment, the first second conductivity type semiconductor layer (P ＋ ) 3 and semiconductor wafer (N － ) 11, a first second conductivity type semiconductor layer (P ＋ A mesa-structured groove 11a is formed that is deeper than the thickness of the first conductive type semiconductor layer (N ＋ ) 12a and the first second conductivity type semiconductor layer (P ＋ ) 3 is subjected to a heat treatment to form the first first conductivity type semiconductor layer (N ＋ ) 12a is thicker and the semiconductor wafer (N － The second first conductivity type semiconductor layer (N) 11 has a higher impurity concentration than the first conductivity type semiconductor layer (N) 11. ＋ ) 12 and a first second conductivity type semiconductor layer (P ＋ ) 3 is thicker than the second conductive type semiconductor layer (anode layer, P ＋ ) 13 is formed. ＋ ) 3 with a thicker anode layer (P ＋) 13 is formed so that the anode layer (P ＋ ) 13 can be formed. When a reverse bias is applied, the depletion layer extends below the groove 11a, eliminating the need to use expensive mirror-finished wafers as in conventional planar structures, thereby reducing costs (see FIGS. 1 and 2(D)). Furthermore, because the grooves are shallower than in conventional mesa structures, wafer warpage is reduced, mechanical strength can be increased, and large diameters of 6 inches or more can be accommodated (see FIGS. 1 and 2(D)). In other words, a method for manufacturing a semiconductor device can be provided that reduces wafer warpage, increases mechanical strength, and makes the wafer less likely to crack, thereby enabling easier manufacturing.

[0041] In addition, in the conventional mesa diode structure in which grooves are formed by cutting with a dicing blade, the corners are right-angled (see FIG. 4), and the surge resistance is reduced due to the concentration of the electric field. In contrast, in the semiconductor device manufacturing method according to this embodiment, the anode layer (P ＋ ) 13 and semiconductor wafer (N － The bottom surface of the groove 11a is formed to be located on the anode layer (P ＋ The corners of the terminal 13 are not right-angled but rounded (see FIGS. 1 and 2(D)). Therefore, the electric field concentration is alleviated and the surge resistance is improved.

[0042] 3 First second conductivity type semiconductor layer (P ＋ ) 11 First first conductivity type semiconductor layer (N － ) 11a mesa structure groove 12 second first conductivity type semiconductor layer (cathode layer, N ＋ ) 12a First first conductivity type semiconductor layer (N ＋ ) 13 Second conductive type semiconductor layer (anode layer, P ＋ ), a second second conductivity type semiconductor layer (anode layer, P ＋ ) 13a Second conductive type semiconductor layer (anode layer, P ＋ ) outermost periphery 15 passivation layer 15a second conductivity type semiconductor layer (anode layer, P ＋ ) upper surface side surface 21 first electrode layer 21a outer periphery of first electrode layer 22 second electrode layer

Claims

1. A semiconductor device comprising: a first first-conductivity type semiconductor layer; a second-conductivity type semiconductor layer disposed on top of and in contact with the first first-conductivity type semiconductor layer and formed inside the first first-conductivity type semiconductor layer in a plan view; a second first-conductivity type semiconductor layer disposed below and in contact with the first first-conductivity type semiconductor layer and having a higher impurity concentration than the first first-conductivity type semiconductor layer; a mesa-structured groove formed in the first first-conductivity type semiconductor layer on the upper surface side of the second-conductivity type semiconductor layer and located on the outer periphery of the second-conductivity type semiconductor layer and outside the outer periphery in a plan view; and a passivation layer formed in the groove and on a side surface on the upper surface side of the second-conductivity type semiconductor layer and on the upper surface side of the first first-conductivity type semiconductor layer, wherein the bottom surface of the groove is located on the second-conductivity type semiconductor layer and the first first-conductivity type semiconductor layer.

2. A semiconductor device according to claim 1, wherein the side surface of the second conductivity type semiconductor layer below the bottom surface of the groove has a rounded shape.

3. A semiconductor device according to claim 1 or 2, comprising: a first electrode layer formed on the second conductive type semiconductor layer; and a second electrode layer formed below the second first conductive type semiconductor layer.

4. A semiconductor device according to claim 3, wherein, in plan view, the outer periphery of the first electrode layer is located inside the outermost periphery of the second conductivity type semiconductor layer.

5. A semiconductor device according to claim 1 or 2, wherein the passivation layer is a glass layer.

6. A method for manufacturing a semiconductor wafer, comprising: (a) a step of introducing a second conductivity type impurity into the upper surface of a first conductivity type semiconductor wafer and introducing a first conductivity type impurity into the lower surface of the semiconductor wafer, thereby forming a first second conductivity type semiconductor layer on the upper surface side of the semiconductor wafer and forming a first first conductivity type semiconductor layer on the lower surface side of the semiconductor wafer, the first second conductivity type semiconductor layer having a higher impurity concentration than the semiconductor wafer; (b) a step of forming a mesa structure groove in the first second conductivity type semiconductor layer and the semiconductor wafer, the groove being deeper than the thickness of the first second conductivity type semiconductor layer; (c) a step of performing a heat treatment on the first first conductivity type semiconductor layer and the first second conductivity type semiconductor layer, thereby forming a second first conductivity type semiconductor layer that is thicker than the first first conductivity type semiconductor layer and has a higher impurity concentration than the semiconductor wafer, and forming a second second conductivity type semiconductor layer that is thicker than the first second conductivity type semiconductor layer; and (d) a step of forming a passivation layer in the groove. a bottom surface of the groove located on the second conductivity type semiconductor layer and the first first conductivity type semiconductor layer in the step (c); and a lower surface of the passivation layer located on the second second conductivity type semiconductor layer and the semiconductor wafer in the step (d).

7. A method for manufacturing a semiconductor device according to claim 6, wherein the grooves in step (b) are formed by cutting with a dicing blade.

8. A method for manufacturing a semiconductor device according to claim 6, wherein the grooves in step (b) are formed by etching.

9. A method for manufacturing a semiconductor device according to claim 6, wherein the grooves in step (b) are formed by cutting with a dicing blade and then etching.

10. A method for manufacturing a semiconductor device according to any one of claims 6 to 9, further comprising, after step (d), step (e) of forming a first electrode layer on the second conductivity type semiconductor layer and forming a second electrode layer below the second first conductivity type semiconductor layer.

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