Circuit board, and semiconductor package comprising same

Abstract

An embodiment of the present invention provides a circuit board including: a first core layer including glass; a second core layer disposed on the first core layer and including glass; a buffer layer disposed on the first core layer and the second core layer; and a cavity penetrating at least a portion of the buffer layer and at least one of the first core layer and the second core layer.

Description

Circuit boards and semiconductor packages including the same

[0001] Embodiments according to the present invention relate to circuit boards and semiconductor packages.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to attach a greater number of packages to a limited-size substrate. However, because typical packages are based on mounting a single semiconductor chip, achieving the desired performance is limited.

[0003] A typical circuit board or package substrate consists of a processor package, which houses the processor chip, and a memory package, which houses the memory chips, all connected together. These package substrates integrate the processor and memory chips into a single package, reducing the chip footprint and enabling high-speed signal transmission through short paths. Due to these advantages, these package substrates are widely used in mobile devices and other devices.

[0004] Meanwhile, the recent advancements in electronic devices, such as mobile devices, and the adoption of High Bandwidth Memory (HBM) have led to larger package sizes. Furthermore, as the number of functions required for application processors increases, there is a growing demand for separate processor chips for each function, along with circuit boards capable of mounting these processor chips. Even when the application processor is split into two processor chips, the number of terminals (input / output) provided on each processor chip is increasing.

[0005] In addition, due to recent trends such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed, the number of terminals on processor chips is gradually increasing due to the increase in power and signal quantity. Accordingly, the area, thickness, and circuit pattern density of circuit boards are also increasing. When the area and thickness of circuit boards increase, it becomes difficult to miniaturize products, and there are problems such as reliability issues such as circuit board warpage and product price increase. Therefore, increasing the circuit pattern density is more advantageous in terms of product price, reliability issues such as warpage, and product miniaturization than increasing the area and thickness of circuit boards. Therefore, the miniaturization of circuit patterns and through-hole electrodes is required.

[0006] In particular, as circuit boards become increasingly thinner, deformations such as warping and twisting that occur during circuit board manufacturing are increasing. To prevent this, a glass core structure, in which a glass plate is formed in the core portion of the circuit board, has been proposed.

[0007] An embodiment of the present invention implements a circuit board and a semiconductor package including the same, in which warpage is suppressed and electrical characteristics are improved even when the thickness increases through a glass layer having high rigidity and a small coefficient of thermal expansion.

[0008] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved structural reliability by improving stress relief by alternately arranging a plurality of core layers and a plurality of buffer layers.

[0009] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved manufacturing ease and improved heat dissipation effect through a cavity penetrating at least a part of a core layer or a part of a buffer layer.

[0010] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved electrical reliability and improved mechanical stability through a protrusion of a cavity side wall or a convex portion of a via electrode.

[0011] The problem to be solved in the embodiment is not limited to this, and it can be said that the purpose or effect that can be understood from the solution or implementation form of the problem described below is also included.

[0012] A circuit board according to an embodiment of the present invention includes: a first core layer including glass; a second core layer disposed on the first core layer and including glass; a buffer layer disposed on the first core layer and the second core layer; and a cavity penetrating at least one of the first core layer and the second core layer and at least a portion of the buffer layer.

[0013] The first core layer may be exposed by the cavity.

[0014] The cavity may penetrate a portion of the first core layer or an upper surface of the first core layer.

[0015] A groove may be formed on the lower surface of the first core layer and the upper surface of the second core layer.

[0016] The side wall of the above cavity may have a stepped structure.

[0017] The above buffer layer is,

[0018] It may include a first buffer layer disposed below the first core layer; a second buffer layer disposed between the first core layer and the second core layer; and a third buffer layer disposed on the second core layer.

[0019] The cavity can penetrate the third buffer layer, the second buffer layer, and the second core layer.

[0020] The cavity may include a side wall and a bottom, and the side wall of the cavity may include a protrusion extending outwardly.

[0021] The above protrusion can overlap horizontally with the third buffer layer and the second buffer layer.

[0022] The cavity may include a first region overlapping the second buffer layer in the horizontal direction; a second region overlapping the second core layer in the horizontal direction; and a third region overlapping the third buffer layer in the horizontal direction.

[0023] The maximum distance between the second region and the center of the cavity may be smaller than the maximum distance between the first region or the third region and the center of the cavity.

[0024] The first buffer layer, the second buffer layer, and the third buffer layer include inorganic fibers, and the inorganic fibers of the second buffer layer and the third buffer layer can be exposed by the cavity.

[0025] The first buffer layer, the second buffer layer, and the third buffer layer may include ABF-GCP.

[0026] At least two of the first buffer layer, the second buffer layer, and the third buffer layer may have different thicknesses.

[0027] The cavity can penetrate the second core layer and at least a portion of the second buffer layer.

[0028] The first core layer and the second core layer may be spaced apart in the thickness direction.

[0029] The first core layer and the second core layer may have different thicknesses.

[0030] It may include a via hole penetrating the first core layer, the second core layer, and the buffer layer.

[0031] It may include a first electrode portion including a first via electrode disposed within the via hole; and a first wiring portion disposed above or below the first via electrode.

[0032] It may include a convex portion arranged in the above via hole or the first via electrode.

[0033] An embodiment of the present invention provides a circuit board and a semiconductor package including the same, in which warpage is suppressed and electrical characteristics are improved even when the thickness increases through a glass layer having high rigidity and a small coefficient of thermal expansion.

[0034] In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved structural reliability by improving stress relief through alternately arranging a plurality of core layers and a plurality of buffer layers.

[0035] In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved manufacturing ease and improved heat dissipation effect through a cavity penetrating at least a part of a core layer or a part of a buffer layer.

[0036] In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved electrical reliability and improved mechanical stability through a protrusion of a cavity side wall or a convex portion of a via electrode.

[0037] The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

[0038] Figure 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention.

[0039] Figure 2 is a drawing for K1 in Figure 1,

[0040] Figure 3 is a drawing explaining the effect of the circuit board of the present invention.

[0041] Fig. 4 is another first example of Fig. 2,

[0042] Figure 5 is another second example of Figure 2,

[0043] Fig. 6 is another third example of Fig. 2,

[0044] Figure 7 is a drawing for K2 in Figure 2,

[0045] Figure 8 is a drawing for K3 in Figure 2,

[0046] Fig. 9 is a cross-sectional view of a circuit board according to a second embodiment of the present invention.

[0047] Figure 10 is a drawing for K4 in Figure 9,

[0048] Fig. 11 is a cross-sectional view of a circuit board according to a third embodiment of the present invention.

[0049] Figure 12 is a drawing for K5 of Figure 11,

[0050] Fig. 13 is a cross-sectional view of a circuit board according to the fourth embodiment of the present invention.

[0051] Figure 14 is a drawing for K6 in Figure 13,

[0052] FIGS. 15 to 23 are drawings explaining a method for manufacturing a circuit board according to the first embodiment of the present invention.

[0053] The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated and described in the drawings. However, this is not to be construed as a specific embodiment of the present invention.

[0054] It is not intended to be limited to the embodiments, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

[0055] Terms that include ordinal numbers, such as "second," "first," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a second component may be referred to as "first component," and similarly, a first component may also be referred to as "second component." The term "and / or" includes a combination of multiple related items described herein or any of multiple related items described herein.

[0056] When a component is referred to as being "connected" or "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but that there may be other components intervening. Conversely, when a component is referred to as being "directly connected" or "connected" to another component, it should be understood that there are no other components intervening.

[0057] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0058] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0059] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0060] Before describing the embodiments, an electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. Various connecting members (e.g., semiconductor elements) may be mounted on the semiconductor package.

[0061] The connecting element may include active components and / or passive components. The active component may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of components are integrated into a single chip. The connecting element may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chip set including a specific combination of the above-mentioned components.

[0062] The memory chip may be a stacked memory such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory. A semiconductor element (not shown) may be electrically connected to the electrode portion through the conductive member described above.

[0063] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0064] Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.

[0065] In the circuit board according to the embodiment of the present invention, the insulating layer may be formed of a plurality of insulating layers. The insulating layer may include a core layer, a buffer layer, and an insulating layer. The buffer layer and the insulating layer may include a build-up layer.

[0066] FIG. 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention, FIG. 2 is a drawing for K1 in FIG. 1, FIG. 3 is a drawing explaining the effect of the circuit board of the present invention, FIG. 4 is another first example of FIG. 2, FIG. 5 is another second example of FIG. 2, FIG. 6 is another third example of FIG. 2, FIG. 7 is a drawing for K2 in FIG. 2, and FIG. 8 is a drawing for K3 in FIG. 2.

[0067] Referring to FIG. 1, a circuit board (100) according to a first embodiment may include a core layer (110), a buffer layer (BF), an insulating layer (BL), an electrode portion (120), and a protective layer (not shown). In addition, the circuit board (100) according to the embodiment may include a semiconductor element (not shown) and a conductive member (not shown) positioned on one side (e.g., an upper side).

[0068] The core layer (110) may be a 'core layer' or a 'substrate layer'. The core layer (110) can suppress warpage that occurs due to thinning of the circuit board. In other words, warpage can be reduced by placing a glass layer (or glass core) with high rigidity and a low coefficient of thermal expansion (CTE) at the center or core of the circuit board. For example, the core layer (110) may have high rigidity and a low coefficient of thermal expansion compared to an insulating layer or a protective layer. In addition, the core layer (110) may have a lower coefficient of thermal expansion compared to the electrode portion (120) (e.g., copper) or the buffer layer (BF). In addition, the buffer layer (BF) or the insulating layer may have a similar coefficient of thermal expansion to the electrode portion.

[0069] Additionally, the core layer (110) may have a thickness greater than that of the buffer layer (BF) or the insulating layer.

[0070] And the core layer (110) can be made of a glass material. For example, the core layer (110) can include pure silicon dioxide (SiO2), soda-lime glass, borosilicate glass, alumino-silicate glass, etc., and is not limited to silicon-based glass compositions, and alternative glass materials, such as fluorine glass, phosphate glass, chalcogen glass, etc., can also be used. In addition, the core layer (110) can further include other additives to form a glass having specific physical properties. These additives can include calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), as well as magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, and carbonates and / or oxides of these elements and other elements.

[0071] Additionally, the core layer (110) may be made of an insulating material. Accordingly, the core layer (110) may be made of an insulating material and may be referred to as an 'insulating layer'.

[0072] Additionally, the core layer (110) may be positioned at the center of the insulating layer (BL). Additionally, the core layer (110) may include a via hole (110h) as described below. The via holes (110h) may have various shapes and be formed at various locations, different from the number and structure illustrated in the drawing.

[0073] There may be a plurality of core layers (110). The core layer (110) according to the embodiment may include a first core layer (111), a second core layer (112), a third core layer (113), and a fourth core layer (114). The second core layer (112) may be positioned on the first core layer (111). The third core layer (113) may be disposed on the second core layer (112). The fourth core layer (114) may be disposed on the third core layer (113). The first core layer (111), the second core layer (112), the third core layer (113), and the fourth core layer (114) may be spaced apart from each other in the stacking (thickness) direction or the vertical direction (Y-axis direction).

[0074] In an embodiment, each core layer may include a top surface and a bottom surface. And, in each core layer, the top surface and the bottom surface may be outer surfaces that are spaced apart from each other at the greatest distance along the stacking direction or the vertical direction.

[0075] The first core layer (111), the second core layer (112), the third core layer (113), and the fourth core layer (114) may be ‘glass layers’ as described above, and may be made of glass material.

[0076] As an example, the core layer (110) may include a via hole (110h). And, a first electrode portion (121) of an electrode portion (120) described later may be positioned in the via hole (110h).

[0077] Furthermore, the drawing illustrates a structure in which the first electrode portion (121) is disposed within the via hole (110h) of the core layer (110). However, each core layer in the core layer (110) may have a through hole, a via hole (110h) may exist within the through hole, and the first electrode portion (121) may be disposed within the via hole (110h). Since the via hole (110h) penetrates a plurality of core layers and a plurality of buffer layers described below, the core layers and buffer layers penetrated by the via hole (110h) may each have a through hole corresponding to the via hole (110h). For example, the first core layer (111) may have a first through hole, and the second core layer (112) may have a second through hole. In addition, the through hole (110h) may be positioned within the first through hole and the second through hole. In addition, the first electrode portion may be positioned within the through hole (110h). At this time, the first through hole and the second via hole can overlap at least partially in the stacking direction (Y-axis direction).

[0078] A buffer layer (BF) may be positioned between a plurality of core layers that are alternately arranged. In an embodiment, a plurality of buffer layers (BF) and a core layer (110) may be alternately arranged along the stacking direction (Y-axis direction).

[0079] The buffer layer (BF) may be composed of various insulating materials. The buffer layer (BF) may be composed of organic or inorganic materials. The buffer layer (BF) may include a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide, similar to the insulating layer (BL) described below. In addition, the insulating layer (BL) may further include a reinforcing material in the resin.

[0080] The buffer layer (BF) may include a plurality of buffer layers. The buffer layer (BF) may include a first buffer layer (BF1), a second buffer layer (BF2), a third buffer layer (BF3), a fourth buffer layer (BF4), and a fifth buffer layer (BF5). The first buffer layer (BF1), the second buffer layer (BF2), the third buffer layer (BF3), the fourth buffer layer (BF4), and the fifth buffer layer (BF5) may be arranged to be spaced apart from each other along the stacking direction (Y-axis direction).

[0081] The first buffer layer (BF1) may be positioned below the first core layer (111). The second buffer layer (BF2) may be positioned between the first core layer (111) and the second core layer (112). The third buffer layer (BF3) may be positioned on the second core layer (112). Alternatively, the third buffer layer (BF3) may be positioned below the third core layer (113). The fourth buffer layer (BF4) may be positioned between the third core layer (113) and the fourth core layer (114). The fifth buffer layer (BF5) may be positioned on the fourth core layer (114). Alternatively, the fifth buffer layer (BF5) may be positioned below the insulating layer (BL).

[0082] The buffer layers (BF) according to the embodiment may have the same or different thicknesses. These buffer layers (BF) are positioned between the spaced core layers (110) to distribute the force (e.g., stress) applied to the circuit board (100) across each layer. This improves stress relief and other effects, thereby enhancing the reliability of the circuit board.

[0083] The insulating layer (BL) can surround at least a portion of the core layer (110) and the buffer layer (BF). For example, the insulating layer (BL) can be positioned on the outer side of the core layer (110) and the buffer layer (BF). Accordingly, damage to the core layer (110) can be prevented. In addition, the insulating layer (BL) can be positioned on the upper or lower side of the core layer (110) and the buffer layer (BF). In an embodiment, the insulating layer (BL) can be in contact with the outer surface or the upper or lower surface of the core layer (110) or the buffer layer (BF). For example, when the core layer (110) is present at the outermost side in the core layer (110) and the buffer layer (BF), the insulating layer (BL) can be in contact with the outermost core layer (110) in the stacking direction (Y-axis direction). In addition, when the buffer layer (BF) is present at the outermost side among the core layer (110) and the buffer layer (BF), the insulating layer (BL) may be in contact with the outermost buffer layer (BF) in the stacking direction (Y-axis direction). For example, the core layer (110) may be composed of two layers. That is, the core layer (110) may include a first core layer (111) and a second core layer (112). At this time, the buffer layer may include a second buffer layer (BF2) disposed between the first core layer (111) and the second core layer (112). Additionally, the buffer layer may further include a first buffer layer or a third buffer layer disposed below the first core layer (111) and above the second core layer (112). When the buffer layer is additionally disposed above or below the core layer disposed at the outermost side in the stacking direction, a bond between the first electrode portion and the buffer layer may exist instead of a bond between the first electrode portion and the core layer. In other words, since the bonding strength between the first electrode portion and the buffer layer is greater than that between the first electrode portion and the core layer, a circuit board with improved reliability can be provided. Hereinafter, the description will be based on the case where the insulating layer (BL) is disposed below the first buffer layer (BF1) and above the fifth buffer layer (Bf5).

[0084] In an embodiment, the insulating layer (BL) may be formed of at least one insulating layer. A plurality of insulating layers may be formed of the same insulating material or different insulating materials.

[0085] As an example, the insulating layer (BL) may include a first insulating layer (115), a second insulating layer (116), a third insulating layer (117), and a fourth insulating layer (118) disposed above or below the core layer (110) and the buffer layer (BF).

[0086] The first insulating layer (115), the second insulating layer (116), the third insulating layer (117), and the fourth insulating layer (118) may be positioned below and above the core layer (110) or the buffer layer (BF), respectively. That is, the insulating layer (BL) may be laminated on the outermost side with the core layer (110) and the buffer layer (BF) at the center.

[0087] Specifically, the first insulating layer (115) may be positioned on the fifth buffer layer (BF5). The second insulating layer (116) may be positioned on the first insulating layer (115). And the third insulating layer (117) may be positioned under the first buffer layer (BF1). The fourth insulating layer (118) may be positioned under the third insulating layer (117).

[0088] As described above, the insulating layer (BL) may be composed of multiple layers depending on the structure or design of the circuit board (100).

[0089] In addition, a plurality of wiring portions (pads, circuit patterns), via holes, via electrodes, etc. may be positioned on the insulating layer (BL). For example, a via hole of the insulating layer (BL) may be connected to a via hole of the core layer (110). In other words, a via electrode positioned on a via hole of the insulating layer (BL) may be electrically connected to a via electrode positioned on a via hole of the core layer (110).

[0090] The insulating layer (BL) may include a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide. Furthermore, the insulating layer (BL) may further include a reinforcing material in the resin. The reinforcing material may be, for example, a fabric reinforcing material, an inorganic filler, etc. The fabric reinforcing material may be glass fiber, and the glass fiber may be impregnated into the resin to form a prepreg (PPG).

[0091] For example, the insulating layer (BL) may be formed of any insulating resin, such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin, such as PID (Photo Imageable Dielectric) resin, can be used. The above-mentioned arbitrary insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as the core, it may include a reinforcing material formed of glass fiber or aramid fiber. For example, the insulating layer (BL) can use ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., as an example, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. can be used. For example, the insulating layer (BL) can include multiple layers composed of ABF.

[0092] Furthermore, the circuit board (100) may include a cavity (CV). In an embodiment, the cavity (CV) may penetrate at least a portion of the plurality of core layers and at least a portion of the plurality of buffer layers. For example, the cavity (CV) may penetrate a core layer and a buffer layer located on top of a core layer that does not penetrate or partially penetrates the core layer.

[0093] For example, the core layer (110) may be composed of two layers. That is, the core layer (110) may include a first core layer (111) and a second core layer (112). In this case, the core layer (110) may penetrate at least one of the first core layer (111) and the second core layer (112) and at least a portion of the buffer layer (BF). This is the case when the core layer (110) only includes the first core layer (111) and the second core layer (112). Furthermore, the same may be applied when an additional core layer other than the first core layer (111) and the second core layer (112) exists.

[0094] In an embodiment, the core layer (110) may include the first core layer (111) to the fourth core layer (114) as described above, and the buffer layer (BF) may include the first buffer layer (BF1) to the fifth buffer layer (BF5). The cavity (CV) may penetrate the second core layer (112) to the fourth core layer (114) and the second buffer layer (BF2) to the fifth buffer layer (BF5). In addition, the cavity (CV) may penetrate at least a portion of the first core layer (111) or may penetrate to the upper surface of the first core layer (111). Here, the cavity (CV) may penetrate at least a portion of the first core layer (111).

[0095] Furthermore, the cavity (CV) can penetrate the insulating layer (BL). The cavity (CV) can penetrate the insulating layer on top of the core layer (110) and the buffer layer (BF). For example, since the cavity (CV) penetrates a portion of the first core layer (111), it can penetrate the first insulating layer (115) and the second insulating layer (116).

[0096] A cavity (CV) may include a side wall (CVI) and a bottom (CVB). The side wall (CVI) of the cavity (CV) may expose the perforated core layer, buffer layer, and insulation layer. The side wall (CVI) of the cavity may also be referred to as a "side," "wall," "inner side wall," or "inner wall."

[0097] The electrode portion (120) may be located in the core layer (110), the buffer layer (BF), and the insulating layer (BL). The electrode portion (120) according to the embodiment may include a plurality of electrode portions. Each electrode portion may include a wiring portion (circuit pattern, pad, etc.) and a via electrode.

[0098] The wiring portion (circuit pattern) can be designed in various forms for transmitting signals and / or power to and from semiconductor devices, and is disposed within each stacked core layer (110) or insulating layer (BL). For example, the electrode portion (120) may include a via electrode, which is a through-hole electrode. The via electrode may be positioned within a through-hole or via hole penetrating the core layer (110), the buffer layer (BF), and the insulating layer (BL). The via electrode is described interchangeably with the term "through-hole electrode."

[0099] In this way, in the electrode portion (120), the via electrode is arranged to penetrate a portion of each insulating layer for vertical connection between circuit patterns arranged on each vertically stacked core layer, buffer layer, and insulating layer. That is, the insulating layer, etc. may include a via hole or a through hole for arrangement of the via electrode. In addition, the via electrode may have a wider width than the circuit pattern for optimization of impedance or heat dissipation, but is not limited thereto and may be freely designed.

[0100] The wiring portion of the electrode portion (120) may include a circuit pattern, pads, etc. The wiring portion of the electrode portion (120) may be arranged on each insulating layer. The pads may be electrically connected to the circuit patterns. In addition, the pads may be electrically connected to semiconductor elements and / or a main board or substrate, etc. In addition, the pads may be electrically connected to via electrodes.

[0101] In particular, pads arranged on the outside in the stacking direction (Y-axis direction) among the pads can be bonded to semiconductor elements, substrates, boards, etc. using solder, wires, conductive adhesives, etc., and can be arranged with a width larger than the width of the circuit pattern to solve problems such as securing yield. However, the present invention is not limited thereto, and may have the same width as the width of the circuit pattern depending on the technical limitations of the bonding process.

[0102] And the pads arranged inside in the stacking direction (Y-axis direction) among the pads function to connect the via electrodes and the circuit patterns. When the via electrodes are arranged with a wider width than the circuit patterns, pads having a wider width than the circuit patterns are provided for positional alignment during the manufacturing process of the via electrodes to be arranged on each circuit pattern. Therefore, each via electrode may have an upper surface that is positioned on the same plane as the lower surface of the upper pad that is in direct contact with the via electrode, and a lower surface that is positioned on the same plane as the upper surface of the lower pad that is in direct contact with the lower surface of the via electrode. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily mean flat surfaces, and it should be understood that even concave or convex surfaces that may appear depending on various processes may be present.

[0103] According to an embodiment, the electrode portion (120) may include a first electrode portion (121), a second electrode portion (122), and a third electrode portion (123).

[0104] The first electrode portion (121) may include a first via electrode (121a) penetrating the core layer (110) and the buffer layer (BF) and a first wiring portion (121b) disposed above and below the buffer layer (BF).

[0105] The second electrode portion (122) may include a second via electrode (122a) penetrating the insulating layer disposed on top of the core layer (110) and the buffer layer (BF) and a second wiring portion (122b) disposed on the insulating layer disposed on top of the core layer (110) and the buffer layer (BF). For example, the second electrode portion (122) may include a second via electrode (122a) penetrating the first insulating layer (115) and the second insulating layer (116) and a second wiring portion (122b) disposed on the first insulating layer (115) and the second insulating layer (116).

[0106] The third electrode portion (123) may include a third via electrode (123a) penetrating the insulating layer disposed under the core layer (110) and the buffer layer (BF), and a third wiring portion (123b) disposed in the insulating layer disposed under the core layer (110) and the buffer layer (BF). For example, the third electrode portion (123) may include a third via electrode (123a) penetrating the third insulating layer (117) and the fourth insulating layer (118), and a third wiring portion (123b) disposed in the third insulating layer (117) and the fourth insulating layer (118).

[0107] The protective layer (not shown) may be positioned above or below the insulating layer (BL). For example, the protective layer (not shown) may be positioned below or above the insulating layer, which is located at the outermost side in the stacking direction (Y-axis direction). Accordingly, the protective layer (not shown) may be positioned at the outermost side in the stacking direction (Y-axis direction) on the circuit board.

[0108] A protective layer (not shown) can have the function of protecting the pad from external moisture or contaminants, and to prevent a short circuit problem when joining a semiconductor element and / or a main board and a circuit board, the protective layer (not shown) may be provided with a solder resist, for example. Specifically, the semiconductor element and / or the main board, etc. have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals may be arranged at a high density. When the plurality of terminals and the pads of the circuit board are joined, solder may be used, for example. When solder is used, a solder short circuit problem may occur between terminals with a high density, and thus, a solder resist that does not have good wettability with the solder may be arranged to solve this short circuit problem. In addition, the protective layer (not shown) may be formed of a material that has insulating properties for electrical connection. The protective layer (not shown) may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc.

[0109] And the protective layer (not shown) located at the outermost side of the circuit board may have an opening. Through the opening, it can be electrically connected to other semiconductor elements, the circuit board, etc.

[0110] For the electrical connection described above, a conductive member (not shown) may be positioned on the upper or lower portion of the circuit board (100). The conductive member positioned on the upper portion may perform electrical connection with a semiconductor element (e.g., a chip) or another circuit board, etc. In addition, the conductive member positioned on the lower portion may perform electrical connection with another board, etc.

[0111] In an embodiment, wiring or electrodes may be arranged for electrical connection between a main board, etc. and a chip (or semiconductor element (not shown), die).

[0112] A semiconductor element (not shown) may be mounted on a circuit board (100). The semiconductor element (not shown) may be mounted in a cavity (CV) of the circuit board (100). The semiconductor element may be a logic chip, a memory chip, or the like, as described above.

[0113] Circuit boards can be divided into package boards and interposers based on their function. The package board serves the function of mounting semiconductor devices and / or interposers. As data increases, the circuit board area increases or the number of insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, to improve the yield of circuit boards with a high number of layers, the yield of the circuit board can be improved by separating them into an interposer and a package board. In addition, as the terminal density of semiconductor devices increases, it can be difficult to implement pads on the package board with an area corresponding to the terminals of the semiconductor devices. Therefore, the pad size of the package board can act as a buffer between the size of the pad and the fine pattern size of the terminals of the semiconductor devices.

[0114] The package substrate and interposer described above can be classified into core substrates and coreless substrates, respectively, depending on the composition of the insulating layer. In an embodiment according to the present invention, a circuit substrate having a core layer including glass is described.

[0115] Referring to FIG. 2, in a circuit board (100) according to an embodiment, a first core layer (111) may be exposed by a cavity (CV). In particular, since the cavity (CV) penetrates a portion of the first core layer (111), an upper surface of the first core layer (111) may be exposed by the cavity (CV).

[0116] And in the embodiment, the side wall (CVI) of the cavity (CV) may include a protrusion (PR) extending outward. Conversely, the outer surface of the buffer layer may have a concave surface (concave surface) due to the protrusion (PR). And the protrusion (PR) may horizontally overlap with the buffer layer penetrated by the cavity (CV). That is, the protrusion (PR) may be located in the buffer layer penetrated by the cavity (CV). For example, the cavity (CV) may penetrate the second buffer layer (BF2), the third buffer layer (BF3), the fourth buffer layer (BF4), and the fifth buffer layer (BF5). The protrusion (PR) may horizontally overlap with the second buffer layer (BF2), the third buffer layer (BF3), the fourth buffer layer (BF4), and the fifth buffer layer (BF5).

[0117] Here, the inner side is the direction toward the central axis (AX) of the cavity, and the outer side is the direction opposite to the inner side. The central axis (AX) of the cavity (CV) may be the center or intersection of a bisector (bisector) of a plane (or direction) perpendicular to the stacking direction (Y-axis direction) in the cavity (CV).

[0118] Additionally, as an example, the cavity (CV) may include a first region (AR1) that overlaps the second buffer layer (BF2) in a horizontal direction (X-axis direction), a second region (AR2) that overlaps the second core layer (112), and a third region (AR3) that overlaps the third buffer layer (BF3) in a horizontal direction (X-axis direction).

[0119] In an embodiment, the first region (AR1), the second region (AR2) and the third region (AR3) may have different maximum lengths from the central axis (AX) or center of the cavity (CV).

[0120] For example, the maximum distance (W2) between the central axis (AX) or center of the second region (AR2) and the cavity (CV) may be smaller than the maximum length (W3) between the central axis (AX) or center of the third region (AR3) and the cavity (CV). Furthermore, the maximum distance (W2) between the central axis (AX) or center of the second region (AR2) and the cavity (CV) may be smaller than the maximum length (W1) between the central axis (AX) or center of the first region (AR1) and the cavity (CV).

[0121] Additionally, the maximum length (W2) between the central axis (AX) or center of the second region (AR2) and the cavity (CV) may be the same as or different from the maximum length (W1) between the central axis (AX) or center of the first region (AR1) and the cavity (CV).

[0122] Furthermore, the length between the central axis (AX) or the center of the cavity (CV) in the protrusion (PR) of the buffer layer (BF) may vary along the stacking direction (Y-axis direction). For example, the length between the central axis (AX) or the center of the cavity (CV) in the protrusion (PR) of the buffer layer (BF) may increase and then decrease along the stacking direction (Y-axis direction). This length change may be implemented in a buffer layer other than the first buffer layer (BF1). That is, this length change may exist only in a buffer layer penetrated by the cavity (CV).

[0123] In addition, the buffer layer (BF) may be formed of various insulating materials as described above. For example, the buffer layer (BF) may include inorganic fibers (IP). For example, the buffer layer (BF) may include resin, filler, and inorganic fibers, and may include, for example, ABF-GCP. In addition, the inorganic fibers (IF) of the buffer layer (BF) may be exposed at the protrusions (PR). In an embodiment, the inorganic fibers of the buffer layer penetrated by the cavity (CV) may be exposed. The inorganic fibers (IF) of the second buffer layer (BF2), the third buffer layer (BF3), the fourth buffer layer (BF4), and the fifth buffer layer (BF5) may be exposed by the cavity (CV). In addition, the inorganic fibers of the first buffer layer (BF1) may not be exposed by the cavity (CV). Accordingly, at least some of the plurality of buffer layers according to the embodiment may not have the inorganic fibers inside exposed by the cavity (CV).

[0124] Furthermore, since the inorganic fibers (IF) are made of a different material from the other materials of the buffer layer (BF), they may partially protrude outside the protrusion (PR). That is, the inorganic fibers (IF) of the buffer layer (BF) may protrude inward from the side wall (CVI) of the cavity (CV).

[0125] In this way, the side wall (CVI) of the cavity (CV) has an outwardly convex protrusion (PR) in some areas, thereby improving bonding strength to the molding member when molding is performed on the cavity (CV). Furthermore, the protrusion (PR) increases the separation distance between the semiconductor device mounted in the cavity (CV), thereby improving electrical reliability.

[0126] And since a part of the first core layer (111) is penetrated by the cavity (CV), a predetermined gap (gap1) can be formed between the exposed surface (111US) of the first core layer (111) adjacent to the second buffer layer (BF2) or the second core layer (112) and the stacking direction (Y-axis direction). In addition, heat dissipation through the first core layer (111) can be easily achieved.

[0127] Additionally, an adhesive layer (APL) may be further disposed on the exposed first core layer (111). The adhesive layer (APL) may improve bonding strength between the first core layer (111) and an additional via electrode or wiring portion. For example, the additional via electrode may be electrically connected to a semiconductor chip mounted within the cavity (CV). In this way, a space in which the adhesive layer (APL) is accommodated and formed can be easily provided through the predetermined gap (gap1) described above.

[0128] Furthermore, depending on the process, the first core layer (111) and the second core layer (112) may be laminated with a through hole or groove to form a cavity (CV) of the circuit board. At this time, the first core layer (111) and the second core layer (112) may be misaligned or misaligned with each other, and their side walls may be spaced apart in the horizontal direction (X-axis direction). However, through such misalignment, the bonding strength between the insulating layer, the core layer, and the molding member can be improved. Furthermore, the peeling phenomenon of each insulating layer, etc. can also be suppressed.

[0129] For example, the buffer layer (BF2) may also exist up to the side of the second core layer (112) or the side of the first core layer (111). Accordingly, a step structure (ST) may exist between each core layer. Such a step structure may also exist between adjacent buffer layers and core layers. As a result, a space for forming an additional electrode part within the cavity (CV) may be secured. Furthermore, due to the step structure, a groove of the cavity (CV) may be formed, so that the cleaning material may be locked during a process such as de-smearing, thereby improving the cleaning effect. Although a step exists in the drawing, the inner side of the cavity of the first core layer (111) may be parallel to the stacking direction, like other core layers.

[0130] In addition, a groove (PT) may exist on the upper or lower surface of the core layer located at the outermost side in the stacking direction (Y-axis direction) in the circuit board according to the embodiment. For example, a groove (PT) may exist on the lower surface of the first core layer (111). When there are two core layers, a groove (PT) may also exist on the upper surface of the second core layer, which is the outermost side. In the drawing, a groove (PT) may exist on the upper surface of the fourth core layer (114). In this way, a groove (PT) may exist on the outer core layer due to the manufacturing process or stress, etc.

[0131] Furthermore, in response to the above-described protrusion, a convex portion (CX) may exist in the via hole or the first via electrode of the first electrode portion. That is, the first via electrode (121a) or via hole (110h) penetrating each buffer layer (BF1 to BF5) may have a convex portion (CX) extending outward from the center of the penetration hole. The convex portion may be positioned in each buffer layer and may overlap with each buffer layer in the horizontal direction (X-axis direction).

[0132] By this configuration, the first via electrode (121a) can increase in width in the horizontal direction in the region where it horizontally overlaps with each buffer layer (BF1 to BF5). By this configuration, the mechanical stress is distributed, so that the mechanical strength of the first via electrode can be improved. That is, the durability against external impact or thermal deformation can be improved. In particular, the phenomenon of the layers of the circuit board being separated due to the stress concentrated at both ends in the stacking direction on the circuit board can be suppressed. In addition, the phenomenon of fracture or layer separation occurring due to the difference in thermal expansion coefficient at the center in the stacking direction on the circuit board can also be suppressed.

[0133] In addition, the surface area is increased by the convex portion (CX), which allows for efficient heat dissipation and reduced resistance, thereby improving electrical performance. In other words, signal integrity and power efficiency can be improved. Furthermore, the bonding strength between the first via electrode (121a) and other components (buffer layers) is increased, thereby improving the reliability of the circuit board.

[0134] The convex portion (CX) may not exist in some areas and is omitted in some drawings.

[0135] In an embodiment, the convex portion (CX) in the via hole (110h) or the first via electrode (121a) may overlap at least partially with the protrusion (PR) in the horizontal direction (X-axis direction). However, a part of the convex portion (CX) may not overlap with the protrusion (PR) in the horizontal direction and may also be spaced apart in the vertical direction. For example, the protrusion (PR) may not exist in the first buffer layer (BF1). However, the convex portion (CX) may exist in the first buffer layer (BF1). That is, the convex portion of the first buffer layer (BF1) may be spaced apart from the protrusion (PR) in the vertical direction and may be positioned misaligned in the horizontal direction.

[0136] Furthermore, as in other examples described below, the convex portion (CX) may also have a varying extension length along the stacking direction. For example, in each of the first buffer layer (BF1) to the fifth buffer layer (BF4), the convex portion may increase or decrease along the stacking direction.

[0137] In addition, at least a portion of the convex portion (CX) may overlap with the cavity (CV). For example, among the plurality of buffer layers (BF1 to BF5), a buffer layer exposed by the cavity (CV) or overlapped in the horizontal direction (X-axis direction) may overlap with the convex portion (CX) in the horizontal direction. In addition, a portion of the convex portion (CX) may not overlap with the cavity (CV) in the horizontal direction.

[0138] In addition, the width (or diameter) of the first via electrode (121a) in the first electrode portion (121) may increase and then decrease toward the bottom in each buffer layer by the convex portion (CX). In addition, among the convex portions (CX), the convex portion arranged at the outermost side in the stacking direction may be in contact with the second wiring portion (122b).

[0139] Furthermore, when a semiconductor element is mounted, the convex portion (CX) and the protrusion portion (PR) may overlap in the horizontal direction (X-axis direction). In addition, unlike the protrusion portion (PR), the distance between the first via electrode (121a) and the central axis (AX) of the cavity (CV) may be minimum at the convex portion (CX).

[0140] Referring further to Fig. 7, a groove (PT) may be positioned on the upper surface of the fourth core layer (114). The groove (PT) may have a structure extending from the upper or lower surface toward the center of each core layer, like a crack. A fifth buffer layer (BF5) may be positioned in the groove (PT) located on the upper surface of the fourth core layer (114). Accordingly, the bonding area between the fifth buffer layer (BF5) and the groove (PT) may increase. Accordingly, the bonding force between the fifth buffer layer (BF5) and the outer fourth core layer (114) increases, and stress distribution may be easily achieved. Therefore, the reliability of the circuit board may be improved.

[0141] As a variation, air gaps or other voids may be formed within the home (PT).

[0142] Referring to Fig. 8, a groove (PT) may be positioned on the lower surface of the first core layer (111). Similarly, the groove (PT) may extend from the upper or lower surface toward the center of each core layer as a crack. In addition, a first buffer layer (BF1) may be positioned in the groove (PT) located on the lower surface of the first core layer (111). Accordingly, the bonding area between the first buffer layer (BF1) and the groove (PT) may increase. As a result, the bonding force between the first buffer layer (BF1) and the outer first core layer (111) increases, and stress distribution may be easily achieved. Accordingly, the reliability of the circuit board may be improved.

[0143] Furthermore, a core layer having a groove (PT) positioned on the outer surface (upper or lower surface) can be positioned on the outer side of multiple core layers in the stacking direction. This increases the bonding area between the outer core layer and the buffer layer, thereby enhancing bonding strength. Furthermore, stress relief can also be further improved.

[0144] As a variation, air gaps or other voids may be formed within the home (PT).

[0145] Referring to FIG. 3, a plurality of buffer layers and a plurality of core layers may be alternately positioned on a circuit board. In an embodiment, a plurality of buffer layers (BF1 to BF5) and core layers (111 to 114) may be alternately positioned along the stacking direction (Y-axis direction).

[0146] This structure, in which multiple buffer layers and core layers (glass cores) are alternately arranged, can more effectively distribute stress, reduce stress concentration, and prevent cracks compared to a single core layer structure. This is because the buffer layers between the multiple core layers serve to absorb and distribute external stress. In a single core layer, stress concentration occurs when external stress is applied, easily causing cracks. However, in a structure in which multiple core layers and buffer layers are alternately arranged, the buffer layers effectively distribute the external stress, so that the entire structure is less likely to crack due to external stress and has a stress-relieving effect. Due to these structural characteristics, a structure using multiple buffer layers and core layers can have high durability and minimize damage caused by stress.

[0147] That is, in the circuit board according to the embodiment, the force (F1) applied to the inside and outside of the circuit board by the buffer layer (BF) is transmitted to the multiple core layers (F2), and the multiple buffer layers can distribute and transmit the force (F2) applied to the core layers in different directions (F2). Accordingly, stress distribution can be performed for each of the multiple buffer layers and the multiple core layers. Therefore, the circuit board according to the embodiment can effectively provide improved stress relief and improved reliability.

[0148] Referring to FIG. 4, in the illustrated first example, the length of each protrusion (PR) in the horizontal direction may differ from at least some of the plurality of buffer layers. The length of such protrusions may vary depending on factors such as heat diffusion and material properties, and the energy distribution of the laser beam when irradiated with the laser beam.

[0149] For example, in the second buffer layer (BF2), the maximum distance (W1) between the central axis (AX) or center of the protrusion (PR) and the cavity (CV) is hereinafter referred to as the 'first maximum distance'. In the third buffer layer (BF3), the maximum distance (W3) between the central axis (AX) or center of the protrusion (PR) and the cavity (CV) is hereinafter referred to as the 'second maximum distance'. In the fourth buffer layer (BF4), the maximum distance (W4) between the central axis (AX) or center of the protrusion (PR) and the cavity (CV) is hereinafter referred to as the 'third maximum distance'. In the fifth buffer layer (BF5), the maximum distance (W5) between the central axis (AX) or center of the protrusion (PR) and the cavity (CV) is hereinafter referred to as the 'fourth maximum distance'.

[0150] At least two of the first maximum distance (W1), the second maximum distance (W3), the third maximum distance (W4) and the fourth maximum distance (W5) may be different from each other.

[0151] In an embodiment, the first maximum distance (W1), the second maximum distance (W3), the third maximum distance (W4), and the fourth maximum distance (W5) may decrease along the stacking direction (Y-axis direction). That is, the protrusion or extension length of the protrusion (PR) may increase toward the lower or first core layer (111). Conversely, the degree of concavity of the side surface of the buffer layer may increase toward the lower or first core layer (111).

[0152] Accordingly, the first maximum distance (W1), the second maximum distance (W3), the third maximum distance (W4), and the fourth maximum distance (W5) can be sequentially reduced. As a result, the separation distance between the connection pin or electrode of the semiconductor element disposed below and the buffer layer can be increased. Accordingly, reliability can be further improved.

[0153] This configuration can aid in heat management by increasing the surface area and thus heat dissipation efficiency, thereby preventing performance degradation and enhancing reliability of circuit boards and semiconductor packages.

[0154] Furthermore, in terms of structural strength, the concave structure can improve the mechanical stability of the substrate by dispersing stress concentrations and increase its resistance to external shocks and thermal deformation. Furthermore, it can help reduce weight by eliminating unnecessary materials and reduce manufacturing costs.

[0155] In particular, the concave structure can contribute to improving the thermal reliability of the package by distributing the thermal expansion of the substrate more evenly and reducing thermal deformation that may occur during thermal cycling.

[0156] As a variation example, the first maximum distance (W1), the second maximum distance (W3), the third maximum distance (W4), and the fourth maximum distance (W5) can increase along the stacking direction (Y-axis direction). This can be changed by the irradiation time or energy intensity of the laser beam, etc.

[0157] Referring to FIG. 5, in the second example, at least two thicknesses of each buffer layer may be different from each other. At least some of the thicknesses (d0, d1, d2, d3, d4) of the first buffer layer (BF1), the second buffer layer (BF2), the third buffer layer (BF3), the fourth buffer layer (BF4), and the fifth buffer layer (BF5) may be different from each other. In the first buffer layer (BF1), the second buffer layer (BF2), the third buffer layer (BF3), the fourth buffer layer (BF4), and the fifth buffer layer (BF5), the thickness of the outermost buffer layer in the stacking direction may be greater than the thickness of the inner buffer layer. For example, the thickness (d0) of the first buffer layer (BF1) and the thickness (d4) of the fifth buffer layer (BF5) may be greater than the thickness (d1) of the second buffer layer (BF2), the thickness (d2) of the third buffer layer (BF3), and the thickness (d3) of the fourth buffer layer (BF4). By this configuration, if the outermost, i.e., the upper buffer layer and the lower buffer layer, are thick among the plurality of buffer layers, the stress can be evenly distributed. In particular, the upper and lower buffer layers located on the outer side must be thick to effectively distribute the stress due to thermal expansion or contraction.

[0158] Referring to FIG. 6, in the third example, at least two thicknesses of each core layer may be different from each other. At least some of the thicknesses (d5, d6, d7, d8) of the first core layer (111), the second core layer (112), the third core layer (113), and the fourth core layer (114) may be different. In the first core layer (111), the second core layer (112), the third core layer (113), and the fourth core layer (114), the thickness of the outermost core layer in the stacking direction may be greater than the thickness of the inner core layer. For example, the thickness (d5) of the first core layer (111) and the thickness (d8) of the fourth core layer (114) may be greater than the thickness (d6) of the second core layer (112) and the thickness (d7) of the third core layer (113). By this configuration, if the outermost, i.e., upper core layer and lower core layer among multiple core layers are thick, stress can be evenly distributed, and mechanical reliability can also be improved.

[0159] FIG. 9 is a cross-sectional view of a circuit board according to a second embodiment of the present invention, and FIG. 10 is a drawing for K4 in FIG. 9.

[0160] Referring to FIGS. 9 and 10, a circuit board (100A) according to the second embodiment may include a core layer (110), a buffer layer (BF), an insulating layer (BL), an electrode portion (120), and a protective layer (not shown). In addition, the circuit board (100) according to the embodiment may include a semiconductor element (not shown) and a conductive member (not shown) positioned on one side (e.g., the upper side). In addition to the contents described below, the contents described above or in other embodiments may be applied.

[0161] In this example, the buffer layer (BF) may include a connection buffer layer (BFH) positioned within the via hole (110h). That is, the connection buffer layer (BFH) may be positioned outside the first via electrode (121a). And the connection buffer layer (BFH) may overlap the first via electrode (121a) in the horizontal direction.

[0162] The connection buffer layer (BFH) may be arranged on the inner surface of the via hole (110h). In this way, the connection buffer layer (BFH) may be present within the via hole (110h) of the plurality of core layers (110), and the first via electrode (121a) may be positioned within the connection buffer layer (BFH).

[0163] In an embodiment, a connection buffer layer (BFH) may be in contact with each buffer layer. The connection buffer layer (BFH) may overlap each buffer layer in the horizontal direction (X-axis direction).

[0164] Additionally, the connection buffer layer (BFH) can be in contact with each core layer. The connection buffer layer (BFH) can be horizontally overlapped with each core layer.

[0165] And the connecting buffer layer (BFH) can connect each buffer layer that is spaced apart from each other. For example, the connecting buffer layer (BFH) can connect the first buffer layer (BF1), the second buffer layer (BF2), the third buffer layer (BF3), the fourth buffer layer (BF4), and the fifth buffer layer (BF5).

[0166] Furthermore, the connection buffer layer (BFH) may have a convex portion formed when forming a through hole for forming the first via electrode (121a). Unlike the first embodiment, the convex portion may be convex based on the entire length in the stacking direction (Y-axis direction) from the first buffer layer (BF1) to the fifth buffer layer (BF5). For example, the first via electrode (121a) may have a jar shape. Accordingly, the convex length of the convex portion according to the present embodiment may be greater than that of the convex portion existing on the outside of the first via electrode (121a) in each buffer layer. That is, the first via electrode (121a) may have a width (length in the horizontal direction) at the center, which is a bisecting point in the stacking direction, greater than the width at the upper or lower surface. In addition, the convex portion according to the present example may overlap the protrusion (PR) in the horizontal direction (X-axis direction). Additionally, the convex portion may overlap with the core layer (110) in the horizontal direction (X-axis direction). Furthermore, the distance between the convex portion and the protrusion (PR) adjacent thereto may be smaller in the inner core layer than in the outer core layer.

[0167] By this configuration, the bonding strength between the connection buffer layer (BFH) and the first via electrode (121a) is improved, and the electrical resistance of the first via electrode (121a) is reduced, so that the electrical characteristics can be improved.

[0168] Fig. 11 is a cross-sectional view of a circuit board according to a third embodiment of the present invention, and Fig. 12 is a drawing for K5 of Fig. 11.

[0169] Referring to FIGS. 11 and 12, a circuit board (100B) according to a third embodiment may include a core layer (110), a buffer layer (BF), an insulating layer (BL), an electrode portion (120), and a protective layer (not shown). In addition, the circuit board (100) according to the embodiment may include a semiconductor element (not shown) and a conductive member (not shown) positioned on one side (e.g., the upper side). In addition to the contents described below, the contents described above or in other embodiments may be applied.

[0170] In this embodiment, the bottom surface (CVB) of the cavity (CV) may correspond to the top surface of any one of the plurality of core layers. For example, the cavity (CV) may not penetrate at least one of the plurality of core layers.

[0171] In an embodiment, the cavity (CV) may penetrate the second core layer (112), the third core layer (113), and the fourth core layer (114). And the cavity (CV) may not penetrate the first core layer (111). In other words, the cavity (CV) may penetrate up to the second buffer layer (BF2). In other words, the upper surface (111US) of the first core layer (111) and the bottom surface (CVB) of the cavity (CV) may be the same surface. This makes it easier to form the cavity (CV). Furthermore, when the cavity (CV) penetrates up to a part of one of the core layers (e.g., the first core layer), there is a problem that the roughness or surface roughness of the bottom surface (CVB) of the cavity (CV) increases. Accordingly, in the circuit board (100B) according to the present embodiment, electrodes for electrical connection with semiconductor elements mounted on the bottom surface (CVB) of the cavity (CV) can be easily formed.

[0172] In addition, by considering the overall thickness of the core layer, the thickness of each core layer, and the thickness of the buffer layer through the core layer arranged at the outermost side, the etching thickness can be performed considering the position of the core layer when forming the cavity (CV). For example, a laser for etching or cutting can be irradiated considering the thickness or position of the lowest or non-penetrating core layer. As a result, the phenomenon of the surface of the core layer being deformed by the material due to the laser, etc., and the increase in surface roughness can be suppressed. In addition, the generation of micro-cracks in some core layers by high-energy laser irradiation or mechanical cutting can be suppressed, and deformation due to local expansion / contraction of the core layer due to heat can be suppressed. In addition, the manufacturing of the cavity (CV) can also be implemented more easily.

[0173] Fig. 13 is a cross-sectional view of a circuit board according to a fourth embodiment of the present invention, and Fig. 14 is a drawing for K6 in Fig. 13.

[0174] A circuit board (100C) according to the fourth embodiment may include a core layer (110), a buffer layer (BF), an insulating layer (BL), an electrode portion (120), and a protective layer (not shown). In addition, the circuit board (100) according to the embodiment may include a semiconductor element (not shown) and a conductive member (not shown) positioned on one side (e.g., the upper side). In addition to the contents described below, the contents described above or in other embodiments may be applied.

[0175] In this embodiment, the cavity (CV) can penetrate at least a portion of one of the plurality of buffer layers. That is, the cavity (CV) can penetrate at least a portion of one of the plurality of buffer layers while penetrating at least a portion of one of the plurality of core layers.

[0176] For example, the cavity (CV) may penetrate at least a portion of the second buffer layer (BF2). Accordingly, the second buffer layer (BF2) may be exposed by the cavity (CV). A portion of the exposed surface of the second buffer layer (BF2) may be the bottom surface (CVB) of the cavity (CV).

[0177] And the upper surface (BF2US) of the second buffer layer (BF2) can be positioned to form a gap (gap2) in the stacking direction (Y-axis direction) with the lower surface (CVB) of the cavity (CV).

[0178] In this way, the bonding strength of the second buffer layer (BF2) with the electrode portion exposed to the bottom surface (CVB) by the cavity (CV) can be improved. In other words, an additional bonding layer may not be required. Therefore, the manufacturing process can be improved. Furthermore, unlike when the first core layer (111) is exposed, the roughness of the bottom surface (CVB) of the cavity (CV) can be improved. Accordingly, additional semiconductor mounting can be performed more easily.

[0179] Likewise, since some core layers are not penetrated, the phenomenon of the surface roughness increasing due to material deformation by lasers or the like on the surface of the core layer can be suppressed. Furthermore, the formation of microcracks in some core layers by high-energy laser irradiation or mechanical cutting can be suppressed, and deformation due to local expansion / contraction of the core layer due to heat can be suppressed.

[0180] FIGS. 15 to 23 are drawings explaining a method for manufacturing a circuit board according to the first embodiment of the present invention.

[0181] A method for manufacturing a circuit board according to a first embodiment of the present invention may include the steps of providing a plurality of core layers and a plurality of buffer layers, alternately stacking a plurality of core layers and a plurality of buffer layers, forming a via hole, forming a first electrode portion, stacking an insulating layer, forming a second electrode portion and a third electrode portion, and forming a cavity. Additionally, the method may include the steps of mounting a semiconductor element or the like in the cavity, or further arranging a protective layer (e.g., solder resist) or a conductive member thereon. Furthermore, the step of forming the cavity may not be performed when each core layer has a hole structure. As another example, in a circuit board made of a glass core layer, after stacking the core layer and the buffer layer, forming a cavity, and then forming the insulating layer, the second electrode portion, and the third electrode portion.

[0182] And for the same components described above, the same drawing symbols are assigned, and duplicate descriptions for the same components are omitted, and only the differences are described.

[0183] Additionally, the circuit board according to the embodiment may correspond to a unit circuit board. That is, during the manufacturing process, the mother circuit board may be composed of multiple unit circuit boards. The mother circuit board may be separated into multiple unit circuit boards along a sawing line. To form such a mother circuit board, a glass layer may be first placed. The following description will focus on the manufacturing of the unit circuit board.

[0184] Referring to FIGS. 15 and 16, a method for manufacturing a circuit board according to an embodiment may provide a core layer made of glass. The core layers may correspond to the first to fourth core layers described above. Each core layer may undergo a rounding process. For example, in the rounding process, the radius of curvature at the edge or periphery may be 0.5R (e.g., 0.5 mm). Additionally, surface treatment may be performed to reduce surface roughness. Furthermore, a bonding layer may be formed on the upper and / or lower surfaces of each core layer.

[0185] Referring to Fig. 17, multiple core layers and multiple bonding layers can be laminated to alternate with each other. For example, a first buffer layer (BF1), a first core layer (111), a second buffer layer (BF2), a second core layer (112), a third buffer layer (BF3), a third core layer (113), a fourth buffer layer (BF4), a fourth core layer (114), and a fifth buffer layer (BF5) can be sequentially laminated.

[0186] Referring to FIG. 18, via holes (110h) can be formed for multiple core layers and multiple bonding layers. The via holes (110h) can be formed by performing etching on the multiple core layers and the multiple bonding layers. For example, the via holes (110h) can be formed by a photolithography process using a photomask, a laser method, mechanical or chemical etching, etc.

[0187] Furthermore, for a plurality of core layers and a plurality of bonding layers, the via hole (110h) may have an expansion direction, that is, a direction in which the width (or diameter) increases, above and below the center of the via hole (110h). However, this is a description of the overall width or diameter ignoring the convex portion. For example, the description of the expansion direction may be applied to the width or diameter based on the glass core layer. That is, along the lamination direction, the width or diameter of the via hole (110h) may decrease and then increase. However, depending on the process, the width or diameter of the via hole (110h) may be formed in various shapes (such as perpendicular to the upper or lower surface).

[0188] Referring to FIG. 19, a first electrode portion (121) may be formed in a plurality of core layers and a plurality of buffer layers. As an example, a first via electrode (121a) may be formed in a via hole (110h). In addition, a first wiring portion (121b) may be formed on the lower portion of the first buffer layer (BF1) and the upper portion of the fifth buffer layer (BF5).

[0189] For example, a seed layer can be formed in a via hole (110h). And, by performing plating, a first via electrode (121a) can be formed. The first via electrode (121a) can be located within the via hole (110h). That is, the first via electrode (121a) can also penetrate the first buffer layer (BF1), the first core layer (111), the second buffer layer (BF2), the second core layer (112), the third buffer layer (BF3), the third core layer (113), the fourth buffer layer (BF4), the fourth core layer (114), and the fifth buffer layer (BF5).

[0190] The first wiring section (121b) can be formed by a manufacturing process of a printed circuit board, such as an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP).

[0191] Referring to FIG. 20, insulating layers (115, 117) may be applied to the upper and lower portions of the plurality of core layers and the plurality of buffer layers. For example, a third insulating layer (117) may be formed under the first buffer layer (BF1). And a first insulating layer (115) may be formed over the fifth buffer layer (BF5).

[0192] Referring to FIGS. 21 and 22, a second electrode portion (122) and a third electrode portion (123) may be formed on an insulating layer. The formation of the electrode portions may be applied in the same manner as described above. Furthermore, there may be multiple insulating layers.

[0193] Accordingly, a second insulating layer (116) may be laminated on the first insulating layer (115). And a fourth insulating layer (118) may be laminated under the third insulating layer (117). Furthermore, a second electrode portion (122) and a third electrode portion (123) may be formed on each of the second insulating layer (116) and the fourth insulating layer (1128).

[0194] Referring to FIG. 23, a cavity (CV) can be formed in the core layer (110), the insulating layer (BL), and the buffer layer (BF). The cavity (CV) can penetrate at least a portion of the plurality of core layers, at least a portion of the plurality of buffer layers, and at least a portion of the plurality of insulating layers. For example, the cavity (CV) can penetrate at least a portion of the first core layer (111). In other words, the cavity (CV) can penetrate the second buffer layer (BF2), the second core layer (112), the third buffer layer (BF3), the third core layer (113), the fourth buffer layer (BF4), the fourth core layer (114), the fifth buffer layer (BF5), the first insulating layer (115), and the second insulating layer (116).

[0195] As described above, the cavity (CV) can be formed by various methods such as a laser. Furthermore, a through hole for a via electrode in each electrode portion described above can also be formed by various methods. For example, a photoresist (PR) (or resist layer) as a mask can be placed, and exposure can be performed by irradiating light (e.g., ultraviolet (UV)). Alternatively, selective etching can be performed using a photoresist, a chrome mask, an etch-resistant film, etc. Then, etching can be performed to remove the mask, etc. The mask can be removed by etching.

[0196] A circuit board according to an embodiment can be manufactured using the method described above. Subsequently, a protective layer can be formed on or under the insulating layer. Additionally, an opening for a conductive member can be formed in the protective layer.

[0197] In various semiconductor packages, circuit boards according to the various embodiments described above may be located in some areas or correspond to one substrate.

[0198] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0199] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0200] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person with ordinary skill in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0201] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. A first core layer including glass; A second core layer disposed on the first core layer and including glass; A buffer layer disposed on the first core layer and the second core layer; and A circuit board comprising a cavity penetrating at least one of the first core layer and the second core layer and at least a portion of the buffer layer.

2. In paragraph 1, A circuit board in which the first core layer is exposed by the cavity.

3. In paragraph 1, The above cavity is a circuit board that penetrates a portion of the first core layer or the upper surface of the first core layer.

4. In paragraph 1, A circuit board having a groove formed on the lower surface of the first core layer and the upper surface of the second core layer.

5. In paragraph 1, The side wall of the above cavity is a circuit board having a step structure.

6. In paragraph 1, The above buffer layer is, A first buffer layer disposed below the first core layer; A second buffer layer disposed between the first core layer and the second core layer; and A circuit board comprising a third buffer layer disposed on the second core layer.

7. In paragraph 6, The above cavity is a circuit board penetrating the third buffer layer, the second buffer layer, and the second core layer.

8. In paragraph 6, The above cavity includes a side wall and a bottom, A circuit board including a side wall of the cavity extending outwardly; 9. In paragraph 8, A circuit board in which the protrusion overlaps horizontally with the third buffer layer and the second buffer layer.

10. In paragraph 9, The above cavity is, A first region overlapping the second buffer layer in the horizontal direction; A second region overlapping the second core layer in the horizontal direction; and A circuit board comprising a third buffer layer and a third region overlapping in the horizontal direction.

Images