Display panel and display device

Abstract

A display panel and a display device. The display panel comprises an array substrate (001) and an opposite substrate (002) arranged opposite to each other. The array substrate (001) comprises a display area (AA) and at least one binding area (BA) located on one side of the display area (AA). The opposite substrate (002) comprises an inwardly-offset boundary (CL) relative to the array substrate (001), and the orthographic projection of the inwardly-offset boundary (CL) on the array substrate (001) is located between the at least one binding area (BA) and the display area (AA). The array substrate (001) further comprises: a plurality of binding terminals (101), the plurality of binding terminals (101) being located in the at least one binding area (BA); a plurality of signal lines (102) extending across the orthographic projection of the inwardly-offset boundary (CL) on the array substrate (001), and the plurality of signal lines (102) being electrically connected to the plurality of binding terminals (101); and an electrode pattern (103) which is spaced apart from the plurality of binding terminals (101) on the side of the display area (AA) close to the at least one binding area (BA), wherein the electrode pattern (103) is configured to load a fixed potential, the electrode pattern (103) and the inwardly-offset boundary (CL) overlap each other in a direction perpendicular to the display panel, and the electrode pattern (103) is insulated from at least some of the signal lines (102).

Description

Display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays.

[0003] Summary of the Invention

[0004] The specific solutions for the display panel and display device provided in this disclosure are as follows:

[0005] On one hand, an embodiment of this disclosure provides a display panel, comprising:

[0006] An array substrate and a counter substrate are placed opposite each other, wherein the array substrate includes a display area and at least one bonding area located on one side of the display area;

[0007] The opposing substrate includes an inwardly recessed boundary relative to the array substrate, the orthographic projection of the inwardly recessed boundary on the array substrate being located between the at least one bonding area and the display area;

[0008] The array substrate further includes:

[0009] Multiple binding terminals, wherein the multiple binding terminals are located in the at least one binding area;

[0010] Multiple signal lines cross the orthographic projection of the recessed boundary onto the array substrate, and the multiple signal lines are electrically connected to the multiple bonding terminals;

[0011] An electrode pattern is provided at intervals with the plurality of bonding terminals on the side of the display area near the at least one bonding area; the electrode pattern is configured to apply a fixed potential, the electrode pattern overlaps with the recessed boundary in a direction perpendicular to the display panel, and the electrode pattern is insulated from at least a portion of the signal lines.

[0012] In some embodiments, in the display panel provided in the present disclosure, the array substrate further includes at least one fan-out area located between the at least one bonding area and the display area;

[0013] The electrode pattern includes an integrally formed main electrode, which intersects with the multiple signal lines between the bonding area and the fan-out area, and extends to the adjacent fan-out areas.

[0014] In some embodiments, in the display panel provided in this disclosure, the plurality of signal lines include a plurality of data lines;

[0015] The electrode pattern also includes a branch electrode integrally disposed with the main electrode. The branch electrode is located between the bonding area and the fan-out area, and the extension line of the branch electrode overlaps with the extension line of the bonding terminal corresponding to the data line.

[0016] In some embodiments, in the display panel provided in the present disclosure, the plurality of signal lines further include a first ground line located between two adjacent fan-out areas;

[0017] The main electrode is electrically connected to the first grounding wire between adjacent fan-out regions.

[0018] In some embodiments, in the display panel provided in the present disclosure, the main electrode includes a first widened portion located between adjacent fan-out areas, and the first ground wire includes a second widened portion between adjacent fan-out areas, wherein the first widened portion and the second widened portion overlap each other and are electrically connected.

[0019] In some embodiments, in the display panel provided in the present disclosure, the first grounding line is located in the gate metal layer, and the electrode pattern is located at least in the transparent electrode layer;

[0020] The array substrate further includes an insulating layer located between the gate metal layer and the transparent electrode layer, and the second widened portion is electrically connected to the first widened portion through a first via penetrating the insulating layer.

[0021] In some embodiments, in the display panel provided in this disclosure, the electrode pattern is located between the source / drain metal layer and the transparent electrode layer;

[0022] The insulating layer includes a first insulating layer located between the gate metal layer and the source / drain metal layer, and a second insulating layer located between the source / drain metal layer and the transparent electrode layer;

[0023] The second widened portion is electrically connected to the first widened portion of the transparent electrode layer through the first through-hole penetrating the first insulating layer and the second insulating layer;

[0024] A second insulating layer is provided between the electrode pattern of the source / drain metal layer and the electrode pattern of the transparent electrode layer;

[0025] The first widened portion of the source / drain metal layer and the first widened portion of the transparent electrode layer are electrically connected through a second via penetrating the second insulating layer.

[0026] In some embodiments, the display panel provided in this disclosure further includes a sealing adhesive surrounding the display area, wherein the first via and the second via are located on the side of the sealing adhesive closer to the display area.

[0027] In some embodiments, in the display panel provided in the present disclosure, the insulating layer includes a first insulating layer located between the gate metal layer and the source / drain metal layer, and a second insulating layer located between the source / drain metal layer and the transparent electrode layer;

[0028] The electrode pattern is located on the source / drain metal layer and the transparent electrode layer, and the electrode pattern on the source / drain metal layer is in contact with the transparent electrode pattern on the transparent electrode layer.

[0029] In some embodiments, in the display panel provided in the present disclosure, the plurality of signal lines further include a first common electrode line located between the data line and the first ground line, the first common electrode line including a groove structure that avoids the first widening portion and the second widening portion.

[0030] In some embodiments, in the display panel provided in the present disclosure, the plurality of signal lines further include a second grounding line, wherein the second grounding line is at least partially surrounded by the first grounding line on the side of the first grounding line away from the first common electrode line, and the second grounding line intersects with the first widened portion.

[0031] In some embodiments, in the display panel provided in the present disclosure, the first grounding wire is electrically connected to at least one of the bonding terminals, the second grounding wire is electrically connected to at least one of the bonding terminals, and the first common electrode wire is electrically connected to at least one of the bonding terminals;

[0032] At least one floating bonding terminal is provided between the bonding terminal corresponding to the first common electrode line and the bonding terminal corresponding to the data line;

[0033] And / or, at least one floating bonding terminal is provided between the bonding terminal corresponding to the first grounding wire and the bonding terminal corresponding to the first common electrode wire;

[0034] And / or, at least one floating bonding terminal is provided between the bonding terminal corresponding to the second grounding wire and the bonding terminal corresponding to the first grounding wire.

[0035] In some embodiments, in the display panel provided in the present disclosure, the array substrate further includes a first non-display area located on one side of the display area, a second non-display area opposite to the first non-display area, and two third non-display areas connecting the first non-display area and the second non-display area; wherein, the first non-display area includes the at least one bonding area;

[0036] The plurality of signal lines further includes at least one third grounding line located within the second non-display area and the third non-display area, the third grounding line being electrically connected to at least one of the bonding terminals near the third non-display area.

[0037] In some embodiments, in the display panel provided in the present disclosure, the plurality of signal lines further include: a data test line located in the third non-display area on the side of the at least one third ground line near the display area;

[0038] The data test line is electrically connected to at least one of the bonding terminals near the third non-display area, and the bonding terminal corresponding to the data test line is located on the side of the bonding terminal corresponding to the third ground line away from the third non-display area.

[0039] In some embodiments, in the display panel provided in the present disclosure, at least one floating bonding terminal is provided between the bonding terminal corresponding to the data test line and the bonding terminal corresponding to the at least one third grounding line.

[0040] In some embodiments, the display panel provided in this disclosure further includes silver paste dots located between the display area and the at least one bonding area; the electrode pattern is electrically connected to the third grounding wire through the silver paste dots.

[0041] In some embodiments, the display panel provided in this disclosure further includes a shielding electrode located on the side of the opposing substrate away from the array substrate, and the shielding electrode is electrically connected to the third grounding wire through the silver paste dots.

[0042] In some embodiments, in the display panel provided in the present disclosure, at least two adjacent signal lines partially wound around the display area include opposing tip structures.

[0043] In some embodiments, the display panel provided in this disclosure further includes a sealing adhesive surrounding the display area, the sealing adhesive covering the signal line furthest from the display area.

[0044] On the other hand, this disclosure provides a display device, including the display panel provided in this disclosure and a backlight module located on the light-incident side of the display panel.

[0045] In some embodiments, the display device provided in this disclosure further includes a circuit board electrically connected to the plurality of bonding terminals, the circuit board including an overvoltage protection device;

[0046] The array substrate includes a data test line and at least one third ground line. The bonding terminal corresponding to the data test line is electrically connected to the overvoltage protection device, and / or the bonding terminal corresponding to the third ground line farthest from the display area is electrically connected to the overvoltage protection device.

[0047] In some embodiments, in the display device provided in the present disclosure, the overvoltage protection device is a varistor and / or a transient suppression diode. Attached Figure Description

[0048] Figure 1 is a schematic diagram of a display panel provided in an embodiment of this disclosure;

[0049] Figure 2 is an enlarged structural diagram of region Z1 in Figure 1;

[0050] Figure 3 is an enlarged structural diagram of region Z2 in Figure 2;

[0051] Figure 4 is an enlarged structural diagram of region Z3 in Figure 2;

[0052] Figure 5 is an enlarged structural diagram of region Z4 in Figure 4;

[0053] Figure 6 is an enlarged structural diagram of region Z5 in Figure 5;

[0054] Figure 7 is a schematic diagram of the gate metal layer in Figure 5;

[0055] Figure 8 is a schematic diagram of the source / drain metal layer in Figure 5;

[0056] Figure 9 is a schematic diagram of the structure of the layer where the vias are located in Figure 5;

[0057] Figure 10 is a schematic diagram of the transparent electrode layer in Figure 5;

[0058] Figure 11 is an enlarged structural diagram of region Z6 in Figure 4;

[0059] Figure 12 is an enlarged structural diagram of region Z7 in Figure 11;

[0060] Figure 13 is a schematic diagram of the cross-sectional structure along line I-I' in Figure 12;

[0061] Figure 14 is a schematic diagram of the gate metal layer in Figure 11;

[0062] Figure 15 is a schematic diagram of the source / drain metal layer in Figure 11;

[0063] Figure 16 is a schematic diagram of the structure of the layer where the vias are located in Figure 11;

[0064] Figure 17 is a schematic diagram of the transparent electrode layer in Figure 11;

[0065] Figure 18 is an enlarged structural diagram of region Z8 in Figure 1;

[0066] Figure 19 is a schematic diagram of another structure of the display panel provided in an embodiment of this disclosure;

[0067] Figure 20 is a partial enlarged view of the structure of adjacent signal lines provided in an embodiment of this disclosure;

[0068] Figure 21 is a schematic diagram of a cross-sectional structure along line II-II' in Figure 20;

[0069] Figure 22 is a schematic diagram of another cross-sectional structure along line II-II' in Figure 20;

[0070] Figure 23 is a schematic diagram of another structure of the display panel provided in an embodiment of this disclosure;

[0071] Figure 24 is a schematic diagram of a display device provided in an embodiment of this disclosure;

[0072] Figure 25 is a schematic diagram of another structure of the display device provided in the embodiments of this disclosure. Detailed Implementation

[0073] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shape of the regions or reflect true proportions; their purpose is merely to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0074] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0075] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0076] Display panels face the risk of electrostatic discharge (ESD) damage during production, assembly, and use. To verify the panel's ESD resistance, an electrostatic discharge assessment is conducted using an electrostatic gun, either in the air or in contact, during the quality evaluation process.

[0077] In some embodiments, the top, left, and right bezels of the display panel are provided with a grounding wire to enhance anti-static capability. When static electricity is generated at the bottom bezel, it can easily burn out the drive circuit (e.g., COF flip-chip) in the bonding area or the vias of the fanout traces in the fanout area, thereby causing display abnormalities.

[0078] To at least improve the aforementioned technical problems, this disclosure provides a display panel. Figure 1 is a structural schematic diagram of the display panel provided in this disclosure embodiment; Figure 2 is an enlarged structural schematic diagram of region Z1 in Figure 1; Figure 3 is an enlarged structural schematic diagram of region Z2 in Figure 2; Figure 4 is an enlarged structural schematic diagram of region Z3 in Figure 2; Figure 5 is an enlarged structural schematic diagram of region Z4 in Figure 4; Figure 6 is an enlarged structural schematic diagram of region Z5 in Figure 5; Figure 7 is a structural schematic diagram of the gate metal layer in Figure 5; and Figure 8 is a structural schematic diagram of the source / drain metal layer in Figure 5. Figure 9 is a schematic diagram of the structure of the layer containing the via in Figure 5; Figure 10 is a schematic diagram of the structure of the transparent electrode layer in Figure 5; Figure 11 is an enlarged schematic diagram of the structure of region Z6 in Figure 4; Figure 12 is an enlarged schematic diagram of the structure of region Z7 in Figure 11; Figure 13 is a schematic diagram of the cross-sectional structure along line I-I' in Figure 12; Figure 14 is a schematic diagram of the structure of the gate metal layer in Figure 11; Figure 15 is a schematic diagram of the structure of the source / drain metal layer in Figure 11; Figure 16 is a schematic diagram of the structure of the layer containing the via in Figure 11; and Figure 17 is a schematic diagram of the structure of the transparent electrode layer in Figure 11.

[0079] As can be seen from Figures 1 to 17, the display panel provided in the embodiments of this disclosure may include:

[0080] The array substrate 001 and the opposing substrate 002 are placed opposite each other. The array substrate 001 includes a display area AA and at least one bonding area BA located on one side of the display area AA. Optionally, the display area AA may include a red sub-pixel area, a green sub-pixel area, a blue sub-pixel area, etc. The bonding area BA may be bonded to a driving circuit (such as a flexible circuit board FPC, or a driving circuit for bonding a data chip source IC, etc.). The non-display area where the bonding area BA is located is a first non-display area DP. The array substrate 001 may also include a second non-display area DPO placed opposite the first non-display area DP, and two third non-display areas GL&GR connecting the first non-display area DP and the second non-display area DPO.

[0081] The opposing substrate 002 includes an inward boundary CL relative to the array substrate 001. The orthographic projection of the inward boundary CL on the array substrate 001 is located between the bonding area BA and the display area AA, so as to expose the bonding area BA and facilitate the bonding connection between the bonding area BA and the driving circuit (such as a flexible circuit board FPC, or a driving circuit for bonding a data chip source IC, etc.).

[0082] The array substrate 001 may also include:

[0083] Multiple bonding terminals 101 are located in at least one bonding region BA. In some embodiments, this disclosure has multiple bonding regions BA, and the number and arrangement of bonding terminals 101 in each bonding region BA can be the same or different. Optionally, the bonding terminals 101 are located on a gate metal layer (GT) and a transparent electrode layer (ITO). The pattern on the gate metal layer (GT) and the pattern on the transparent electrode layer (ITO) of the same bonding terminal 101 are electrically connected through a connection hole V. In some embodiments, the material of the gate metal layer (GT) may include at least one metal such as gold (Au), silver (Ag), copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). The gate metal layer (GT) can be a single-layer structure or a stacked structure. For example, the gate metal layer (GT) is a single-layer structure composed of a molybdenum metal layer. The material of the transparent electrode layer (ITO) may include at least one transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc aluminum oxide (AZO), and zinc gallium oxide (GZO). Additionally, it should be noted that the array substrate 001 in this disclosure may include only the transparent electrode layer where the pixel electrode is located, or it may include both the transparent electrode layer where the pixel electrode is located and the transparent electrode layer where the common electrode (com) is located. In the case where the array substrate 001 has two transparent electrode layers, the transparent electrode layer where the bonding terminal 101 is located is the transparent electrode layer that is closer to the opposing substrate 002.

[0084] Multiple signal lines 102 cross the orthographic projection of the indentation boundary CL onto the array substrate 001. The multiple signal lines CL are electrically connected to multiple bonding terminals 101. Optionally, the signal lines 102 located in the bonding area BA can be multiplexed as the gate metal layer (GT) pattern of the corresponding bonding terminal 101. In some embodiments, the signal lines 102 may include data lines (DL), gate drive circuit lines (GOA lines), ground lines (GND lines), and common electrode lines (Com lines). The gate drive circuit lines (GOA lines), ground lines (GND lines), and common electrode lines (Com lines) may be located outside the display area AA, while the data lines DL are located both inside and outside the display area AA. The data lines DL can be disposed in different layers or in the same layer inside and outside the display area AA. Optionally, the data lines DL are located in the source / drain metal layer (SD) inside the display area AA and in the gate metal layer (GT) outside the display area AA.

[0085] The data line DL can be electrically connected to the bonding terminal 101 in the middle of each bonding area BA. The gate drive line (GOA line) and the ground line (GND line) can be electrically connected to the bonding terminal 101 on the left edge of the left bonding area BA and the bonding terminal 101 on the right edge of the right bonding area BA. The common electrode line (Com line) can be electrically connected to the bonding terminal 101 on the right edge of the left bonding area BA, the bonding terminal 101 on the left edge of the right bonding area BA, and the bonding terminals 101 on the left and right edges of the middle bonding area BA.

[0086] In some embodiments, the gate drive line (GOA line) may include one or more of the following: frame start signal lines STV1A and STV1B, total reset signal line STV0, clock signal lines CLK1 to CLK12 (specifically, the number of clock signal lines is not limited; this example uses 12 lines), noise reduction signal lines VDDO and VDDE, and low-level signal line VGL. The frame start signal line may be one or more, which is not limited here. This example uses two frame start signal lines as an example. Frame start signal lines STV1A and STV1B are the trigger input signals for odd-numbered and even-numbered rows, respectively. Clock signal lines CLK1 to CLK12 are responsible for providing the output voltage of each row's gate. Noise reduction signal lines VDDO and VDDE provide input signals to the noise reduction unit of the gate drive circuit, with a 50% duty cycle and alternating high and low levels. The low-level signal line VGL provides an internal low-level voltage to the gate drive circuit.

[0087] Electrode patterns 103 are spaced apart from multiple bonding terminals 101 on the side of the display area AA near the bonding area BA to prevent the multiple bonding terminals 101 from being short-circuited through the electrode patterns 103. Optionally, to achieve the effect of shielding against static electricity, the electrode patterns 103 are configured to carry a fixed potential (e.g., ground). The electrode patterns 103 may also overlap with the recessed boundary CL in a direction perpendicular to the display panel to protect the signal lines 102 of the film layer below the electrode patterns 103 during the cutting process to form the recessed boundary CL. In some embodiments, the electrode patterns 103 are at least insulated from at least a portion of the signal lines 102, for example, the electrode patterns 103 are insulated from signal lines 102 carrying non-fixed potentials such as data lines DL and gate drive circuit signal lines (GOA lines) to prevent the electrode patterns 103 from causing signal crosstalk to the non-fixed potential signal lines 102. Optionally, the electrode pattern 103 may be located on the transparent electrode layer (ITO) where the bonding terminal 101 is located, or the electrode pattern 103 may be located on the transparent electrode layer (ITO) where the bonding terminal 101 is located and the source / drain metal layer (SD). The material of the source / drain metal layer (SD) may include at least one metal such as gold (Au), silver (Ag), copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). The source / drain metal layer (SD) may be a single-layer structure or a stacked structure. For example, the source / drain metal layer (SD) may be a stacked structure composed of a titanium metal layer / aluminum metal layer / titanium metal layer.

[0088] In the display panel provided in this embodiment, by providing an electrode pattern 103 on the DP side where the bonding area BA is located, electrostatic shielding can be provided when static electricity is generated on the DP side, thereby improving the antistatic capability of the panel on the DP side. Furthermore, the electrode pattern 103 is spaced apart from the bonding terminal 101 and insulated from the signal line 102 which has a non-fixed potential, preventing short circuits between the electrode pattern 103 and the bonding terminal 101 or the signal line 102. Simultaneously, the electrode pattern 103 can also prevent the signal line 102 from being cut during the cutting process of the opposing substrate 102. Therefore, the addition of the electrode pattern 103 improves the antistatic capability without affecting the normal display function.

[0089] In some embodiments, in the display panel provided in the present disclosure, as shown in Figures 1 to 10, the array substrate 001 may further include at least one fan-out area FA located between the bonding area BA and the display area AA; the electrode pattern 103 may include a main electrode 1031, which intersects with multiple signal lines 102 between the bonding area BA and the fan-out area FA and extends to adjacent fan-out areas FA, thus ensuring that the main electrode 1031 has a large area and strong antistatic ability. A floating structure can be provided to cut and protect the signal lines 102. In this disclosure, each floating structure can be connected together in its arrangement direction (i.e., the left-right direction shown in the figure) as the main electrode 1031. Alternatively, if the wiring space allows, to further increase the area of ​​the main electrode 1031 and improve the antistatic ability, the main electrode 1031 can cover the pattern of each floating structure connected in its arrangement direction (i.e., the left-right direction shown in the figure).

[0090] In some embodiments, as shown in Figures 1 to 6, the electrode pattern 103 in the above-described display panel provided in this disclosure may further include branch electrodes 1032 integrally disposed with the main electrode 1031, such that the electrode pattern 103 has a comb-like structure. The branch electrode 1032 is located between the bonding area BA and the fan-out area FA, and the extension line of the branch electrode 1032 overlaps with the extension line of the bonding terminal 101 corresponding to the data line DL (Figures 5 and 7 show the complete patterns of the two data lines DL near the first common electrode line COM1, and the remaining data lines DL show the pattern of vertical extension and omit the pattern of oblique extension). Optionally, the extended branch electrode 1032 substantially coincides with the bonding terminal 101 corresponding to the data line DL. In some embodiments, the branch electrode 1032 may be reused with the floating structure that cuts and protects the signal line 102 in the related art. In this case, this disclosure only needs to add a main electrode 1031 connecting the floating structure together on the side of the floating structure near the fan-out area FA to obtain the comb-like electrode pattern 103.

[0091] It should be noted that in the embodiments provided in this disclosure, due to limitations of process conditions or the influence of other factors such as measurement, "approximately coincident" may coincide exactly, or there may be some deviation (e.g., a deviation of ±2μm). Therefore, as long as the relationship of "approximately coincident" between related features meets the error allowance, it is within the protection scope of this disclosure.

[0092] In some embodiments, as shown in FIG1, FIG3 to FIG17, a first grounding wire GND1 may be provided between two adjacent fan-out areas FA, and the main electrode 1031 may be electrically connected to the first grounding wire GND1 so that the electrode pattern 103 conducts static electricity to the external ground through the first grounding wire GND1 for release.

[0093] In some embodiments, in the display panel provided in this disclosure, as shown in Figures 1, 3, 4, and 11 to 17, to enhance the electrical connection effect, the main electrode 1031 may include a first widened portion WP1 located between adjacent fan-out regions FA, and the first ground wire GND1 includes a second widened portion WP2 located between adjacent fan-out regions FA. The first widened portion WP1 and the second widened portion WP2 overlap and are electrically connected. Optionally, the first ground wire GND1 is located on the gate metal layer (GT), and the electrode pattern 103 is located at least on the transparent electrode layer (ITO). An insulating layer 104 is provided between the gate metal layer (GT) and the transparent electrode layer (ITO), and the second widened portion WP2 is electrically connected to the first widened portion WP1 through a first via V1 penetrating the insulating layer 104. In some embodiments, the electrode pattern 103 is located simultaneously on the source / drain metal layer (SD) and the transparent electrode layer (ITO); the insulating layer 104 includes a first insulating layer 1041 located between the gate metal layer (GT) and the source / drain metal layer (SD), and a second insulating layer 1042 located between the source / drain metal layer (SD) and the transparent electrode layer (ITO); the second widening portion WP2 is electrically connected to the first widening portion WP1 of the transparent electrode layer (ITO) through a first via V1 penetrating the first insulating layer 1041 and the second insulating layer 1042.

[0094] In some embodiments of the display panel provided in this disclosure, as shown in FIGS. 11 to 17, when a second insulating layer 1042 is provided between the electrode pattern 103 of the source / drain metal layer (SD) and the electrode pattern 103 of the transparent electrode layer (ITO), the first widened portion WP1 of the source / drain metal layer (SD) and the first widened portion WP1 of the transparent electrode layer (ITO) are electrically connected through a second via V2 penetrating the second insulating layer 1042. Optionally, as shown in FIG. 3, the first via V1 and the second via V2 may be located on the side of the sealant 105 near the display area AA, so as to prevent water and oxygen from eroding the first via V1 and the second via V2 through the sealant 105. Optionally, when the source / drain metal layer (SD) is located between the gate metal layer (GT) and the transparent electrode layer (ITO), as shown in FIG. 12, the first widened portion WP1 of the source / drain metal layer (SD) may include a cutout structure O exposing the first via V1. Furthermore, the orthographic shape and size of the first via V1 and the second via V2 in this disclosure can be approximately the same as the orthographic shape and size of the connection hole V of the bonding terminal 101, in order to simplify the via fabrication process. In some other embodiments, the second insulating layer 1042 may be omitted between the electrode pattern 103 of the source / drain metal layer (SD) and the electrode pattern 103 of the transparent electrode layer (ITO), so that the electrode pattern 103 of the source / drain metal layer (SD) and the electrode pattern 103 of the transparent electrode layer (ITO) are in contact.

[0095] In some embodiments, as shown in Figures 3 to 17, a first common electrode line Com1 may be provided between the data line DL and the first ground line GND1 in the display panel provided in the embodiments of this disclosure. Optionally, the first ground line GND1 and the first common electrode line Com1 may be disposed in the same layer and made of the same material. For example, the first ground line GND1 and the first common electrode line Com1 are located in the gate metal layer (GT). In some embodiments, the first common electrode line Com1 includes a groove structure GS that avoids the first widening portion WP1 and the second widening portion WP2 to prevent the first common electrode line Com1 from being short-circuited with the first common electrode line Com1.

[0096] In some embodiments, in the display panel provided in the present disclosure, as shown in Figures 4 to 17, the signal line 102 may further include a second grounding line GND2 disposed on the same layer and of the same material as the first grounding line GND1 between adjacent fan-out areas FA. The second grounding line GND2 is at least partially surrounded by the first grounding line GND1 on the side of the first grounding line GND1 away from the first common electrode line Com1, and the second grounding line GND2 is disposed intersecting with the first widened portion WP1, so as to further improve the antistatic capability by utilizing the second grounding line GND2. Optionally, the second grounding line GND2 and the first widened portion WP1 may be electrically connected or insulated from each other, which is not limited in this disclosure.

[0097] In some embodiments, in the display panel provided in this disclosure, as shown in Figures 4 to 10, the first grounding wire GND1 can be electrically connected to at least one bonding terminal 101, the second grounding wire GND2 can be electrically connected to at least one bonding terminal 101, and the first common electrode wire Com1 can be electrically connected to at least one bonding terminal 101. When the first grounding wire GND1, the second grounding wire GND2, and the first common electrode wire Com1 are respectively electrically connected to multiple bonding terminals 101, the bonding effect can be enhanced, and the electrostatic discharge path of the grounding wires (including the first grounding wire GND1 and the second grounding wire GND2) can be increased, thereby improving the speed of electrostatic charge release. Optionally, at least one floating bonding terminal 101 is provided between the bonding terminal 101 corresponding to the first common electrode line Com1 and the bonding terminal 101 corresponding to the data line DL; and / or, at least one floating bonding terminal 101 is provided between the bonding terminal 101 corresponding to the first ground line GND1 and the bonding terminal 101 corresponding to the first common electrode line Com1; and / or, at least one floating bonding terminal 101 is provided between the bonding terminal 101 corresponding to the second ground line GND2 and the bonding terminal 101 corresponding to the first ground line GND1. By adding floating bonding terminals 101 to the bonding terminals 101 corresponding to the first ground line GND1 and the second ground line GND2 and other signals (such as the first common electrode line Com1), it is possible to effectively prevent electrostatic discharge of the gold ball at the bonding position from burning other signal lines (such as the first common electrode line Com1).

[0098] In some embodiments, in the display panel provided in the present disclosure, FIG18 is an enlarged structural schematic diagram of the Z8 region in FIG1, and FIG19 is another structural schematic diagram of the display panel provided in the present disclosure. As shown in FIG1, FIG18 and FIG19, in order to increase the electrostatic discharge path and improve the antistatic capability, at least one third grounding wire GND3 can be provided in the second non-display area DPO and the third non-display area GL&GR, and the third grounding wire GND3 can be electrically connected to at least one bonding terminal 101 near the third non-display area GL&GR. For example, the third grounding wire GND3 is electrically connected to 1 to 4 bonding terminals 101 near the third non-display area GL&GR.

[0099] In some embodiments of the display panel provided in this disclosure, as shown in Figures 1 and 18, a data test line ADD is provided on the side of the third grounding line GND3 near the display area AA. The data test line ADD is electrically connected to at least one (e.g., four) bonding terminals 101 near the third non-display area GL&GR, and the bonding terminal 101 corresponding to the data test line ADD is located on the side of the bonding terminal 101 corresponding to the third grounding line GND3 away from the third non-display area GL&GR. The data test line ADD is used to detect whether there is a broken wire in the data line DL in the array stage, and to conduct static electricity on the data line DL to the grounding line or common electrode line in the cell stage. When the data test line ADD is electrically connected to multiple bonding terminals 101, the static discharge path is increased, the static discharge speed is improved, and thus the anti-static capability can be effectively improved.

[0100] In some embodiments, as shown in FIG18, in the display panel provided in the present disclosure, at least one floating bonding terminal 101 may be provided between the bonding terminal 101 corresponding to the data test line ADD and the bonding terminal 101 corresponding to the third ground line GND3, so as to prevent the electrostatic discharge of the third ground line GND3 from burning the data test line ADD.

[0101] In some embodiments of the display panel provided in this disclosure, FIG20 is a partial enlarged view of the structure of adjacent signal lines 102 provided in this disclosure. As shown in FIG20, in addition to the third ground line GND3 and data test line ADD that are at least partially wound around the display area AA, the signal lines 102 may also include the second common electrode line Com2, clock signal line CLK, etc., that are at least partially wound around the display area AA. The line width of these signal lines 102 may vary due to wiring limitations, and the thinnest part of the trace is usually preferentially broken down when static electricity is generated. In this regard, at least some adjacent signal lines 102 in this disclosure may include serrated tip structures arranged opposite each other to release accumulated static electricity through the tip structures, preventing electrostatic breakdown at the thinner part of the signal lines 102. Furthermore, since there are many serrated tip structures, static electricity is preferentially attracted to the tip structures for release, and has almost no impact on the effective trace of signal transmission. In some embodiments, the distance between the oppositely arranged tip structures is greater than or equal to ≥5μm.

[0102] In some embodiments, as shown in FIG21, the sealant 105 may cover the clock signal line CLK, the second common electrode line Com2, and partially overlap with the data test line ADD. The third ground line GND3 is located outside the sealant 105 (i.e., the side away from the display area AA) and is not covered by the sealant 105. Since the third ground line GND3 in the signal line 102 is closest to the cutting line of the panel on the DPO side and GL&GR side (i.e., the flush boundary between the array substrate 001 and the opposing substrate 002 on the DPO side and GL&GR side), when static electricity is generated, static electricity can easily enter from the gap between the array substrate 001 and the opposing substrate 002, causing the third ground line GND3 exposed by the sealant 105 to burn out. Based on this, as shown in Figure 22, in some embodiments, the sealing adhesive 105 can be set to cover the third grounding wire GND3, which is furthest from the display area AA. This allows the sealing adhesive 105 to shield / absorb and consume static electricity when it is generated, so that the static electricity cannot actually act on the third grounding wire GND3 or the static electricity value is very small and not enough to burn the third grounding wire GND3, thereby enhancing the anti-static capability of the panel.

[0103] In some embodiments, the display panel provided in this disclosure, as shown in FIG23, may further include a shielding electrode 003 located on the side of the opposing substrate 002 away from the array substrate 001. This shielding electrode 003 can be electrically connected to the third grounding wire GND3 via the silver paste dots AD (Ag dot) shown in FIG2, thereby further improving the anti-static capability of the display panel. It should be understood that in this disclosure, a good anti-static effect can be achieved using the above-described scheme other than the shielding electrode 003. Therefore, the shielding electrode 003 may be omitted in this disclosure to suit FIC / low reflectivity products. It should be noted that in this case, the connection between the electrode pattern 103 and the GND signal can be achieved by providing a signal through the pads (i.e., bonding terminals 101) corresponding to the GND1 signal lines between adjacent COFs, or by enabling signal conduction through the pads corresponding to the third ground line GND3, or by simultaneously enabling signal conduction through the pads corresponding to the GND1 signal lines between adjacent COFs and the pads corresponding to the third ground line GND3. This is not limited here. In addition, as shown in Figure 2, the electrode pattern 103 of this disclosure can also be electrically connected to the third ground line GND3 through silver paste dots AD, so that the electrode pattern 103 can conduct static electricity to the external ground through the third ground line GND3 for release, thereby further improving the antistatic capability.

[0104] In some embodiments, as shown in FIG1, 4, and 18, the array substrate 001 may further include an alignment mark MK located on the gate metal layer (GT), a dummy pattern DY located on the transparent electrode layer (ITO), and a gate drive circuit GOA located in the third non-display area GL&GR. Additionally, to enhance the curing effect of the sealant 105, as shown in FIG5, areas with larger linewidths of signal lines 102, such as the first common electrode line com1, can be cut out. Other essential components of the array substrate are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limitations on this disclosure.

[0105] In some embodiments, as shown in FIG23, in the display panel provided in the present disclosure, a liquid crystal layer 004 may be disposed between the array substrate 001 and the opposing substrate 002. A first polarizer 005 may be disposed on the side of the array substrate 001 away from the opposing substrate 002, and a second polarizer 006 may be disposed on the side of the opposing substrate 002 away from the array substrate 001. The polarization direction of the first polarizer 005 and the polarization direction of the second polarizer 006 are perpendicular to each other. Other essential components of the display panel are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the present disclosure.

[0106] Based on the same inventive concept, this disclosure provides a display device. Figures 24 and 25 are schematic diagrams of a structure of the display device provided in this disclosure. As shown in Figures 24 and 25, the display device provided in this disclosure may include the display panel PNL provided in this disclosure, and a backlight module BLU located on the light-incident side of the display panel PNL. The backlight module BLU may be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source may be light-emitting devices (LEDs), such as quantum dot light-emitting devices.

[0107] In some embodiments, the LEDs can also be micro-light-emitting devices (such as Mini LEDs and Micro LEDs). Sub-millimeter or even micrometer-scale micro-light-emitting devices, like organic light-emitting devices (OLEDs), are self-emissive devices. Like OLEDs, they offer advantages such as high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic light-emitting devices emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic light-emitting devices (based on organic materials) in terms of lower power consumption, greater resistance to high and low temperatures, and longer lifespan. Moreover, when micro-light-emitting devices are used as backlights, they can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while also solving the glare problem caused by traditional dynamic backlighting between bright and dark areas of the screen, thus optimizing the visual experience.

[0108] In some embodiments, the display device provided in the present disclosure, as shown in FIG25, may further include a circuit board XPCB electrically connected to a plurality of bonding terminals 101. The circuit board XPCB includes an overvoltage protection device OVP (e.g., a varistor and / or a transient voltage suppressor diode TVS). Optionally, the bonding terminal 101 corresponding to the data test line ADD is electrically connected to the overvoltage protection device OVP, and / or the bonding terminal 101 corresponding to the third ground line GND3 farthest from the display area AA is electrically connected to the overvoltage protection device OVP. Under normal conditions, the data test line ADD and the third grounding line GND3 are disconnected. When electrostatic high voltage arrives, it will cause the data test line ADD and the third grounding line GND3 to become connected, achieving rapid discharge of static electricity. In addition, the outermost third grounding line GND3 has an overvoltage protection device OVP connected in series on the XPCB, and then connected in parallel with the inner third grounding line GND3. The other grounding designs of the XPCB can be consistent with relevant technologies. In this way, when the display panel is working normally, the GND signal at the circuit end mainly acts through the inner third grounding line GND3. When a momentary electrostatic high voltage is generated, the outer third grounding line GND3 with the overvoltage protection device OVP can absorb the excess current and clamp the voltage to a relatively fixed voltage value to protect the in-plane traces, thereby improving the anti-static capability of the panel.

[0109] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a television, monitor, projector, 3D printer, virtual reality device, mobile phone, tablet computer, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include memory, a power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or arrange different components.

[0110] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0111] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A display panel, wherein, Comprising: opposite array substrate and opposite substrate, wherein the array substrate comprises a display area, and at least one binding area located on one side of the display area; The opposite substrate comprises a retracted boundary relative to the array substrate, and the orthogonal projection of the retracted boundary on the array substrate is located between the at least one binding area and the display area; The array substrate further comprises: A plurality of binding terminals, the plurality of binding terminals are located in the at least one binding area; A plurality of signal lines, the orthogonal projection of the plurality of signal lines on the array substrate across the retracted boundary, the plurality of signal lines are electrically connected with the plurality of binding terminals; The electrode pattern is arranged between the display area and the plurality of binding terminals; the electrode pattern is configured to load a fixed potential, the electrode pattern and the retracted boundary are mutually overlapped in the direction perpendicular to the display panel, and the electrode pattern and at least part of the signal line are mutually insulated.

2. The display panel of claim 1, wherein, The array substrate further comprises at least one fan-out area between the at least one binding area and the display area; The electrode pattern comprises a trunk electrode arranged integrally, the trunk electrode crosses the plurality of signal lines between the binding area and the fan-out area, and extends to between adjacent fan-out areas.

3. The display panel of claim 2, wherein, The plurality of signal lines comprises a plurality of data lines; The electrode pattern further comprises a branch electrode arranged integrally with the trunk electrode, the branch electrode is located between the binding area and the fan-out area, and the extension line of the branch electrode and the extension line of the binding terminal corresponding to the data line are mutually overlapped.

4. The display panel of claim 3, wherein, The plurality of signal lines further comprises a first ground line between adjacent two fan-out areas; The trunk electrode and the first ground line are electrically connected between adjacent fan-out areas.

5. The display panel of claim 4, wherein, The trunk electrode comprises a first widened part between adjacent fan-out areas, the first ground line comprises a second widened part between adjacent fan-out areas, the first widened part and the second widened part are mutually overlapped and electrically connected.

6. The display panel of claim 5, wherein, The first ground line is located in a gate metal layer, and the electrode pattern is located in a transparent electrode layer; The array substrate further comprises an insulating layer between the gate metal layer and the transparent electrode layer, and the second widened part is electrically connected with the first widened part through a first via hole penetrating the insulating layer.

7. The display panel of claim 6, wherein, The electrode pattern is located in a source-drain metal layer and the transparent electrode layer; The insulating layer comprises a first insulating layer between the gate metal layer and the source-drain metal layer, and a second insulating layer between the source-drain metal layer and the transparent electrode layer; The second widened part is electrically connected with the first widened part of the transparent electrode layer through the first via hole penetrating the first insulating layer and the second insulating layer; The electrode pattern of the source-drain metal layer and the electrode pattern of the transparent electrode layer have the second insulating layer therebetween; The first widened part of the source-drain metal layer and the first widened part of the transparent electrode layer are electrically connected through a second via hole penetrating the second insulating layer.

8. The display panel of claim 7, wherein, The array substrate further comprises a sealant surrounding the display area, the first via and the second via are located on a side of the sealant close to the display area.

9. The display panel of claim 6, wherein, The insulating layer comprises a first insulating layer between the gate metal layer and the source-drain metal layer, and a second insulating layer between the source-drain metal layer and the transparent electrode layer. The electrode pattern is located on the source-drain metal layer and the transparent electrode layer, and the electrode pattern of the source-drain metal layer is arranged in contact with the transparent electrode pattern of the transparent electrode layer.

10. The display panel of any of claims 5-9, wherein, The plurality of signal lines further comprises a first common electrode line between the data line and the first ground line, and the first common electrode line comprises a groove structure avoiding the first widened portion and the second widened portion.

11. The display panel of claim 10, wherein, The plurality of signal lines further comprises a second ground line, and the second ground line is at least partially surrounded by the first ground line on a side of the first ground line away from the first common electrode line, and the second ground line is arranged to intersect the first widened portion.

12. The display panel of claim 11, wherein, The first ground line is electrically connected to at least one of the bonding terminals, the second ground line is electrically connected to at least one of the bonding terminals, and the first common electrode line is electrically connected to at least one of the bonding terminals. At least one of the bonding terminals is floating between the bonding terminal corresponding to the first common electrode line and the bonding terminal corresponding to the data line. At least one of the bonding terminals is floating between the bonding terminal corresponding to the first ground line and the bonding terminal corresponding to the first common electrode line. At least one of the bonding terminals is floating between the bonding terminal corresponding to the second ground line and the bonding terminal corresponding to the first ground line.

13. The display panel of any one of claims 1 to 12, wherein, The array substrate further comprises a first non-display area on a side of the display area, a second non-display area opposite to the first non-display area, and two third non-display areas connecting the first non-display area and the second non-display area; wherein the first non-display area comprises the at least one binding area. The plurality of signal lines further comprises at least one third ground line in the second non-display area and the third non-display area, and the third ground line is electrically connected to at least one of the bonding terminals close to the third non-display area.

14. The display panel of claim 13, wherein, The plurality of signal lines further comprises a data test line in the third non-display area on a side of the at least one third ground line close to the display area. The data test line is electrically connected to at least one of the bonding terminals close to the third non-display area, and the bonding terminal corresponding to the data test line is located on a side of the bonding terminal corresponding to the third ground line away from the third non-display area. At least one of the bonding terminals is floating between the bonding terminal corresponding to the data test line and the bonding terminal corresponding to the at least one third ground line.

15. The display panel of claim 14, wherein, The array substrate further comprises a silver paste point between the display area and the at least one binding area; and the electrode pattern is electrically connected to the third ground line through the silver paste point.

16. The display panel of any of claims 13-15, wherein, ​ 17. The display panel of claim 16, wherein, The display panel further comprises a shielding electrode on a side of the opposite substrate distal to the array substrate, and the shielding electrode is electrically connected to the third ground line through the silver paste point.

18. The display panel of any one of claims 1-17, wherein, At least part of the two adjacent signal lines around the display area comprises a relatively arranged sharp end structure.

19. The display panel of any one of claims 1-18, wherein, The display panel further comprises a frame sealant around the display area, and the frame sealant covers the signal line farthest from the display area.

20. A display device comprising: The display panel further comprises a backlight module on a light-in side of the display panel.

21. The display device of claim 20, wherein, The display panel further comprises a circuit board electrically connected to the plurality of binding terminals, and the circuit board comprises an overvoltage protection device. The array substrate comprises a data test line and at least one third ground line, the binding terminal corresponding to the data test line is electrically connected to the overvoltage protection device, and / or the binding terminal corresponding to the third ground line farthest from the display area is electrically connected to the overvoltage protection device.

22. The display device of claim 21, wherein, The overvoltage protection device is a pressure-sensitive resistor and / or a transient suppression diode.

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