Solar cell, preparation method for solar cell, and photovoltaic module

Abstract

The present application relates to the technical field of photovoltaics, and discloses a solar cell, a preparation method for the solar cell, and a photovoltaic module. The solar cell comprises: a substrate, wherein the substrate has a first surface and a second surface opposite to each other, and the first surface comprises a first region and a second region spaced apart from each other and a third region located between the first region and the second region; a first doped layer and a second doped layer, wherein the first doped layer is arranged on the surface of the first region or at least partially embedded in the surface of the first region, the second doped layer is arranged on the surface of the second region or at least partially embedded in the surface of the second region, and the second doped layer and the first doped layer have opposite polarities; and a dielectric layer and a conductive path layer, wherein in a direction moving away from the substrate, the dielectric layer and the conductive path layer are sequentially stacked in the third region, the dielectric layer isolates the first doped layer from the second doped layer, and the conductive path layer connects part of the first doped layer to part of the second doped layer.

Description

Solar cells, methods for manufacturing solar cells, and photovoltaic modules Technical Field

[0001] This application relates to the field of photovoltaic technology, specifically to a solar cell, a method for preparing a solar cell, and a photovoltaic module. Background Technology

[0002] Solar cells can convert solar energy into electrical energy. Back-contact solar cells, a type of solar cell, have their electrodes located on the back of the cell to prevent them from blocking the front, thus improving the photoelectric conversion efficiency.

[0003] Existing back-contact solar cells typically include a substrate with a front and a back side. The back side has a first region, a second region, and a third region disposed between the first and second regions. A first doped layer is stacked in the first region, a second doped layer is stacked in the second region, and a dielectric layer is stacked in the third region. The dielectric layer blocks the first and second doped layers, preventing leakage current and improving the photoelectric conversion efficiency of the solar cell.

[0004] However, existing back-contact solar cells are prone to hot spot problems. Summary of the Invention

[0005] This application discloses a solar cell, a method for preparing the solar cell, and a photovoltaic module, to solve or at least partially solve the problem of hot spots easily occurring in back-contact solar cells in the prior art.

[0006] To solve the above-mentioned technical problems, this application is implemented as follows:

[0007] In a first aspect, this application discloses a solar cell, the solar cell comprising: a substrate having a first surface and a second surface disposed opposite to each other, the first surface including a first region and a second region disposed at intervals and a third region located between the first region and the second region; a first doped layer and a second doped layer, the first doped layer being disposed on the surface of the first region or at least partially embedded in the surface of the first region, the second doped layer being disposed on the surface of the second region or at least partially embedded in the surface of the second region, the second doped layer having opposite polarity to the first doped layer; a dielectric layer and a conductive path layer, wherein the dielectric layer and the conductive path layer are sequentially stacked in the third region along a direction away from the substrate, the dielectric layer blocking the first doped layer and the second doped layer, and the conductive path layer connecting a portion of the first doped layer and a portion of the second doped layer.

[0008] Optionally, along the thickness direction of the battery cell, the thickness of the dielectric layer is greater than the thickness of the conductive path layer.

[0009] Optionally, along the thickness direction of the battery cell, the thickness of the conductive path layer is greater than the thickness of the dielectric layer.

[0010] Optionally, the base materials of the dielectric layer and the conductive path layer are the same; or, the base materials of the dielectric layer and the conductive path layer are different.

[0011] Optionally, the conductive path layer includes a layer doped with one element; and / or, the conductive path layer includes a layer doped with two elements of opposite polarity.

[0012] Optionally, the conductive path layer includes a single-doped path layer and a co-doped path layer, wherein the single-doped path layer is stacked on the side of the dielectric layer away from the substrate, and the co-doped path layer is stacked on the side of the single-doped path layer away from the dielectric layer; the single-doped path layer is doped with one element, and the co-doped path layer is doped with two elements of opposite polarity.

[0013] Optionally, the single-doped path layer and the co-doped path layer have the same conductivity type.

[0014] Optionally, the surface element doping concentration of the conductive path layer is greater than or equal to the surface element doping concentration of the first doped layer; and / or, the surface element doping concentration of the conductive path layer is greater than or equal to the surface element doping concentration of the second doped layer.

[0015] Optionally, along the thickness direction of the solar cell, the thickness of the conductive path layer is d1, satisfying 10nm ≤ d1 ≤ 120nm; and / or, the elemental doping concentration of the conductive path layer is greater than 1E18cm. -3 And less than 5E22cm -3 .

[0016] Optionally, the elemental doping concentration of the dielectric layer is less than 1E13cm. -3 ; and / or, along the thickness direction of the battery cell, the thickness of the dielectric layer is d2, satisfying 20nm≤d2≤490nm.

[0017] Optionally, the substrate corresponding to the third region has a third doped region, the elemental doping concentration of the third doped region being less than 1E13cm. -3 .

[0018] Optionally, the substrate corresponding to the first region has a first doped region, wherein the elemental doping concentration of the first doped region is greater than 1E13cm. -3; and / or, the substrate corresponding to the second region has a second doped region, the elemental doping concentration of the second doped region being greater than 1E13cm⁻¹. -3 .

[0019] Optionally, the first doped layer includes a first mono-doped layer and a first co-doped layer. The first mono-doped layer is doped with one element, and the first co-doped layer is doped with two elements of opposite polarity. The first mono-doped layer is stacked on the surface of the first region or at least partially embedded in the surface of the first region. The first co-doped layer is stacked on the side of the first mono-doped layer away from the substrate. The first co-doped layer has an opposite conductivity type to the first mono-doped layer. The solar cell further includes a first electrode coupled to a first region of the substrate. The first co-doped layer is provided with a through-groove. The first electrode is embedded in the through-groove and connected to the first mono-doped layer or the first region of the substrate. There is a gap between the first electrode and the inner wall of the through-groove.

[0020] Optionally, the uniformity of element doping concentration in the first single-doped layer is better than the uniformity of element doping concentration in the first co-doped layer.

[0021] Optionally, the second doped layer includes a second mono-doped layer and a second co-doped layer. The second mono-doped layer is doped with one element, and the second co-doped layer is doped with two elements of opposite polarity. The second mono-doped layer is stacked on the surface of the second region or at least partially embedded in the surface of the second region, and the second co-doped layer is stacked on the side of the second mono-doped layer away from the substrate. The second co-doped layer has the same conductivity type as the second mono-doped layer.

[0022] Optionally, along the thickness direction of the battery cell, the thickness of the second co-doped layer is greater than the thickness of the first co-doped layer of the first doped layer, and the thickness of the first co-doped layer is greater than or equal to the thickness of the co-doped path layer of the conductive path layer, wherein the first co-doped layer contains two elements with opposite polarities, and the co-doped path layer contains two elements with opposite polarities.

[0023] Optionally, the first doped layer has a first concentration gradient co-doped region on the side near the conductive path layer; and / or, the second doped layer has a second concentration gradient co-doped region on the side near the conductive path layer.

[0024] Optionally, when the first doped layer is a P-type doped layer and the second doped layer is an N-type doped layer, the width of the first concentration-gradient co-doped region is greater than the width of the second concentration-gradient co-doped region.

[0025] Optionally, the conductive path layer has a first depth-gradient co-doped region on the side near the first doped layer, and the conductive path layer has a second depth-gradient co-doped region on the side near the second doped layer.

[0026] Secondly, this application also discloses a method for fabricating a solar cell, the method comprising: providing a substrate having a first surface and a second surface disposed opposite to each other, the first surface including a first region and a second region disposed at intervals and a third region located between the first region and the second region; forming a first doped layer on the surface of the first region or within the surface of the first region, and forming a second doped layer on the surface of the second region or within the surface of the second region, the first doped layer and the second doped layer having opposite polarities; and sequentially stacking a dielectric layer and a conductive path layer in the third region along a direction away from the substrate, so as to block the first doped layer and the second doped layer through the dielectric layer, and to connect a portion of the first doped layer and a portion of the second doped layer through the conductive path layer.

[0027] Optionally, forming a first doped layer on or within the surface of the first region, and forming a second doped layer on or within the surface of the second region, includes: forming a semiconductor layer on the first surface of the substrate; forming a first doped source layer and a second doped source layer at positions on the semiconductor layer corresponding to the first region and the second region, respectively; heating and advancing the first doped source layer and the second doped source layer so that the portion of the semiconductor layer corresponding to the first region forms the first doped layer, and the portion of the semiconductor layer corresponding to the second region forms the second doped layer, wherein the polarities of the first doped layer and the second doped layer are opposite.

[0028] Optionally, the step of sequentially stacking the dielectric layer and the conductive path layer in the third region along a direction away from the substrate includes: forming a semiconductor layer on a first surface of the substrate, forming a third doped source layer at a position of the semiconductor layer corresponding to the third region; and heating and advancing the third doped source layer so that the portion of the semiconductor layer corresponding to the third region sequentially forms the stacked dielectric layer and the conductive path layer along a direction away from the substrate.

[0029] Optionally, forming a first doped layer on or within the surface of the first region includes: forming a semiconductor layer on a first surface of the substrate, forming a first doped source layer at a position of the semiconductor layer corresponding to the first region; heating and advancing the first doped source layer to form a first mono-doped layer at a portion of the semiconductor layer corresponding to the first region; forming a fourth doped source layer on the first mono-doped layer; heating and advancing the fourth doped source layer to form a first co-doped layer on a side of the first mono-doped layer away from the substrate, wherein the first mono-doped layer and the first co-doped layer constitute the first doped layer; the method further includes: forming a through-groove on the first co-doped layer, embedding a first electrode in the through-groove, and connecting it to the first mono-doped layer or a first region of the substrate, wherein there is a gap between the first electrode and the inner wall of the through-groove.

[0030] Thirdly, this application also discloses a photovoltaic module comprising the solar cells described in the first aspect.

[0031] This application discloses a solar cell, a method for fabricating a solar cell, and a photovoltaic module. The solar cell includes a substrate having a first surface and a second surface disposed opposite to each other. The first surface includes a first region and a second region spaced apart, and a third region located between the first region and the second region. It also includes a first doped layer and a second doped layer, wherein the first doped layer is disposed on the surface of the first region or at least partially embedded within the surface of the first region, and the second doped layer is disposed on the surface of the second region or at least partially embedded within the surface of the second region, with the second doped layer having the opposite polarity to the first doped layer. Furthermore, it includes a dielectric layer and a conductive path layer, which are sequentially stacked in the third region along a direction away from the substrate. The dielectric layer blocks the first doped layer and the second doped layer, and the conductive path layer connects a portion of the first doped layer and a portion of the second doped layer.

[0032] The solar cell disclosed in this application includes a substrate. The first surface of the substrate includes a first region and a second region spaced apart, and a third region located between the first region and the second region. A first doped layer is disposed on the surface of the first region or at least partially embedded in the surface of the first region, and a second doped layer is disposed on the surface of the second region or at least partially embedded in the surface of the second region. The first doped layer and the second doped layer have opposite polarities to collect the current generated on the substrate through the first doped layer and the second doped layer.

[0033] Furthermore, along the direction away from the substrate, the dielectric layer and the conductive path layer are sequentially stacked in the third region to block the first doped layer and the second doped layer through the dielectric layer. The dielectric layer can also block the substrate and the conductive path layer, preventing short circuits in the solar cell, ensuring the normal operation of the solar cell, and improving the photoelectric conversion efficiency of the solar cell.

[0034] Furthermore, the conductive path layer connects part of the first doped layer and part of the second doped layer. This conductive path layer enables soft breakdown between the first and second doped layers, preventing hot spot effects when the solar cell is shaded. Moreover, while preventing hot spot effects, it also ensures the photoelectric conversion efficiency of the solar cell under normal operating conditions. Attached Figure Description

[0035] Figure 1 shows a cross-sectional view of the solar cell described in an embodiment of this application;

[0036] Figure 2 shows a second cross-sectional view of the solar cell described in an embodiment of this application;

[0037] Figure 3 shows a cross-sectional view of the solar cell described in the embodiment of this application;

[0038] Figure 4 shows a cross-sectional view of the solar cell according to another embodiment of this application;

[0039] Figure 5 shows a second cross-sectional view of the solar cell described in another embodiment of this application;

[0040] Figure 6 shows a cross-sectional view three of the solar cell described in another embodiment of this application;

[0041] Figure 7 shows a cross-sectional view four of the solar cell described in another embodiment of this application;

[0042] Figure 8 shows a cross-sectional view of the solar cell described in yet another embodiment of this application;

[0043] Figure 9 shows a second cross-sectional view of the solar cell described in yet another embodiment of this application;

[0044] Figure 10 shows a third cross-sectional view of the solar cell described in yet another embodiment of this application;

[0045] Figure 11 shows a cross-sectional view four of the solar cell described in yet another embodiment of this application;

[0046] Figure 12 shows a flowchart of the solar cell fabrication method described in the embodiments of this application.

[0047] Reference numerals: 100: Substrate; 101: First doped layer; 1011: First mono-doped layer; 1012: First co-doped layer; 1012a: Through-hole; 102: Second doped layer; 1021: Second mono-doped layer; 1022: Second co-doped layer; 1031: Dielectric layer; 1032: Conductive path layer; 1032a: Single doped path layer; 1032b: Co-doped path layer; 1032c: First depth-gradient co-doped region; 104: Interface passivation layer; 105: Surface passivation layer or anti-reflection layer; 106: First electrode; 107: Second electrode; 108: Second concentration-gradient co-doped region. Detailed Implementation

[0048] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of this application.

[0049] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0050] Referring to Figure 1, a cross-sectional view of the solar cell in an embodiment of this application is shown; referring to Figure 2, a cross-sectional view of the solar cell in an embodiment of this application is shown; referring to Figure 3, a cross-sectional view of the solar cell in an embodiment of this application is shown; referring to Figure 4, a cross-sectional view of the solar cell in another embodiment of this application is shown; referring to Figure 5, a cross-sectional view of the solar cell in another embodiment of this application is shown; referring to Figure 6, a cross-sectional view of the solar cell in another embodiment of this application is shown; referring to Figure 7, a cross-sectional view of the solar cell in another embodiment of this application is shown; referring to Figure 8, a cross-sectional view of the solar cell in yet another embodiment of this application is shown; referring to Figure 9, a cross-sectional view of the solar cell in yet another embodiment of this application is shown; referring to Figure 10, a cross-sectional view of the solar cell in yet another embodiment of this application is shown; referring to Figure 11, a cross-sectional view of the solar cell in yet another embodiment of this application is shown.

[0051] As shown in Figures 1 to 11, this application discloses a solar cell, which includes a substrate 100. The substrate 100 has a first surface and a second surface disposed opposite to each other. The first surface includes a first region and a second region disposed at intervals, and a third region located between the first region and the second region. A first doped layer 101 and a second doped layer 102 are also included. The first doped layer 101 is disposed on the surface of the first region or at least partially embedded in the surface of the first region, and the second doped layer 102 is disposed on the surface of the second region or at least partially embedded in the surface of the second region. The polarity of the second doped layer 102 is opposite to that of the first doped layer 101. A dielectric layer 1031 and a conductive path layer 1032 are also included. Along a direction away from the substrate 100, the dielectric layer 1031 and the conductive path layer 1032 are sequentially stacked in the third region. The dielectric layer 1031 blocks the first doped layer 101 and the second doped layer 102, and the conductive path layer 1032 connects a portion of the first doped layer 101 and a portion of the second doped layer 102.

[0052] Solar cells are the core component of photovoltaic modules, converting solar energy into electrical energy. As shown in Figures 1 to 11, embodiments of this application disclose a solar cell that can be used in photovoltaic modules to prevent hot spot effects from occurring on the solar cells when the photovoltaic module is shaded, thus affecting the photoelectric conversion efficiency of the photovoltaic module.

[0053] As shown in Figures 1 to 11, the solar cell disclosed in this application includes a substrate 100. The substrate 100 is the core component of the solar cell, which converts solar energy into electrical energy. Exemplarily, the substrate 100 can be a P-type substrate, an N-type substrate, or an intrinsically conductive silicon wafer. The crystal type can be monocrystalline or polycrystalline, etc. Of course, the substrate 100 can also be other types of substrates. Here, no specific restrictions are placed on the specific type of substrate 100. In practical applications, those skilled in the art can select appropriate materials as the substrate 100 as needed.

[0054] The substrate 100 in this embodiment has a first surface and a second surface disposed opposite to each other, wherein the first surface is the back side of the solar cell and the second surface is the front side of the solar cell. In other words, the solar cell disclosed in this embodiment is a back-contact solar cell.

[0055] As shown in Figures 1 to 11, the first surface of the substrate 100 includes a first region and a second region spaced apart, and a third region located between the first region and the second region. A first doped layer 101 is disposed on the surface of the first region or at least partially embedded in the surface of the first region, and a second doped layer 102 is disposed on the surface of the second region or at least partially embedded in the surface of the second region. The polarity of the second doped layer 102 is opposite to that of the first doped layer 101, so as to collect the current generated by the substrate 100 through the first doped layer 101 and the second doped layer 102.

[0056] It should be noted that the first doped layer 101 and the second doped layer 102 can be one or more of polycrystalline silicon, amorphous silicon, microcrystalline silicon, and monocrystalline silicon. When the first doped layer 101 is a P-type doped layer, the second doped layer 102 is an N-type doped layer. When the first doped layer 101 is an N-type doped layer, the second doped layer 102 is a P-type doped layer. P-type layers are generally doped with Group IIIA elements, and N-type layers are generally doped with Group VA elements.

[0057] As shown in Figures 1 to 11, along the direction away from the substrate 100, the dielectric layer 1031 and the conductive path layer 1032 are sequentially stacked in the third region. The dielectric layer 1031 blocks the first doped layer 101 and the second doped layer 102, and also blocks the substrate 100 and the conductive path layer 1032, thus preventing short circuits in the solar cell, ensuring normal operation of the solar cell, and improving the photoelectric conversion efficiency of the solar cell.

[0058] It should be noted that the dielectric layer 1031 in this embodiment includes a semiconductor layer and / or an insulating layer. When the dielectric layer 1031 includes a semiconductor layer and an insulating layer, the insulating layer and the semiconductor layer are sequentially stacked on the surface of the third region along the direction away from the substrate 100. The conductive path layer 1032 is stacked on the side of the semiconductor layer away from the insulating layer. The semiconductor layer includes an intrinsic semiconductor layer and an electrically neutral co-doped semiconductor layer, wherein the intrinsic semiconductor layer includes at least one of intrinsic amorphous silicon, intrinsic polycrystalline silicon, and intrinsic monocrystalline silicon. The electrically neutral co-doped semiconductor layer refers to a layer with an elemental doping concentration not exceeding 1E18cm⁻¹. -3 Co-doped semiconductor layers exhibiting absolute electrical neutrality, weak positive charge, or weak negative charge, exemplarily, a polycrystalline silicon layer simultaneously doped with phosphorus and boron.

[0059] As shown in Figures 1 to 11, in this embodiment of the application, a conductive path layer 1032 is stacked on the side of the dielectric layer 1031 away from the substrate 100. The conductive path layer 1032 connects a portion of the first doped layer 101 and a portion of the second doped layer 102, thus conducting the first doped layer 101 and the second doped layer 102. The conductive path layer 1032 enables soft breakdown of the first doped layer 101 and the second doped layer 102, preventing hot spot effects when the solar cell is shaded. Furthermore, this arrangement, while addressing the hot spot effect, also ensures the photoelectric conversion efficiency of the solar cell under normal operating conditions.

[0060] Optionally, along the thickness direction of the solar cell, the thickness of the dielectric layer 1031 is greater than the thickness of the conductive path layer 1032.

[0061] In this embodiment, the thickness of the dielectric layer 1031 is set to be greater than the thickness of the conductive path layer 1032 along the thickness direction of the solar cell. This setting results in a thicker dielectric layer 1031, which ensures electrical isolation between the first doped layer 101 and the second doped layer 102, as well as electrical isolation between the substrate 100 and the conductive path layer 1032. This leads to higher photoelectric conversion efficiency of the solar cell under normal operating conditions.

[0062] In this embodiment, the conductive path layer 1032 is thinner than the dielectric layer 1031, and soft breakdown between the first doped layer 101 and the second doped layer 102 is achieved through the conductive path layer 1032. When the solar cell is shaded, the conductive path layer 1032 can prevent hot spots, thus avoiding the hot spot effect on the solar cell.

[0063] Furthermore, the above configuration allows for the placement of a dielectric layer 1031 between the first doped layer 101 and the second doped layer 102 across the entire area of ​​the solar cell, achieving heat spot prevention across the entire area. This eliminates the need for other spatial spacing grooves, simplifying the fabrication process of the solar cell and reducing its production cost.

[0064] Optionally, along the thickness direction of the solar cell, the thickness of the conductive path layer 1032 is greater than the thickness of the dielectric layer 1031.

[0065] In this embodiment, the thickness of the conductive path layer 1032 is set to be greater than the thickness of the dielectric layer 1031 along the thickness direction of the battery cell to increase the conductive path. Only a small number of anti-hot spot structures are needed across the entire battery cell area to achieve the anti-hot spot effect of the entire battery cell.

[0066] Specifically, the dielectric layer 1031 and the conductive path layer 1032 can be sequentially stacked over the entire area of ​​at least one third region on the first surface of the substrate 100, or the dielectric layer 1031 and the conductive path layer 1032 can be sequentially stacked over at least a portion of the area of ​​at least one third region on the first surface of the substrate 100.

[0067] It should be noted that the positions of the different conductive path layers 1032 located on the multiple third regions of the first surface of the substrate 100 can correspond to each other or be staggered. This application does not impose specific limitations on this. In practical applications, those skilled in the art can configure them as needed.

[0068] Optionally, the base material of the dielectric layer 1031 and the conductive path layer 1032 is the same.

[0069] In this embodiment, the dielectric layer 1031 and the conductive path layer 1032 are made of the same base material. Exemplarily, both the dielectric layer 1031 and the conductive path layer 1032 comprise polysilicon; the conductive path layer 1032 is formed by doped polysilicon, and the dielectric layer 1031 is formed by undoped polysilicon. The undoped polysilicon can also be referred to as intrinsic polysilicon. Of course, the above specific embodiments are merely individual examples of this application and are not intended to limit the application. In practical applications, those skilled in the art can set the base materials of the dielectric layer 1031 and the conductive path layer 1032 as needed.

[0070] It should be noted that the base materials of the dielectric layer 1031 and the conductive path layer 1032 in this embodiment are the same as the base materials of the first doped layer 101 and the second doped layer 102. This configuration simplifies the cell fabrication process, enabling the patterning of the cell. By depositing semiconductor films in a single step and performing different degrees of doping, the aforementioned structure can be formed.

[0071] Optionally, the base materials of the dielectric layer 1031 and the conductive path layer 1032 are different.

[0072] The base materials of the dielectric layer 1031 and the conductive path layer 1032 in this embodiment can also be different. The dielectric layer 1031 can also be an insulating layer. Exemplarily, the dielectric layer 1031 can be at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, silicon carbide, intrinsic amorphous silicon, intrinsic polycrystalline silicon, and intrinsic monocrystalline silicon. The conductive path layer 1032 can be at least one of doped amorphous silicon, doped polycrystalline silicon, and doped monocrystalline silicon.

[0073] Optionally, the conductive path layer 1032 includes a layer doped with one element; and / or, the conductive path layer 1032 includes a layer doped with two elements of opposite polarity.

[0074] In this embodiment, the conductive path layer 1032 may be doped with an element to improve its conductivity, achieving soft breakdown of the first doped layer 101 and the second doped layer 102, and preventing hot spot effects when the solar cell is shaded. For example, the conductive path layer 1032 may be doped with only boron, or only phosphorus.

[0075] Of course, the conductive path layer 1032 can also be doped with two elements of opposite polarity to simplify the cell fabrication process, facilitate cell fabrication, and reduce cell fabrication costs. For example, the conductive path layer 1032 is doped with both boron and phosphorus.

[0076] It should be noted that when one element is doped in the conductive path layer 1032, the concentration of the doped element decreases along the direction from the conductive path layer 1032 to the substrate 100.

[0077] Optionally, as shown in FIG2, the conductive path layer 1032 in this embodiment includes a single-doped path layer 1032a and a co-doped path layer 1032b, wherein the single-doped path layer 1032a is stacked on the side of the dielectric layer 1031 away from the substrate 100, and the co-doped path layer 1032b is stacked on the side of the single-doped path layer 1032a away from the dielectric layer 1031; the single-doped path layer 1032a is doped with one element, and the co-doped path layer 1032b is doped with two elements of opposite polarity.

[0078] As shown in Figure 2, in this embodiment, the conductive path layer 1032 is configured as two layers. One layer is a single-doped path layer 1032a, which is stacked on the side of the dielectric layer 1031 away from the substrate 100. The single-doped path layer 1032a is doped with one element. The other layer is a co-doped path layer 1032b, which is stacked on the side of the single-doped path layer 1032a away from the dielectric layer 1031. The co-doped path layer 1032b is doped with two elements of opposite polarity. One of these two elements is the same as the doping element in the single-doped path layer 1032a.

[0079] The above-described design reduces the manufacturing complexity of solar cells, simplifies the cell fabrication process, and lowers production costs. Furthermore, this design also prevents hot spot effects when the cells are shaded. Moreover, while preventing hot spot effects, it also ensures the photoelectric conversion efficiency of the cells under normal operating conditions.

[0080] Optionally, the single-doped path layer 1032a and the co-doped path layer 1032b have the same conductivity type.

[0081] In this embodiment, the conductivity type of the single-doped path layer 1032a is set to be the same as that of the co-doped path layer 1032b, so that the soft breakdown interface between the first doped layer 101 and the second doped layer 102 is more uniform and the hot spot prevention effect is better.

[0082] Furthermore, setting the conductivity type of the single-doped path layer 1032a to be the same as that of the co-doped path layer 1032b can also prevent the soft breakdown layer from being too thick, which would lead to a loss of cell efficiency.

[0083] Optionally, the surface element doping concentration of the conductive path layer 1032 is greater than or equal to the surface element doping concentration of the first doped layer 101; and / or, the surface element doping concentration of the conductive path layer 1032 is greater than or equal to the surface element doping concentration of the second doped layer 102.

[0084] In this embodiment, the surface element doping concentration of the conductive path layer 1032 is set to be greater than or equal to the surface element doping concentration of the first doped layer 101; and / or, the surface element doping concentration of the conductive path layer 1032 is set to be greater than or equal to the surface element doping concentration of the second doped layer 102.

[0085] By setting the above, the surface element doping concentration of the conductive path layer 1032 can be controlled, making the conductive path layer 1032 thinner, thereby improving the heat spot prevention effect of the solar cell and ensuring the photoelectric conversion efficiency of the solar cell.

[0086] Optionally, along the thickness direction of the solar cell, the thickness of the conductive path layer 1032 is d1, satisfying 10nm ≤ d1 ≤ 120nm; and / or, the elemental doping concentration of the conductive path layer 1032 is greater than 1E18cm. -3 And less than 5E22cm -3 .

[0087] In this embodiment, the thickness of the conductive path layer 1032 is set to d1 along the thickness direction of the battery cell. Here, d1 is greater than or equal to 10 nm and less than or equal to 120 nm. By setting the thickness of the conductive path layer 1032, its thickness is made relatively thin, thereby ensuring the soft breakdown effect of the battery cell.

[0088] For example, the thickness of the conductive path layer 1032 along the thickness direction of the battery cell can be 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, etc.

[0089] In this embodiment, the doping concentration of the elements within the conductive path layer 1032 is greater than or equal to 1E18cm⁻¹. -3 And less than 5E22cm -3 By setting the doping concentration of elements within the conductive path layer 1032 to be greater than or equal to 1E18cm⁻¹ -3 And less than 5E22cm -3 This allows the conductive path layer 1032 to conduct electricity, achieving a soft breakdown effect in the solar cell.

[0090] For example, the elemental doping concentration within the conductive path layer 1032 can be 1E18cm⁻¹. -3 1E20cm -3 2E18cm -3 3E18cm -3 4E18cm -3 5E18cm -3 5E22cm -3 wait.

[0091] Optionally, the elemental doping concentration of the dielectric layer 1031 is less than 1E13cm. -3 ; and / or, along the thickness direction of the cell, the thickness of the dielectric layer 1031 is d2, satisfying 20nm≤d2≤490nm.

[0092] In this embodiment, the doping concentration of the elements in the dielectric layer 1031 is set to be less than 1E13cm. -3 This makes the dielectric layer 1031 insulating. The dielectric layer 1031 can block the first doped layer 101 and the second doped layer 102, as well as the substrate 100 and the conductive path layer 1032, thereby achieving electrical isolation between the first doped layer 101 and the second doped layer 102, and between the substrate 100 and the conductive path layer 1032.

[0093] For example, the doping concentration of elements within the dielectric layer 1031 can be 1E12cm. -3 1E11cm -3 1E10cm -3 1E9cm -3 wait.

[0094] In this embodiment of the application, the thickness of the dielectric layer 1031 is set to d2 along the thickness direction of the battery cell, wherein d2 is greater than or equal to 20nm and less than or equal to 490nm, so as to block the first doped layer 101 and the second doped layer 102, as well as the substrate 100 and the conductive path layer 1032 through the dielectric layer 1031, thereby achieving electrical isolation between the first doped layer 101 and the second doped layer 102, and electrical isolation between the substrate 100 and the conductive path layer 1032.

[0095] For example, along the thickness direction of the battery cell, the thickness of the dielectric layer 1031 can be 20nm, 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 490nm, etc.

[0096] Optionally, the substrate 100 corresponding to the third region has a third doped region, the elemental doping concentration of the third doped region being less than 1E13cm. -3 .

[0097] In this embodiment, the substrate 100 has a third doped region at the position corresponding to the third region, and the doping concentration of the elements in the third doped region is set to be less than 1E13cm. -3 A dielectric layer 1031 is disposed between the conductive path layer 1032 and the third doped region of the substrate 100. The dielectric layer 1031 can block the conductive path layer 1032 and the third doped region of the substrate 100, preventing the doped elements in the conductive path layer 1032 from diffusing into the third doped region of the substrate 100, so as to ensure that the solar cell has a higher photoelectric conversion efficiency under normal working conditions.

[0098] For example, the doping concentration of the elements in the third doped region of the substrate 100 can be 1E12cm. -3 1E11cm -3 1E10cm -3 1E9cm -3 1E8cm -3 wait.

[0099] Optionally, the substrate 100 corresponding to the first region has a first doped region, and the elemental doping concentration of the first doped region is greater than 1E13cm. -3 ; and / or, a second doped region is present within the substrate 100 corresponding to the second region, wherein the elemental doping concentration of the second doped region is greater than 1E13cm. -3 .

[0100] In this embodiment, the substrate 100 has a first doped region at the position corresponding to the first region, a second doped region at the position corresponding to the second region, and a third doped region located between the first doped region and the second doped region.

[0101] In this embodiment, the doping concentration of the element in the first doping region is set to be greater than 1E13cm. -3 And / or, the doping concentration of the elements in the second doped region is also set to be greater than 1E13cm. -3Furthermore, the first doped region and the second doped region have different depths within the substrate 100. This arrangement matches the solid solubility of different doping elements, enabling effective doping of the first doped layer 101 and the second doped layer 102, and achieving sufficient separation of charge carriers.

[0102] For example, taking boron and phosphorus as dopants, the boron dopant has a deeper diffusion depth in the substrate 100, while the phosphorus dopant has a relatively shallower diffusion depth. In this application, the boron diffusion depth is defined as E17cm. -3 The cutoff value for phosphorus diffusion depth is E18cm. -3 Deadline.

[0103] Optionally, as shown in Figures 6, 7, and 9 to 11, the first doped layer 101 in this embodiment includes a first mono-doped layer 1011 and a first co-doped layer 1012. The first co-doped layer 1012 is doped with two elements of opposite polarity. The first mono-doped layer 1011 is stacked on the surface of the first region or at least partially embedded in the surface of the first region. The first co-doped layer 1012 is stacked on the side of the first mono-doped layer 1011 away from the substrate 100. The first co-doped layer 1012 has an opposite conductivity type to the first mono-doped layer 1011. The solar cell also includes a first electrode 106, which is coupled to the first region of the substrate 100. The first co-doped layer 1012 is provided with a through groove 1012a. The first electrode 106 is embedded in the through groove 1012a and connected to the first mono-doped layer 1011 or the first region of the substrate 100. There is a gap between the first electrode 106 and the inner wall of the through groove 1012a.

[0104] As shown in Figures 6, 7, and 9 to 11, in this embodiment of the application, the first doped layer 101 is configured as two layers: a first mono-doped layer 1011 and a first co-doped layer 1012. The first mono-doped layer 1011 and the first co-doped layer 1012 have opposite conductivity types. The first mono-doped layer 1011 is doped with one element and is stacked on the surface of the first region or at least partially embedded in the surface of the first region. The first co-doped layer 1012 is doped with two elements of opposite polarity and is stacked on the side of the first mono-doped layer 1011 away from the substrate 100. This configuration reduces the manufacturing difficulty of the solar cell, simplifies the process flow, and lowers the manufacturing cost.

[0105] The battery cell disclosed in this embodiment further includes a first electrode 106, which is coupled to a first region of the substrate 100 to collect charge carriers generated in the first region of the substrate 100. Specifically, as shown in FIG4, the first electrode 106 can be embedded in a surface passivation layer or antireflection layer 105 and connected to a first co-doped layer 1012. As shown in FIG5, the first electrode 106 can also be embedded in the surface passivation layer or antireflection layer 105 and the first co-doped layer 1012, with one end of the first electrode 106 connected to the position of the first mono-doped layer 1011 corresponding to the first region. As shown in FIG6, the first electrode 106 can also be embedded in the surface passivation layer or antireflection layer 105, the first co-doped layer 1012, and the first mono-doped layer 1011, with one end of the first electrode 106 connected to the surface of the tunneling passivation layer or the first region of the substrate 100. Through the above configuration, the first electrode 106 can collect charge carriers generated in the first region of the substrate 100.

[0106] As shown in Figures 9 to 11, in this embodiment of the application, a through-groove 1012a can also be provided on the first co-doped layer 1012, and one end of the first electrode 106 can be connected to the position corresponding to the first mono-doped layer 1011 and the first region through the through-groove 1012a, or one end of the first electrode 106 can be directly connected to the surface of the first region of the tunneling passivation layer or the substrate 100. There is a gap between the sidewall of the first electrode 106 and the inner wall of the through-groove 1012a, so as to reduce the risk of leakage of the cell and improve the photoelectric conversion efficiency of the cell.

[0107] It should be noted that the configuration of the second electrode 107 in this embodiment is similar to that of the first electrode 106, and will not be described again here.

[0108] Optionally, the uniformity of element doping concentration in the first single-doped layer 1011 is better than the uniformity of element doping concentration in the first co-doped layer 1012.

[0109] In this embodiment, the first single-doped layer 1011 is used as the first conductivity type, and the first co-doped layer 1012 is used as the second conductivity type for explanation. It can be understood that the first single-doped layer 1011 is doped with only one type of element, while the first co-doped layer 1012 is doped with both one type of element and two types of elements. The type of element can be a group IIIA element, such as boron, aluminum, gallium, etc. The type of element can be a group VA element, such as phosphorus, antimony, arsenic, etc. The thickness of the first single-doped layer 1011 is greater than or equal to 20 nm and less than or equal to 490 nm, and the thickness of the first co-doped layer 1012 is greater than or equal to 10 nm and less than or equal to 480 nm.

[0110] In the first co-doped layer 1012, along the direction away from the substrate 100, the doping concentration distribution of one type of element is basically on the same order of magnitude, and the concentration uniformity is less than 50%. In the first mono-doped layer 1011, along the direction away from the substrate 100, the doping concentration of one type of element is almost uniformly distributed, and the concentration uniformity is less than 20%. The doping concentrations of one type of element in the first co-doped layer 1012 and the first mono-doped layer 1011 are basically on the same order of magnitude.

[0111] It should be noted that the uniformity of concentration in the embodiments of this application is equal to (maximum concentration - minimum concentration) / (maximum concentration + minimum concentration).

[0112] For example, in the embodiments of this application, the doping concentration of one type of element in the first single-doped layer 1011 ranges from 1E16cm. -3 Up to 1E21cm -3 In the first co-doped layer 10¹², the doping concentration of one type of element ranges from 1E¹⁶ cm⁻¹. -3 Up to 1E21cm -3 The doping concentration range for the second type of element is 1E17cm. -3 Up to 1E22cm -3 .

[0113] In the same region, the boron doping concentration at different depths in the first monodoped layer 1011 was tested. In the first monodoped layer 1011, near the substrate 100, the boron doping concentration was 6E19cm. -3 At a location 100 units away from the substrate, the boron doping concentration is 7E19cm⁻¹. -3 The concentrations were all 7.7% (7-6) / (7+6) = 7.7%, which is less than 20%.

[0114] In the same region, the boron doping concentration at different depths in the first co-doped layer 1012 was tested. In the first co-doped layer 1012, near the substrate 100, the boron doping concentration was 7E19cm. -3 At a location 100 units away from the substrate, the boron doping concentration is 3E19cm⁻¹. -3 The concentrations are all 40% (7-3) / (7+3), which is less than 50%.

[0115] In this embodiment, the uniformity of elemental doping concentration within the first mono-doped layer 1011 is set to be better than the uniformity of elemental doping concentration within the first co-doped layer 1012. This setting ensures the carrier separation efficiency within the first mono-doped layer 1011. Furthermore, this setting also ensures that the first mono-doped layer 1011 does not affect the passivation effect of the substrate 100.

[0116] Optionally, as shown in Figures 8 to 11, the second doped layer 102 in this embodiment includes a second mono-doped layer 1021 and a second co-doped layer 1022. The second co-doped layer 1022 is doped with two elements of opposite polarity. The second mono-doped layer 1021 is stacked on the surface of the second region or at least partially embedded in the surface of the second region. The second co-doped layer 1022 is stacked on the side of the second mono-doped layer 1021 away from the substrate 100. The second co-doped layer 1022 and the second mono-doped layer 1021 have the same conductivity type.

[0117] As shown in Figures 8 to 11, the second doped layer 102 in this embodiment includes two layers: a second mono-doped layer 1021, in which one element is doped; and a second co-doped layer 1022, in which two elements with opposite polarities are doped. The second mono-doped layer 1021 and the second co-doped layer 1022 have the same conductivity type.

[0118] As shown in Figures 8 to 11, the second mono-doped layer 1021 is stacked on the surface of the second region or at least partially embedded in the surface of the second region, and the second co-doped layer 1022 is stacked on the side of the second mono-doped layer 1021 away from the substrate 100. This configuration reduces the manufacturing difficulty of the solar cell, simplifies the process flow, and lowers the manufacturing cost.

[0119] It should be noted that, in this embodiment, regardless of whether the second mono-doped layer 1021 and the second co-doped layer 1022 have the same or different conductivity types, the second electrode 107 can contact the second mono-doped layer 1021 alone or the second co-doped layer 1022 alone. Of course, the second electrode 107 can also contact the second mono-doped layer 1021 and the second co-doped layer 1022 simultaneously. When the second electrode 107 contacts the second mono-doped layer 1021 and the second co-doped layer 1022 simultaneously, the contact formed is better, and the reliability of the solar cell is higher.

[0120] Optionally, along the thickness direction of the solar cell, the thickness of the second co-doped layer 1022 is greater than the thickness of the first co-doped layer 1012, and the thickness of the first co-doped layer 1012 is greater than or equal to the thickness of the co-doped path layer 1032b.

[0121] Along the thickness direction of the solar cell, the thickness of the co-doped path layer 1032b cannot be too thick to ensure the effectiveness of the solar cell in preventing hot spots and maintaining its photoelectric conversion efficiency. The second co-doped layer 1022 does not affect the conductivity type of the second doped layer 102; therefore, the thickness of the second co-doped layer 1022 can be relatively thick. However, the thickness of the first co-doped layer 1012 cannot be too thick, as an excessively thick first co-doped layer 1012 will affect the carrier collection efficiency in the first region. Of course, the thickness of the first co-doped layer 1012 also cannot be too thin. An excessively thin first co-doped layer 1012 will increase the number of processing steps required for the solar cell, necessitating separate processing to form the co-doped path layer 1032b, thus increasing the manufacturing cost of the solar cell.

[0122] Based on the above, in this embodiment of the application, along the thickness direction of the battery cell, the thickness of the second co-doped layer 1022 is set to be greater than the thickness of the first co-doped layer 1012, and the thickness of the first co-doped layer 1012 is set to be greater than or equal to the thickness of the co-doped path layer 1032b.

[0123] Optionally, as shown in FIG3, in this embodiment of the application, the first doped layer 101 has a first concentration gradient co-doped region (not shown in the figure) on the side near the conductive path layer 1032; and / or, the second doped layer 102 has a second concentration gradient co-doped region 108 on the side near the conductive path layer 1032.

[0124] As shown in Figure 3, the region of the first doped layer 101 near the first electrode 106 has a higher element doping concentration to facilitate carrier collection, as well as current transmission and collection. In particular, the element doping concentration is even higher in the first doped layer 101 below the first electrode 106 to effectively reduce the metal-semiconductor contact resistance. On the side of the first doped layer 101 near the conductive path layer 1032, the element doping concentration is lower, which is conducive to Auger recombination, thereby improving the photoelectric conversion efficiency of the solar cell.

[0125] Based on the above, in this embodiment of the application, a first concentration gradient co-doped region is provided on the side of the first doped layer 101 near the conductive path layer 1032, and / or a second concentration gradient co-doped region 108 is provided on the side of the second doped layer 102 near the conductive path layer 1032, so as to improve the current collection efficiency of the solar cell and improve the photoelectric conversion efficiency of the solar cell.

[0126] Optionally, when the first doped layer 101 is a P-type doped layer and the second doped layer 102 is an N-type doped layer, the width of the first concentration-gradient co-doped region is greater than the width of the second concentration-gradient co-doped region 108.

[0127] When the first doped layer 101 is a P-type doped layer, that is, boron is doped in the first doped layer 101, and the second doped layer 102 is an N-type doped layer, that is, phosphorus is doped in the second doped layer 102, the width of the first concentration gradient co-doped region is greater than the width of the second concentration gradient co-doped region 108.

[0128] The above settings can improve carrier transport efficiency, current transport and collection efficiency, and reduce metal-semiconductor contact without increasing process complexity.

[0129] Of course, the above-described method of setting the first doped layer 101 as a P-type doped layer and the second doped layer 102 as an N-type doped layer is merely a specific example of this application and is not intended to limit the scope of this application. In practical applications, those skilled in the art can set the specific doping types of the first doped layer 101 and the second doped layer 102 as needed.

[0130] Optionally, the conductive path layer 1032 has a first depth-gradient co-doped region 1032c on the side near the first doped layer 101, and a second depth-gradient co-doped region (not shown in the figure) on the side near the second doped layer 102.

[0131] In this embodiment, a first depth-gradient co-doped region 1032c is formed on the side of the conductive path layer 1032 near the first doped layer 101, and a second depth-gradient co-doped region is formed on the side of the conductive path layer 1032 near the second doped layer 102. This increases the effective depth of the soft breakdown path and reduces the excessive concentration of heating current regions in the first doped layer 101 and the second doped layer 102. Furthermore, it can also reduce the heating temperature of a single or single-point soft breakdown, thereby reducing safety risks.

[0132] A heat dissipation test was conducted on the solar cell disclosed in the embodiments of this application. The heat dissipation test standard was as follows: a reverse bias voltage of 15V was applied for 100ms, and the temperature difference of the cell before and after the application was measured. The temperature at the point of highest temperature change after applying current was used as the standard ΔT / ℃. The heat dissipation test results are shown in Table 1 below.

[0133] It should be noted that in the comparative examples, the solar cell only separates the first doped layer 101 and the second doped layer 102 by spatial spacing, without providing a conductive path layer 1032 and a dielectric layer 1031. In Embodiment 1, as shown in Figures 1 to 3, the first doped layer 101 and the second doped layer 102 of the solar cell are connected by the dielectric layer 1031 and the conductive path layer 1032. In Embodiment 2, as shown in Figures 4 to 7, the first doped layer 101 and the second doped layer 102 of the solar cell are connected by the dielectric layer 1031 and the conductive path layer 1032. The first doped layer 101 includes a first single-doped layer 1011 and a first co-doped layer 1012. In Embodiment 3, as shown in Figures 8 to 11, the first doped layer 101 and the second doped layer 102 of the solar cell are connected by the dielectric layer 1031 and the conductive path layer 1032. The first doped layer 101 includes a first mono-doped layer 1011 and a first co-doped layer 1012, and the second doped layer 102 includes a second mono-doped layer 1021 and a second co-doped layer 1022.

[0134] Table 1. Results of solar cell heating test

[0135] As shown in Table 1, compared with the solar cells disclosed in the comparative examples, the solar cells disclosed in Examples 1, 2, and 3 of this application have lower hot spot test temperatures, a lower proportion of cells exceeding 3°C, and better protection against hot spot effects. The photoelectric conversion efficiency of the solar cells with co-doped layers disclosed in Examples 2 and 3 is slightly improved.

[0136] Referring to Figure 12, a flowchart of the battery cell preparation method described in the embodiments of this application is shown.

[0137] As shown in Figure 12, an embodiment of this application discloses a method for preparing a battery cell, the method comprising:

[0138] 201, providing a substrate having a first surface and a second surface disposed opposite to each other, the first surface including a first region and a second region disposed at intervals and a third region located between the first region and the second region.

[0139] In this embodiment, the substrate serves as the core component of the solar cell, converting solar energy into electrical energy. Exemplarily, the substrate can be a P-type substrate, an N-type substrate, or an intrinsically conductive silicon wafer. The crystal type can be monocrystalline or polycrystalline, etc. Of course, the substrate can also be other types. Here, no specific restrictions are placed on the type of substrate; in practical applications, those skilled in the art can select appropriate materials as the substrate according to their needs.

[0140] It should be noted that, in this embodiment of the application, the substrate needs to undergo surface treatment before being provided. Surface treatment includes steps such as removing damage, removing stains, polishing, and texturing. The substrate in this embodiment of the application has a first surface and a second surface disposed opposite to each other, wherein the first surface is the back side of the battery cell, and the second surface is the front side of the battery cell.

[0141] In other words, the solar cell disclosed in this application is a back-contact solar cell. The first surface of the substrate has a first region and a second region spaced apart, and a third region located between the first region and the second region.

[0142] 202, a first doped layer is formed on or within the surface of the first region, and a second doped layer is formed on or within the surface of the second region, wherein the polarities of the first doped layer and the second doped layer are opposite.

[0143] It should be noted that the first doped layer 101 and the second doped layer 102 can both be one or more of polycrystalline silicon, amorphous silicon, and microcrystalline silicon. When the first doped layer 101 is a P-type doped layer, the second doped layer 102 is an N-type doped layer. When the first doped layer 101 is an N-type doped layer, the second doped layer 102 is a P-type doped layer. P-type layers are generally doped with Group IIIA elements, and N-type layers are generally doped with Group VA elements.

[0144] In this embodiment, there is no specific restriction on the formation order of the first doped layer 101 and the second doped layer 102. The first doped layer 101 can be formed first, followed by the second doped layer 102. Alternatively, the second doped layer 102 can be formed first, followed by the first doped layer 101. In practical applications, those skilled in the art can choose according to their needs.

[0145] Specifically, forming a first doped layer on or within the surface of the first region, and forming a second doped layer on or within the surface of the second region, includes: forming a semiconductor layer on a first surface of the substrate, and forming a first doped source layer and a second doped source layer at positions of the semiconductor layer corresponding to the first and second regions, respectively. Heating is used to advance the first and second doped source layers, such that the portion of the semiconductor layer corresponding to the first region forms the first doped layer, and the portion of the semiconductor layer corresponding to the second region forms the second doped layer, with the first and second doped layers having opposite polarities.

[0146] It should be noted that, in the embodiments of this application, laser heating can be used to propel elements within the first and second doped source layers to form the first and second doped layers. Of course, the above-described laser heating propulsion method is merely a specific example of the embodiments of this application and is not intended to limit the scope of this application. In practical applications, those skilled in the art can select appropriate doping methods as needed.

[0147] In this embodiment, there are no specific restrictions on the formation order of the first doped source layer and the second doped source layer, nor on the heating and advancing order of the first and second doped source layers. For example, in this embodiment, the first doped source layer can be formed first, then heated and advanced, followed by the formation of the second doped source layer, and then heated and advanced again. Alternatively, the second doped source layer can be formed first, followed by the formation of the first doped source layer, and then the heating and advancing of the first and second doped source layers sequentially.

[0148] It should be noted that, in this embodiment, before forming a semiconductor layer on the first surface of the substrate, an interface passivation layer 104 can be formed on the first surface of the substrate to protect the substrate. The interface passivation layer 104 in this embodiment can be a single-layer structure or a multi-layer structure. The interface passivation layer 104 includes one or more of the following: silicon nitride layer, silicon oxide layer, silicon oxynitride layer, aluminum oxide layer, silicon carbide layer, and amorphous silicon layer.

[0149] Specifically, forming a first doped layer on or within the surface of the first region includes:

[0150] A semiconductor layer is formed on a first surface of a substrate, and a first doped source layer is formed at a location corresponding to a first region of the semiconductor layer. The first doped source layer is then heated and advanced to form a first mono-doped layer at a portion of the semiconductor layer corresponding to the first region. A fourth doped source layer is formed on the first mono-doped layer. The fourth doped source layer is then heated and advanced to form a first co-doped layer on the side of the first mono-doped layer away from the substrate. The first mono-doped layer and the first co-doped layer constitute the first doped layer. In this application, the fourth doped source layer and the second doped source layer can be the same layer.

[0151] The preparation of the first doped layer by the above method, which includes a first mono-doped layer and a first co-doped layer, can reduce the process difficulty of solar cells, simplify the process flow of solar cells, and reduce the manufacturing cost of solar cells.

[0152] Of course, the above method can also be used to form a second doped layer on or within the surface of the second region. Further details will not be elaborated here.

[0153] After heating and advancing the fourth doped source layer to form a first co-doped layer in the portion of the first single-doped layer away from the substrate, the method further includes:

[0154] A through-groove is provided on the first co-doped layer, and a first electrode is embedded in the through-groove and connected to the first region of the first mono-doped layer or the substrate. There is a gap between the first electrode and the inner wall of the through-groove.

[0155] In this embodiment, a through-groove is provided in the first co-doped layer, a first electrode is embedded in the through-groove, and one end of the first electrode is connected to the first mono-doped layer or the first region of the substrate, so as to collect the charge carriers generated in the first region of the substrate through the first electrode.

[0156] It should be noted that, in the embodiments of this application, there is a gap between the sidewall of the first electrode and the inner wall of the through groove, so as to reduce the risk of leakage of the battery cell and improve the photoelectric conversion efficiency of the battery cell.

[0157] 203. Along the direction away from the substrate, a dielectric layer and a conductive path layer are sequentially stacked in the third region to block the first doped layer and the second doped layer through the dielectric layer, and to connect a portion of the first doped layer and a portion of the second doped layer through the conductive path layer.

[0158] The solar cell fabrication method disclosed in the embodiments of this application is used to fabricate a solar cell. Along the direction away from the substrate, a dielectric layer and a conductive path layer are sequentially stacked in the third region. The dielectric layer blocks the first doped layer and the second doped layer. The dielectric layer can also block the substrate and the conductive path layer, avoid short circuits in the solar cell, ensure normal operation of the solar cell, and improve the photoelectric conversion efficiency of the solar cell.

[0159] Furthermore, by connecting part of the first doped layer and part of the second doped layer through the conductive path layer, the conductive path layer can achieve soft breakdown between the first doped layer and the second doped layer, avoiding the hot spot effect when the solar cell is shaded. In addition, while taking into account the hot spot effect, it can also ensure the photoelectric conversion efficiency of the cell under normal operation.

[0160] Specifically, in the third region, along a direction away from the substrate, the dielectric layer and the conductive path layer are sequentially stacked, including:

[0161] A semiconductor layer is formed on the first surface of the substrate, and a third doped source layer is formed at the position of the semiconductor layer corresponding to the third region. The third doped source layer is heated and advanced so that a dielectric layer and a conductive path layer are sequentially formed in the part of the semiconductor layer corresponding to the third region in a direction away from the substrate.

[0162] The method for fabricating a battery cell disclosed in this application, after forming a first doped layer, a second doped layer, a dielectric layer, and a conductive path layer, further includes:

[0163] The process involves removing residual dopant sources from the surface of the solar cells and cleaning them. Further surface modification steps, such as etching, are then required. Etching modifies the surface dopant in different areas, removing surfaces with excessively high or low doping concentrations. Surfaces with excessively high doping concentrations can lead to Auger recombination regions, while surfaces with excessively low doping concentrations are detrimental to subsequent contact between the surface metal and electrodes. These processes result in improved solar cell performance.

[0164] After sequentially stacking a dielectric layer and a conductive path layer in the third region along a direction away from the substrate, the method further includes:

[0165] A surface passivation layer is formed on the side of the first doped layer, the second doped layer, and the conductive path layer away from the substrate. A first electrode and a second electrode are formed within the surface passivation layer. The first electrode is electrically connected to the first doped layer, and the second electrode is electrically connected to the second doped layer. The first electrode collects charge carriers in the first doped layer and transmits the current collected in the first doped layer, while the second electrode collects charge carriers in the second doped layer and transmits the current collected in the second doped layer.

[0166] In a preferred embodiment, during the surface passivation process, a surface passivation layer or antireflection layer can be formed simultaneously on the side of the first doped layer away from the substrate, the side of the second doped layer away from the substrate, and the side of the conductive path layer away from the substrate. This ensures that the structure of the surface passivation layer or antireflection layer corresponding to the first region, the second region, and the third region is completely identical.

[0167] It should be noted that the surface passivation layer or antireflection layer in the embodiments of this application can be a single-layer structure or a multi-layer structure. The surface passivation layer or antireflection layer includes one or more of the following: silicon nitride layer, silicon oxide layer, silicon oxynitride layer, aluminum oxide layer, silicon carbide layer, amorphous silicon layer, and transparent conductive oxide (TCO). In the process of preparing the surface passivation layer or antireflection layer, atomic layer deposition (ALD), chemical vapor deposition (CVD), such as plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), and physical vapor deposition (PECVD), such as evaporation and sputtering, can be used to prepare the surface passivation layer or antireflection layer.

[0168] For example, in the process of preparing a surface passivation layer or antireflection layer, an aluminum oxide passivation layer can be prepared first by atomic layer deposition (ALD), and then one or more silicon nitride layers can be formed on the aluminum oxide passivation layer by plasma enhanced chemical vapor deposition (PECVD).

[0169] The first and second electrodes in this embodiment can be made of metals such as Ag, Cu, Al, Ni, Au, Zn, Sn, Pb, etc., or metal nitrides such as TiN, metal carbides such as TiC, etc., or metal sulfides. In this embodiment, no specific limitations are placed on the materials used for the first and second electrodes. In practical applications, those skilled in the art can select appropriate materials as needed.

[0170] This application also discloses a photovoltaic module, which includes the solar cells described in the above embodiments.

[0171] It should be noted that in this embodiment, the photovoltaic module includes solar cells with the same structure as the solar cells described in the above embodiments, and their beneficial effects are similar, so they will not be repeated here.

[0172] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0173] Although optional embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the optional embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0174] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used merely to distinguish one entity from another, and do not necessarily require or imply any such actual relationship or order between these entities. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or terminal device that includes that element.

[0175] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the principles and implementation methods of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

A solar cell includes: a substrate having a first surface and a second surface oppositely arranged, the first surface including a first region and a second region arranged at intervals and a third region between the first region and the second region; a first doped layer arranged on a surface of the first region or at least partially embedded in the surface of the first region, and a second doped layer arranged on a surface of the second region or at least partially embedded in the surface of the second region, the second doped layer having a polarity opposite to that of the first doped layer; a dielectric layer and a conductive path layer, arranged in the third region in sequence away from the substrate, the dielectric layer blocking the first doped layer and the second doped layer, and the conductive path layer connecting part of the first doped layer and part of the second doped layer. The solar cell according to claim 1, wherein In a thickness direction of the cell, a thickness of the dielectric layer is greater than a thickness of the conductive path layer. The solar cell according to claim 1, wherein In the thickness direction of the cell, the thickness of the conductive path layer is greater than the thickness of the dielectric layer. The solar cell according to claim 1, wherein The dielectric layer and the conductive path layer are made of the same base material. Alternatively, the dielectric layer and the conductive path layer are made of different base materials. The solar cell according to claim 1, wherein The conductive path layer includes a layer doped with one element. And / or, the conductive path layer includes a layer doped with two elements having opposite polarities. The solar cell according to claim 1, wherein The conductive path layer includes a single-doped path layer and a co-doped path layer, wherein the single-doped path layer is arranged on a side of the dielectric layer away from the substrate, and the co-doped path layer is arranged on a side of the single-doped path layer away from the dielectric layer; the single-doped path layer is doped with one element, and the co-doped path layer is doped with two elements having opposite polarities. The solar cell according to claim 6, wherein The single-doped path layer and the co-doped path layer have the same conductivity type. The solar cell according to claim 1, wherein A surface element doping concentration of the conductive path layer is greater than or equal to a surface element doping concentration of the first doped layer. And / or, a surface element doping concentration of the conductive path layer is greater than or equal to a surface element doping concentration of the second doped layer. The solar cell according to claim 1, wherein In the thickness direction of the cell, a thickness of the conductive path layer is d1, satisfying 10nm≤d1≤120nm. And / or, The element doping concentration of the conductive path layer is greater than 1E18 cm -3 and less than 5E22 cm -3 . The solar cell according to claim 1, wherein The element doping concentration of the medium layer is less than 1E13 cm -3 ; And / or, in the thickness direction of the cell, a thickness of the dielectric layer is d2, satisfying 20nm≤d2≤490nm. The solar cell according to claim 1, wherein The substrate corresponding to the third region has a third doped region therein, the third doped region having an elemental doping concentration less than 1E13 cm -3 . The solar cell according to claim 1, wherein The substrate corresponding to the first region has a first doped region therein, the first doped region having an elemental doping concentration greater than 1E13 cm -3 ; and / or, the substrate has a second doped region within the second region, the second doped region having an elemental doping concentration greater than 1E13 cm -3 . The solar cell according to any one of claims 1 to 12, wherein The first doped layer includes a first single-doped layer and a first co-doped layer, the first single-doped layer is doped with one element, and the first co-doped layer is doped with two elements having opposite polarities, wherein the first single-doped layer is arranged on a surface of the first region or at least partially embedded in the surface of the first region, and the first co-doped layer is arranged on a side of the first single-doped layer away from the substrate, the first co-doped layer having a conductivity type opposite to that of the first single-doped layer. The solar cell further comprises a first electrode coupled to the first region of the substrate, the first co-doped layer is provided with a through groove, the first electrode is embedded in the through groove and connected to the first single-doped layer or the first region of the substrate, and a space is formed between the first electrode and the inner wall of the through groove. The solar cell according to claim 13, wherein The uniformity of the element doping concentration in the first single-doped layer is better than that in the first co-doped layer. The solar cell according to any one of claims 1 to 12, wherein The second doping layer comprises a second single-doped layer and a second co-doped layer, the second single-doped layer is doped with one element, and the second co-doped layer is doped with two elements with opposite polarities, wherein The second single-doped layer is stacked on the surface of the second region or at least partially embedded in the surface of the second region, and the second co-doped layer is stacked on the side of the second single-doped layer away from the substrate, and the second co-doped layer has the same conductivity type as the second single-doped layer. The solar cell according to claim 15, wherein In the thickness direction of the solar cell, the thickness of the second co-doped layer is greater than the thickness of the first co-doped layer of the first doping layer, and the thickness of the first co-doped layer is greater than or equal to the thickness of the co-doped path layer of the conductive path layer, wherein the first co-doped layer is doped with two elements with opposite polarities, and the co-doped path layer is doped with two elements with opposite polarities. The solar cell according to claim 1, wherein The side of the first doping layer close to the conductive path layer has a first concentration gradient co-doped region; The side of the second doping layer close to the conductive path layer has a second concentration gradient co-doped region. The solar cell according to claim 17, wherein In the case that the first doping layer is a P-type doping layer and the second doping layer is an N-type doping layer, the width of the first concentration gradient co-doped region is greater than the width of the second concentration gradient co-doped region. The solar cell according to claim 1, wherein The side of the conductive path layer close to the first doping layer has a first depth gradient co-doped region, and the side of the conductive path layer close to the second doping layer has a second depth gradient co-doped region. A method for manufacturing a solar cell, the method comprising: providing a substrate having oppositely arranged first and second surfaces, the first surface comprising first and second regions arranged with a space therebetween and a third region between the first and second regions; forming a first doping layer on or in the surface of the first region and a second doping layer on or in the surface of the second region, the first and second doping layers having opposite polarities; in a direction away from the substrate, sequentially stacking a dielectric layer and a conductive path layer on the third region to block the first and second doping layers by the dielectric layer and to connect part of the first doping layer and part of the second doping layer by the conductive path layer. The method for manufacturing a solar cell according to claim 20, wherein The forming a first doping layer on or in the surface of the first region and a second doping layer on or in the surface of the second region comprises: forming a semiconductor layer on a first surface of the substrate, and forming a first doped source layer and a second doped source layer on positions of the semiconductor layer corresponding to the first region and the second region respectively; heating and advancing the first doped source layer and the second doped source layer to form the first doped layer on a portion of the semiconductor layer corresponding to the first region and the second doped layer on a portion of the semiconductor layer corresponding to the second region, the first doped layer and the second doped layer having opposite polarities. The method for manufacturing a solar cell according to claim 20, wherein the third region comprises, in sequence from the substrate, a dielectric layer and a conductive path layer; forming a semiconductor layer on a first surface of the substrate, and forming a third doped source layer on a position of the semiconductor layer corresponding to the third region; heating and advancing the third doped source layer to form, in sequence from the substrate, the dielectric layer and the conductive path layer on a portion of the semiconductor layer corresponding to the third region. The method for manufacturing a solar cell according to claim 20, wherein the first doped layer formed on or in the first region comprises: forming a semiconductor layer on a first surface of the substrate, and forming a first doped source layer on a position of the semiconductor layer corresponding to the first region; heating and advancing the first doped source layer to form a first single-doped layer on a portion of the semiconductor layer corresponding to the first region; forming a fourth doped source layer on the first single-doped layer; heating and advancing the fourth doped source layer to form a first co-doped layer on a side of the first single-doped layer away from the substrate, the first single-doped layer and the first co-doped layer constituting the first doped layer; the method further comprises: providing a through slot on the first co-doped layer, and embedding a first electrode in the through slot and connecting the first electrode to the first single-doped layer or the first region of the substrate, the first electrode having a spacing from an inner wall of the through slot. A photovoltaic module comprising the solar cell of any one of claims 1-19.

Images