Communication method, apparatus and system

Abstract

The present application relates to the technical field of communications. Disclosed are a communication method, apparatus and system. The method comprises: a first communication apparatus generating a synchronization signal on the basis of a first sequence, and sending the synchronization signal, wherein the first sequence has an ideal autocorrelation characteristic, and a value set of elements of the first sequence is {-A,0,A}, with A being a constant. By means of the method, a first sequence comprises at least one element with the value being 0, and the first sequence has an ideal autocorrelation characteristic, such that the detection performance for a synchronization signal can be ensured, and the detection complexity for the synchronization signal can also be reduced.

Description

A communication method, apparatus and system Cross Reference to Related Applications This application claims priority to the Chinese Patent Application No. 202410982213.2, filed on July 19, 2024, and entitled "A communication method, apparatus and system", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD The present application relates to the field of communication technology, and in particular to a communication method, apparatus and system. BACKGROUND In a wireless communication system, a synchronization signal is used for time-frequency synchronization between a terminal device and a network device. For example, a network device can send a synchronization signal (SS) / physical broadcast channel (PBCH) block (SS / PBCH block), and then the terminal device can perform time-frequency synchronization and obtain information (such as a physical cell identity (PCI)) of a cell after receiving the SS / PBCH block, so as to access the cell. The SS / PBCH block includes a primary synchronization signal (PSS), a secondary synchronization signal (SSS) and a physical broadcast channel (PBCH). The terminal device performs time-frequency synchronization based on the primary synchronization signal, and therefore the detection complexity of the primary synchronization signal is high. How to reduce the detection complexity of the primary synchronization signal still needs further research. SUMMARY The present application provides a communication method, apparatus and system for reducing the detection complexity of a synchronization signal. In a first aspect, an embodiment of the present application provides a communication method, which can be applied to a first communication apparatus. The first communication apparatus can be a network device or a component (such as a chip or a circuit) in the network device. For example, in the method provided in the first aspect, the first communication apparatus generates a synchronization signal according to a first sequence; and sends the synchronization signal; wherein the first sequence is ideally autocorrelated, and the value set of elements of the first sequence is {-A, 0, A}, A being a constant. By using the above method, since the first sequence includes at least one element with a value of 0 and the first sequence is ideally autocorrelated, the detection complexity of the synchronization signal can be reduced while ensuring the detection performance of the synchronization signal. In one possible design, a synchronization signal is generated from a first sequence, including performing DFT processing on the first sequence to obtain a second sequence, mapping the second sequence onto a plurality of subcarriers, and performing IFFT processing to generate the synchronization signal, where the first sequence is denoted as [x(n)], the second sequence is denoted as [y(n)], n = 0, 1, 2,..., L-1, and the second sequence and the first sequence satisfy: In this way, the synchronization signal is generated by performing DFT processing, subcarrier mapping, and IFFT processing on the first sequence, i.e., the synchronization signal is transmitted using a DFT-s-OFDM waveform. In one possible design, a synchronization signal is generated from a first sequence, including mapping the first sequence onto a plurality of subcarriers, and performing IFFT processing to generate the synchronization signal. In this way, the synchronization signal is generated by performing subcarrier mapping and IFFT processing on the first sequence, i.e., the synchronization signal is transmitted using an OFDM waveform. In one possible design, A = 1. In one possible design, the first sequence is derived based on a third sequence, and the third sequence has a value set of {0, 1, 2} for elements; the first sequence is denoted as [x(n)], the third sequence is denoted as [s(n)], and the first sequence and the third sequence satisfy: It can be understood that for a ternary sequence, the value set of elements is {0, 1, 2}, 1 and -2 are congruent modulo 3, and 2 and -1 are congruent modulo 3, and thus, element 2 in the finally generated sequence can be replaced by -1. In one possible design, a transmission power of the synchronization signal is a first power plus a power offset, and the power offset is equal to L represents a length of the first sequence, and m represents a number of elements with a value of 0 in the first sequence; where the first power is predefined or preconfigured. In one possible design, L represents a length of the first sequence, and m represents a number of elements with a value of 0 in the first sequence. In one possible design, the first sequence is derived based on a third sequence, and the third sequence has a value set of {0, 1, 2} for elements; the first sequence is denoted as [x(n)], the third sequence is denoted as [s(n)], and the first sequence and the third sequence satisfy: It can be understood that, since at least one element with value 0 is included in the ternary sequence, the transmission power associated factor is multiplied on the basis of the ternary sequence (value set is {-1, 0, 1}) The power normalization of the transmitted signal is facilitated. In a possible design, the transmission power of the synchronization signal is a first power, and the first power is predefined or preconfigured. In a possible design, the first sequence is obtained based on a third sequence, the third sequence is one of W sequences, the W sequences are obtained according to W recursive formulas, and W is an integer greater than 1. In a possible design, the cross-correlation values between the W sequences are less than or equal to a first threshold. In this way, the detection performance of the synchronization signal is facilitated. In a possible design, the first threshold is 0.26. In a possible design, the W recursive formulas include any one of the following formulas: s(n+5) = (2s(n+2) + 2s(n+1) + s(n)) mod 3; s(n+5) = (2s(n+3) + 2s(n+2) + s(n+1) + s(n)) mod 3; s(n+5) = (2s(n+4) + 2s(n+1) + s(n)) mod 3. In a possible design, a normalized secondary peak of a ambiguity function of the synchronization signal is less than or equal to a second threshold, and the frequency offset performance of the synchronization signal is facilitated. In a possible design, the second threshold is 0.135. In a possible design, the length of the first sequence is 3 k -1 / 2, and k is an integer greater than 1. In a possible design, when k is equal to 5, the number of elements with value 0 in the first sequence is 40. In a second aspect, an embodiment of the present application provides a communication method, which can be applied to a second communication device, and the second communication device can be a terminal device or a component (such as a chip or a circuit) in the terminal device. For example, in the method provided in the second aspect, the second communication device detects a synchronization signal, and the synchronization signal is a signal obtained according to the first sequence; and the first sequence has ideal autocorrelation, and the value set of elements of the first sequence is {-A, 0, A}, and A is a constant. In a possible design, the method further includes: obtaining the first sequence, and processing the received signal according to the first sequence to detect the synchronization signal; or obtaining a third sequence, obtaining the first sequence according to the third sequence, and processing the received signal according to the first sequence to detect the synchronization signal; or processing the received signal according to a sequence in a synchronization sequence set to detect the synchronization signal, where the sequence in the synchronization sequence set includes the first sequence. In a possible design, processing the received signal according to the first sequence includes: performing discrete Fourier transform (DFT) on the first sequence to obtain a second sequence; mapping the second sequence onto a plurality of subcarriers and performing inverse fast Fourier transform (IFFT) processing; and performing correlation processing on the received signal according to the IFFT-processed sequence, where the first sequence is denoted as [x(n)], the second sequence is denoted as [y(n)], n=0, 1, 2,..., L-1, and the second sequence and the first sequence satisfy: In this way, the terminal device can directly perform correlation processing on the received signal in the time domain, without the need to first perform DFT processing on the received signal to transform to the frequency domain and then perform processing, thereby greatly reducing the detection complexity of the synchronization signal. In addition, since the first sequence includes at least one element with a value of 0, the number of addition operations and / or the number of multiplication operations in each correlation operation can be reduced, and in turn, the detection complexity of the synchronization signal is reduced. In a possible design, processing the received signal according to the first sequence includes: oversampling the first sequence, and performing correlation processing on the received signal according to the oversampled sequence; or performing downsampling on the received signal, and performing correlation processing on the downsampled signal according to the first sequence. In this way, the terminal device can directly perform correlation processing on the received signal in the time domain, without the need to first perform DFT processing on the received signal to transform to the frequency domain and then perform processing, thereby greatly reducing the detection complexity of the synchronization signal. In addition, since the first sequence includes at least one element with a value of 0, the number of addition operations and / or the number of multiplication operations in each correlation operation can be reduced, and in turn, the detection complexity of the synchronization signal is reduced. It can be understood that when the synchronization signal is a signal of a DFT-s-OFDM waveform, the sending of the synchronization signal is simulated by using a DFT-s-OFDM waveform to simulate a time-domain square wave, because the DFT-s-OFDM waveform can be compatible with signals of OFDM waveforms of other channels of the current system, thereby reducing interference on signals of other channels, and meanwhile enabling a terminal device to directly perform correlation processing on a received signal in the time domain. Therefore, the terminal device can perform correlation on a signal obtained by processing the first sequence by using a DFT-s-OFDM waveform, or can directly perform correlation on the first sequence after oversampling (that is, repeating sequence elements) and on the received signal, or can perform correlation on the received signal after downsampling and on the first sequence. In a possible design, processing the received signal according to the first sequence includes: mapping the first sequence onto a plurality of subcarriers to obtain a frequency-domain sequence; performing DFT processing on the received signal to obtain a frequency-domain signal; performing conjugate point multiplication on the frequency-domain sequence and the frequency-domain signal, and performing IDFT processing on the sequence after the conjugate point multiplication. In this way, because the second sequence includes at least one element with a value of 0, the complexity required by multiplication operation in frequency-domain detection and the complexity of IDFT can be reduced, and in turn the detection complexity of the synchronization signal is reduced. In a possible design, A=1. In a possible design, the first sequence is obtained based on a third sequence, and a value set of elements in the third sequence is {0, 1, 2}; the first sequence is denoted as [x(n)], the third sequence is denoted as [s(n)], and the first sequence and the third sequence satisfy: In a possible design, L represents the length of the first sequence, and m represents the number of elements with a value of 0 in the first sequence. In a possible design, the first sequence is obtained based on a third sequence, and a value set of elements in the third sequence is {0, 1, 2}; the first sequence is denoted as [x(n)], the third sequence is denoted as [s(n)], and the first sequence and the third sequence satisfy: In a possible design, the first sequence is obtained based on a third sequence, and the third sequence is one of W sequences, and the W sequences are obtained according to W recursive formulas; where a cross-correlation value between the W sequences is less than or equal to a first threshold value, and W is an integer greater than 1. In a possible design, the first threshold value is 0.26. In a possible design, the W recursive formulas include any of the following polynomials: s(n+5) = (2s(n+2) + 2s(n+1) + s(n)) mod 3; s(n+5) = (2s(n+3) + 2s(n+2) + s(n+1) + s(n)) mod 3; s(n+5) = (2s(n+4) + 2s(n+1) + s(n)) mod 3. In a possible design, a normalized secondary peak of a ambiguity function of the synchronization signal is less than or equal to a second threshold value. In a possible design, the second threshold value is 0.135. In a possible design, the first sequence has a length of 3 k -1 / 2, k is an integer greater than 1. In a possible design, when k is equal to 5, the number of elements with a value of 0 in the first sequence is 40. In a third aspect, an embodiment of the present application provides a communication method, which includes: generating a synchronization signal according to a first sequence, and sending the synchronization signal; and processing a received signal according to the first sequence to detect the synchronization signal; wherein the first sequence has ideal autocorrelation, and a value set of elements of the first sequence is {-A, 0, A}, A being a constant. It can be understood that other technical features of the third aspect can refer to the descriptions of the first aspect and the second aspect, and will not be repeated. In a fourth aspect, the present application provides a communication apparatus, which has functions related to the first aspect or the second aspect, for example, the communication apparatus includes modules or units or means for performing operations related to the first aspect or the second aspect, and the functions or units or means can be implemented by software, or by hardware, or by hardware executing corresponding software. In a possible design, the communication apparatus includes a processing unit and a communication unit, where the communication unit can be configured to transceive signals to implement communication between the communication apparatus and other apparatuses; and the processing unit can be configured to perform some internal operations of the communication apparatus. The functions performed by the processing unit and the communication unit can correspond to operations related to the first aspect or the second aspect. In a possible design, the communication apparatus includes a processor, which can be configured to be coupled with a memory. The memory can store computer programs or instructions necessary for implementing the functions of the first aspect or the second aspect. The processor can execute the computer programs or instructions stored in the memory, and when the computer programs or instructions are executed, the communication apparatus can implement the method in any possible design or implementation manner of the first aspect or the second aspect. In a possible design, the communication apparatus includes a processor and a memory, and the memory can store computer programs or instructions necessary for implementing the functions of the first aspect or the second aspect. The processor can execute the computer programs or instructions stored in the memory, and when the computer programs or instructions are executed, the communication apparatus can implement the method in any possible design or implementation manner of the first aspect or the second aspect. In a possible design, the communication apparatus includes a processor and an interface circuit, where the processor is configured to communicate with other apparatuses through the interface circuit, and implement the method in any possible design or implementation manner of the first aspect or the second aspect. It can be understood that, in the fourth aspect, the processor can be implemented by hardware or software. When implemented by hardware, the processor can be a logic circuit, an integrated circuit, or the like. When implemented by software, the processor can be a general-purpose processor, which implements the functions by reading software codes stored in the memory. In addition, the processor can be one or more, and the memory can be one or more. The memory can be integrated with the processor, or the memory and the processor can be separately arranged. In a specific implementation process, the memory can be integrated with the processor on the same chip, or can be separately arranged on different chips, and the type of the memory and the arrangement manner of the memory and the processor are not limited in the embodiments of the present application. In a fifth aspect, the present application provides a communication system, which can include a first communication apparatus and a second communication apparatus. The first communication apparatus is configured to implement the method in the first aspect, and the second communication apparatus is configured to implement the method in the second aspect. In a sixth aspect, the present application provides a computer readable storage medium, which stores computer programs (or computer readable instructions). When part or all of the computer readable instructions are read and executed by a computer, the method in any possible design of the first aspect or the second aspect is implemented. By way of example, and not limitation, computer-readable media can include non-transitory computer-readable media, random-access memories (RAMs), read-only memories (ROMs), electrically erasable programmable ROMs (EEPROMs), CD-ROMs or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a computer. In a seventh aspect, the present application provides a computer program product, when a computer reads and executes the computer program product, the method in any possible design of the first aspect or the second aspect is executed. In an eighth aspect, the present application provides a chip (or a chip system), the chip includes a processor, the processor is coupled with a memory, the memory stores a computer program; the processor is used to call part or all of the computer program in the memory, so that the method in any possible design of the first aspect or the second aspect is executed. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a schematic diagram of an architecture of a communication system to which embodiments of the present application are applied; FIG. 2 is a schematic diagram of an SS / PBCH block provided by an embodiment of the present application; FIG. 3 is a schematic diagram of a basic structure of a feedback shift register provided by an embodiment of the present application; FIG. 4 is a schematic diagram of a flow corresponding to a communication method provided by an embodiment of the present application; FIG. 5 is a schematic diagram of a generation architecture of a ternary sequence provided by an embodiment of the present application; FIG. 6 is a possible exemplary block diagram of an apparatus involved in an embodiment of the present application; FIG. 7 is a schematic diagram of a structure of a communication apparatus provided by an embodiment of the present application. DETAILED DESCRIPTION The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. The present application will present various aspects, embodiments or features around a system that can include a plurality of devices, components, modules, etc. It should be understood and appreciated that each system can include additional devices, components, modules, etc., and / or can not include all the devices, components, modules, etc. discussed in connection with the drawings. In addition, combinations of these solutions can also be used. In the embodiments of the present application, the words "exemplary", "for example", "for instance", etc. are used to mean example, illustration, or description. Any embodiment or design solution described in the present application as "exemplary" should not be interpreted as being more preferred or advantageous than other embodiments or design solutions. In fact, the word "exemplary" is used to present concepts in a particular manner. In the embodiments of the present application, "of", "corresponding" and "corresponding" are sometimes mixed. It should be pointed out that when the difference is not emphasized, the meanings expressed are consistent. The technical solutions of the embodiments of the present application can be applied to various wireless communication systems, such as universal mobile communication system (UMTS), wireless local area network (WLAN), short-range wireless communication system (such as sidelink, wireless fidelity (Wi-Fi), Bluetooth, etc.), wired network, vehicle to everything (V2X) communication system, device-to-device (D2D) communication system, Internet of Vehicles communication system, 4th generation (4G) mobile communication system (such as long term evolution (LTE) system), LTE frequency division duplex (FDD) system, LTE time division duplex (TDD), worldwide interoperability for microwave access (WiMAX) communication system, 5th generation (5G) mobile communication system (such as new radio (NR) system), future communication system, or other similar communication systems, etc. without limitation. The embodiments of the present application are described taking the communication system shown in FIG. 1 as an example. When the technical solutions of the embodiments of the present application are applied to other communication systems, the devices, components, modules, etc. in the embodiments can be replaced by corresponding devices, components, modules in other communication systems without limitation. FIG. 1 is a schematic diagram of an architecture of a communication system to which embodiments of the present application are applied. As shown in FIG. 1, the communication system includes an access network 100. Optionally, the communication system can also include a core network 200 and an Internet 300. The access network 100 can include at least one network device, such as 110a and 110b in FIG. 1, and at least one terminal device, such as 120a-120j in FIG. 1. Among them, 110a is a base station, 110b is a micro station, 120a, 120e, 120f and 120j are mobile phones, 120b is a car, 120c is a fuel dispenser, 120d is a home access point (HAP) arranged indoors or outdoors, 120g is a notebook computer, 120h is a printer, and 120i is a drone. Among them, the same terminal device or network device can provide different functions in different application scenarios. For example, the mobile phones in FIG. 1 are 120a, 120e, 120f and 120j. The mobile phone 120a can access the base station 110a, connect to the car 120b, communicate directly with the mobile phone 120e and access the HAP. The car 120b can access the HAP and communicate directly with the mobile phone 120a. The mobile phone 120f can access the micro station 110b, connect to the notebook computer 120g and connect to the printer 120h. The mobile phone 120j can control the drone 120i. (1) Network device A network device is a network-side device with wireless transceiving function. The network device can be a device in a radio access network (RAN) that provides wireless communication function for terminal devices, referred to as a RAN device. The RAN can be an access network in the 3rd generation partnership project (3GPP), such as 4G, 5G or future network. The RAN can also be an open RAN (O-RAN or ORAN), a cloud radio access network (CRAN), or a communication network of two or more of the above networks. The RAN device can also be a base station, an evolved NodeB (eNodeB), a transmission reception point (TRP), a next generation NodeB (gNB) in a 5G mobile communication system, a base station in a future mobile communication system, or an access node in a WiFi system, etc. The RAN device can also be a module or unit that completes the function of the base station part, for example, can be a central unit (CU), can also be a distributed unit (DU), and can also be a radio unit (RU). The CU here completes the function of the radio resource control (RRC) and the PDCP of the base station, and can also complete the function of the service data adaptation protocol (SDAP); the CU can be further divided into a CU control panel (CP) (CU-CP) and a CU user panel (UP) (CU-UP). The DU completes the function of the RLC layer and the MA layer of the base station, and can also complete part of the function of the physical layer or the entire function of the physical layer. For specific descriptions of the above-mentioned protocol layers, refer to the related technical specifications of 3GPP. The CU and the DU can be separately arranged, or can also be included in the same network element, for example, in a baseband unit (BBU). The RU can be included in a radio frequency device or a radio frequency unit, for example, included in a remote radio unit (RRU), an active antenna processing unit (AAU), or a remote radio head (RRH). In different systems, the CU, the DU, or the RU can also have different names, but those skilled in the art can understand their meanings. For example, in an ORAN system, the CU can also be referred to as an O-CU (open CU), the DU can also be referred to as an O-DU, and the RU can also be referred to as an O-RU. Any one of the CU (or CU-CP, CU-UP), the DU, and the RU in this application can be implemented by a software module, a hardware module, or a combination of a software module and a hardware module. The RAN device can be a macro base station (such as 110a in FIG. 1), can also be a micro base station or an indoor station (such as 110b in FIG. 1), and can also be a relay node or a donor node, etc. The embodiments of this application do not limit the specific technology and specific device form adopted by the network device. In the embodiments of this application, the function of the network device can also be executed by a module (such as a chip) in the network device, or can also be executed by a control subsystem containing the function of the network device. The control subsystem containing the function of the network device here can be a control center in the above-mentioned application scenarios such as smart grid, industrial control, intelligent transportation, and smart city. (2) Terminal device A terminal device is a user-side device with wireless transceiving function. The terminal device can also be referred to as a terminal, a user equipment (UE), a mobile station, a mobile terminal, etc. The terminal device can be widely applied in various scenarios, such as device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-type communication (MTC), internet of things (IOT), virtual reality, augmented reality, industrial control, automatic driving, remote medical treatment, smart power grid, smart furniture, smart office, smart wear, smart transportation, smart city, etc. The terminal device can be a mobile phone, a tablet computer, a computer with wireless transceiving function, a wearable device, a vehicle, a drone, a helicopter, an airplane, a ship, a robot, a mechanical arm, a smart home device, etc. In embodiments of the present application, a device for implementing the function of a terminal device can be a terminal device, or a device capable of supporting the terminal device to implement the function, such as a chip system or a combination device or component capable of implementing the function of the terminal device, which can be installed in the terminal device. Embodiments of the present application do not limit the specific technology and specific device form adopted by the terminal device. In embodiments of the present application, the function of a terminal device can also be performed by a module (such as a chip or a modem) in the terminal device, or by a device containing the function of the terminal device. The network device and the terminal device can be fixed in position or movable. The network device and the terminal device can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; can be deployed on water surface; or can be deployed on an airplane, a balloon or a man-made satellite in the air. Embodiments of the present application do not limit the application scenarios of the network device and the terminal device. The roles of the network device and the terminal device can be relative, for example, the helicopter or the drone 120i in FIG. 1 can be configured as a mobile network device, and for those terminal devices 120j accessing the wireless access network 100 through 120i, the terminal device 120i is a network device; but for the network device 110a, 120i is a terminal device, that is, 110a and 120i communicate with each other through a wireless air interface protocol. Of course, 110a and 120i can also communicate with each other through an interface protocol between network devices and network devices, in which case, relative to 110a, 120i is also a network device. Therefore, the network device and the terminal device can be collectively referred to as a communication device, 110a and 110b in FIG. 1 can be referred to as a communication device with network device function, and 120a-120j in FIG. 1 can be referred to as a communication device with terminal device function. The network device and the terminal device, the network device and the network device, and the terminal device and the terminal device can communicate through an authorized frequency spectrum, an unlicensed frequency spectrum, or both, without limitation. The network architecture and the service scenario described in the present application are used to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art can know that, with the evolution of network architecture and the emergence of new service scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems. The related terms or technical features involved in the embodiments of the present application will be explained first. These explanations are to make the embodiments of the present application easier to understand, and should not be regarded as a strict limitation on the terms in the claimed scope of the present application. (1) Sequence The "sequence" in the embodiments of the present application includes one or more elements. Among them, the element can be represented as a complex number, including a real part and an imaginary part; or the element can also be represented as a real number, without specific limitation. For example, the sequence [s(n)] includes L elements, and L is an integer greater than 1. n belongs to [0, …, L-1], that is, n∈[0, …, L-1]. "…" in [0, …, L-1] represents the integers between 0 and L-1. For example, when L=5, n∈[0, 1, 2, 3, 4]. The L elements in [s(n)] can be s(0), …, s(L-1) respectively; in other words, the element with number n in [s(n)] can be s(n). It can be understood that the embodiments of the present application take the numbering mode with the starting number 0 and the increment of 1 as an example, but are not limited thereto. For example, the numbering mode can also be that the starting number is 1 and the increment is 1. For another example, the numbering mode can also be that the starting number is X and the increment is 1, and X is an integer greater than 1. "[·]" and "{·}" can be used interchangeably, which are used to represent multiple elements and can be understood as a set, a group, or a sequence, without limitation. (2) Correlation operation If two sequences are the same, the correlation operation between them is called autocorrelation; if two sequences are different, the correlation operation between them is called cross-correlation. For two sequences of length L, such as [s1(n)] and [s2(n)], without considering the time domain cyclic shift, the cross-correlation value between [s1(n)] and [s2(n)] satisfies the following formula: wherein c(s1, s2)' represents the cross-correlation value between [s1(n)] and [s2(n)] (i.e., the cross-correlation value before normalization), c(s1, s2) represents the cross-correlation value between [s1(n)] and [s2(n)] (i.e., the cross-correlation value after normalization), and abs represents the absolute value. In the case of considering the time domain cyclic shift, the cross-correlation value between [s1(n)] and [s2(n)] satisfies the following formula: wherein c(s1, s2)' represents the cross-correlation value between [s1(n)] and [s2(n)] (i.e., the cross-correlation value before normalization), c(s1, s2) represents the cross-correlation value between [s1(n)] and [s2(n)] (i.e., the cross-correlation value after normalization), τ is the time domain multipath delay, and the value range of τ is [0, L-1]. If the above [s1(n)] and [s2(n)] are the same sequence (or [s1(n)] and [s2(n)] are the same sequence), and the autocorrelation value c(s1, s2) between [s1(n)] or [s2(n)] satisfies: then it can be considered that [s1(n)] or [s2(n)] is ideal autocorrelation. (3) SS / PBCH block Taking the 5G communication system as an example, the SS / PBCH block includes PSS, SSS and PBCH. As shown in FIG. 2, in the time domain, 1 SS / PBCH block occupies 4 orthogonal frequency division multiplexing (OFDM) symbols, such as symbol 0-symbol 3; in the frequency domain, 1 SS / PBCH block occupies 20 resource blocks (RBs) (one RB includes 12 subcarriers), that is, 240 subcarriers, and the subcarrier number is 0-239. The PSS is located on the middle 127 subcarriers of symbol 0, and the SSS is located on the middle 127 subcarriers of symbol 2. In order to protect the PSS and the SSS, there are different guard subcarriers, and the guard subcarriers are not used to carry signals, and subcarriers are left on both sides of the SSS as guard subcarriers, such as the blank areas on both sides of the SSS in FIG. 2. The PBCH occupies all subcarriers of symbol 1 and symbol 3, and occupies a part of the remaining subcarriers (i.e., subcarriers other than the guard subcarriers) in the remaining subcarriers in the whole subcarriers of symbol 2 except the subcarriers occupied by the SSS. (4) Generation of PSS and SSS Before detecting the PSS, the terminal device does not know the center frequency of the cell, and the carrier frequency calibration between the terminal device and the network device is not completed, therefore, the PSS is a signal used by the terminal device to determine the center frequency of the carrier of the cell, and the detection performance is ensured in the case of time deviation and frequency deviation. The PSS in NR adopts an m sequence. The m sequence is introduced as follows: the m sequence is the abbreviation of the longest linear feedback shift register sequence, and is a sequence with the longest period generated by a shift register with linear feedback. Generally, the longest period generated by a v-level linear feedback shift register is equal to 2 v -1. FIG. 3 is the basic structure of a feedback shift register, the bit data used for initialization is stored in a memory, a new value is generated through a feedback function and is supplemented to the memory. It is assumed that the feedback function is an exclusive OR operation on all the bits in the memory, that is, The output sequence is The length of the output sequence is 2 v -1. It can be understood that the m sequence is determined by the initial value sequence stored in the register and the primitive polynomial, the value set of the elements in the initial value sequence is {0, 1}, and the order of the primitive polynomial is the highest power in the polynomial. For example, the recursive formula corresponding to the primitive polynomial f(x) = x 7 +x+1 is s(t)+s(t-6)+s(t-7)=0, since the binary addition is defined as modulo 2 addition, the recursive formula can be converted to s(t)=s(t-6)+s(t-7), that is, the recursive formula corresponding to the primitive polynomial f(x) = x 7 +x+1 is s(t)=s(t-6)+s(t-7). The recursive formula corresponds to the primitive polynomial one-to-one, and the "recursive formula" in the embodiment of the application can be replaced by "primitive polynomial". When the PSS adopts the m sequence, a possible generation formula of the PSS sequence (denoted as [d(n)]) is as follows: d(n)=1-2x(m) 0≤n<127 Wherein, mod is the modulo operation, The introduction of x(i+7)=(x(i+4)+x(i))mod2, [x(6), x(5), x(4), x(3), x(2), x(1), x(0)] is the initial value preconfigured or predefined, such as [x(6), x(5), x(4), x(3), x(2), x(1), x(0)] = [1, 1, 1, 0, 1, 1, 0]. After the m sequence is generated according to the above formula, the m sequence is modulated by BPSK, and a PSS sequence can be obtained. The value set of elements in the PSS sequence is {1, -1}. Further, the network device can generate a PSS according to the PSS sequence. For example, the network device maps the elements in the PSS sequence to a plurality of subcarriers, and performs inverse fast Fourier transformation (IFFT) processing to generate the PSS, that is, the PSS is an OFDM waveform signal. In addition, the SSS in NR adopts a gold sequence, which can be obtained by performing element-wise exclusive OR on two m sequences with different primitive polynomials. The gold sequence has good autocorrelation and cross-correlation characteristics, and a large number of gold sequences can be used to carry information. When the SSS adopts the gold sequence, the generation formula of the SSS sequence can refer to the prior art, which will not be described here. After the network device generates the SSS sequence according to the generation formula of the SSS sequence, the network device can generate the SSS according to the SSS sequence. (5) Functions of PSS, SSS, and PBCH PSS: used for frequency synchronization and symbol-level time synchronization. The PSS sequence is used to carry may be referred to as a cell number, The value set of the cell number is {0, 1, 2}. Since The value set of the cell number has three values, and therefore there can be three PSS sequences. The three PSS sequences can correspond to the same recursive formula, that is, the three PSS sequences are obtained by cyclically shifting the m sequence obtained according to the same recursive formula. SSS: used to carry may be referred to as a cell group number, The value set of the cell group number is {0, 1, 2, …, 335}. The cell number and the cell group number jointly determine a plurality of PCIs in the 5G communication system, and the PCI (denoted as The calculation method of the PCI is as follows: Therefore, there are a total of 1008 PCIs. The PSS sequence has three types in total, and after the terminal device detects the PSS sequence, the terminal device can determine Further, the terminal device maps to the detection of the SSS. Once It is determined that there are 336 possible SSS sequences in total. The terminal device needs to use the 336 different SSS sequences for cross-correlation detection, and the SSS sequence corresponding to the maximum cross-correlation value is the actually transmitted sequence. Once the terminal device successfully searches for the PSS and the SSS, the information (such as the PCI) of the cell is obtained, and the terminal device has the ability to analyze the system message contained in the SS / PBCH block. PBCH: used to carry the system message contained in the SS / PBCH block, such as the main information block (MIB). The MIB includes information necessary for the terminal device to access the network, such as the system frame number, the initial access subcarrier spacing, and the like. Since the information contained in the MIB is limited and is not enough to support the terminal device to access the 5G cell, the terminal device must also obtain some necessary system messages, such as the system information block (SIB) 1. The SIB1 is transmitted on the physical downlink shared channel (PDSCH) with a period of 160 milliseconds. Since the terminal device has obtained the parameters used for SIB1 transmission and the control resource distribution for scheduling it in the MIB carried by the PBCH, it can receive the SIB1. In this way, the terminal device can obtain the system message necessary for accessing the 5G cell, and can subsequently access the 5G cell. Since the terminal device performs time-frequency synchronization based on the PSS, the detection complexity of the PSS is high. Specifically, it is assumed that the received signal of the terminal device is [r(n)] = [r(0), r(1), …, r(L'-1)], where the length L' of the received signal corresponds to the length of the receiving window, and the length of the receiving window is predetermined, such as the length of the receiving window can be related to the transmission period of the PSS. For example, the length of the receiving window is set to 5ms. The terminal device can generate three time domain sequences according to the three PSS sequences, and use the three time domain sequences to detect the received signal. Taking one of the PSS sequences as an example, the terminal device performs subcarrier mapping and IFFT processing on the PSS sequence with a length of L to obtain a time domain sequence p (in the case of no oversampling, the sequence p includes L elements, and in the case of oversampling, the sequence p includes N elements, N is greater than L, and here the case of oversampling is taken as an example). For the received signal, the terminal device slides one sample point each time, such as the signal r tmp obtained by sliding the sample point i times is [r(i-1), r(i), … r(N+i-1)], and the inner product of the sequence p and the sequence r tmp is obtained to obtain the cross-correlation value between the sequence p and the sequence r tmp ​ Optionally, the terminal device normalizes the cross-correlation value to obtain c(p, r tmp )′, and a specific calculation formula can be referred to the foregoing. The terminal device can sequentially slide each sampling point in the N sampling points to obtain N cross-correlation values. Due to the crystal frequency offset and the mobility of the terminal device, there is a frequency offset in the received signal. Considering the maximum crystal frequency offset (related to the device characteristics) and the maximum moving speed of the terminal device, the terminal device can know the maximum frequency offset range (for example, less than or equal to twice the subcarrier spacing) in advance. Further, the terminal device can compensate the received signal according to the step to traverse different frequency offset values, and then perform the foregoing correlation operation. The step of traversal can be set to 0.2 or 0.5 times the subcarrier spacing (SCS). Taking 0.5 times the subcarrier spacing as an example, when the frequency offset value f d = 0.5*SCS, the signal r tmp corrected for the i-th sliding sampling point is obtained. Further, the cross-correlation value c(p, r tmp,1 )′ between the sequence p and the sequence r tmp,1 is obtained through the correlation operation. That is, when detecting the PSS, the terminal device needs to traverse different PSS sequences, different time delays (i.e., sampling points), and different frequency offset values for correlation calculation. For example, there are M frequency offset values in the maximum frequency offset range, the number of sampling points is N, and the number of PSS sequences is 3. Therefore, 3*M*N correlation operations are required to traverse 3 PSS sequences, M frequency offset values, and N sampling points. According to the foregoing correlation calculation formula, each correlation operation needs to perform N-1 addition operations and N multiplication operations, thereby resulting in high detection complexity. Based on this, the embodiment of the present application provides a communication method for reducing the detection complexity of the synchronization signal. Exemplarily, in the communication method provided by the embodiment of the present application, the sending side generates a synchronization signal according to a first sequence, and sends the synchronization signal; wherein the first sequence is ideal autocorrelation, and the value set of the elements of the first sequence is {-A, 0, A}, and A is a constant. The synchronization signal can be a signal of a discrete fourier transformation-spread-orthogonal frequency division multiplexing (DFT-s-OFDM) waveform, in which case, since the first sequence includes at least one element with a value of 0, the number of addition operations and / or the number of multiplication operations in each correlation operation can be reduced, thereby reducing the detection complexity of the synchronization signal. Alternatively, the synchronization signal can be a signal of an orthogonal frequency division multiplexing (OFDM) waveform, in which case, since the first sequence includes at least one element with a value of 0, the complexity required for the multiplication operation in the frequency domain detection and the complexity of the inverse discrete fourier transform (IDFT) can be reduced, thereby reducing the detection complexity of the synchronization signal. The communication method provided by the embodiment of the present application relates to a first communication device and a second communication device. The first communication device is the sending side of the synchronization signal, and the second communication device is the receiving side of the synchronization signal. For example, the first communication device is a network device or a component in the network device, such as a chip or a chip system arranged in the network device; and the second communication device is a terminal device or a component in the terminal device, such as a chip or a chip system arranged in the terminal device. In the embodiment of the present application, the first communication device is taken as an example of a network device, and the second communication device is taken as an example of a terminal device. FIG. 4 is a flowchart of the communication method provided by the embodiment of the present application. As shown in FIG. 4, the flowchart can include the following steps: S401, the network device generates a synchronization signal according to a first sequence. Exemplarily, the synchronization signal can be a PSS, or other possible signals for time and / or frequency synchronization, which are not limited in detail. Exemplarily, the network device can first obtain the first sequence, and then generate the synchronization signal according to the first sequence. The network device can obtain the first sequence in various ways, such as directly obtaining a predefined or preconfigured first sequence, or obtaining a predefined or preconfigured third sequence and obtaining the first sequence according to the third sequence, which will be described below. (1) describe the first sequence. The first sequence is a ternary sequence, which can be generated based on a cyclic shift register, and refer to FIG. 5 for a possible generation architecture of the ternary sequence. The primitive polynomial corresponding to FIG. 5 is f(x) = x 5 + x 2 + 2, and the corresponding recurrence formula is s(n+5) + s(n+2) + s(n+1) + 2s(n) = 0, and s(n+5) = (2s(n+2) + 2s(n+1) + s(n)) mod 3 is derived. It can be understood that for the ternary sequence, the element value set is {0, 1, 2}, 1 and -2 are congruent modulo 3, and 2 and -1 are congruent modulo 3, so the element 2 in the finally generated sequence can be replaced by -1. wherein the first sequence has ideal autocorrelation, and the element value set of the first sequence is {-A, 0, A}, A being a constant. The length of the first sequence is 3 k -1 / 2, k being an integer greater than 1. When k is equal to 5, i.e., the length of the first sequence is 121, the number of elements with a value of 0 in the first sequence is 40. For example, A = 1, i.e., the element value set of the first sequence is {-1, 0, 1}. Exemplarily, the first sequence is obtained based on a third sequence, the element value set of the third sequence is {0, 1, 2}; the first sequence is denoted as [x(n)], and the third sequence is denoted as [s(n)], and the first sequence and the third sequence satisfy: For another example, L represents the length of the first sequence, and m represents the number of elements with a value of 0 in the first sequence, i.e., the element value set of the first sequence is Exemplarily, the first sequence is obtained based on a third sequence, and the first sequence and the third sequence satisfy: That is, the fourth sequence can be obtained according to the third sequence, the element value set of the fourth sequence is {-1, 0, 1}, and then the fourth sequence is multiplied by a transmission power related factor to obtain the first sequence, wherein the transmission power related factor is In this way, the elements in the fourth sequence are multiplied by the transmission power related factor to obtain the first sequence, and the synchronization signal is generated according to the first sequence, which can ensure the power normalization of the transmitted signal. The third sequence is one of the W sequences, and the W sequences are ternary sequences with ideal autocorrelation. The W sequences are obtained according to W recursive formulas, the W sequences correspond to the W recursive formulas one by one, and the W sequences are obtained according to the W recursive formulas. For example, the W sequences include sequence 1, sequence 2,..., and sequence w, the W recursive formulas include recursive formula 1, recursive formula 2,..., and recursive formula w, the recursive formula 1 to the recursive formula w are different recursive formulas; the sequence 1 is obtained according to the recursive formula 1 and the initial value sequence 1, the sequence 2 is obtained according to the recursive formula 2 and the initial value sequence 2, and so on, and the sequence w is obtained according to the recursive formula w and the initial value sequence w. The initial value sequence 1 to the initial value sequence w can be the same initial value sequence (for example, the initial value sequence 1 to the initial value sequence w are all [s(4)s(3)s(2)s(1)s(0)] = [0 1 2 3 0] ) or can be different initial value sequences.

[0001] For example, the cross-correlation values between the W recursive formulas are less than or equal to a first threshold value, and the cross-correlation values between different recursive formulas can refer to the cross-correlation values between the sequences obtained based on different recursive formulas; that is, the cross-correlation values between the W sequences are less than or equal to the first threshold value. The first threshold value can be set according to actual needs, for example, the first threshold value is 0.26. For example, the length of each sequence in the W sequences is 121, and the W recursive formulas can include any multiple of the following recursive formula 1 to recursive formula 3: Recursive formula 1: s(n+5) = (2s(n+2) + 2s(n+1) + s(n)) mod 3; Recursive formula 2: s(n+5) = (2s(n+3) + 2s(n+2) + s(n+1) + s(n)) mod 3; Recursive formula 3: s(n+5) = (2s(n+4) + 2s(n+1) + s(n)) mod 3. (2) The implementation of obtaining the first sequence by the network device is described. As a possible implementation, the third sequence is a pre-configured or pre-defined sequence, in this case, the network device can directly obtain the pre-defined or pre-configured third sequence, and obtain the first sequence according to the third sequence, and then generate the synchronization signal according to the first sequence. Alternatively, the W sequences are pre-configured or pre-defined sequences, in this case, the network device can select one sequence from the W sequences as the third sequence, and obtain the first sequence according to the third sequence, and then generate the synchronization signal according to the first sequence. Optionally, the third sequence is associated with a cell identifier, for example, the third sequence is associated with For example, ​The value set of the cell identifier is {0, 1, 2}, and then W (W=3) sequences can be preconfigured or predefined, and the three sequences are associated with different values, for example, sequence 1 is associated with "0", sequence 2 is associated with "1", and sequence 3 is associated with "2" The value set of the cell identifier is {0, 1, 2}, and then W (W=3) sequences can be preconfigured or predefined, and the three sequences are associated with different values, for example, sequence 1 is associated with "0", sequence 2 is associated with "1", and sequence 3 is associated with "2" The value set of the cell identifier is {0, 1, 2}, and then W (W=3) sequences can be preconfigured or predefined, and the three sequences are associated with different values, for example, sequence 1 is associated with "0", sequence 2 is associated with "1", and sequence 3 is associated with "2" The value set of the cell identifier is {0, 1, 2}, and then W (W=3) sequences can be preconfigured or predefined, and the three sequences are associated with different values, for example, sequence 1 is associated with "0", sequence 2 is associated with "1", and sequence 3 is associated with "2" That is, one sequence can be preconfigured or predefined, and the sequence is the third sequence; in this case, the preconfigured or predefined sequence can not be associated with the cell identifier. Alternatively, W sequences can be preconfigured or predefined, and the third sequence is one of the W sequences; in this case, the preconfigured or predefined sequence can be associated with the cell identifier. As another possible implementation, the first sequence is a preconfigured or predefined sequence, in which case the network device can directly obtain the predefined or preconfigured first sequence and generate the synchronization signal according to the first sequence. Alternatively, W' sequences are preconfigured or predefined (i.e., the synchronization sequence set includes W' sequences), and the W' sequences are obtained from the W sequences, in which case the network device selects one sequence from the W' sequences as the first sequence and generates the synchronization signal according to the first sequence. That is, one sequence can be preconfigured or predefined, and the sequence is the third sequence; in this case, the preconfigured or predefined sequence can not be associated with the cell identifier. Alternatively, W sequences can be preconfigured or predefined, and the third sequence is one of the W sequences; in this case, the preconfigured or predefined sequence can be associated with the cell identifier. (3) The implementation of "the network device generating the synchronization signal according to the first sequence" is described. For example, the synchronization signal can be understood as a time domain sequence. In the case of no oversampling, the number of elements in the time domain sequence is the same as the number of elements in the second sequence, and in the case of oversampling, the number of elements in the time domain sequence is greater than the number of elements in the second sequence. In the embodiments of the present application, the case of oversampling is described, for example, the synchronization signal is denoted as sequence [t(n)], n=0, 1, 2,..., N-1, and N is greater than L. As a possible implementation, the network device performs a discrete fourier transformation (DFT) process, a subcarrier mapping, and an IFFT process on the first sequence to generate the synchronization signal. Optionally, the network device can also perform other possible processes, which are not limited in specific, and it should be noted that the process performed by the network device on the first sequence does not include modulation. For example, the network device performs a DFT process on the first sequence to obtain a second sequence, then maps the second sequence to a plurality of subcarriers, and performs an IFFT process to generate the synchronization signal. In this case, the synchronization signal is a DFT-s-OFDM waveform signal. The first sequence is denoted as [x(n)], and the second sequence is denoted as [y(n)], and the second sequence and the first sequence satisfy: As another possible implementation, the network device performs a subcarrier mapping and an IFFT process on the first sequence to generate the synchronization signal. Optionally, the network device can also perform other possible processes, which are not limited in specific, and it should be noted that the process performed by the network device on the first sequence does not include modulation and a DFT process. For example, the network device maps the first sequence to a plurality of subcarriers and performs an IFFT process to generate the synchronization signal. In this case, the synchronization signal is an OFDM waveform signal. That is, in the embodiments of the present application, the network device can use a DFT-s-OFDM waveform to transmit the synchronization signal, or can also use an OFDM waveform to transmit the synchronization signal according to the prior art. It can be understood that, as described above, the three PSS sequences in NR can correspond to the same recursive formula; and in the embodiments of the present application, when the DFT-s-OFDM waveform is used, if the different cyclic shifts based on the same sequence in the NR protocol are followed to distinguish the different synchronization signals, the three PSS sequences in NR cannot be distinguished. Three similar correlation peaks will appear when time domain detection is performed, which will cause time domain synchronization failure or PCI detection failure. Therefore, the W sequences can correspond to different recursive formulas to facilitate guaranteeing the synchronization performance. It can be understood that if the synchronization signal continues to use the OFDM waveform, the W sequences can correspond to different recursive formulas, or the W sequences can also be obtained according to different cyclic shifts of the same sequence. (4) The ambiguity function of the synchronization signal is described. Due to the moving speed of the terminal device and the frequency offset of the crystal oscillator, the terminal device receives a signal with a large frequency offset, and thus the anti-frequency offset capability of the synchronization signal needs to be evaluated. The synchronization signal refers to the synchronization signal generated by the baseband chip and not yet sent to the radio frequency chip. The anti-frequency offset capability is generally evaluated by the second peak of the ambiguity function. The smaller the second peak of the ambiguity function is, the stronger the anti-frequency offset capability is. In the embodiment of the present application, the normalized second peak of the ambiguity function of the synchronization signal is less than or equal to a second threshold, so as to ensure the anti-frequency offset performance of the synchronization signal. The second threshold can be set according to actual needs, for example, the second threshold is 0.135. The synchronization signal generated by the network device according to the first sequence is denoted as [t(n)], and the expression of the ambiguity function of [t(n)] is: wherein A(f d ,τ) is the ambiguity function of [t(n)], f d is a frequency offset value, τ is a time-domain multipath delay, the value range of τ is [0, N-1], t * (n+τ) is the conjugate of t(n+τ). For example, the main peak of the ambiguity function of [t(n)] is A(0, 0), and A(f d ,τ) ′ =A(f d ,τ) / A(0, 0), A(f d ,τ) ′ is obtained by normalizing A(f d ,τ). S402, the network device sends the synchronization signal; correspondingly, the terminal device receives the corresponding signal. It can be understood that the synchronization signal is generated by the baseband chip of the network device. The network device sending the synchronization signal includes the baseband chip of the network device sending the synchronization signal to the radio frequency chip of the network device. The network device sending the synchronization signal also includes the radio frequency chip of the network device sending the synchronization signal to the terminal device. The transmission power of the synchronization signal can refer to the power used by the radio frequency chip of the network device to send the synchronization signal to the terminal device. In the embodiment of the present application, in order to ensure the normalization of the transmission power, the first sequence can be obtained according to the factor (i.e. ) associated with the third sequence and the transmission power. In this case, the value set of the elements in the first sequence is (Corresponding to the above-mentioned implementation manner 2), the transmission power of the synchronization signal can be a first power, which is predefined or preconfigured. Alternatively, the value set of the elements in the first sequence is {-1, 0, 1}, and the network device can control the transmission power of the synchronization signal, such as the transmission power of the synchronization signal being the first power plus a power offset, and the power offset being equal to S403, the terminal device detects the synchronization signal. Exemplarily, the terminal device acquires the first sequence, and processes the received signal according to the first sequence to detect the synchronization signal; or the terminal device acquires the third sequence, obtains the first sequence according to the third sequence, and processes the received signal according to the first sequence to detect the synchronization signal; or the terminal device processes the received signal according to the sequence in the synchronization sequence set to detect the synchronization signal, such as the synchronization sequence set including W' sequences, and the W' sequences including the first sequence. The specific implementation can refer to the description of “the network device acquires the first sequence” in the foregoing. As described above, the synchronization signal can be a DFT-s-OFDM waveform signal, or can also be an OFDM waveform signal. Next, the specific implementation of “the terminal device detects the synchronization signal” is described respectively for the two cases. (1) The synchronization signal is a DFT-s-OFDM waveform signal. For this case, three possible implementations are described. The first implementation is that the terminal device performs DFT processing on the first sequence to obtain a second sequence, maps the second sequence to a plurality of subcarriers, and performs IFFT processing, and then performs correlation processing on the received signal according to the sequence (referred to as sequence a1, in the case of no oversampling, sequence a1 includes L elements, and in the case of oversampling, sequence a1 includes N elements, N is greater than L, and here, the case of oversampling is taken as an example) after IFFT processing. For example, for the received signal, the terminal device obtains the signal r tmp = [r(i-1), r(i), … r(N+i-1)] when the frequency offset value f d = 0.5*SCS, the signal r tmp corrected for frequency offset is obtained. tmp,1 The terminal device performs inner product on sequence a1 and sequence r tmp,1 , obtains the cross-correlation value c(a1, r tmp ) between sequence a1 and sequence r tmp , and performs normalization to obtain c(a1, r tmp )'. The second implementation is that the terminal device directly oversamples (i.e., element repetition) the first sequence to obtain a sequence a2, and performs correlation processing on the received signal according to the sequence a2. For details, refer to the description of "the terminal device performs correlation processing on the received signal according to the sequence a1". The third implementation is that the terminal device down-samples the received signal to obtain a sequence a3, and performs correlation processing on the sequence a3 according to the first sequence. For example, for the received signal, the terminal device obtains a signal r tmp = [r(i-1), r(i), … r(N+i-1)] by the i-th sliding sampling point, and obtains r tmp by down-sampling r tmp’ , and r tmp’ includes L elements. When the frequency offset value f d = 0.5*SCS, the terminal device obtains r tmp’ by correcting the frequency offset of the signal r tmp’,1 obtained by the i-th sliding sampling point. The terminal device performs inner product on the first sequence and the sequence r tmp’, 1 to obtain a normalized cross-correlation value between the first sequence and the sequence r tmp’, 1. The above three implementations are examples of the first sequence. When there are multiple predefined or preconfigured sequences, the terminal device can traverse multiple sequences. That is, in the above three implementations, the terminal device can traverse multiple sequences, multiple sampling points, and multiple frequency offset values to perform correlation calculation to obtain multiple cross-correlation values. Further, the terminal device determines the sequence (i.e., detects the synchronization signal), the time delay, and the frequency offset value actually transmitted by the network device according to the maximum cross-correlation value in the multiple cross-correlation values. It can be understood that in some scenarios, there can be only one frequency offset value or one sequence, and the specific implementation is not limited. In the embodiments of the present application, on the one hand, since the synchronization signal has timing function, the terminal device needs to perform sliding correlation detection in the time domain, and the synchronization signal adopts the DFT-s-OFDM waveform, which can enable the terminal device to directly perform correlation processing on the received signal in the time domain without first performing DFT processing on the received signal to transform it to the frequency domain for processing, thereby greatly reducing the detection complexity of the synchronization signal. On the other hand, the DFT-s-OFDM waveform can be used to simulate a square wave to ensure the performance of time domain detection. For example, after the first sequence is oversampled (i.e., element repetition) and after the first sequence is processed by the DFT-s-OFDM waveform, it can be found that the positions of high and low levels completely coincide. Therefore, the DFT-s-OFDM waveform can be used to simulate a square wave. It should be understood that the time domain signal generated by the first sequence processed by the DFT-s-OFDM waveform can also be subjected to time domain filtering and other operations to make the final waveform more consistent with the square wave, and the embodiments of the present application do not limit these possible operations. Further, taking the synchronization signal as the PSS as an example, as described above, in the current NR, the m sequence is BPSK modulated to obtain the PSS sequence, and then the network device performs subcarrier mapping and IFFT processing on the PSS sequence to generate the PSS, i.e., the PSS is an OFDM waveform signal; correspondingly, the terminal device detects the PSS according to the PSS sequence. Among them, since the PSS sequence obtained by BPSK modulating the m sequence has an element value set of {1, -1}, the elements in the PSS generated by subcarrier mapping and IFFT processing are all complex elements, resulting in N-1 addition operations and N multiplication operations in each correlation operation. In the embodiments of the present application, the network device performs DFT processing, subcarrier mapping and IFFT processing on the first sequence to generate the PSS, i.e., the PSS is a DFT-s-OFDM waveform signal; correspondingly, the terminal device detects the PSS according to the first sequence. Since the first sequence has ideal autocorrelation, the detection performance of the PSS can be guaranteed; further, since the first sequence includes at least one element with a value of 0, the terminal device can reduce the number of addition operations in each correlation operation when the above-mentioned second implementation and third implementation are adopted; and since the values of the other elements in the first sequence except the 0 element are -1 or 1 (or the values of the other elements are Or Then the terminal device can convert to -1, and convert The conversion into 1) can thus be ignored in each correlation operation in the second and third implementations described above. In the first implementation described above, the terminal device performs DFT processing, subcarrier mapping and IFFT processing on the first sequence, and further quantizes the elements in the final time-domain sequence (i.e., quantizes the elements in the time-domain sequence to 0 / 1 / -1), so that the first implementation can also reduce the number of addition operations and ignore the number of multiplication operations in each correlation operation. That is, the scheme in the embodiments of the present application can reduce the number of addition operations and / or multiplication operations in each correlation operation, thereby reducing the detection complexity of the PSS. For example, referring to Table 1, when the length of the PSS sequence is 121 (assuming no oversampling), the scheme in NR requires 120 addition operations and 121 multiplication operations in each correlation operation; the scheme in the present application requires 80 addition operations and 0 multiplication operations in each correlation operation. Table 1: Complexity Example Since the multiplication operation can be implemented by an adder and a cyclic shift register, the total number of NAND gates is X times the number of additions, where X is the bit quantization bit width, which is generally 16. Therefore, the calculation process of the complexity reduction ratio is as follows: (2) Synchronization signal is an OFDM waveform signal The terminal device maps the first sequence onto a plurality of subcarriers to obtain a frequency-domain sequence. In addition, the terminal device performs DFT processing on the received signal to obtain a frequency-domain signal; for example, for the received signal r = [r(0), r(1), …, r(L'-1)], when the frequency offset value f d = 0.5*SCS, the terminal device corrects the frequency offset of the signal r to obtain a signal r1, and performs DFT processing on the signal r1 to obtain a frequency-domain signal. Further, the terminal device performs conjugate point multiplication on the frequency-domain sequence and the frequency-domain signal, and performs IDFT processing on the sequence after conjugate point multiplication to determine the maximum correlation peak position corresponding to the frequency offset value in the time domain. In this way, after traversing a plurality of frequency offset values, the sequence actually transmitted by the network device (i.e., the synchronization signal is detected), the time delay and the frequency offset value can be determined according to the maximum correlation peak positions corresponding to the plurality of frequency offset values. In the embodiments of the present application, taking the PSS as an example, the network device performs subcarrier mapping and IFFT processing on the first sequence to generate the PSS, i.e., the PSS is an OFDM waveform signal; accordingly, the terminal device detects the PSS according to the first sequence. Since the first sequence includes at least one element with a value of 0, the complexity of the frequency-domain multiplication operation and the complexity of the IDFT can be reduced, thereby reducing the detection complexity of the synchronization signal. For the above embodiments, it can be understood that: (1) In the embodiments of the present application, the terms and / or descriptions in different examples or implementation manners are consistent and can be referred to each other if there is no special description and logical conflict. The technical features in different examples or implementation manners can be combined to form new embodiments according to their inherent logical relationship. In addition, different implementation manners or different examples can refer to or refer to each other. (2) The various numerical numbers involved in the present application are only for the convenience of differentiation and do not limit the scope of the present application. The step numbers of the above various flowcharts are only an example of the execution flow and do not constitute a limitation on the execution order of the steps, that is, the size of each step number does not mean the execution order, and the execution order of each step should be determined according to its function and inherent logic. In addition, the steps shown in each flowchart are not all the steps that must be executed, and some steps can be added or deleted based on each flowchart as needed. The above mainly introduces the scheme provided by the embodiments of the present application from the perspective of the interaction between the first communication device and the second communication device. It can be understood that, in order to realize the above functions, the first communication device and the second communication device can include corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed in the present application, the embodiments of the present application can be realized in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the form of hardware or computer software driven hardware depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application. The embodiments of the present application can divide the functional units of the first communication device and the second communication device according to the above method examples, for example, each functional unit can be divided according to each function, or two or more functions can be integrated into one unit. The integrated unit can be realized in the form of hardware or software functional unit. In the case of integrated units, FIG. 6 shows a possible exemplary block diagram of the device involved in the embodiments of the present application. As shown in FIG. 6, the device 600 can include a processing unit 602 and a communication unit 603. The processing unit 602 is used to control and manage the actions of the device 600. The communication unit 603 is used to support the communication of the device 600 with other devices. Optionally, the communication unit 603, also known as the transceiver unit, can include a receiving unit and / or a sending unit for performing receiving and sending operations, respectively. The device 600 can also include a storage unit 601 for storing the program code and / or data of the device 600. (1) The apparatus 600 can be the first communication apparatus in the above embodiments. The processing unit 602 can enable the apparatus 600 to perform the actions of the first communication apparatus in the above method embodiments. Alternatively, the processing unit 602 mainly performs the internal actions of the first communication apparatus in the method embodiments, and the communication unit 603 can enable the apparatus 600 to communicate with other devices. For example, in an embodiment, the processing unit 602 is configured to generate a synchronization signal according to a first sequence; and the communication unit 603 is configured to transmit the synchronization signal; wherein the first sequence is ideal autocorrelation, and the value set of elements of the first sequence is {-A, 0, A}, and A is a constant. In a possible design, the processing unit 602 is specifically configured to perform DFT processing on the first sequence to obtain a second sequence; and map the second sequence onto a plurality of subcarriers and perform IFFT processing to generate the synchronization signal; wherein the first sequence is denoted as [x(n)], the second sequence is denoted as [y(n)], n=0, 1, 2, …, L-1, and the second sequence and the first sequence satisfy: In a possible design, the processing unit 602 is specifically configured to map the first sequence onto a plurality of subcarriers and perform IFFT processing to generate the synchronization signal. In a possible design, A=1. In a possible design, the first sequence is obtained based on a third sequence, and the value set of elements of the third sequence is {0, 1, 2}; the first sequence is denoted as [x(n)], the third sequence is denoted as [s(n)], and the first sequence and the third sequence satisfy: In a possible design, the transmission power of the synchronization signal is a first power plus a power offset, and the power offset is equal to L represents the length of the first sequence, and m represents the number of elements with a value of 0 in the first sequence; wherein the first power is predefined or preconfigured. In a possible design, L represents the length of the first sequence, and m represents the number of elements with a value of 0 in the first sequence. In one possible design, the first sequence is derived based on a third sequence, and a set of values of elements in the third sequence is {0, 1, 2}; the first sequence is denoted as [x(n)], and the third sequence is denoted as [s(n)], where the first sequence and the third sequence satisfy: In one possible design, the transmission power of the synchronization signal is a first power, and the first power is predefined or preconfigured. In one possible design, the first sequence is derived based on a third sequence, and the third sequence is one of W sequences, where the W sequences are derived based on W recursive formulas; and a cross-correlation value between the W sequences is less than or equal to a first threshold, and W is an integer greater than 1. In one possible design, the W recursive formulas include any of the following: s(n+5) = (2s(n+2) + 2s(n+1) + s(n)) mod 3; s(n+5) = (2s(n+3) + 2s(n+2) + s(n+1) + s(n)) mod 3; s(n+5) = (2s(n+4) + 2s(n+1) + s(n)) mod 3. In one possible design, a normalized secondary peak of a ambiguity function of the synchronization signal is less than or equal to a second threshold. (2) The apparatus 600 can be the second communication apparatus in the above embodiments. The processing unit 602 can enable the apparatus 600 to perform the actions of the second communication apparatus in the above method embodiments. Alternatively, the processing unit 602 mainly performs the internal actions of the second communication apparatus in the method embodiments, and the communication unit 603 can enable the apparatus 600 to communicate with other devices. For example, in one embodiment, the processing unit 602 is configured to: detect a synchronization signal, where the synchronization signal is a signal derived based on the first sequence, and the first sequence has ideal autocorrelation, and a set of values of elements in the first sequence is {-A, 0, A}, where A is a constant. In one possible design, the processing unit 602 is specifically configured to: obtain the first sequence, and process a received signal based on the first sequence to detect the synchronization signal; or obtain a third sequence, derive the first sequence based on the third sequence, and process the received signal based on the first sequence to detect the synchronization signal; or process the received signal based on a sequence in a synchronization sequence set to detect the synchronization signal, where the sequence in the synchronization sequence set includes the first sequence. In one possible design, the processing unit 602 is configured to perform a discrete Fourier transform (DFT) on the first sequence to obtain a second sequence, map the second sequence onto a plurality of subcarriers, and perform an inverse fast Fourier transform (IFFT) on the mapped second sequence, and perform correlation on the received signal based on the IFFT-processed sequence. The first sequence is denoted as [x(n)], the second sequence is denoted as [y(n)], n = 0, 1, 2,..., L-1, and the second sequence and the first sequence satisfy: In one possible design, the processing unit 602 is configured to perform oversampling on the first sequence, perform correlation on the received signal based on the oversampled sequence, or perform downsampling on the received signal, and perform correlation on the downsampled signal based on the first sequence. In one possible design, the processing unit 602 is configured to map the first sequence onto a plurality of subcarriers to obtain a frequency-domain sequence, perform DFT on the received signal to obtain a frequency-domain signal, perform conjugate point multiplication on the frequency-domain sequence and the frequency-domain signal, and perform inverse discrete Fourier transform (IDFT) on the conjugate point multiplied sequence. In one possible design, A = 1. In one possible design, the first sequence is obtained based on a third sequence, and the third sequence has a value set of {0, 1, 2} for elements in the third sequence. The first sequence is denoted as [x(n)], the third sequence is denoted as [s(n)], and the first sequence and the third sequence satisfy: In one possible design, L denotes a length of the first sequence, and m denotes a number of elements with a value of 0 in the first sequence. In one possible design, the first sequence is obtained based on a third sequence, and the third sequence has a value set of {0, 1, 2} for elements in the third sequence. The first sequence is denoted as [x(n)], the third sequence is denoted as [s(n)], and the first sequence and the third sequence satisfy: In one possible design, the first sequence is obtained based on a third sequence, and the third sequence is one of W sequences, and the W sequences are obtained based on W recursive formulas. The W sequences have a cross-correlation value less than or equal to a first threshold, and W is an integer greater than 1. In one possible design, the W recursive formulas include any of the following: s(n+5) = (2s(n+2) + 2s(n+1) + s(n)) mod 3; s(n+5) = (2s(n+3) + 2s(n+2) + s(n+1) + s(n)) mod 3; s(n+5) = (2s(n+4) + 2s(n+1) + s(n)) mod 3. In a possible design, a normalized secondary peak of the ambiguity function of the synchronization signal is less than or equal to a second threshold. It should be understood that the division of units in the above apparatus is only a logical function division, and all or part of the units can be integrated into one physical entity, or can be physically separated. The units in the apparatus can all be implemented in the form of software invoked by a processing element; or all be implemented in the form of hardware; or some units are implemented in the form of software invoked by a processing element, and some units are implemented in the form of hardware. For example, each unit can be a separately established processing element, or can be integrated into a chip of the apparatus, and in addition, can be stored in the form of a program in a memory, and the function of the unit is invoked and executed by a processing element of the apparatus. In addition, all or part of the units can be integrated together, or can be independently implemented. The processing element mentioned herein can be a processor, which can be an integrated circuit with signal processing capability. In the implementation process, the operations of the above method or the above units can be implemented by integrated logic circuits of hardware in the processing element, or in the form of software invoked by the processing element. In one example, the units in any of the above apparatuses can be one or more integrated circuits configured to implement the above method, for example, one or more application specific integrated circuits (ASICs), or one or more digital signal processors (DSPs), or one or more field programmable gate arrays (FPGAs), or a combination of at least two of these integrated circuit forms. For another example, when the units in the apparatus can be implemented in the form of a program invoked by a processing element, the processing element can be a processor, such as a general purpose central processing unit (CPU), or other processors that can invoke programs. For another example, the units can be integrated together, and implemented in the form of SoC. The above receiving unit is an interface circuit of the apparatus for receiving signals from other apparatuses. For example, when the apparatus is implemented in the form of a chip, the receiving unit is an interface circuit of the chip for receiving signals from other chips or apparatuses. The above sending unit is an interface circuit of the apparatus for sending signals to other apparatuses. For example, when the apparatus is implemented in the form of a chip, the sending unit is an interface circuit of the chip for sending signals to other chips or apparatuses. Based on the same technical concept, the embodiments of the present application further provide a communication apparatus for implementing the functions of the first communication apparatus or the second communication apparatus in the above embodiments. As shown in FIG. 7, the apparatus can be a communication device or a chip in a communication device. The apparatus includes a processor 701 and a communication interface 702, and optionally, a memory 703. FIG. 7 only shows the main components of the communication apparatus. In addition to the processor 701 and the communication interface 702, the communication apparatus can further include the memory 703 and an input / output device (not shown in the figure). The processor 701 is configured to execute the program code stored in the memory 703, and specifically, to execute the actions of the processing unit 602. Details are not described herein again. The communication interface 702 is specifically configured to execute the actions of the communication unit 603. Details are not described herein again. The processor 701 can be a CPU, or a digital processing unit, etc. The processor 701 can be configured to process communication protocols and communication data, control the whole communication apparatus, execute software programs, process data of the software programs, such as but not limited to, baseband related processing. The communication interface 702 can be configured to transceive signals, such as but not limited to, radio frequency signals. The above devices can be respectively arranged on independent chips, or at least partially or entirely arranged on the same chip. For example, the processor 701 can be further divided into an analog baseband processor and a digital baseband processor. The analog baseband processor can be integrated on the same chip as the transceiver, and the digital baseband processor can be arranged on an independent chip. With the continuous development of integrated circuit technology, more and more devices can be integrated on the same chip. For example, the digital baseband processor can be integrated on the same chip as various application processors, such as but not limited to, graphic processors, multimedia processors, etc. Such a chip can be called a system on chip. Whether to arrange the devices independently on different chips or to integrate them on one or more chips often depends on the specific needs of product design. The embodiments of the present application do not limit the specific implementation forms of the above devices. The communication interface 702 can be a transceiver, an interface circuit such as a transceiver circuit, a transceiver chip, or the like. Optionally, the communication interface 702 can include a radio frequency circuit and an antenna, where the radio frequency circuit is mainly used for conversion between a baseband signal and a radio frequency signal and processing of the radio frequency signal. The antenna is mainly used for transmitting and receiving radio frequency signals in the form of electromagnetic waves. Input and output devices, such as a touch screen, a display screen, a keyboard, and the like, are mainly used for receiving user input data and outputting data to the user. The memory 703 is used to store programs executed by the processor 701. The memory 703 can be a non-volatile memory such as a hard disk drive (HDD) or a solid-state drive (SSD), or a volatile memory such as a random-access memory (RAM). The memory 703 can be any other medium capable of carrying or storing desired program codes in the form of instructions or data structures and capable of being accessed by a computer, but is not limited thereto. When the communication device is powered on, the processor 701 can read the software program in the memory 703, interpret and execute the instructions of the software program, and process the data of the software program. When data needs to be transmitted wirelessly, the processor 701 performs baseband processing on the data to be transmitted, and outputs the baseband signal to the radio frequency circuit. The radio frequency circuit performs radio frequency processing on the baseband signal, and transmits the radio frequency signal in the form of electromagnetic waves through the antenna. When data is transmitted to the communication device, the radio frequency circuit receives the radio frequency signal through the antenna, converts the radio frequency signal into a baseband signal, and outputs the baseband signal to the processor 701. The processor 701 converts the baseband signal into data and processes the data. In another implementation, the radio frequency circuit and the antenna can be arranged independently of the processor performing baseband processing, for example, in a distributed scenario, the radio frequency circuit and the antenna can be arranged remotely from the communication device. The specific connection medium between the communication interface 702, the processor 701, and the memory 703 in the embodiments of the present application is not limited. In FIG. 7, the memory 703, the processor 701, and the communication interface 702 are connected through a bus 704, which is represented by a thick line in FIG. 7. The connection mode between other components is only illustrative and is not limited. The bus can be divided into an address bus, a data bus, a control bus, and the like. For convenience of representation, only one thick line is used in FIG. 7, but it does not mean that there is only one bus or only one type of bus. Optionally, the above-mentioned communication device can be an independent device or can be part of a larger device. For example, the communication device can be: (1) an independent integrated circuit (IC), or chip, or chip system or subsystem; (2) a set of one or more ICs that can optionally also include storage for data, instructions, etc. (3) an application specific integrated circuit (ASIC), such as a modem; (4) a module that can be embedded within other devices; (5) a receiver, a smart terminal, a wireless device, a handset, a mobile unit, a car device, a cloud device, an artificial intelligence device, etc. (6) and / or the like. In the embodiments of the present application, "multiple" can mean two or more than two. In view of this, "multiple" in the embodiments of the present application can also be understood as "at least two". "At least one" can be understood as one or more, for example, as one, two or more. For example, "including at least one" means including one, two or more, for example, including at least one of A, B and C, and the included can be A, B, C, A and B, A and C, B and C, or A, B and C. "And / or" describes the association relationship of the associated objects, and specifically can exist in three relationships, for example, A and / or B can represent: A exists alone, A and B exist together, and B exists alone. In addition, the character " / ", if not specially stated, generally represents that the associated objects before and after are in an "or" relationship. In addition, the terms "system" and "network" in the embodiments of the present application can be used interchangeably, and "according to" and "based on" can be used interchangeably. The ordinal numbers "first", "second" and the like mentioned in the embodiments of the present application are generally used to distinguish different objects, and are not used to limit the order, time sequence, priority or importance of multiple objects. For example, the first communication device and the second communication device in the embodiments of the present application are used to distinguish two communication devices, and do not limit the priority or importance of the two communication devices. Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer usable program code. The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks or in combination with the flowchart block or blocks. These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart block or blocks. The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks or in combination with the flowchart block or blocks. These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart block or blocks. The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks or in combination with the flowchart block or blocks. These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart block or blocks.

Claims

1. A communication method characterized by comprising: The method comprises: generating a synchronization signal according to a first sequence; sending the synchronization signal; wherein the first sequence is ideally autocorrelated, and a value set of elements of the first sequence is {-A, 0, A}, A being a constant.

2. The method of claim 1, wherein, The method comprises: generating a synchronization signal according to a first sequence; performing discrete Fourier transform (DFT) processing on the first sequence to obtain a second sequence; wherein the first sequence is denoted as [x(n)], the second sequence is denoted as [y(n)], n = 0, 1, 2,..., L-1, the second sequence and the first sequence satisfy:

3. The method of claim 1, wherein, mapping the second sequence onto a plurality of subcarriers and performing inverse fast Fourier transform (IFFT) processing to generate the synchronization signal; The method comprises:

4. The method according to any one of claims 1 to 3, characterized in that, A＝1。 5. The method of claim 4, wherein, mapping the first sequence onto a plurality of subcarriers and performing IFFT processing to generate the synchronization signal. The first sequence is denoted as [x(n)], and the third sequence is denoted as [s(n)], the first sequence and the third sequence satisfy:

6. The method according to claim 4 or 5, characterized in that, The transmission power of the synchronization signal is a first power plus a power offset, and the power offset is equal to L represents a length of the first sequence, and m represents a number of elements with a value of 0 in the first sequence; wherein the first power is predefined or preconfigured.

7. The method according to any one of claims 1 to 3, characterized in that, L denotes the length of the first sequence, and m denotes the number of elements with value 0 in the first sequence.

8. The method of claim 7, wherein, The first sequence is obtained based on a third sequence, and a value set of elements of the third sequence is {0, 1, 2}; The first sequence is denoted as [x(n)], and the third sequence is denoted as [s(n)], the first sequence and the third sequence satisfy:

9. The method according to claim 7 or 8, characterized in that, The first sequence is obtained based on a third sequence, and a value set of elements of the third sequence is {0, 1, 2}; 10. The method according to any one of claims 1 to 9, characterized in that, The sending power of the synchronization signal is a first power, and the first power is predefined or preconfigured. The first sequence is obtained based on a third sequence, and the third sequence is one of W sequences, and the W sequences are obtained according to W recursive formulas; 11. The method of claim 10, wherein, wherein the cross-correlation values between the W sequences are less than or equal to a first threshold value, and W is an integer greater than 1.

12. The method according to any one of claims 1 to 11, characterized in that, The W recursive formulas include any of the following multiple terms: s(n+5) = (2s(n+2) + 2s(n+1) + s(n)) mod 3; s(n+5) = (2s(n+3) + 2s(n+2) + s(n+1) + s(n)) mod 3; s(n+5) = (2s(n+4) + 2s(n+1) + s(n)) mod 3.

13. A method of communication, comprising: The normalized second peak of the ambiguity function of the synchronization signal is less than or equal to a second threshold value. The method comprises: detecting a synchronization signal, the synchronization signal being a signal obtained according to the first sequence; 14. The method of claim 13, wherein, wherein the first sequence is ideally autocorrelated, and a value set of elements of the first sequence is {-A, 0, A}, A being a constant. The method comprises: obtaining the first sequence, and processing the received signal according to the first sequence to detect the synchronization signal; or obtaining a third sequence, obtaining the first sequence according to the third sequence, and processing the received signal according to the first sequence to detect the synchronization signal; or 15. The method of claim 14, wherein, processing the received signal according to a sequence in a synchronization sequence set to detect the synchronization signal, the sequence in the synchronization sequence set including the first sequence. The method comprises: performing discrete Fourier transform (DFT) processing on the first sequence to obtain a second sequence; mapping the second sequence onto a plurality of subcarriers and performing inverse fast Fourier transform (IFFT) processing; wherein the first sequence is denoted as [x(n)], the second sequence is denoted as [y(n)], n = 0, 1, 2,..., L-1, the second sequence and the first sequence satisfy:

16. The method of claim 14, wherein, performing correlation processing on the received signal according to the sequence after IFFT processing; The method comprises: performing oversampling on the first sequence, and performing correlation processing on the received signal according to the oversampled sequence; or Downsample the received signal, and perform correlation processing on the downsampled signal according to the first sequence.

17. The method of claim 14, wherein, Processing the received signal according to the first sequence comprises: Mapping the first sequence onto a plurality of subcarriers to obtain a frequency domain sequence; Performing DFT processing on the received signal to obtain a frequency domain signal; Conjugate point multiplication is performed on the frequency domain sequence and the frequency domain signal, and inverse discrete Fourier transform (IDFT) processing is performed on the conjugate point multiplied sequence.

18. The method according to any one of claims 13 to 17, characterized in that, A＝1。 19. The method of claim 18, wherein, The first sequence is obtained based on a third sequence, and a value set of elements in the third sequence is {0, 1, 2}; The first sequence is denoted as [x(n)], and the third sequence is denoted as [s(n)], the first sequence and the third sequence satisfy:

20. The method of any one of claims 13-17, wherein, L denotes the length of the first sequence, and m denotes the number of elements with value 0 in the first sequence.

21. The method of claim 20, wherein, The first sequence is obtained based on a third sequence, and a value set of elements in the third sequence is {0, 1, 2}; The first sequence is denoted as [x(n)], and the third sequence is denoted as [s(n)], the first sequence and the third sequence satisfy:

22. The method of any one of claims 13-21, wherein, The first sequence is obtained based on a third sequence, and the third sequence is one of W sequences, and the W sequences are obtained according to W recursive formulas. The cross-correlation values between the W sequences are less than or equal to a first threshold value, and W is an integer greater than 1.

23. The method of claim 22, wherein, The W recursive formulas include any of the following terms: s(n+5)=(2s(n+2)+2s(n+1)+s(n))mod3; s(n+5)=(2s(n+3)+2s(n+2)+s(n+1)+s(n))mod3; s(n+5)=(2s(n+4)+2s(n+1)+s(n))mod3.

24. The method of any one of claims 13-23, wherein, The normalized secondary peak of the ambiguity function of the synchronization signal is less than or equal to a second threshold value.

25. A communications device, characterized by The communication system comprises a first communication device and a second communication device, the first communication device is configured to perform the method of any one of claims 1 to 12, and the second communication device is configured to perform the method of any one of claims 13 to 24.

26. A communications device, characterized by The storage medium stores a computer program, and when part or all of the computer program is executed by a computer, the method of any one of claims 1 to 24 is performed.

27. A communication system, characterized by When the computer reads and executes the computer program product, the method of any one of claims 1 to 24 is performed.

28. A computer-readable storage medium, characterized in that, ​ 29. A computer program product, characterised in that, ​

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