Method for producing a contact structure in particular for a back contact solar cell

Abstract

The invention relates to a method for producing contact structures (2), in particular for a solar cell (1), comprising at least the following method steps: (a) providing a silicon substrate (3) having first and second subregions (7, 17), in each case on a back side (9) of the silicon substrate; (b) creating a back-side layer stack (19) covering the first and second subregions, the back-side layer stack having a silicon oxide-containing back-side passivation layer (21) and a doped polycrystalline silicon layer (23); (c) carrying out an annealing step by introducing the silicon substrate into an annealing atmosphere at temperatures above 700°C, oxygen being added to the annealing atmosphere at least temporarily such that a thin silicon oxide layer (25) is formed adjacent to the polycrystalline silicon layer; (d) removing the thin silicon oxide layer by laser ablation in the first subregions; and (e) carrying out a selective etching step by introducing the silicon substrate into a highly selective etching substance and thereby removing the polycrystalline silicon layer in the first subregions. As an alternative to method steps (c) and (d), the polycrystalline silicon layer can also be locally selectively oxidized in the second subregions by irradiating the silicon substrate accommodated in an oxygen-containing atmosphere with laser light in order locally to form the thin silicon oxide layer there by laser oxidation. The invention further relates to a method for producing a solar cell (1) as a back-contact solar cell, wherein the first-mentioned method is used to produce contact structures (2).

Description

[0001] METHOD FOR MANUFACTURING A CONTACT STRUCTURE, IN PARTICULAR FOR A

[0002] BACK-CONTACT SOLAR CELL

[0003] AREA OF INVENTION

[0004] The present invention relates to a method for manufacturing a contact structure, particularly for a solar cell. Furthermore, the present invention relates to a method for manufacturing a solar cell, in particular a solar cell with back-side contacts.

[0005] TECHNICAL BACKGROUND

[0006] Solar cells serve to convert light, especially that emitted by the sun, into electrical energy. Such solar cells are also called photovoltaic cells.

[0007] Numerous solar cell concepts and manufacturing processes exist. The fundamental objectives are typically to achieve high efficiency while simultaneously ensuring the simplest and most cost-effective manufacturing process possible. The efficiency achievable with a solar cell concept, both theoretically and ultimately in practice, is influenced by a multitude of factors. These include, for example, the properties of various materials that may be used, both before, during, and after processing; the geometric and / or functional arrangement of different material layers relative to one another; and so on. Furthermore, a wide range of manufacturing factors must be considered.For example, as few consumables as possible should be required, especially few costly consumables such as expensive screen printing pastes and / or few processing substances that are expensive or difficult to procure or dispose of. Furthermore, equipment used in manufacturing should be inexpensive, easy to use and maintain, and reliable, etc.

[0008] Due to the enormous number of possible materials, equipment, processing sequences, etc., and the resulting interactions, potential synergy effects, or degeneration effects, etc., the development and optimization of solar cell concepts and corresponding manufacturing processes is regularly extremely complex.

[0009] Solar cell concepts have been and are being developed that are intended to be superior to conventional concepts such as the PERC solar cell concept, which has been implemented industrially for many years, in terms of achievable efficiencies and / or usable manufacturing possibilities.

[0010] This includes, among other things, solar cell concepts that employ special contact structures, sometimes referred to as charge carrier-selective contact structures or passivating contact structures. Such contact structures are characterized, among other things, by being electrically permeable to one type of charge carrier (such as negative charge carriers, i.e., electrons) and electrically blocking to the opposite type of charge carrier (such as positive charge carriers, i.e., holes).This makes it possible to extract charge carriers of the first type with low electrical resistance from a substrate adjacent to the contact structure using the contact structure, whereas charge carriers of the second type are blocked and the contact structure thus acts as an electrical insulator for them and accordingly acts as a very good electrical passivator on the surface of the adjacent substrate.

[0011] Such contact structures can be created by having a very thin dielectric layer and an adjacent doped semiconductor layer, whereby the resulting layer stack is deposited adjacent to a substrate from which the charge carriers are to be extracted. A silicon oxide layer, for example, can act as the dielectric layer. The dielectric layer should be very thin, i.e., designed as a thin film, so that charge carriers can pass through it, for example, due to tunneling effects and / or along so-called pinholes that can extend through the thin film. A doped silicon layer, in particular a doped polycrystalline silicon layer (hereinafter sometimes also referred to as a poly-Si layer), can serve as the adjacent semiconductor layer.Depending on which type of charge carrier is to be selectively extracted with the contact structure, the polycrystalline silicon layer can be either p-type or n-type doped.

[0012] Solar cell concepts that employ such charge carrier-selective, passivating contact structures are sometimes referred to as TOPCon solar cell concepts (Tunneling Oxide Passivated Contact) or POLO solar cell concepts (POLysilicon on Oxide). TOPCon-like or POLO-like contact structures can be located on both opposite surfaces of a semiconductor substrate. Alternatively, contact structures for extracting electrons and contact structures for extracting holes can each be arranged on the back side of the semiconductor substrate facing away from the sun during operation. The latter concepts are also referred to as back-contact solar cells or IBC solar cells (Interdigitated Back Contact). Examples of such solar cell concepts, as well as details on their structural and manufacturing possibilities, have been presented in numerous publications. Examples include:

[0013] - Dullweber et al.: „TOWARDS COST-EFFECTIVE HIGH-EFFICIENCY POLO IBC SOLAR CELLS WITH MINIMAL CONVERSION INVEST FOR EXISTING PERC+ PRODUCTION LINES", 8th World Conference on Photovoltaic Energy Conversion (2022), p. 35

[0014] - Peibst et al.: "On the chances and challenges of combining electron-collecting nPOLO and hole-collecting Al-p+ contacts in highly efficient p-type c-Si solar cells", Progress in Photovoltaics, Volume 31, Issue 4, Special Issue: Passivating Contacts Based Silicon Solar Cells; April 2023; Pages 327-340; https: / / doi.org / 10.1002 / pip.3545;

[0015] - Wang et al.: "Development of TOPCon tunnel-IBC solar cells with screen-printed fire- through contacts by laser patterning", Solar Energy Materials and Solar Cells, Volume 220, January 2021 , 110834; https: / / doi.Org / 10.1016 / j.solmat.2020.110834;

[0016] - EP 2 297 788 B1

[0017] - DE 10 2021 133 039 A1

[0018] SUMMARY OF THE INVENTION AND FORM OF EXECUTION

[0019] There may be a need for an alternative and, in particular, improved method for manufacturing contact structures, especially for solar cells.

[0020] In particular, there may be a need to be able to manufacture charge carrier-selective, passivating contact structures advantageously, i.e., cost-effectively, with minimal equipment, using small quantities of consumables, reliably, etc. Furthermore, there may be a need for a method for manufacturing solar cells equipped with such contact structures.

[0021] The aforementioned needs can be at least partially met by a method according to one of the independent claims of the present application. Advantageous embodiments are specified in the dependent claims, the following description, and the figures. According to a first aspect of the present invention, a method for manufacturing a contact structure, particularly for a solar cell, is described. The method comprises at least the following steps, preferably in the order shown:

[0022] (a) Providing a silicon substrate with first sub-areas and second sub-areas each on a back side of the silicon substrate;

[0023] (b) Forming a back-layer stack covering the first and second sub-regions, the back-layer stack comprising at least a silicon oxide-containing back-layer passivation layer and a doped polycrystalline silicon layer; (c+d) Forming a silicon oxide thin film covering central regions of the second sub-regions and, optionally, peripheral regions of the second sub-regions, and not covering the first sub-regions, by performing a combination of steps (cl) and (dl) defined below, or alternatively by performing a combination of steps (c2) and (d2) defined below:

[0024] (cl) Performing an anneal step by introducing the silicon substrate with the back-layer stack into an anneal atmosphere at temperatures above 700°C, wherein oxygen is added to the anneal atmosphere at least temporarily, so that a silicon oxide thin film forms adjacent to the polycrystalline silicon layer during the anneal step, and (dl) removing the silicon oxide thin film by laser ablation in the first sub-regions and, optionally, in the edge regions of the second sub-regions; or (c2) Performing an anneal step by introducing the silicon substrate with the back-layer stack into an anneal atmosphere at temperatures above 700°C, and

[0025] (d2) Performing a local oxidation step on the polycrystalline silicon layer by locally irradiating the central regions and, optionally, the peripheral regions of the silicon substrate, which is embedded in an oxygen-containing atmosphere, with laser light such that a silicon oxide thin film is formed in the central regions and, optionally, the peripheral regions as a result of the oxidation step; (e) Performing a selective etching step by immersing the silicon substrate in a highly selective etching agent which has a high etch rate for silicon and a low etch rate for silicon oxide, and thereby removing the polycrystalline silicon layer in the first subregions and, optionally, in the peripheral regions of the second subregions.

[0026] According to a second aspect of the present invention, a method for manufacturing a solar cell is described, which comprises at least the following steps, preferably in the specified order:

[0027] (a) Providing a silicon substrate with first sub-areas and second sub-areas each on a back side of the silicon substrate;

[0028] (b) Producing a first backside layer stack and a first silicon oxide thin film in the first sub-areas, wherein the first backside layer stack comprises at least a first silicon oxide-containing backside passivation layer and a first polycrystalline silicon layer of a first doping type, wherein the back side of the silicon substrate in second sub-areas adjacent to the first sub-areas is free of the first backside layer stack;

[0029] (c) Producing a second backside layer stack covering the first and second sub-areas, the second backside layer stack comprising at least a second silicon oxide-containing backside passivation layer and a second polycrystalline silicon layer of a second doping type opposite to the first doping type;

[0030] (d+e) Forming a second silicon oxide thin film which covers central regions of the second subregions and, optionally, peripheral regions of the second subregions and which does not cover the first subregions, by performing a combination of the steps (dl ) and (ei ) defined below or alternatively by performing a combination of the steps (d2) and (e2) defined below:

[0031] (dl) Performing an anneal step by introducing the silicon substrate provided with the second back-side layer stack into an anneal atmosphere at temperatures above 700°C, wherein oxygen is added to the anneal atmosphere at least temporarily, so that during the anneal step a second silicon oxide thin film is formed adjacent to the second polycrystalline silicon layer, and

[0032] (ei) Removal of the second silicon oxide thin layer by laser ablation in the first sub-regions and, optionally, in edge regions of the second sub-regions; or (d2) Performing an anneal step by introducing the silicon substrate provided with the second back-side layer stack into an anneal atmosphere at temperatures above 700°C, and

[0033] (e2) Carrying out a local oxidation step on the second polycrystalline silicon layer by locally irradiating the central areas and, optionally, the edge areas of the silicon substrate taken up in an oxygen-containing atmosphere with laser light such that a second silicon oxide thin film is formed by the oxidation step in the central areas and, optionally, the edge areas;

[0034] (f) Performing a selective etching step by immersing the silicon substrate in a highly selective etching agent which has a high etch rate for silicon and a low etch rate for silicon oxide, thereby removing the second polycrystalline silicon layer in the first sub-regions and, optionally, in the edge regions of the second sub-regions; and

[0035] (g) Applying electrical first contacts to the first polycrystalline silicon layer in the first sub-areas and electrical second contacts to the second polycrystalline silicon layer in the second sub-areas.

[0036] In the introduction, the basic ideas for embodiments of the invention described herein will be briefly explained, whereby this explanation is to be interpreted as merely a rough summary and not as limiting the invention: The present invention relates in particular to a method according to an embodiment of the first aspect of the invention, by means of which a small-area contact structure or a plurality of small-area contact structures can be formed on a surface of a silicon substrate that is large-area in comparison.

[0037] The contact structure is formed with a layer stack comprising at least a thin silicon oxide-containing passivation layer and a significantly thicker doped polycrystalline silicon layer. To form the contact structure(s), the layer stack is first produced over a large area on the surface of the silicon substrate, covering adjacent areas, which are subsequently referred to as the first and second sub-regions.

[0038] The silicon substrate with the layer stack applied to it is then subjected to an annealing step, in which, in particular, the doped polycrystalline silicon layer deposited during the formation of the layer stack is exposed to high temperatures of over 700 °C for a process duration in order to anneal it, i.e., in particular to repair damage or defects created during deposition and to condition the SiÜ2 interface.

[0039] This annealing step, generally used in the production of poly-Si layers for contact structures, is carried out in a first embodiment of the proposed method in such a way that oxygen is added, at least temporarily, to the hot atmosphere surrounding the substrate, or that oxygen contained in this atmosphere is specifically used to oxidize the surface of the poly-Si layer. This results in the formation of a silicon oxide thin film, usually only a few nanometers thick, adjacent to the polycrystalline silicon layer during the annealing step.

[0040] The silicon oxide thin film formed in this way is then used to locally structure the underlying polycrystalline silicon layer or the entire layer stack through subsequent process steps, i.e., to selectively remove parts of it. According to the first embodiment of the proposed method, the silicon oxide thin film is removed by laser ablation in the first sub-regions and optionally in laterally adjacent edge regions of the second sub-regions, whereas the silicon oxide thin film remains in the second sub-regions, at least in central areas within their edge regions. In other words, the silicon oxide thin film co-generated during the annealing step is opened in the first sub-regions but remains in the second sub-regions or at least in an inner sub-area of ​​these second sub-regions.The remaining areas of the silicon oxide thin film after laser ablation are used as a kind of etching mask during a subsequent selective etching step.

[0041] According to an alternative second embodiment of the proposed method, a so-called laser oxidation can be performed to generate a local thin oxide layer. In this process, the annealing step is carried out in an inert atmosphere such as nitrogen. If necessary, a thin, full-surface oxide layer formed during this step can then be completely removed by RF etching. Subsequently, the poly-Si layer is locally illuminated and briefly heated with a laser in the central regions of the second sub-areas to be oxidized, as well as in any adjacent peripheral regions of the second sub-areas, using an oxygen-containing atmosphere such as air, O2, or O3. This allows for the local generation of an oxide layer approximately 10 nm thick, which can then serve as a local silicon thin film and an etching mask.

[0042] To account for the typically thin silicon oxide layer in the two aforementioned embodiments of the process, a highly selective etching agent, such as a potassium hydroxide-based etching solution, is used in the selective etching step. Additives may be added to enhance the selectivity of the etching solution. This ensures that, on the one hand, the areas of the poly-Si layer located in the initial sections previously freed from the silicon oxide layer are etched away as completely as possible by the highly corrosive silicon-corrosive agent, while on the other hand, the areas of the poly-Si layer remaining covered with the silicon oxide layer after laser ablation are protected from the etching effect of the agent, which, due to its highly selective etching properties, only minimally attacks the silicon oxide.

[0043] In the first embodiment of the proposed method, a spatially precisely defined, small-area contact structure with a TOPCon or POLO layer stack, or a spatially precisely defined pattern of many such small-area contact structures, can be generated on the silicon substrate by simultaneously producing the silicon oxide thin film during the annealing step, the subsequent local partial removal of the silicon oxide thin film by laser ablation in the first sub-areas, and the subsequent highly selective etching of the polycrystalline silicon layer in the exposed first sub-areas, while simultaneously masking this silicon layer with the remaining surface area of ​​the silicon oxide thin film in the second sub-areas. The same applies accordingly to the second embodiment of the proposed method, in which the silicon oxide thin film serving as the etching mask is produced by laser oxidation.

[0044] A process sequence proposed herein for manufacturing such a contact structure or pattern, as well as the individual process steps to be carried out, can be implemented simply, cost-effectively, reliably and / or on an industrial scale.

[0045] It should be noted that although the method according to the first aspect of the invention is predominantly described herein in relation to the manufacture of contact structures for solar cells, it can also be used to manufacture contact structures on other semiconductor devices.

[0046] According to one embodiment of the second aspect of the invention, a method for manufacturing an entire solar cell is described. This method includes, in particular, the process steps already used in embodiments of the first aspect of the invention. Process steps (a) to (e) of the method according to the first aspect of the invention correspond to process steps (a), (c) to (f) of the method according to the second aspect of the invention.

[0047] Furthermore, the manufacturing of the solar cell according to the second aspect of the invention includes further process steps (b) and (g).

[0048] The additional process step (b) includes, in particular, the production of a further layer stack consisting of a silicon oxide-containing passivation layer, a polycrystalline silicon layer, and a silicon oxide thin film covering the latter. This layer stack is spatially structured such that it covers the silicon substrate only in the first sub-regions, leaving the second sub-regions uncovered. Accordingly, in the solar cell produced overall, the first sub-regions are covered by this further layer stack, which is preferably produced first in the method proposed herein and is deposited on the back side of the silicon substrate, and is therefore referred to herein as the "first back-side layer stack". The second sub-regions, on the other hand, are covered by the layer stack produced using the same process steps as those already employed for the first aspect of the invention.Since this layer stack is preferably produced second in the method proposed herein and is also deposited on the back side of the silicon substrate, it is referred to herein as the "second backside layer stack". Analogously to the backside layer stacks, the passivation layers and polycrystalline silicon layers used therein are also referred to as the first and second silicon oxide-containing backside passivation layers, respectively, and as the first and second polycrystalline silicon layers, respectively.

[0049] The first and second polycrystalline silicon layers are doped with opposite dopants. That is, if the first polycrystalline silicon layer is p-type doped, for example by boron incorporation, the second polycrystalline silicon layer is n-type doped, for example by phosphorus incorporation, and vice versa. This causes the contact structures formed with the first back-layer stack to act as charge carrier-selective contacts for the selective dissipation of a first charge carrier type, whereas the other contact structures formed with the second back-layer stack act as charge carrier-selective contacts for the selective dissipation of the opposite second charge carrier type.

[0050] The additional process step (g) involves generating electrical contacts for the solar cell. For this purpose, electrical contacts, e.g., metal contacts which can be applied locally by means of screen printing, are applied as first contacts to the first polycrystalline silicon layer in the first sub-areas and as second contacts to the second polycrystalline silicon layer in the second sub-areas.

[0051] Embodiments of the method described herein for manufacturing a solar cell according to the second aspect of the invention, as well as the individual process steps to be carried out, can be implemented simply, cost-effectively, reliably and / or on an industrial scale.

[0052] It should be noted that possible embodiments, details, properties and / or advantages of the invention described herein are largely described in this application with reference to the second aspect of the invention. Since the method described herein for manufacturing a solar cell includes the fabrication of contact structures, as described in a more general form for embodiments according to the first aspect of the invention, the stated embodiments, details, properties and / or advantages can each be transferred in the same or analogous manner to embodiments of the first aspect of the invention.

[0053] In this context, it should be understood that the terms "first" and "second," as used in relation to the backside layer stacks, the silicon oxide-containing backside passivation layer, the polycrystalline silicon layer, and the silicon oxide thin film in the definition of the method according to the second aspect of the invention, are merely used as adjectives to distinguish the respective layers and are not necessarily intended to imply any order, importance, or the like. Furthermore, it should be understood that a corresponding nomenclature is not used in the definition of the method according to the first aspect of the invention, since in this case there are not necessarily two different backside layer stacks that would need to be distinguished from one another. It is noted that the various layers, orThe resulting layer stack, as defined in the first aspect of the invention, corresponds to the respective "second" layers or the "second" layer stack as defined in the second aspect of the invention. Accordingly, all features, details, properties, and / or advantages described herein for the respective second layers or the second back-side layer stack can be transferred and, if necessary, adapted in the same or analogous manner for the layers or the back-side layer stack used in embodiments of the method according to the first aspect of the invention.

[0054] It is further noted that the method for manufacturing a solar cell according to the second aspect of the invention can be understood as employing contact structures, such as those that can be manufactured according to the first aspect of the invention, to form a solar cell according to a specific solar cell concept. In this solar cell concept, both electrical contact types are located on the back side of the silicon substrate, so that the manufactured solar cell can also be referred to as a back-contact solar cell or, in particular, as an IBC solar cell. Both electrical contact types are formed using TOPCon-type or POLO-type contact structures with appropriate layer stacks.

[0055] However, it should be explicitly pointed out that the method for manufacturing contact structures according to the first aspect of the invention can be used very generally and in particular also in the context of manufacturing other solar cell concepts.

[0056] For example, in an alternative solar cell concept, only one of the electrical contact types may be designed with a TOPCon-like or POLO-like contact structure, whereas another contact type may be designed with a different contact structure, such as a metal contact applied to an aluminum back-surface field (AI-BSF).

[0057] Furthermore, it is explicitly pointed out that the method according to the second aspect of the invention relates to the fabrication of back-contact solar cells, and that only for this reason is the surface of the silicon substrate on which the contact structures are deposited referred to herein as the back of the silicon substrate. For the first aspect of the invention, which is to be understood more generally, the contact structures to be produced can be attached to any surface of the substrate, so that the term "back" in this case is not to be interpreted restrictively, but rather the contact structures can also be produced on a surface of a silicon substrate facing, for example, the sun, which is often referred to as the front in relation to solar cells. Finally, it is pointed out that the term "silicon oxide" herein is used generally as a generic term for various silicon-containing oxides (SiO₂). x) is to be understood and in particular includes silicon monoxide (SiO₂), silicon dioxide (SiO₂), and silicon oxynitride (SiO₂). x N y ) should include.

[0058] Possible embodiments and advantages of the method for manufacturing the solar cell according to the second aspect of the invention, as well as corresponding embodiments of the method for manufacturing the contact structure according to the first aspect of the invention, are described in more detail below. Reference is generally made to the nomenclatures and numbering (a) to (g) of the process steps as specified for the definition of the second aspect of the invention.

[0059] The silicon substrate to be provided in process step (a) can be any substrate consisting partially or entirely of silicon. For example, the silicon substrate can be a silicon wafer. The silicon substrate can preferably be crystalline, in particular monocrystalline. The silicon substrate can have a p-type or an n-type base doping. It has been observed that silicon substrates with an n-type base doping often exhibit a higher and more stable charge carrier lifetime, thus enabling higher efficiencies and therefore potentially being preferred for use in the manufacturing process proposed here.

[0060] The silicon substrate can be in the form of sheets or plates. The silicon substrate can have dimensions typically used for manufacturing solar cells. For example, the silicon substrate can have a thickness of at least 20 pm, preferably at least 50 pm or at least 90 pm, and at most 500 pm, preferably at most 300 pm or at most 200 pm. The silicon substrate can have an area of ​​at least 1 cm². 2 , preferably at least 4 cm 2 , at least 20 cm 2 , at least 100 cm 2 or at least 200 cm 2 , but usually no more than 1000 cm 2 , preferably no more than 500 cm 2 or at most 300 cm 2 exhibit.

[0061] The silicon substrate has opposing surfaces in the form of a back and a front. On the back side, the silicon substrate has first and second sub-regions, in which different types of contact structures are to be formed in the manufactured solar cell. The first and second sub-regions can directly adjoin each other laterally. Accordingly, the entire surface of the back side of the silicon substrate can be composed of the first and second sub-regions.

[0062] The first back-side layer stack to be produced in process step (b), as well as the first silicon oxide thin film covering this first back-side layer stack, are produced such that they are only generated in the first sub-regions of the back side of the silicon substrate, whereas neither the first back-side layer stack nor the first silicon oxide thin film is present in the adjacent second sub-regions. The first back-side layer stack can completely cover the first sub-regions and / or be completely covered by the first silicon oxide thin film.

[0063] To produce the first backside layer stack and the first silicon oxide thin layer, several processing sub-steps (bl ), (b2), (b3), etc. can be carried out, as explained in more detail below.

[0064] The first backside layer stack comprises a first silicon oxide-containing backside passivation layer and a first polycrystalline silicon layer featuring a first doping type.

[0065] The first silicon oxide-containing backside passivation layer can consist entirely or partially of silicon oxide, particularly silicon dioxide. For example, it can be a high-quality silicon oxide layer that provides excellent surface passivation. It can also be a thermally oxidized silicon layer, i.e., formed by thermal growth. Alternatively, the silicon oxide-containing backside passivation layer can be deposited by deposition processes such as chemical vapor deposition (CVD), in particular plasma-enhanced CVD (PECVD) or low-pressure CVD (LPCVD). It can have a very small thickness, for example, less than 20 nm, preferably less than 10 nm, less than 5 nm, or even less than 3 nm, but usually more than 0.5 nm or more than 1 nm.

[0066] Due to its small thickness, the first backside passivation layer can also be called a tunnel oxide layer. Charge carriers may be able to tunnel through this very thin layer. Alternatively or additionally, charge carriers may also pass through the thin first backside passivation layer along microscopic pinholes.

[0067] The first polycrystalline silicon layer can consist entirely or partially of polycrystalline silicon. It can have a thickness of typically at least 10 nm, preferably at least 20 nm, at least 30 nm, at least 50 nm, or even at least 100 nm, but usually less than 300 nm, less than 200 nm, or less than 150 nm. The first poly-Si layer can be produced, for example, by vapor deposition, in particular PECVD or LPCVD. The first poly-Si layer is at least partially doped with dopants. For example, boron can be incorporated into the first poly-Si layer to dope it with a p-type dopant. Alternatively, phosphorus can be incorporated into the first poly-Si layer to dope it with an n-type dopant.

[0068] The first poly-Si layer can be produced in such a way that it achieves homogeneous doping. Alternatively, the first poly-Si layer can be inhomogeneously doped. For example, this layer can be multilayered, where one poly-Si sublayer can be weakly doped or undoped (i.e., intrinsically doped), and an adjacent poly-Si sublayer can be more heavily doped. The doping concentration of the poly-Si layer can, for example, be at least 1 x 10⁻⁶. 18 cm -3 , preferably at least 1x10 19 cr 3 , but usually less than 1 x 10 21 cm -3 be.

[0069] The first silicon oxide thin film covering the first back-layer stack can have a thickness less than that of the first polycrystalline silicon layer, in particular less than one-half, one-third, one-quarter, one-fifth, one-seventh, or one-tenth of the thickness of the first polycrystalline silicon layer. For example, the silicon oxide thin film can be thinner than 50 nm, preferably thinner than 30 nm, thinner than 20 nm, thinner than 10 nm, or even thinner than 5 nm, but most often thicker than 1 nm, preferably thicker than 2 nm or thicker than 3 nm.The first silicon oxide thin film can preferably consist of a thermally grown silicon oxide, wherein the silicon oxide thin film can grow on the underlying poly-Si layer by immersing the entire silicon substrate together with the poly-Si layer at least temporarily in a hot, oxygen-containing atmosphere, or wherein the silicon oxide thin film can grow on the underlying poly-Si layer by temporarily heating the poly-Si layer locally by irradiating it with laser light and being surrounded by an oxygen-containing atmosphere.

[0070] In process step (c), a second backside layer stack is then produced in such a way that it covers both the first and second sub-regions. In other words, the second backside layer stack can be produced in such a way that it covers the entire backside of the silicon substrate, including the backside layer stack and the silicon oxide thin film already formed there in the first sub-regions. Similar to the first backside layer stack, the second backside layer stack comprises a second silicon oxide-containing backside passivation layer and a second polycrystalline silicon layer. The second silicon oxide-containing backside passivation layer can have similar properties to the first silicon oxide-containing backside passivation layer, particularly with regard to its chemical composition, the processes used for its production, and its geometric properties.Similarly, the second poly-Si layer can exhibit properties similar to the first poly-Si layer, particularly with regard to its chemical composition, the processes used for its fabrication, and its geometric properties. However, the second poly-Si layer differs from the first in its doping. Specifically, the second poly-Si layer is doped with the opposite type of dopant compared to the first. Doping concentrations may also differ between the two poly-Si layers.

[0071] Subsequently, a combined process sequence (d+e) is carried out, in which a second silicon oxide thin film is ultimately formed. This second film covers the central regions of the second sub-regions and, optionally, the peripheral regions of the second sub-regions, while leaving the first sub-regions uncovered. According to a first embodiment of the process, this is achieved by combining steps (dl) and (ei) as defined below, or, alternatively, according to a second embodiment, by combining steps (d2) and (e2) as defined below:

[0072] In process step (dl), an annealing step is performed. For this purpose, the silicon substrate, together with the second back-side layer stack previously formed on it, is placed in a hot gas atmosphere, referred to herein as the annealing atmosphere, for example in a furnace, and held there at high temperatures for a predetermined process duration. This process duration can range from several minutes to a few hours, i.e., usually more than 1 minute, preferably more than 5 minutes, more than 10 minutes, or more than 20 minutes, but usually less than 3 hours, less than 1 hour, or less than 40 minutes. The temperatures acting on the substrate are above 700 °C, usually above 800 °C, typically in the range of 850 ± 50 °C.

[0073] In such an annealing step, microscopic damage, such as that caused during the production of the second polycrystalline silicon layer within the same or adjacent second silicon oxide-containing backside passivation layer or the adjacent silicon substrate, can be at least partially repaired.

[0074] The anneal atmosphere can consist largely of an inert gas such as nitrogen. However, in the first embodiment of the proposed method, the silicon substrate is not surrounded exclusively by inert gas throughout the entire annealing step. Instead, the annealing step is designed to be carried out in such a way that the annealing atmosphere contains at least a small proportion of oxygen, at least temporarily. This oxygen can, for example, be selectively introduced or dosed into the annealing atmosphere. For instance, after a process duration in which the annealing step is carried out with purely inert gas, oxygen can be selectively injected into the annealing atmosphere towards the end of the step. Alternatively, it can be ensured that the annealing atmosphere has at least a small proportion of oxygen, i.e., a low partial pressure of oxygen, during the annealing step.

[0075] The oxygen content in the anneal atmosphere, as well as the duration for which the silicon substrate is exposed to this oxygen-enriched atmosphere, should be precisely controlled such that, due to the presence of oxygen and the high temperatures, a second silicon oxide thin film forms on an exposed surface of the previously deposited second polycrystalline silicon layer. In other words, the second poly-Si layer is selectively thermally oxidized during the annealing step to form the second silicon oxide thin film. The thickness of this second silicon oxide thin film depends on various process parameters, such as the process duration, process temperature, amount of oxygen present, oxygen partial pressure, etc. As explained in more detail below, these parameters can be adjusted to produce a silicon oxide thin film with a very small thickness.

[0076] In the subsequent process step (ei), in the first embodiment of the method, the previously formed second silicon oxide thin layer is removed by laser ablation, at least in the first sub-areas. It may also be possible to remove the second silicon oxide thin layer by laser ablation in the outer edge regions of the second sub-areas.

[0077] For this purpose, a laser beam emitted by a laser with suitable laser properties can be directed onto the silicon oxide thin layer in the initial sub-regions and optionally also in the edge regions. The laser beam can, for example, be successively guided as a focused spot across these regions, i.e., scanned. The laser properties are selected such that the laser beam is absorbed in the silicon oxide thin layer or the adjacent doped polycrystalline silicon layer, releasing sufficient energy to cause ablation, i.e., local flaking and / or vaporization of material from the second silicon oxide thin layer, thus removing the second silicon oxide thin layer in the irradiated areas. Possible properties of a laser to be used in this process are explained in more detail below with reference to one embodiment.

[0078] As an alternative to the process sequence (d1 +e1) described above according to the first embodiment of the process, the locally structured silicon oxide thin film can also be produced using so-called laser oxidation by means of a process sequence (d2+e2) according to the second embodiment of the process.

[0079] For this purpose, the previously produced polycrystalline silicon layer can be locally irradiated with laser light in the second sub-regions after an annealing step preferably carried out in an inert atmosphere. The properties of the laser used, or rather the laser light emitted by it, are set such that the poly-Si layer is heated intensely for a short time by the laser irradiation, but ablation generally does not occur. Typically, a laser is used that, with regard to emitted wavelength and other parameters, may be similar to lasers designed for ablation, but in which, for example, the laser pulse length may be longer or the laser pulse energy lower than in lasers used for ablation.Briefly heating the poly-Si layer with a laser can cause a chemical reaction in the heated areas with the oxygen contained in the surrounding atmosphere, resulting in the local growth of a thin second silicon oxide layer.

[0080] Subsequently, in process step (f), selective etching is carried out in which the silicon substrate, along with the various layers previously formed on it, is immersed in a highly selective etching agent. The etching agent can be a liquid, particularly a solution. Alternatively, a paste, a gas, a vapor, or a plasma can also be used as the etching agent.

[0081] The etching agent is selected to have a high etch rate for silicon but a significantly lower etch rate for silicon oxide. In other words, the chemical properties of the etching agent can be chosen such that silicon is etched much faster than silicon oxide. For example, the etch rate for silicon can be at least 2 times, preferably 5 times, 10 times, 20 times, 50 times, or even 100 times greater than the etch rate for silicon oxide.

[0082] This ensures that, on the one hand, in the first sub-areas where the second poly-Si layer was previously freed from the overlying silicon oxide thin layer by laser ablation, or where no silicon oxide thin layer was created by laser oxidation and where the etching agent can therefore directly attack the second poly-Si layer, this second poly-Si layer is quickly etched and removed as completely as possible within a short process time. Simultaneously, in the adjacent sub-areas, which are covered by the second silicon oxide thin layer and where this thin layer acts as an etching mask, the etching agent cannot come into direct contact with the second poly-Si layer. Instead, the etching agent can only etch the second silicon oxide thin layer in these areas.However, due to the highly selective etching effect of the highly selective etching agent, the silicon oxide thin layer is etched only very slowly at best.

[0083] Accordingly, even a relatively thin silicon oxide thin film, which is particularly thinner than the underlying second polycrystalline silicon layer, can suffice to withstand the etching agent throughout the entire selective etching process, i.e., to retain its masking effect for the underlying areas of the second poly-Si layer. Thus, the selective etching step can preferably remove the second poly-Si layer completely in the first sub-areas and, optionally, in the edge regions of the second sub-areas, and allow it to remain largely unetched, at least within the edge regions of the second sub-areas, protected by the second silicon oxide thin film. In these second sub-areas, the second polycrystalline silicon layer, together with the underlying silicon oxide-containing backside passivation layer, can therefore serve as a local contact structure.In a final process step (g), electrical first contacts can then be applied to the first polycrystalline silicon layer in the first sub-areas, and electrical second contacts can be applied to the second polycrystalline silicon layer in the second sub-areas. Locally applied layers of an electrically conductive material can be used as the electrical first and second contacts. For example, the contacts can be applied by screen printing, as explained in more detail below.

[0084] Overall, a silicon solar cell can be manufactured using the method described above, in which both opposite contact types are arranged on the back of the silicon substrate and are each realized using TOPCon-like or POLO-like contact structures.

[0085] It should be noted that the process used to manufacture the solar cell can involve further process steps beyond those already mentioned. For example, the silicon substrate can be etched to remove surface saw damage, textured, and / or polished. Furthermore, additional layers, such as passivation layers, masking layers, or antireflective coatings, can be applied locally or across the entire surface and, if necessary, locally ablated to create further texture through additional steps.

[0086] According to one embodiment, in process step (dl) the annealing step or in process step (e2) the oxidation step is carried out such that the second silicon oxide thin film is formed with a thickness of at least 1 nm, preferably at least 2 nm, at least 4 nm or at least 8 nm and at most 40 nm, preferably at most 30 nm, at most 20 nm or at most 12 nm.

[0087] In other words, process parameters that influence the formation of the silicon oxide thin film during the annealing or oxidation step should be selected such that the silicon oxide thin film is produced with a minimum thickness sufficient to function adequately as an etching mask during the subsequent etching step. In other words, the silicon oxide thin film should be produced thick enough that it is not completely etched away during the subsequent etching step. Generally, it is sufficient to grow the silicon oxide thin film with a thickness of at least 1 nm to 15 nm.

[0088] On the other hand, the silicon oxide thin film should not be formed with excessive thickness. During the thermal growth of the second silicon oxide thin film on the second poly-Si layer, silicon oxide is formed by the oxidation of silicon from the poly-Si layer, so the poly-Si layer is partially consumed or transformed in the process. Forming the second silicon oxide thin film with excessive thickness would mean that the second poly-Si layer would lose a significant amount of thickness and would therefore either have to be deposited beforehand with a greater thickness, which would be costly, or would result in an insufficient thickness. Therefore, forming the second silicon oxide thin film with excessive thickness would require a longer process time both for the formation of the silicon oxide thin film itself and for the formation of the underlying second poly-Si layer.

[0089] As detailed elsewhere herein, in the method presented here, it is not necessary to produce a particularly thick second silicon oxide thin layer to achieve a sufficient masking effect, since, due to the high etch selectivity of the etching substance used in the subsequent step, a thin second silicon oxide thin layer is sufficient to adequately mask and protect the second poly-Si layer covered by it.

[0090] According to one embodiment, in process step (ei) the second silicon oxide thin layer is ablated using a laser, or in process step (e2) the second polycrystalline silicon layer is irradiated with a laser whose emitted laser light has a penetration depth into the second polycrystalline silicon layer which is less than the thickness of the second polycrystalline silicon layer.

[0091] In other words, the penetration depth to which a predominant proportion, i.e., for example, more than 50%, preferably more than 70%, more than 90%, or even more than 95%, of the laser light emitted by the laser penetrates the material of the second poly-Si layer before being absorbed, should be less than the thickness of the second poly-Si layer itself. The penetration depth of the emitted laser light in silicon can be, for example, less than 200 nm, preferably less than 150 nm, less than 100 nm, less than 50 nm, less than 30 nm, less than 20 nm, or even less than 10 nm. In other words, a laser should be used for ablating the second silicon oxide thin film, or for laser oxidizing the poly-Si layer, whose emitted laser light, due to its physical properties, is absorbed to a significant extent, largely, or even completely within the second poly-Si layer.The energy converted during absorption leads to intense local heating, which, depending on the temporarily reached temperature, then results in either the ablation of the adjacent second silicon oxide thin layer or the laser oxidation of the poly-Si layer. Consequently, in this case, little or no of the incident laser light penetrates the second poly-Si layer and thus does not reach the underlying silicon substrate, where it could have an undesirable or even damaging effect.

[0092] Laser properties that influence absorption in a material, and thus the penetration depth, include the frequency or wavelength of the laser light. For the processes described herein, it has been found that lasers with an emission wavelength of less than 700 nm, preferably less than 600 nm, less than 500 nm, less than 400 nm, or even less than 350 nm—that is, lasers whose emitted laser light lies in the green, blue, violet, or even ultraviolet wavelength range—are preferably used for ablating the second silicon oxide thin layer. Other laser properties that can influence the penetration depth include laser power, laser pulse duration, laser pulse energy, etc.

[0093] According to one embodiment, the highly selective etching agent comprises potassium hydroxide and an etch selectivity-enhancing additive, such that the etch rate for silicon is at least 2 times higher, preferably at least 5 times higher, at least 10 times higher, at least 20 times higher, at least 30 times higher, at least 50 times higher or even at least 100 times higher than the etch rate for silicon oxide.

[0094] In other words, the etching agent used during the etching step can be a potassium hydroxide (KOH)-based solution. Even in its pure form, i.e., without any additives, such a KOH solution etches silicon faster than silicon dioxide and thus already exhibits a certain degree of etch selectivity. However, the etch selectivity of the KOH solution can be significantly increased by adding specific substances that act as etch selectivity-enhancing additives.

[0095] Such additives are currently being developed by companies well-known in the PV industry, such as Rena GmbH (Germany). This makes it possible, in particular, to significantly increase the etch rate ratio (the ratio of the etch rate for silicon to the etch rate for silicon oxide) compared to pure KOH, for example by a factor of more than 2, more than 5, or even more than 10.

[0096] In principle, the higher the etch rate quotient of the etching agent used during the etching step, the smaller the layer thickness of the silicon oxide thin film serving as an etching mask can be without there being a risk that the silicon oxide thin film will dissolve during the etching process and thus lose its masking effect.

[0097] According to one embodiment, the first polycrystalline silicon layer is p-type doped and the second polycrystalline silicon layer is n-type doped. It has been observed that p-type doped polycrystalline silicon can generally be more difficult to etch than n-type doped poly-Si. Therefore, the first poly-Si layer, which is formed first and may need to be etched back, is preferably p-type doped so that it can be etched for a long time if necessary without risking excessive attack on a further, already deposited n-type doped poly-Si layer. Only in a subsequent step is the second poly-Si layer then produced and n-type doped.

[0098] It is possible that the first polycrystalline silicon layer can be deposited, at least in some areas, with a different, and in particular a higher, doping concentration than the second polycrystalline silicon layer.

[0099] For example, the first poly-Si layer can be produced by first depositing a doped, intrinsic poly-Si layer and then a highly doped second poly-Si layer. That is, the first poly-Si layer can be produced as a double layer or layer stack. This can be particularly advantageous if the first poly-Si layer is p-type doped with boron as the dopant. It has been observed that boron can diffuse relatively easily into a silicon oxide layer at an interface and from there into the underlying silicon substrate.Since this is usually undesirable, it is considered advantageous to form the p-type-doped first poly-Si layer not as a homogeneously doped single layer, but preferably as an inhomogeneously doped layer stack, in which at least one outer poly-Si partial layer, which is spaced apart from the silicon oxide-containing passivation layer by an intervening intrinsic poly-Si partial layer, is formed with a particularly high doping concentration. This high doping concentration is preferably greater than that of the second poly-Si layer. Such a highly doped outer polycrystalline partial layer of the first polycrystalline silicon layer can be difficult to etch due to its high doping concentration and thus may act very efficiently as an etching barrier. According to one embodiment, process step (f) can additionally comprise at least one of the following substeps:

[0100] (fl) Performing a hydrofluoric acid etching step by immersing the silicon substrate in hydrofluoric acid;

[0101] (f2) Performing a cleaning step by introducing the silicon substrate into a cleaning substance.

[0102] During the hydrofluoric acid etching step according to the process substep (fl), hydrofluoric acid, i.e., a solution of hydrogen fluoride (HF) and water (H₂O), wets the silicon substrate or the various layers currently located on it. Pure hydrofluoric acid, i.e., without the addition of oxidizing media such as nitric acid (HNO₃) or hydrogen peroxide (H₂O₂), is highly selective in its etching action, as it strongly corrosively attacks dielectrics such as silicon oxide or silicon nitride, but not pure silicon.Accordingly, in the hydrofluoric acid etching step, exposed dielectric layers, such as in particular exposed surface areas of the first and / or second silicon oxide thin film, the first and / or second silicon oxide-containing backside passivation layer and / or other layers such as a silicon nitride layer, are removed, but adjacent areas of the silicon substrate or one of the polycrystalline silicon layers are not attacked.

[0103] Optionally, a further cleaning step can be performed in which the silicon substrate is immersed in a cleaning agent such as an ozone-containing etching solution, in particular, for example, an HCIO3 / HF solution. This removes, among other things, dirt, contaminants, etc., from the surface of the silicon substrate and the layers formed on it.

[0104] According to one embodiment, the proposed method further comprises an additional step (gl) after step (f). This process step (gl) involves applying a surface-passivating dielectric layer to the first and second backside layer stacks produced on the back side. In other words, after the etching step, but typically before the application of the first and second electrical contacts in step (g), an additional dielectric layer can be applied to the back side of the silicon substrate. This dielectric layer can cover both exposed areas of the silicon substrate surface and areas of the silicon substrate surface that are covered with other layers, such as, in particular, the first and second backside layer stacks. The dielectric layer can be configured as a single layer, a double layer, or layer stacks.For example, the dielectric layer can be a single layer made of silicon nitride, aluminum oxide, silicon dioxide, or similar dielectrics. Alternatively, the dielectric layer can be a double layer, for example, consisting of a silicon nitride layer and an aluminum oxide layer. Such dielectric layers can effectively passivate the surfaces they cover.

[0105] According to a more specific embodiment, the surface-passivating dielectric layer is deposited over the entire surface.

[0106] In other words, the dielectric layer to be applied in step (gl ) can be deposited along the entire surface of the back side of the silicon substrate and preferably also on the front side of the silicon substrate. Such full-surface deposition is technically easy to carry out, for example using chemical or physical vapor deposition.

[0107] According to one embodiment, the first polycrystalline silicon layer and / or the second polycrystalline silicon layer are deposited by chemical vapor deposition with the simultaneous introduction of dopants.

[0108] In other words, the polycrystalline silicon layers of the first and / or second back-layer stack can be deposited by chemical vapor deposition (CVD) such as PECVD or LPCVD. Dopants such as boron or phosphorus, or chemical compounds containing these dopants, can be simultaneously introduced into the gas phase from which the polycrystalline silicon layer is formed. This allows the dopants to be directly incorporated into the silicon layers during their formation, acting as dopant. This enables the polycrystalline silicon layer to be produced with the desired doping in a single process step, eliminating the need for subsequent process steps to dope an initially undoped silicon layer.Furthermore, a largely homogeneous doping can be created in the polycrystalline silicon layer.

[0109] Particularly in the case of producing boron-doped polycrystalline silicon layers, it can be advantageous not only to deposit a single, homogeneously doped silicon layer, but instead to deposit a double layer consisting of an undoped, i.e., intrinsic, polycrystalline silicon layer and a polycrystalline silicon layer heavily doped with boron. In a subsequent high-temperature step, such as an annealing step, boron can then diffuse from the latter silicon layer into the underlying, previously undoped polycrystalline silicon layer, thus doping it as well. Deposition of such a double layer can, among other things, prevent excessive amounts of boron from migrating into the silicon oxide-containing backside passivation layer or the adjacent silicon substrate.

[0110] According to one embodiment, step (b) of the method according to the second aspect of the invention comprises at least the following substeps, preferably in the order shown:

[0111] (bl ) Creating the first backside layer stack with the first silicon oxide-containing backside passivation layer and the first polycrystalline silicon layer covering the first and second sub-areas of the backside of the silicon substrate;(b2) Forming a silicon oxide thin film covering the first sub-regions and not covering the second sub-regions by performing a combination of steps (b2a) and (b4a) and optionally (b3a) as defined below, or alternatively by performing sub-steps (b2b) and (b3b) and, optionally, (b4b): (b2a) Performing an anneal step by introducing the silicon substrate provided with the first back-side layer stack into an anneal atmosphere at temperatures above 700°C, the anneal atmosphere being supplied with oxygen at least temporarily, so that during the anneal step the first silicon oxide thin film forms adjacent to the first polycrystalline silicon layer, (b3a) optionally: depositing a silicon nitride layer over the first silicon oxide thin film, and;

[0112] (b4a) Removal of the silicon oxide thin film and, optionally, the overlying silicon nitride layer by laser ablation in the second sub-regions; or (b2b) Performing an anneal step by introducing the silicon substrate coated with the first backside layer stack into an anneal atmosphere at temperatures above 700°C, and

[0113] (b3b) Performing a local oxidation step on the first polycrystalline silicon layer by locally irradiating the first sub-areas of the silicon substrate, which is embedded in an oxygen-containing atmosphere, with laser light such that a silicon oxide thin film is formed in the first sub-areas by the oxidation step; and

[0114] (b4b) optional: Deposition of a silicon nitride layer over the first silicon oxide thin film,

[0115] (b5) optional: Performing an etching step by immersing the silicon substrate in a silicon-etching etching substance and thereby removing the first polycrystalline silicon layer in the second sub-areas;

[0116] (b6), optional: Performing a hydrofluoric acid etching step by immersing the silicon substrate in hydrofluoric acid and / or performing a cleaning step by immersing the silicon substrate in a cleaning substance.

[0117] The first back-layer stack to be produced in process step (b) can thus be produced using similar techniques and the same or similar process steps as described above and below for the second back-layer stack. Process steps (bl) to (b6) essentially correspond to the previously described process steps (c), (d), (e), (f), (f1), and (f2). Possible details regarding implementations of process steps (bl) to (b6) are explained further below in the description of a specific embodiment of the manufacturing process according to the second aspect of the invention, with reference to accompanying Figure 2.

[0118] According to one embodiment, in step (g) the electrical contacts are applied by printing and baking on metal-containing pastes.

[0119] In other words, the electrical first and / or second contacts can be locally applied to the previously formed contact structures with the first or second layer stacks using printing techniques in which metal-containing pastes are printed locally onto the respective first and second sub-areas. For example, screen printing pastes containing metal particles such as silver or aluminum particles can be used as metal-containing pastes. The pastes can be applied using printing techniques such as screen printing, roll printing, mask printing, or similar methods. Such techniques for applying electrical contacts have long been established in the industrial manufacturing of solar cells and enable the reliable and relatively cost-effective formation of electrical contacts.

[0120] It is noted that possible advantages and embodiments of the invention are described herein partly with reference to a method according to the invention for manufacturing contact structures, particularly for a solar cell, and partly with reference to a method according to the invention for manufacturing an entire solar cell. Those skilled in the art will recognize that the described features can be appropriately transferred, adapted, exchanged, or modified to arrive at further embodiments of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0121] Embodiments of the invention are described below with reference to the accompanying drawings, whereby neither the drawings nor the description are to be interpreted as limiting the invention.

[0122] Figs. 1 (a) - (e) illustrate a sequence of process steps of a method for manufacturing a contact structure according to a first embodiment of the first aspect of the invention.

[0123] Figs. 2 (a) - (e) illustrate a sequence of process steps of a method for manufacturing a contact structure according to a second embodiment of the first aspect of the invention.

[0124] Figs. 3 (a) - (g) illustrate a sequence of process steps of a method for manufacturing a solar cell according to an embodiment of the second aspect of the invention.

[0125] Figs. 4 (a) - (e) illustrate a sequence of process steps of a method for manufacturing a solar cell according to a further embodiment of the second aspect of the invention.

[0126] The figures are merely schematic and not to scale. In particular, it should be noted that the dimensions shown in the figures are not realistic representations, but are intended only to illustrate basic principles.

[0127] Identical reference symbols denote identical or equivalent features in the different figures. DESCRIPTION OF PREFERRED EXECUTIONS

[0128] Fig. 1 illustrates an exemplary first embodiment of a method by which a contact structure can be manufactured, for example, for forming electrical contacts for solar cells. In the figure, sub-figures (a) to (e) correspond to the process steps as defined in the first aspect of the invention and as specified in the main claim.

[0129] In process step (a), a silicon substrate 3 is provided in the form of a monocrystalline silicon wafer. The silicon substrate 3 has nine laterally adjacent first sub-regions 7 and second sub-regions 17 on its back side.

[0130] In process step (b), a backside layer stack 19 is formed on the back side 9 of the silicon substrate 3. The backside layer stack 19 covers the first and second sub-regions 7, 17 and consists of a silicon dioxide layer only a few nanometers thick, which acts as a silicon oxide-containing backside passivation layer 21, and a doped polycrystalline silicon layer 23 deposited on top of it with a thickness of between 100 nm and 150 nm.

[0131] In process step (cl), the silicon substrate 3 with the back-layer stack 19 applied to it undergoes an annealing step by being placed in an annealing atmosphere maintained at a high temperature of approximately 850 °C for a process duration of approximately 30 min. At the beginning of the annealing step, the atmosphere can consist of an inert gas, such as nitrogen. Towards the end of the annealing step, oxygen can then be selectively added to the atmosphere. This oxygen causes the silicon present on the surface of the polycrystalline silicon layer 23 to oxidize to silicon dioxide, so that a silicon oxide thin film 25 is successively thermally grown, completely covering the outer surface of the polycrystalline silicon layer 23.In process step (d1), parts of the previously formed silicon oxide thin layer 25 in the first sub-regions 7 and optionally also in edge regions 27 of the second sub-regions 17 are removed by laser ablation. Accordingly, only parts of the silicon oxide thin layer 25 remain in the inner central regions 26 of the second sub-regions 17.

[0132] As an alternative to the process sequence with a combination of steps (cl) and (dl) as shown in Fig. 1, a second embodiment of the process, as shown in Fig. 2, allows for an initial annealing step in step (c2) without the targeted addition of oxygen and / or optionally with subsequent removal of any oxide layer formed, e.g., by hydrofluoric acid etching. Subsequently, in step (d2), a locally acting oxidation step can be carried out in which central regions 26 and optionally also peripheral regions 27 of the second subregions 17 are irradiated with laser light 28 of suitable wavelengths and intensity, so that near-surface regions of the poly-Si layer 23 are oxidized.

[0133] Finally, in process step (e), an etching step is carried out in which the silicon substrate 3, together with the back-layer stack 19 and the remaining parts of the silicon oxide thin film 25, is immersed in a highly selective etching agent, for example, in the form of a potassium hydroxide solution containing additives. The etching agent is selected to have a high etch rate for silicon and a significantly lower etch rate for silicon oxide. Furthermore, other process parameters such as etching time, etching agent concentration, process temperature, etc., are determined., which influence the etching effect of the etching substance, are chosen such that during the etching step, on the one hand, the polycrystalline silicon layer 23 in the first sub-areas 7 and the edge areas 27 of the second sub-areas 17, which are not covered by the silicon oxide thin layer 25, is completely etched back, and on the other hand, due to the low etch rate for silicon dioxide, the silicon oxide thin layer 25 over the second sub-areas 17 is only minimally attacked and thus, in particular, the underlying parts of the polycrystalline silicon layer 23 are not attacked.

[0134] Further process steps may be performed before, during, and / or after the described process sequence. For example, the silicon substrate 3 can be pre-etched to remove saw damage, create surface texturing, and / or smooth or polish the back side. During the sequence, additional layers, such as one or more dielectric layers, can be deposited as passivation layers, masking layers, or similar, and / or partially or completely removed, for example, by etching or laser ablation. Following the last described process step (e), further process steps can be performed, for example, to remove externally exposed areas of the silicon oxide thin film 25 and the silicon oxide-containing back-side passivation layer 21 using a hydrofluoric acid-based etching solution.Furthermore, electrical contacts can be applied to the generated contact structures, for example by printing on metal-containing pastes.

[0135] As a result of this process sequence, small-area contact structures 2 can be produced on the silicon substrate 3, in which the back side 9 of the silicon substrate 3 is only covered with the back side layer stacks 19 in the second sub-areas 17, but no back side layer stacks 19 are present in the adjacent first sub-areas 7.

[0136] Fig. 3 illustrates an exemplary embodiment of a method by which a solar cell 1 can be manufactured. In the figure, sub-figures (a), (b), (c), (dl), (ei), (f), and (g) correspond to the process steps as defined in the second aspect of the invention and specified in the dependent claim. The additionally numbered sub-figures (bl), (b2a), (b3a), (b4a), (b5), (b6), (f1), (f2), and (g1) relate to sub-steps as defined in the dependent claims.

[0137] In process step (a), a silicon substrate 3 in the form of a silicon wafer with an n-type base doping is provided, which has been previously textured on its front side and polished on its back side 9. The back side 9 of the silicon substrate 3 is subdivided into first sub-areas 7 and second sub-areas 17.

[0138] A subsequent process step (b) comprises several sub-steps (bl ) to (b6).

[0139] In step (bl ), a first backside layer stack 5 is initially produced, comprising a first silicon oxide-containing backside passivation layer 11 and an overlying first p-type doped polycrystalline silicon layer 13. The first backside layer stack 5 initially covers both the first and second sub-regions 7, 17 on the backside 9 of the silicon substrate 3 and can exhibit similar properties to those described for the embodiment shown in Fig. 1.

[0140] Subsequently, in substep (b2a), an annealing step is performed in which the silicon substrate 3, together with the first back-layer stack 5, is introduced into an annealing atmosphere heated to approximately 850 °C. Oxygen is added to the annealing atmosphere, at least temporarily. Accordingly, a first silicon oxide thin film 15 forms on the outer surface of the first polycrystalline silicon layer 13. Process parameters are adjusted during the annealing step such that the first silicon oxide thin film 15 grows to a thickness of approximately 20 nm ± 10 nm.

[0141] Over this first silicon oxide thin layer 15, a silicon nitride layer 35 approximately 30 nm ±10 nm thick is subsequently deposited in a sub-step (b3a).

[0142] In substep (b4a), the silicon nitride layer 35 and the silicon oxide thin film 27 in the second sub-regions 17 are then locally removed by laser ablation. Alternatively to substeps (b2a), (b3a), and (b4a), a locally structured silicon oxide thin film 15 can be produced by laser oxidation according to a second embodiment of the process. Substeps (b2b) and (b3b) to be carried out in this case correspond to process steps (c2) and (d2) as previously explained with reference to Fig. 2. In an optional substep (b4b), a silicon nitride layer 35 can additionally be produced over the first silicon oxide thin film 15.

[0143] Subsequently, in step (b5), the first polycrystalline silicon layer 13 is removed in the second sub-areas 17 by immersing the silicon substrate 3 in an etching agent such as a potassium hydroxide solution, which selectively etches silicon but does not etch dielectrics such as silicon oxide or silicon nitride, or at least does so to a significantly lesser extent. Accordingly, the first back-side layer stacks 5, along with the silicon oxide thin film 15 grown on them and the overlying silicon nitride layer 35, remain in the first sub-areas 7. In the second sub-areas 17, however, the first polycrystalline silicon layer 13 is removed as completely as possible.Since the underlying silicon oxide-containing backside passivation layer 11 is only very thin, process parameters can be set such that, despite the low etching power of the etching substance for silicon oxide, this layer 11 is locally etched away in the second sub-areas 17 and, if necessary, even a surface sub-layer of the underlying silicon substrate 3 is etched away.

[0144] Subsequently, in substep (b6), a cleaning step is carried out in which the silicon substrate 3 is immersed in a cleaning substance to remove, for example, residues, contaminants, or similar substances. The cleaning substance can be, for example, an etching solution containing various acids such as hydrochloric acid (HCl), hydrofluoric acid (HF), or similar substances, and which may be enhanced by the addition of oxidizing media such as ozone to improve its etching or cleaning properties. After a structured first backside layer stack 5 has been produced using substeps (b1) - (b6), covering the backside 9 of the silicon substrate 3 in the first sub-regions 7 but leaving adjacent second sub-regions 17 uncovered, a second backside layer stack 19 is produced in process step (c). This is deposited over the entire backside 9 and thus covers both the first and second sub-regions 7 and 17.The second back-side layer stack 19 comprises a second silicon oxide-containing back-side passivation layer 21 and an n-type doped second polycrystalline silicon layer 23, which can be identical or similar in thickness and optionally other parameters to the corresponding first layers 11, 13 of the first back-side layer stack 5 described above. However, the second poly-Si layer 23 is doped with an opposite doping type compared to the first poly-Si layer 13.

[0145] Subsequently, in process step (dl), another annealing step is performed, in which the silicon substrate is introduced into an anneal atmosphere at approximately 850 °C and oxygen is added, at least temporarily, to form a second silicon oxide thin film 25 adjacent to the second poly-Si layer 23. The second silicon oxide thin film 25 is grown to a thickness of approximately 20 nm ± 10 nm by appropriately adjusting process parameters during the annealing step, similar to the first silicon oxide thin film 15 described above. The second silicon oxide thin film 25 covers the second poly-Si layer 23 in both the first sub-regions 7 and the second sub-regions 17.

[0146] Subsequently, in process step (ei), a further laser ablation is performed, in which the second silicon oxide thin layer 25 is removed in the first sub-regions 7 and possibly in laterally adjacent edge regions 27 of the second sub-regions 17, but remains within the edge regions 27 of the second sub-regions 17. Alternatively to steps (d1) and (e1), the second silicon oxide thin layer 25 could also be produced by laser oxidation with steps (d2) and (e2), which correspond to steps (c2) and (d2) in Fig. 2, analogous to the embodiment shown in Fig. 2 and described above.

[0147] In the subsequent etching step (f), the silicon substrate 3 is immersed in a highly selective etching solution. This solution has a high etching rate for silicon but a particularly low etching rate for silicon oxide. For example, a potassium hydroxide solution can be used, to which special additives have been added that can significantly increase the etching selectivity of the solution, so that silicon is etched at least 50 times or even at least 100 times faster than silicon oxide. Accordingly, in this etching step, the areas of the second polycrystalline silicon layer 23, previously freed from the second silicon oxide thin layer 25, are etched back in the first sub-regions 7 and the edge regions 27 of the second sub-regions 17.In the areas of the second sub-areas 17 that are still covered by the second silicon oxide thin layer 25, the second silicon oxide thin layer 25 acts as a masking layer against an etching effect of the highly selective etching substance, so that the second polycrystalline silicon layer 23 remains largely unaffected there.

[0148] In a supplementary substep (fl), a hydrofluoric acid etching step can subsequently be carried out, in which the silicon substrate 3 is immersed in hydrofluoric acid. The hydrofluoric acid then etches back the exposed areas of the silicon oxide-containing second backside passivation layer 21, the silicon nitride layer 35, and the first silicon oxide thin film 15 in the first sub-areas 7.

[0149] Following this, a further substep (f2) can optionally be carried out in which the silicon substrate 3 is cleaned by immersion in a cleaning substance. The cleaning substance can be similar to that already described above for substep (b6). Subsequently, in a substep (g1), a surface-passivating dielectric layer 33 is applied to the first and second backside layer stacks 5, 19 and the intervening areas on the backside 9 of the silicon substrate 3. Preferably, the dielectric layer 33 is applied over the entire surface of both sides of the silicon substrate 3.In the illustrated example, the dielectric layer 33 consists of a double layer composed of an aluminum oxide layer 32 and a silicon nitride layer 34 deposited on top of it, resulting in very good surface passivation of the entire surface of the silicon substrate 3, including the various backside layer stacks 5, 19 deposited on it. In the illustrated example, the dielectric layer 33 is also deposited on the front side of the silicon substrate 3.

[0150] Finally, in a process step (g), electrical first contacts 29 are applied to the first polycrystalline silicon layer 13 of the first back-side layer stack 5 in the first sub-areas 7, and electrical second contacts 31 are applied to the second polycrystalline silicon layer 23 of the second back-side layer stack 19 in the second sub-areas 17. For this purpose, for example, a metal particle-containing paste can be locally printed using screen printing technologies, dried, and then fired through the dielectric layer 33.

[0151] Overall, a solar cell 1 can be manufactured using the process sequence described above, in which both contact types are nested on the back side 9 of the silicon substrate 3, with p-type contacts being formed on TOPCon-like or POLO-like contact structures 2' in the first sub-regions 7 and n-type contacts being formed on similarly TOPCon-like or POLO-like contact structures 2" in the second sub-regions 17. The general method for manufacturing contact structures 2 described with reference to Figure 1 is used, in particular to form the contact structures 2" on the IBC-like solar cell 1. It should be noted that the method described with reference to Figure 3, according to the second aspect of the present invention, is only one of several possibilities for using the method for manufacturing TOPCon-like or POLO-like contact structures 2 to advantageously manufacture a solar cell 1.In principle, however, this method can also be used to manufacture other types of solar cells 1 with TOPCon-like or POLO-like contact structures 2.

[0152] As just one further example, the manufacturing of an IBC-type solar cell 1 is briefly described below with reference to Fig. 4, in which only one of the back contact types is formed using the method described herein to create TOPCon-type or POLO-type contact structures 2, whereas the opposite back contact type is formed using a different technology.

[0153] As indicated in the process sequence in Fig. 4, in step (a) a silicon substrate 3 in the form of a p-type wafer is first provided. In step (b), a plurality of contact structures 2 are then produced on the back side 9 of the silicon substrate 3 using the method according to the first aspect of the invention. Each of the contact structures 2 comprises a backside layer stack 19 with a silicon oxide-containing backside passivation layer 21 and an n-type doped polycrystalline silicon layer 23. In step (c), the entire surface of the silicon substrate 3 is then deposited with a passivating dielectric layer 33 in the form of a double layer consisting of an aluminum oxide layer 32 and an aluminum nitride layer 34 on both sides of the silicon substrate 3. Subsequently, in step (d), the dielectric layer 33 is locally opened, for example by laser ablation, in regions 37 laterally between the previously produced contact structures 2.Finally, in these opened areas 37, an aluminum-containing paste is first locally printed by screen printing and a local aluminum back-surface field (AI-BSF) 39 is created by firing it in. Subsequently, this AI-BSF is contacted by locally printing a silver-containing paste and then firing it in through silver contact fingers 41. Additionally, the contact structures 2 can also be contacted with silver contact fingers 43, which are locally printed by screen printing and then fired through the dielectric layer 33.

[0154] It should be noted that terms such as "comprising," "encompassing," etc., do not exclude other elements or steps, and terms such as "a" or "an" do not exclude a plurality. Furthermore, it should be noted that features or steps described with reference to one of the above embodiments may also be used in combination with other features or steps of other embodiments described above. Reference numerals in the claims are not to be considered as a limitation.

[0155] REFERENCE MARK LIST

[0156] 1 solar cell

[0157] 2 Contact structure

[0158] 3 Silicon substrate

[0159] 5 first backside layer stack

[0160] 7 first sub-areas

[0161] 9 Back

[0162] 1 1 first backside passivation layer

[0163] 13 first polycrystalline silicon layer of the first doping type

[0164] 15 first silicon oxide thin film

[0165] 17 second sub-areas

[0166] 19 second back-side layer stack

[0167] 21 second backside passivation layer

[0168] 23 second polycrystalline silicon layer of the second doping type

[0169] 25 second silicon oxide thin film

[0170] 26 Central Area

[0171] 27 peripheral areas of the second sub-areas

[0172] 28 laser light

[0173] 29 first contacts

[0174] 31 second contacts

[0175] 32 Aluminum oxide layer

[0176] 33 surface passivating dielectric layer

[0177] 34 Silicon nitride layer

[0178] 35 Silicon nitride layer

[0179] 37 open areas

[0180] 39 AI-BSF 41 Silver Contact Finger

[0181] 43 silver contact fingers

Claims

Claims:

1. Method for manufacturing a contact structure (2) in particular for a solar cell (1), comprising at least the following process steps: (a) Providing a silicon substrate (3) with first sub-areas (7) and second sub-areas (17) each on a rear side (9) of the silicon substrate (3); (b) Generating a backside layer stack (19) covering the first and second sub-areas (7, 17), wherein the backside layer stack (19) comprises at least a silicon oxide-containing backside passivation layer (21) and a doped polycrystalline silicon layer (23); (c+d) Forming a silicon oxide thin film (25) which covers central regions (26) of the second subregions (17) and, optionally, edge regions (27) of the second subregions (17) and which does not cover the first subregions (7), by performing a combination of the steps (c1) and (dl) defined below or alternatively by performing a combination of the steps (c2) and (d2) defined below: (c1) Performing an annealing step by introducing the silicon substrate (3) provided with the back-layer stack (19) into an annealing atmosphere at temperatures above 700°C, wherein oxygen is added to the annealing atmosphere at least temporarily, so that during the annealing step the silicon oxide thin film (25) forms adjacent to the polycrystalline silicon layer (23), and (dl) Removal of the silicon oxide thin layer (25) by laser ablation in the first sub-areas (7) and, optionally, in the edge regions (27) of the second sub-areas (17); or (c2) Performing an anneal step by introducing the silicon substrate (3) provided with the back-layer stack (19) into a Anneal atmosphere at temperatures above 700°C, and (d2) carrying out a local oxidation step on the polycrystalline silicon layer (23) by locally irradiating the central regions (26) and, optionally, the edge regions (27) of the silicon substrate (3) taken up in an oxygen-containing atmosphere with laser light (28) such that the silicon oxide thin film (25) is formed by the oxidation step in the central regions (26) and, optionally, the edge regions (27); and (e) Performing a selective etching step by introducing the silicon substrate (3) into a highly selective etching substance which has a high etch rate for silicon and a low etch rate for silicon oxide, thereby removing the polycrystalline silicon layer (23) in the first sub-regions (7) and, optionally, in the edge regions (27) of the second sub-regions (17).

2. The method of claim 1, further comprising a further step: (f) Performing a hydrofluoric acid etching step by immersing the silicon substrate (3) in hydrofluoric acid.

3. Method for manufacturing a solar cell (1), comprising at least the following steps: (a) Providing a silicon substrate (3) with first sub-areas (7) and second sub-areas (17) each on a rear side (9) of the silicon substrate (3); (b) Producing a first backside layer stack (5) and a first silicon oxide thin film (15) in the first sub-regions (7), wherein the first backside layer stack (5) comprises at least a first silicon oxide-containing backside passivation layer (11) and a first polycrystalline silicon layer (13) of a first doping type, wherein the back side (9) of the silicon substrate (3) in second sub-regions (17) adjacent to the first sub-regions (7) is free of the first backside layer stack (5); (c) Creating a second backside layer stack (19) covering the first and second sub-regions (7, 17), wherein the second back-side layer stack (19) comprises at least a second silicon oxide-containing back-side passivation layer (21) and a second polycrystalline silicon layer (23) of a second doping type opposite to the first doping type; (d+e) forming a second silicon oxide thin film (25) covering central regions (26) of the second sub-regions (17) and, optionally, edge regions (27) of the second sub-regions (17) and not covering the first sub-regions (7), by performing a combination of steps (dl) and (e1) defined below or alternatively by performing a combination of steps (d2) and (e2) defined below: (dl) Performing an anneal step by introducing the silicon substrate (3) provided with the second back-side layer stack (19) into an anneal atmosphere at temperatures above 700°C, wherein oxygen is added to the anneal atmosphere at least temporarily, so that during the anneal step the second silicon oxide thin film (25) forms adjacent to the second polycrystalline silicon layer (23), and (e1) Removal of the second silicon oxide thin layer (25) by laser ablation in the first sub-areas (7) and, optionally, in edge areas (27) of the second sub-areas (17); or (d2) Performing an anneal step by introducing the silicon substrate (3) provided with the second backside layer stack (19) into an anneal atmosphere at temperatures above 700°C, and (e2) Performing a local oxidation step on the second polycrystalline silicon layer (23) by locally irradiating the central regions (26) and, optionally, the edge regions (27) of the silicon substrate (3) received in an oxygen-containing atmosphere with laser light (28) such that the second silicon oxide thin layer (25) is formed by the oxidation step in the central regions (26) and, optionally, the edge regions (27); (f) Performing a selective etching step by introducing the silicon substrate (3) into a highly selective etching agent, which has a high etch rate for silicon and a low etch rate for silicon oxide, and thereby removing the second polycrystalline silicon layer (23) in the first sub-regions (7) and, optionally, in the edge regions (27) of the second sub-regions (17); and (g) Applying electrical first contacts (29) to the first polycrystalline silicon layer (13) in the first sub-areas (7) and electrical second contacts (31) to the second polycrystalline silicon layer (23) in the second sub-areas (17).

4. The method of claim 3, wherein in process step (dl) the annealing step is carried out in such a manner or wherein in process step (e2) the oxidation step is carried out in such a manner that the second silicon oxide thin layer (25) is formed with a thickness of at least 1 nm and at most 40 nm.

5. Method according to one of claims 3 and 4, wherein in process step (ei) the second silicon oxide thin layer (25) is ablated using a laser or wherein in process step (e2) the second polycrystalline silicon layer (23) is irradiated with a laser whose emitted laser light has a penetration depth into the second polycrystalline silicon layer (23) which is less than a thickness of the second polycrystalline silicon layer (23).

6. Method according to any one of claims 3 to 5, wherein the highly selective etching agent comprises potassium hydroxide and an etch selectivity-enhancing additive such that the etch rate for silicon is at least 2 times higher than the etch rate for silicon oxide.

7. Method according to any one of claims 3 to 6, wherein the first polycrystalline silicon layer (13) is p-type doped and the second polycrystalline silicon layer (23) is n-type doped.

8. Method according to any one of claims 3 to 7, wherein step (f) additionally comprises at least one of the following substeps: (f1) Performing a hydrofluoric acid etching step by immersing the silicon substrate (3) in hydrofluoric acid; (f2) Performing a cleaning step by introducing the silicon substrate (3) into a cleaning substance.

9. Method according to any one of claims 3 to 8, further comprising a further sub-step (gl) after step (f): (g1) Applying a surface passivating dielectric layer (33) to the first and second backside layer stacks (5, 19) produced on the backside (9).

10. Method according to claim 9, wherein the surface passivating dielectric layer (33) is deposited over the entire surface.

11. Method according to any one of claims 3 to 10, wherein the first polycrystalline silicon layer (13) and / or the second polycrystalline silicon layer (25) are deposited by chemical vapor deposition with simultaneous introduction of dopants.

12. Method according to any one of claims 3 to 11, wherein step (b) comprises at least the following substeps: (bl ) Generating the first backside layer stack (5) with the first covering the first and second sub-areas (7, 17) of the back side (9) of the silicon substrate (3) with silicon oxide-containing backside passivation layer (11) and the first polycrystalline silicon layer (13); (b2) Forming the first silicon oxide thin film (15) covering the first sub-regions (7) and not covering the second sub-regions (17) by performing a combination of steps (b2a) and (b4a) as defined below, and optionally (b3a), or alternatively by performing sub-steps (b2b) and (b3b) and, optionally, (b4b): (b2a) Performing an anneal step by introducing the silicon substrate (3) provided with the first backside layer stack (5) into an anneal atmosphere at temperatures above 700°C, wherein oxygen is added to the anneal atmosphere at least temporarily, so that during the anneal step the first silicon oxide thin film (15) is formed adjacent to the first polycrystalline silicon layer (13), (b3a) optional: Deposition of a silicon nitride layer (35) over the first silicon oxide thin film (15), and (b4a) Removal of the first silicon oxide thin layer (15) and, optionally, the overlying silicon nitride layer (35) by laser ablation in the second sub-areas (17); or (b2b) Performing an anneal step by introducing the silicon substrate (3) provided with the first backside layer stack (5) into an anneal atmosphere at temperatures above 700°C, and (b3b) Performing a local oxidation step on the first polycrystalline silicon layer (13) by locally irradiating the first sub-regions (7) of the silicon substrate (3) absorbed in an oxygen-containing atmosphere with laser light such that the first silicon oxide thin film (15) is formed by the oxidation step in the first sub-regions (7); and (b4b) optionally: depositing a silicon nitride layer (35) over the first silicon oxide thin film (15), (b5) Performing an etching step by introducing the silicon substrate (3) into a selective silicon-etching etching substance and thereby removing the first polycrystalline silicon layer (13) in the second sub-areas (17); (b6), optional: Performing a hydrofluoric acid etching step by immersing the silicon substrate (3) in hydrofluoric acid and / or performing a cleaning step by introducing the silicon substrate (3) into a cleaning substance.

13. Method according to any one of claims 3 to 12, wherein in step (g) the electrical contacts (29, 31) are marked by printing and Metal-containing pastes are applied for baking.

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