Semiconductor die and three-dimensional lamination device

Abstract

This semiconductor die (12) is used in a three-dimensional lamination device (10) provided with a plurality of interlayered semiconductor dies (12) of mutually identical configuration, said semiconductor die (12) comprising a body (13) having an upper surface (14) and a lower surface (15), a plurality of first bonding pads (16) positioned on the upper surface (14), and a plurality of second bonding pads (17) positioned on the lower surface (15). The positions of the plurality of first bonding pads (16) coincide with the positions at which the plurality of second bonding pads (17) are moved in the plane of the lower surface (15) while maintaining the mutual positional relationship, when viewed from the direction perpendicular to the upper surface (14) or the lower surface (15).

Description

Semiconductor dies and 3D stacked devices

[0001] The present disclosure relates to semiconductor dies and the like.

[0002] In recent years, SoCs (System on Chip), which incorporate various functions such as a CPU, GPU, or memory on a single semiconductor chip, have become widely used. Known SoC manufacturing techniques include fabricating the CPU, GPU, or memory as individual parts (i.e., semiconductor dies) from different wafers and then electrically connecting these parts on a package substrate. Methods for electrically connecting multiple semiconductor dies include the 2.5-dimensional stacking method and the 3-dimensional stacking method disclosed in Patent Document 1.

[0003] In Patent Document 1, cores with the same computing functions are arranged in an array on a semiconductor die, and the semiconductor dies are then stacked using a three-dimensional stacking method in an attempt to meet the performance requirements of GPUs for AI calculations, which require enormous computing power.

[0004] Also, Patent Document 2 discloses an SoC in which multiple semiconductor dies having the same structure are stacked using a three-dimensional stacking method. In Patent Document 2, the stacked semiconductor dies are surrounded (i.e., packaged) by a highly thermally conductive member, which makes it easier to dissipate heat generated by each semiconductor die during operation of the SoC.

[0005] Furthermore, Non-Patent Document 1 discloses the results of a simulation performed assuming that two semiconductor dies having the same functions and in which the layout of each circuit is a mirror image of each other are stacked in order to shift the heat-generating points between the semiconductor dies positioned above and below.

[0006] US Patent Application Publication No. 2024 / 0128216 US Patent Application Publication No. 2023 / 0253369

[0007] R. Mathur et al. , “Thermal Analysis of a 3D stacked High-Performance Commercial Microprocessor using Face-to-Face Wafer Bonding Technology,” 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2020, pp. 541-547, doi:10.1109 / ECTC32862.2020.00091.

[0008] However, in the SoC described in Patent Document 2, as pointed out in Non-Patent Document 1, stacking multiple semiconductor dies having the same structure means that the heat generation points of each semiconductor die are the same in the stacking direction, which increases the density of heat sources inside the SoC. In other words, in the SoC described in Patent Document 2, heat may become trapped inside the SoC and may not be able to be dissipated sufficiently.

[0009] Furthermore, the SoC described in Non-Patent Document 1 requires the manufacture of two types of semiconductor dies that have the same functions but different layouts. Manufacturing two types of semiconductor dies that have the same functions but different configurations in this way can cause problems, such as longer time or higher costs than conventional designs for the semiconductor dies used in the SoC.

[0010] The present disclosure has been made to solve such problems, and aims to provide a semiconductor die or the like that has the same configuration and can more efficiently dissipate heat generated inside an SoC that includes multiple stacked semiconductor dies.

[0011] In order to achieve the above object, one aspect of the semiconductor die disclosed herein is a semiconductor die used in a three-dimensional stacked device having multiple semiconductor dies having the same configuration and stacked on top of each other, the semiconductor die comprising: a main body having an upper surface and a lower surface; multiple first bonding pads arranged on the upper surface; and multiple second bonding pads arranged on the lower surface, wherein the upper surface is one surface of the main body, the lower surface is a surface opposite to the upper surface, and the positions of the multiple first bonding pads are positions that coincide with the positions of the multiple second bonding pads when viewed from a direction perpendicular to the upper surface or the lower surface, where the positions are determined by moving the multiple second bonding pads within the plane of the lower surface while maintaining their relative positions relative to each other.

[0012] In order to achieve the above goal, one aspect of the three-dimensional stacked device according to the present disclosure is a three-dimensional stacked device having a structure in which a plurality of semiconductor dies according to the present disclosure are stacked, in which the second semiconductor die is stacked on the first semiconductor die so that the positions of the plurality of second bonding pads on the second semiconductor die and the positions of the plurality of first bonding pads on the first semiconductor die coincide with each other when viewed from a direction perpendicular to the top surface or the bottom surface.

[0013] In order to achieve the above goal, one aspect of the three-dimensional stacked device according to the present disclosure is a three-dimensional stacked device having a structure in which a plurality of semiconductor dies according to the present disclosure are stacked, in which the second semiconductor die is stacked on the first semiconductor die so that the positions of the plurality of second bonding pads on the second semiconductor die and the positions of the plurality of first bonding pads on the first semiconductor die coincide with each other when viewed from a direction perpendicular to the top surface or the bottom surface, or so that the positions of the plurality of second bonding pads on the second semiconductor die and the positions of the plurality of third bonding pads on the first semiconductor die coincide with each other when viewed from a direction perpendicular to the top surface or the bottom surface.

[0014] In order to achieve the above goal, one aspect of the three-dimensional stacked device according to the present disclosure is a three-dimensional stacked device having a structure in which a plurality of semiconductor dies according to the present disclosure are stacked, in which the second semiconductor die is stacked on the first semiconductor die such that the positions of the plurality of second bonding pads on the second semiconductor die and the positions of the plurality of first bonding pads on the first semiconductor die coincide with each other when viewed from a direction perpendicular to the top surface or the bottom surface, or such that the positions of the plurality of fourth bonding pads on the second semiconductor die and the positions of the plurality of first bonding pads on the first semiconductor die coincide with each other when viewed from a direction perpendicular to the top surface or the bottom surface.

[0015] According to the present disclosure, a semiconductor die or the like is provided that has the same configuration and is capable of more efficiently dissipating heat generated inside an SoC that includes multiple stacked semiconductor dies.

[0016] FIG. 1 is a schematic diagram showing an example of the structure of a semiconductor die according to the first embodiment. FIG. 2A is a schematic diagram showing the structure of a three-dimensional stacked device as viewed from a direction parallel to the Y direction. FIG. 2B is a schematic diagram showing the structure of a three-dimensional stacked device as viewed from a direction parallel to the Z direction. FIG. 3A is a schematic diagram showing the structure of a three-dimensional stacked device as viewed from a direction parallel to the Y direction. FIG. 3B is a schematic diagram showing the structure of a three-dimensional stacked device as viewed from a direction parallel to the Z direction. FIG. 4 is a schematic diagram showing an example of an electrical connection relationship of the three-dimensional stacked device according to the first embodiment. FIG. 5A is a schematic diagram showing a first connection pattern in which each of three semiconductor dies includes a plurality of first bonding pads, a plurality of second bonding pads, and a plurality of third bonding pads. FIG. 5B is a schematic diagram showing a second connection pattern in which each of three semiconductor dies includes a plurality of first bonding pads, a plurality of second bonding pads, and a plurality of third bonding pads. 6A is a schematic diagram showing a first connection pattern in which each of three semiconductor dies has a plurality of first bonding pads, a plurality of second bonding pads, and a plurality of fourth bonding pads. FIG. 6B is a schematic diagram showing a second connection pattern in which each of three semiconductor dies has a plurality of first bonding pads, a plurality of second bonding pads, and a plurality of fourth bonding pads. FIG. 7A is a schematic diagram showing the structure of a three-dimensional stacked device as viewed from a direction parallel to the Y direction. FIG. 7B is a schematic diagram showing the structure of a three-dimensional stacked device as viewed from a direction parallel to the Z direction. FIG. 8 is a schematic diagram showing an example of the structure of a semiconductor die according to the second embodiment. FIG. 9A is a schematic diagram showing the structure of a three-dimensional stacked device as viewed from a direction parallel to the Y direction. FIG. 9B is a schematic diagram showing the structure of a three-dimensional stacked device as viewed from a direction parallel to the Z direction. FIG. 10A is a schematic diagram showing the structure of a three-dimensional stacked device as viewed from a direction parallel to the Y direction. Fig. 10B is a schematic diagram showing the structure of the three-dimensional stacked device when viewed from a direction parallel to the Z direction. Fig. 11 is a schematic diagram showing the electrical connection relationship of the three-dimensional stacked device shown in Figs. 9A and 9B. Fig. 12A is a schematic diagram showing the structure of the three-dimensional stacked device when viewed from a direction parallel to the Y direction.FIG. 12B is a schematic diagram showing the structure of the three-dimensional stacked device when viewed in a direction parallel to the Z direction.

[0017] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that each of the embodiments described below represents a specific example of the present disclosure. Therefore, the numerical values, shapes, materials, components, the arrangement and connection of the components, processes (steps), and the order of the processes shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Therefore, among the components in the following embodiments, components that are not described in the independent claims that represent the superordinate concept of the present disclosure will be described as optional components.

[0018] Note that each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, the scales and the like do not necessarily match in each figure. Furthermore, in each figure, substantially the same configuration is assigned the same reference numeral, and duplicate explanations are omitted or simplified. Furthermore, in this specification, the terms "up" and "down" do not necessarily refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition.

[0019] Furthermore, in this specification, terms indicating the relationship between elements, such as orthogonal and parallel, terms indicating the shape of elements, such as rectangle, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also mean a substantially equivalent range, for example, including a difference of about a few percent.

[0020] In each drawing, the direction in which semiconductor dies are stacked is defined as the Z direction, and two directions that are included in a plane perpendicular to the Z direction and are orthogonal to each other are defined as the X direction and the Y direction.

[0021] First Embodiment [Semiconductor Die] FIG. 1 is a schematic diagram illustrating an example of the structure of a semiconductor die 12 according to a first embodiment. The hatching on the first bonding pads 16, the second bonding pads 17, the third bonding pads 18, and the fourth bonding pads 19 shown in FIG. 1 is used for emphasis and does not represent a cross section. This also applies to the following drawings. FIG. 1 is a diagram illustrating the interior of the semiconductor die 12 to explain the structure of the semiconductor die 12. FIG. 1A is a schematic diagram illustrating the structure of the semiconductor die 12 as viewed in a direction parallel to the Y direction. The lines connecting the bonding pads shown in FIG. 1A are lines that schematically represent electrical connections, not lines that represent precise wiring paths. This also applies to the following drawings. FIG. 1B is a schematic diagram illustrating the structure of the semiconductor die 12 as viewed in a direction parallel to the X direction. FIG. 1C is a schematic diagram showing the structure of the semiconductor die 12 when viewed in a direction parallel to the Z direction.

[0022] 1, the semiconductor die 12 is a semiconductor chip such as a CPU, GPU, or memory having a rectangular parallelepiped structure. The semiconductor die 12 is used, for example, in a three-dimensional stacked device including multiple semiconductor dies 12 that have the same structure and are stacked on top of each other. Note that the shape of the semiconductor die 12 may be other than a rectangular parallelepiped, and may be any other shape such as a polygonal prism, as long as the shape allows multiple semiconductor dies 12 to be stacked.

[0023] Semiconductor die 12 also includes a body 13, a plurality of first bonding pads 16, a plurality of second bonding pads 17, a plurality of third bonding pads 18, and a plurality of fourth bonding pads 19.

[0024] The main body 13 is, for example, an element including a semiconductor, and has elements such as transistors and wiring therein. The main body 13 also has an upper surface 14 and a lower surface 15.

[0025] The upper surface 14 is one surface of the main body 13 and is one of the planes perpendicular to the Z direction.

[0026] The lower surface 15 is one of the surfaces of the main body 13 and is one of the planes perpendicular to the Z direction. The lower surface 15 is also a surface opposite to the upper surface 14.

[0027] A plurality of first bonding pads 16, a plurality of second bonding pads 17, a plurality of third bonding pads 18, and a plurality of fourth bonding pads 19 are pads used for electrical connection with another semiconductor die 12 or an electronic component.

[0028] As shown in FIG. 1A , a plurality of first bonding pads 16 and a plurality of third bonding pads 18 are disposed on the upper surface 14. A plurality of second bonding pads 17 and a plurality of fourth bonding pads 19 are disposed on the lower surface 15. While the schematic diagram shown in FIG. 1A illustrates an example in which the semiconductor die 12 includes three first bonding pads 16, the semiconductor die 12 may include at least two first bonding pads 16. The same applies to the plurality of second bonding pads 17, the plurality of third bonding pads 18, and the plurality of fourth bonding pads 19 provided on the semiconductor die 12. The semiconductor die 12 may include at least a plurality of first bonding pads 16 and a plurality of second bonding pads 17. That is, the semiconductor die 12 may not have a plurality of third bonding pads 18 and a plurality of fourth bonding pads 19, or may have either a plurality of third bonding pads 18 or a plurality of fourth bonding pads 19.

[0029] Furthermore, the plurality of first bonding pads 16 and the plurality of third bonding pads 18 are arranged so that the ratio of their numbers is 1:1, but this is not limited thereto. For example, the plurality of first bonding pads 16 and the plurality of third bonding pads 18 may be arranged so that the ratio of their numbers is 2:1. This also applies to the arrangement of the plurality of second bonding pads 17 and the plurality of fourth bonding pads 19.

[0030] Furthermore, among the multiple bonding pads provided on the semiconductor die 12, a set of bonding pads, namely, first bonding pad 16, second bonding pad 17, third bonding pad 18, and fourth bonding pad 19, are electrically connected to each other by wiring. Specifically, first bonding pad 16 and third bonding pad 18 are electrically connected, second bonding pad 17 and fourth bonding pad 19 are electrically connected, and further, first bonding pad 16 and third bonding pad 18 are electrically connected to second bonding pad 17 and fourth bonding pad 19. Note that a set of bonding pads does not need to be directly connected. For example, first bonding pad 16, second bonding pad 17, third bonding pad 18, and fourth bonding pad 19 may be electrically connected via an element such as a transistor.

[0031] Furthermore, the wiring connecting the pair of bonding pads, first bonding pad 16 and third bonding pad 18, may be provided inside semiconductor die 12 or on the top surface thereof. Furthermore, the wiring connecting the pair of bonding pads, second bonding pad 17 and fourth bonding pad 19, may be provided inside semiconductor die 12 or on the bottom surface thereof.

[0032] Furthermore, it is not necessary for the first bonding pads 16 to be electrically connected to each other. This also applies to the connection relationships between the second bonding pads 17, the third bonding pads 18, and the fourth bonding pads 19.

[0033] 1A, 1B, and 1C, the first bonding pads 16, the second bonding pads 17, the third bonding pads 18, and the fourth bonding pads 19 are each arranged in a line along the X direction. For example, the first bonding pads 16, the second bonding pads 17, the third bonding pads 18, and the fourth bonding pads 19 may each be arranged in a line along the Y direction, or they may not be arranged in a line when viewed from any direction on the X-Y plane. Furthermore, when viewed from a direction parallel to the X direction, the first bonding pads 16 and the third bonding pads 18 do not have to be arranged in overlapping positions. Similarly, when viewed from a direction parallel to the X direction, the second bonding pads 17 and the fourth bonding pads 19 do not have to be arranged in overlapping positions. Furthermore, when viewed from a direction parallel to the X direction, the plurality of first bonding pads 16, the plurality of second bonding pads 17, the plurality of third bonding pads 18, and the plurality of fourth bonding pads 19 may be arranged on the same straight line parallel to the Z direction.

[0034] Furthermore, the plurality of first bonding pads 16 are arranged at positions that do not overlap with the plurality of second bonding pads 17 and the plurality of fourth bonding pads 19 when viewed from a direction parallel to the Z direction. The positions of the plurality of first bonding pads 16 are positions that coincide with positions obtained by moving the plurality of second bonding pads 17 within the plane of the lower surface 15 while maintaining their relative positions, when viewed from a direction perpendicular to the upper surface 14 or the lower surface 15. The positions of the plurality of first bonding pads 16 are positions that coincide with positions obtained by moving the plurality of fourth bonding pads 19 within the plane of the lower surface 15 while maintaining their relative positions, when viewed from a direction perpendicular to the upper surface 14 or the lower surface 15. Specifically, as shown in FIG. 1C , when the positions of the plurality of second bonding pads 17 and the positions of the plurality of fourth bonding pads 19 are translated within the X-Y plane, they coincide with the positions of the plurality of first bonding pads 16 when viewed from a direction parallel to the Z direction.

[0035] The positions of the plurality of third bonding pads 18 are positions that coincide with the positions of the plurality of second bonding pads 17 moved within the plane of the lower surface 15 while maintaining their relative positions, when viewed from a direction perpendicular to the upper surface 14 or the lower surface 15. Furthermore, the positions of the plurality of third bonding pads 18 are positions that coincide with the positions of the plurality of fourth bonding pads 19 moved within the plane of the lower surface 15 while maintaining their relative positions, when viewed from a direction perpendicular to the upper surface 14 or the lower surface 15. Specifically, as shown in FIG. 1C , when the positions of the plurality of second bonding pads 17 and the positions of the plurality of fourth bonding pads 19 are translated within the X-Y plane, they coincide with the positions of the plurality of third bonding pads 18 when viewed from a direction parallel to the Z direction.

[0036] [Three-Dimensional Stacked Device] The following describes a three-dimensional stacked device having a structure in which multiple semiconductor dies 12 described above are stacked. Although the following description exemplifies a three-dimensional stacked device in which three semiconductor dies 12 are stacked, any three-dimensional stacked device in which two or more semiconductor dies 12 are stacked is also included in the present disclosure. In the following description, the numerals, such as semiconductor dies 12A, 12B, and 12C, are suffixed with "A," "B," or "C." This distinction is made for ease of explanation; each of the semiconductor dies 12A, 12B, and 12C has the same configuration. Therefore, when there is no need to distinguish between them, they may simply be referred to as "semiconductor dies 12." For the same reason, the numerals of the components of the semiconductor dies 12A, 12B, and 12C are suffixed with "A," "B," or "C." However, when there is no need to distinguish between them, they may be referred to without the suffixes "A," "B," or "C."

[0037] In the following description, the location of the main heat source that generates heat in the semiconductor die 12 when the three-dimensional stacked device is operating is indicated as heat 20. The heat 20 indicated on the semiconductor die 12 is a mark indicating a location where a particularly large amount of heat is generated inside the semiconductor die 12. Therefore, when a three-dimensional stacked device in which multiple semiconductor dies 12 having the same configuration are stacked is operating, the locations of the heat sources on each of the multiple semiconductor dies 12 are the same when compared among the individual semiconductor dies 12. For ease of explanation, the heat 20 indicated on each of the semiconductor dies 12A, 12B, and 12C is indicated with a suffix "A," "B," or "C." However, when there is no need to distinguish between them, the heat 20 may be indicated without the suffix "A," "B," or "C."

[0038] An example of the structure of the three-dimensional stacked device 10 according to the first embodiment will be described with reference to Figures 2A and 2B. Figure 2A is a schematic diagram showing the structure of the three-dimensional stacked device 10 when viewed from a direction parallel to the Y direction. Figure 2B is a schematic diagram showing the structure of the three-dimensional stacked device 10 when viewed from a direction parallel to the Z direction. Note that Figure 2B is a schematic diagram of the three-dimensional stacked device 10 shown in Figure 2A when viewed from a direction parallel to the Z direction.

[0039] 2A, the three-dimensional stacked device 10 is composed of a substrate 11, three semiconductor dies 12, and bumps 30. In the three-dimensional stacked device 10, the substrate 11, the semiconductor die 12A, the semiconductor die 12B, and the semiconductor die 12C are stacked in this order from the bottom up. The substrate 11 is a silicon substrate or the like having wiring provided inside or on its surface.

[0040] The three-dimensional stacked device 10 is an SoC in which multiple semiconductor dies are electrically connected by a three-dimensional stacking method.

[0041] Bumps 30, which provide electrical and mechanical connections, are used to connect the substrate 11 and the semiconductor die 12A and to connect the three semiconductor dies 12. There is no limitation on the material of the bumps 30, but they may be made of, for example, Cu, Ag, Ni, or solder-based materials such as Sn—Ag—Cu or Sn—Pb.

[0042] 2A and 2B, when focusing on the positional relationship between the semiconductor die 12A and the semiconductor die 12B, the semiconductor die 12B is disposed on the semiconductor die 12A so that a portion of the semiconductor die 12B does not overlap with the semiconductor die 12A when viewed from a direction parallel to the Z direction. Specifically, the semiconductor die 12B is disposed at a position translated in a direction parallel to the X direction with respect to the semiconductor die 12A.

[0043] Furthermore, when focusing on the positional relationship between the semiconductor die 12B and the semiconductor die 12C, the semiconductor die 12C is disposed on the semiconductor die 12B so that a portion of the semiconductor die 12C does not overlap with the semiconductor die 12B when viewed from a direction parallel to the Z direction. Specifically, the semiconductor die 12C is disposed at a position translated in a direction parallel to the X direction with respect to the semiconductor die 12B.

[0044] As described above, the three-dimensional stacked device 10 has a structure as shown in Figures 2A and 2B, so when viewed from a direction parallel to the Z direction (stacking direction) as shown in Figure 2B, the positions of the heat sources (i.e., heat sources 20A, 20B, and 20C) are misaligned.

[0045] Next, another example of the structure of the three-dimensional stacked device 10 according to the first embodiment will be described with reference to FIGS. 3A and 3B. FIG. 3A is a schematic diagram showing the structure of the three-dimensional stacked device 10 as viewed from a direction parallel to the Y direction. FIG. 3B is a schematic diagram showing the structure of the three-dimensional stacked device 10 as viewed from a direction parallel to the Z direction. Note that FIG. 3B is a schematic diagram of the three-dimensional stacked device 10 shown in FIG. 3A as viewed from a direction parallel to the Z direction. In addition, the description of FIGS. 3A and 3B will focus on differences from the structure of the three-dimensional stacked device 10 shown in FIGS. 2A and 2B.

[0046] 3A and 3B, when focusing on the positional relationship between the semiconductor die 12A and the semiconductor die 12B, the semiconductor die 12B is disposed on the semiconductor die 12A so that a portion of the semiconductor die 12B does not overlap with the semiconductor die 12A when viewed from a direction parallel to the Z direction. Specifically, the semiconductor die 12B is disposed at a position shifted in a direction parallel to the X direction and a direction parallel to the Y direction with respect to the semiconductor die 12A.

[0047] Furthermore, when focusing on the positional relationship between the semiconductor die 12B and the semiconductor die 12C, when viewed from a direction parallel to the Z direction, the semiconductor die 12C is disposed on the semiconductor die 12B so that a portion of the semiconductor die 12C does not overlap with the semiconductor die 12B. Specifically, the semiconductor die 12C is disposed at a position shifted in a direction parallel to the X direction and in a direction parallel to the Y direction with respect to the semiconductor die 12B.

[0048] As described above, the three-dimensional stacked device 10 has a structure as shown in Figures 3A and 3B, so when viewed from a direction parallel to the Z direction (stacking direction) as shown in Figure 3B, the positions of the heat sources (i.e., heat sources 20A, 20B, and 20C) are misaligned.

[0049] The direction in which one semiconductor die 12 moves parallel to another semiconductor die 12 may be any direction included in the XY plane.

[0050] Next, a description will be given of the electrical connections of the three-dimensional stacked device 10 according to embodiment 1. Note that Figures 4 to 6B below are diagrams illustrating the interior of the three-dimensional stacked device 10 in order to explain the electrical connections of the three-dimensional stacked device 10.

[0051] FIG. 4 is a schematic diagram showing an example of the electrical connection relationship of the three-dimensional stacked device 10 according to the first embodiment. In FIG. 4, each of the three semiconductor dies 12 includes a plurality of first bonding pads 16 and a plurality of second bonding pads 17. To avoid cluttering the schematic diagram, only one first bonding pad 16 and one second bonding pad 17 are shown for each semiconductor die 12. The positions of the first bonding pads 16 included in the semiconductor die 12 used in the three-dimensional stacked device 10 shown in FIG. 4 are the same as the positions obtained by translating the second bonding pads 17 within the plane of the lower surface 15 while maintaining their relative positions, when viewed from a direction parallel to the Z direction (stacking direction). This is also true for FIGS. 5A to 6B.

[0052] 4, the lines extending from each bonding pad are lines that schematically show the electrical connection between the substrate 11 and the semiconductor die 12A and the electrical connection between the three semiconductor dies 12, but are not lines that show the exact wiring paths. This is also true in FIGS. 5A to 6B.

[0053] As shown in FIG. 4, focusing on the connection relationship between the substrate 11 and the semiconductor die 12A, the plurality of second bonding pads 17A provided on the semiconductor die 12A are electrically connected to the substrate 11 via bumps 30.

[0054] Furthermore, when attention is paid to the connection relationship between the semiconductor die 12A and the semiconductor die 12B, the plurality of second bonding pads 17B provided on the semiconductor die 12B are electrically connected to the plurality of first bonding pads 16A provided on the semiconductor die 12A via bumps 30. In other words, the semiconductor die 12B is stacked on the semiconductor die 12A so that the positions of the plurality of second bonding pads 17B provided on the semiconductor die 12B and the positions of the plurality of first bonding pads 16A provided on the semiconductor die 12A coincide with and are electrically connected to each other when viewed from a direction perpendicular to the top surface 14 or the bottom surface 15.

[0055] Furthermore, when attention is paid to the connection relationship between the semiconductor die 12B and the semiconductor die 12C, the plurality of second bonding pads 17C provided on the semiconductor die 12C are electrically connected to the plurality of first bonding pads 16B provided on the semiconductor die 12B via bumps 30. In other words, the semiconductor die 12C is stacked on the semiconductor die 12B so that the positions of the plurality of second bonding pads 17C provided on the semiconductor die 12C and the positions of the plurality of first bonding pads 16B provided on the semiconductor die 12B coincide with and are electrically connected to each other when viewed from a direction perpendicular to the top surface 14 or the bottom surface 15.

[0056] Another example of the electrical connection relationship of the three-dimensional stacked device according to embodiment 1 will be described with reference to Figures 5A and 5B. Figure 5A is a schematic diagram showing a first connection pattern in which each of the three semiconductor dies 12 includes a plurality of first bonding pads 16, a plurality of second bonding pads 17, and a plurality of third bonding pads 18. Figure 5B is a schematic diagram showing a second connection pattern in which each of the three semiconductor dies 12 includes a plurality of first bonding pads 16, a plurality of second bonding pads 17, and a plurality of third bonding pads 18.

[0057] 5A and 5B differ from the three semiconductor dies 12 shown in FIG. 4 in that each of the three semiconductor dies 12 further includes a plurality of third bonding pads 18. Similarly to FIG. 4, in order to avoid cluttering the schematic diagrams, each semiconductor die 12 is shown with only one first bonding pad 16, one second bonding pad 17, and one third bonding pad 18. The positions of the plurality of third bonding pads 18 included in the semiconductor die 12 used in the three-dimensional stacked device 10 shown in FIG. 5A and 5B are aligned with the positions of the plurality of second bonding pads 17 translated within the plane of the lower surface 15 while maintaining their relative positions, as viewed in a direction parallel to the Z direction (stacking direction).

[0058] The schematic diagram shown in FIG. 5A differs from the schematic diagram shown in FIG. 4 in that it has a plurality of third bonding pads 18, but the electrical connection relationship between the substrate 11 and the semiconductor die 12A and the electrical connection relationship among the three semiconductor dies 12 are the same as those in the schematic diagram shown in FIG. 4.

[0059] Also in Figure 5B, the electrical connection relationship between the substrate 11 and the semiconductor die 12A is the same as the connection relationship shown in the schematic diagram of Figure 4. Below, differences from Figure 4 will be described.

[0060] 5B , focusing on the connection relationship between the semiconductor die 12A and the semiconductor die 12B, the plurality of second bonding pads 17B of the semiconductor die 12B are electrically connected to the plurality of third bonding pads 18A of the semiconductor die 12A via bumps 30. In other words, the semiconductor die 12B is stacked on the semiconductor die 12A so that the positions of the plurality of second bonding pads 17B of the semiconductor die 12B and the positions of the plurality of third bonding pads 18A of the semiconductor die 12A coincide with and are electrically connected to each other when viewed from a direction perpendicular to the top surface 14 or the bottom surface 15.

[0061] Furthermore, when attention is paid to the connection relationship between the semiconductor die 12B and the semiconductor die 12C, the plurality of second bonding pads 17C provided on the semiconductor die 12C are electrically connected to the plurality of third bonding pads 18B provided on the semiconductor die 12B via bumps 30. In other words, the semiconductor die 12C is stacked on the semiconductor die 12B so that the positions of the plurality of second bonding pads 17C provided on the semiconductor die 12C and the positions of the plurality of third bonding pads 18B provided on the semiconductor die 12B coincide with and are electrically connected to each other when viewed from a direction perpendicular to the top surface 14 or the bottom surface 15.

[0062] 5A and 5B, the distance by which semiconductor die 12B is translated relative to semiconductor die 12A (i.e., the length of the double-headed arrow) and the distance by which semiconductor die 12C is translated relative to semiconductor die 12A (i.e., the length of the double-headed arrow) are different. The length of the double-headed arrow corresponds to the distance by which semiconductor die 12B is translated in the X-Y plane so that the positions of the plurality of second bonding pads 17 on semiconductor die 12 coincide with the positions of the plurality of first bonding pads 16 or the positions of the plurality of third bonding pads 18 on semiconductor die 12, as viewed from a direction parallel to the Z direction.

[0063] As described above, semiconductor die 12 includes a plurality of first bonding pads 16 and a plurality of third bonding pads 18 arranged on upper surface 14, and a plurality of second bonding pads 17 arranged on lower surface 15. Therefore, when stacking a plurality of semiconductor dies 12, a user can appropriately select bonding pads to be connected to the plurality of second bonding pads 17 from the plurality of first bonding pads 16 and the plurality of third bonding pads 18.

[0064] 5A and 5B show the case where the translation distances are all the same, but this is not limiting. For example, the second bonding pads 17B of the semiconductor die 12B may be electrically connected to the first bonding pads 16A of the semiconductor die 12A via bumps 30, respectively, and the second bonding pads 17C of the semiconductor die 12C may be electrically connected to the third bonding pads 18B of the semiconductor die 12B via bumps 30, respectively.

[0065] 6A and 6B , a further example of the electrical connection relationship of the three-dimensional stacked device 10 according to the first embodiment will be described. Fig. 6A is a schematic diagram showing a first connection pattern in which each of the three semiconductor dies 12 includes a plurality of first bonding pads 16, a plurality of second bonding pads 17, and a plurality of fourth bonding pads 19. Fig. 6B is a schematic diagram showing a second connection pattern in which each of the three semiconductor dies 12 includes a plurality of first bonding pads 16, a plurality of second bonding pads 17, and a plurality of fourth bonding pads 19.

[0066] 6A and 6B differ from the three semiconductor dies 12 shown in FIG. 4 in that each of the three semiconductor dies 12 shown in FIG. 6A and 6B further includes a plurality of fourth bonding pads 19. Similarly to FIG. 4, in order to avoid complicating the schematic diagrams, each semiconductor die 12 is shown with only one first bonding pad 16, one second bonding pad 17, and one fourth bonding pad 19. The positions of the plurality of first bonding pads 16 included in the semiconductor die 12 used in the three-dimensional stacked device 10 shown in FIG. 6A and 6B are aligned with the positions of the plurality of fourth bonding pads 19 when translated in parallel within the plane of the lower surface 15 while maintaining their relative positions, as viewed in a direction parallel to the Z direction (stacking direction).

[0067] The schematic diagram shown in FIG. 6A differs from the schematic diagram shown in FIG. 4 in that it has a plurality of fourth bonding pads 19, but the electrical connection relationship between the substrate 11 and the semiconductor die 12A and the electrical connection relationship among the three semiconductor dies 12 are the same as those in the schematic diagram shown in FIG. 4.

[0068] As shown in FIG. 6B, when focusing on the connection relationship between the substrate 11 and the semiconductor die 12A, the plurality of fourth bonding pads 19A provided on the semiconductor die 12A are electrically connected to the substrate 11 via bumps 30.

[0069] Furthermore, when attention is paid to the connection relationship between the semiconductor die 12A and the semiconductor die 12B, the plurality of fourth bonding pads 19B provided on the semiconductor die 12B are electrically connected to the plurality of first bonding pads 16A provided on the semiconductor die 12A via bumps 30. In other words, the semiconductor die 12B is stacked on the semiconductor die 12A so that the positions of the plurality of fourth bonding pads 19B provided on the semiconductor die 12B and the positions of the plurality of first bonding pads 16A provided on the semiconductor die 12A coincide with and are electrically connected to each other when viewed from a direction perpendicular to the top surface 14 or the bottom surface 15.

[0070] Furthermore, when attention is paid to the connection relationship between the semiconductor die 12B and the semiconductor die 12C, the plurality of fourth bonding pads 19C provided on the semiconductor die 12C are electrically connected to the plurality of first bonding pads 16B provided on the semiconductor die 12B via bumps 30. In other words, the semiconductor die 12C is stacked on the semiconductor die 12B so that the positions of the plurality of fourth bonding pads 19C provided on the semiconductor die 12C and the positions of the plurality of first bonding pads 16B provided on the semiconductor die 12B coincide with and are electrically connected to each other when viewed from a direction perpendicular to the top surface 14 or the bottom surface 15.

[0071] 6A and 6B, the distance by which semiconductor die 12B is translated relative to semiconductor die 12A (i.e., the length of the double-headed arrow) and the distance by which semiconductor die 12C is translated relative to semiconductor die 12A (i.e., the length of the double-headed arrow) are different. The length of the double-headed arrow corresponds to the distance by which semiconductor die 12B is translated relative to semiconductor die 12A in the X-Y plane so that the positions of the second bonding pads 17 or the fourth bonding pads 19 on semiconductor die 12 coincide with the positions of the first bonding pads 16 on semiconductor die 12 when viewed from a direction parallel to the Z direction.

[0072] As described above, semiconductor die 12 includes a plurality of first bonding pads 16 arranged on top surface 14, and a plurality of second bonding pads 17 and a plurality of fourth bonding pads 19 arranged on bottom surface 15. Therefore, when stacking a plurality of semiconductor dies 12, a user can appropriately select bonding pads to connect with the plurality of first bonding pads 16 from the plurality of second bonding pads 17 and the plurality of fourth bonding pads 19.

[0073] 6A and 6B show the case where the distances of the translations are all the same, but this is not limiting. For example, the second bonding pads 17B of the semiconductor die 12B may be electrically connected to the first bonding pads 16A of the semiconductor die 12A via bumps 30, respectively, and the fourth bonding pads 19C of the semiconductor die 12C may be electrically connected to the first bonding pads 16B of the semiconductor die 12B via bumps 30, respectively.

[0074] [Comparative Example] Next, as a comparative example, a conventional three-dimensional stacked device 100 will be described with reference to Fig. 7A and Fig. 7B. Fig. 7A is a schematic diagram showing the structure of the three-dimensional stacked device 100 when viewed from a direction parallel to the Y direction. Fig. 7B is a schematic diagram showing the structure of the three-dimensional stacked device 100 when viewed from a direction parallel to the Z direction. Fig. 7B is a schematic diagram of the three-dimensional stacked device 100 shown in Fig. 7A when viewed from a direction parallel to the Z direction.

[0075] 7A, the three-dimensional stacked device 100 is composed of a substrate 101, a semiconductor die 102A, a semiconductor die 102B, a semiconductor die 102C, and bumps 130. In the three-dimensional stacked device 100, the substrate 101, the semiconductor die 102A, the semiconductor die 102B, and the semiconductor die 102C are stacked in this order from the bottom up.

[0076] The substrate 101 is, like the substrate 11, a silicon substrate or the like having wiring provided inside or on its surface.

[0077] The semiconductor die 102A, the semiconductor die 102B, and the semiconductor die 102C are semiconductor chips having the same shape and configuration. In the following description, unless there is a particular need to distinguish between them, they may be simply referred to as "semiconductor die 102."

[0078] Like bumps 30, bumps 130 provide electrical and mechanical connections between substrate 101 and semiconductor die 102A, and between the three semiconductor dies 102.

[0079] Heat 120A indicates the location of the main heat source that generates heat in the semiconductor die 102A when the three-dimensional stacked device 100 is operating. The heat 120A shown on the semiconductor 102A is a mark indicating a location where a particularly large amount of heat is generated inside the semiconductor die 102A. The same applies to heat 120B and 120C. Therefore, when the three-dimensional stacked device 100, in which three semiconductor dies 102 having the same configuration are stacked, is operating, the locations of the heat sources of each of the three semiconductor dies 102 are the same when compared among the individual semiconductor dies 102.

[0080] 7A and 7B, when viewed from a direction parallel to the Z direction, the three semiconductor dies 102 are stacked so as to overlap. Specifically, when viewed from a direction parallel to the Z direction, the three semiconductor dies 102 are stacked so that the four vertices of each of the three semiconductor dies 102 overlap. In other words, in the three-dimensional stacked device 100, when viewed from a direction parallel to the Z direction (stacking direction) as shown in FIG. 7B, the positions of the heat sources (i.e., heat sources 120A, 120B, and 120C) are aligned, thereby increasing the density of the heat sources.

[0081] [Effects, etc.] As described above, the semiconductor die 12 according to this embodiment is a semiconductor die 12 used in a three-dimensional stacked device 10 including a plurality of semiconductor dies 12 having the same configuration and stacked on top of each other, and includes a main body 13 having an upper surface 14 and a lower surface 15, a plurality of first bonding pads 16 arranged on the upper surface 14, and a plurality of second bonding pads 17 arranged on the lower surface 15, wherein the upper surface 14 is one surface of the main body 13, the lower surface 15 is a surface opposite to the upper surface 14, and the positions of the plurality of first bonding pads 16 coincide with the positions of the plurality of second bonding pads 17 moved within the plane of the lower surface 15 while maintaining their positional relationship with each other, when viewed from a direction perpendicular to the upper surface 14 or the lower surface 15.

[0082] According to this, the positions of the plurality of first bonding pads 16 of the semiconductor die 12 are aligned, as viewed perpendicular to the upper surface 14 or the lower surface 15, with the positions of the plurality of second bonding pads 17 moved within the plane of the lower surface 15 while maintaining their relative positions. In other words, when the plurality of semiconductor dies 12 are stacked, the positions of the main heat sources that generate heat in each semiconductor die 12 can be shifted. Therefore, the semiconductor die 12 can reduce the density of heat sources within the three-dimensional stacked device 10 compared to the density of heat sources in the three-dimensional stacked device 100 of the comparative example. Therefore, the semiconductor die 12 can more efficiently dissipate heat generated within the three-dimensional stacked device 10 (i.e., SoC) that includes the same configuration and multiple stacked semiconductor dies 12.

[0083] Furthermore, in the semiconductor die 12 according to this embodiment, the moved positions are positions obtained by moving the second bonding pads 17 in parallel with respect to the first bonding pads 16 .

[0084] According to this, when viewed from a direction perpendicular to the top surface 14 or bottom surface 15, the semiconductor die 12 is arranged in a position where the plurality of first bonding pads 16 do not overlap with the plurality of second bonding pads 17, so that when the plurality of semiconductor dies 12 are stacked, the position of the main heat source that generates heat in each semiconductor die 12 can be shifted. Therefore, the semiconductor dies 12 have the same configuration, and the three-dimensional stacked device 10 (i.e., SoC) including the plurality of stacked semiconductor dies 12 can dissipate internal heat more efficiently.

[0085] In addition, the semiconductor die 12 according to this embodiment further includes a plurality of third bonding pads 18 arranged on the upper surface 14 of the main body 13, and the positions of the plurality of third bonding pads 18 are the same as the positions of the plurality of second bonding pads 17 when moved within the plane of the lower surface 15 while maintaining their relative positions relative to each other, when viewed from a direction perpendicular to the upper surface 14 or the lower surface 15, and the plurality of third bonding pads 18 are each electrically connected to a plurality of first bonding pads 16 arranged on the same main body 13.

[0086] According to this, the semiconductor die 12 further includes a plurality of third bonding pads 18 arranged on the upper surface 14, so that when stacking the plurality of semiconductor dies 12, the user can appropriately select bonding pads to connect to the plurality of second bonding pads 17 from the plurality of first bonding pads 16 and the plurality of third bonding pads 18. Therefore, the user can change the electrical connection paths of the plurality of semiconductor dies 12 depending on the amount of heat generated by each semiconductor die 12.

[0087] In addition, the semiconductor die 12 according to this embodiment further includes a plurality of fourth bonding pads 19 arranged on the lower surface 15 of the main body 13, and the positions of the plurality of first bonding pads 16 are the same as the positions to which the plurality of fourth bonding pads 19 are moved within the plane of the lower surface 15 while maintaining their relative positions relative to each other, when viewed from a direction perpendicular to the upper surface 14 or the lower surface 15, and the plurality of fourth bonding pads 19 are each electrically connected to a plurality of second bonding pads 17 arranged on the same main body 13.

[0088] According to this, the semiconductor die 12 further includes a plurality of fourth bonding pads 19 arranged on the lower surface 15, so that when stacking the plurality of semiconductor dies 12, the user can appropriately select bonding pads to connect to the plurality of first bonding pads 16 from the plurality of second bonding pads 17 and the plurality of fourth bonding pads 19. Therefore, the user can change the electrical connection paths of the plurality of semiconductor dies 12 depending on the amount of heat generated by each semiconductor die 12.

[0089] Furthermore, the three-dimensional stacked device 10 according to this embodiment is a three-dimensional stacked device 10 having a structure in which a plurality of semiconductor dies 12 according to this embodiment are stacked, and the second semiconductor die 12 is stacked on the first semiconductor die 12 so that the positions of the plurality of second bonding pads 17 provided on the second semiconductor die 12 and the positions of the plurality of first bonding pads 16 provided on the first semiconductor die 12 coincide with each other when viewed from a direction perpendicular to the top surface 14 or the bottom surface 15.

[0090] As a result, the semiconductor dies 12 are stacked with the main heat source that generates heat in each semiconductor die 12 shifted in position, so the three-dimensional stacked device 10 can have a lower density of heat sources than the comparative three-dimensional stacked device 100. Therefore, the three-dimensional stacked device 10 (i.e., SoC) can more efficiently dissipate heat generated inside.

[0091] Furthermore, the three-dimensional stacked device 10 according to this embodiment is stacked so that a portion of the second semiconductor die 12 does not overlap with the first semiconductor die 12 when viewed from a direction perpendicular to the top surface 14 or bottom surface 15.

[0092] This allows the three-dimensional stacked device 10 (i.e., SoC) to more efficiently dissipate heat generated internally, since heat is more easily dissipated in areas where a portion of the second semiconductor die 12 does not overlap with the first semiconductor die 12 than in areas where the two semiconductor dies overlap.

[0093] Furthermore, the three-dimensional stacked device 10 according to this embodiment is a three-dimensional stacked device 10 having a structure in which a plurality of semiconductor dies 12 according to this embodiment are stacked, and the second semiconductor die 12 is stacked on the first semiconductor die 12 so that the positions of the plurality of second bonding pads 17 provided on the second semiconductor die 12 and the positions of the plurality of first bonding pads 16 provided on the first semiconductor die 12 coincide with each other when viewed from a direction perpendicular to the upper surface 14 or the lower surface 15, or so that the positions of the plurality of second bonding pads 17 provided on the second semiconductor die 12 coincide with the positions of the plurality of third bonding pads 18 provided on the first semiconductor die 12 when viewed from a direction perpendicular to the upper surface 14 or the lower surface 15.

[0094] This provides the same effects as the above-described three-dimensional stacked device 10. Furthermore, when stacking the second semiconductor die 12 on the first semiconductor die 12, the user can appropriately select the bonding pads to be connected to the second bonding pads 17 from the first bonding pads 16 and the third bonding pads 18. Therefore, the user can change the electrical connection paths of the semiconductor dies 12 depending on the amount of heat generated by each semiconductor die 12.

[0095] Furthermore, the three-dimensional stacked device 10 according to this embodiment is a three-dimensional stacked device 10 having a structure in which a plurality of semiconductor dies 12 according to this embodiment are stacked, and the second semiconductor die 12 is stacked on the first semiconductor die 12 so that the positions of the plurality of second bonding pads 17 provided on the second semiconductor die 12 and the positions of the plurality of first bonding pads 16 provided on the first semiconductor die 12 coincide with each other when viewed from a direction perpendicular to the upper surface 14 or the lower surface 15, or so that the positions of the plurality of fourth bonding pads 19 provided on the second semiconductor die 12 and the positions of the plurality of first bonding pads 16 provided on the first semiconductor die 12 coincide with each other when viewed from a direction perpendicular to the upper surface 14 or the lower surface 15.

[0096] This provides the same effects as the above-described three-dimensional stacked device 10. Furthermore, when stacking the second semiconductor die 12 on the first semiconductor die 12, the user can appropriately select the bonding pads to be connected to the plurality of first bonding pads 16 from the plurality of second bonding pads 17 and the plurality of fourth bonding pads 19. Therefore, the user can change the electrical connection paths of the plurality of semiconductor dies 12 depending on the amount of heat generated by each semiconductor die 12.

[0097] Second Embodiment Next, a second embodiment will be described. In this embodiment, the positional relationship between the bonding pads arranged on the upper surface 14 of the semiconductor die 12 (i.e., the plurality of first bonding pads 16 and the plurality of third bonding pads 18) and the bonding pads arranged on the lower surface 15 of the semiconductor die 12 (i.e., the plurality of second bonding pads 17 and the plurality of fourth bonding pads 19) is different from that in the first embodiment. The following description of this embodiment will focus on the differences from the first embodiment.

[0098] [Semiconductor Die] FIG. 8 is a schematic diagram illustrating an example of the structure of a semiconductor die 12 according to the second embodiment. To avoid complicating the schematic diagram, FIG. 8 illustrates an example of the structure of a semiconductor die 12 that does not include a plurality of third bonding pads 18 and a plurality of fourth bonding pads 19. FIG. 8 also illustrates the interior of the semiconductor die 12 to explain the structure of the semiconductor die 12. Line A-A in FIG. 8 is a straight line passing through a predetermined point T located on the lower surface 15 and parallel to the Z direction. (a) of FIG. 8 is a schematic diagram illustrating the structure of the semiconductor die 12 as viewed from a direction parallel to the Y direction. (b) of FIG. 8 is a schematic diagram illustrating the structure of the semiconductor die 12 as viewed from a direction parallel to the X direction. (c) of FIG. 8 is a schematic diagram illustrating the structure of the semiconductor die 12 as viewed from a direction parallel to the Z direction.

[0099] As shown in FIG. 8 , the first bonding pads 16 are arranged along the Y direction, and the second bonding pads 17 are arranged along the X direction. In other words, the positions of the first bonding pads 16 are the same as the positions of the second bonding pads 17 that are obtained by moving the second bonding pads 17 within the plane of the lower surface 15 while maintaining their relative positions relative to each other, as viewed from a direction perpendicular to the upper surface 14 or the lower surface 15. Specifically, as shown in FIG. 8 (c), the positions of the second bonding pads 17 are the same as the positions of the first bonding pads 16 when viewed from a direction parallel to the Z direction after being rotated 90° counterclockwise around line A-A (i.e., a predetermined point T located on the lower surface 15) within the X-Y plane. If the lower surface 15 of the semiconductor die 12 is rectangular, the predetermined point T may be the intersection of the diagonals of the rectangle.

[0100] Furthermore, a plurality of third bonding pads 18 and a plurality of fourth bonding pads 19 may be arranged. For example, the plurality of third bonding pads 18 may be arranged so that the positions of the plurality of second bonding pads 17 are rotated 45° counterclockwise around a predetermined point T in the X-Y plane and coincide with the positions of the plurality of third bonding pads 18 when viewed from a direction parallel to the Z direction. Furthermore, the fourth bonding pad 19 may be arranged so that the position of the fourth bonding pad 19 is rotated 135° counterclockwise around a predetermined point T in the X-Y plane and coincides with the positions of the plurality of first bonding pads 16 when viewed from a direction parallel to the Z direction. Note that the angles shown above are merely examples, and angles other than those described above may also be used.

[0101] 1 and the rotational movement described in FIG. 8. That is, the second bonding pads 17 may be arranged such that the positions of the second bonding pads 17 are aligned with the positions of the first bonding pads 16 when viewed from a direction parallel to the Z direction by translating the second bonding pads 17 in the X-Y plane relative to the first bonding pads 16 and rotating the second bonding pads 17 about a predetermined point T in the X-Y plane. The same applies to the case where the semiconductor die 12 includes a plurality of third bonding pads 18 and a plurality of fourth bonding pads 19.

[0102] The angles shown in the description of FIG. 8 are merely examples, and other angles such as 30° or 60° may also be used.

[0103] Furthermore, the plurality of first bonding pads 16, the plurality of second bonding pads 17, the plurality of third bonding pads 18, and the plurality of fourth bonding pads 19 do not have to be arranged in a row when viewed from any direction on the X-Y plane.

[0104] [Three-Dimensional Stacked Device] The following describes a three-dimensional stacked device having a structure in which multiple semiconductor dies 12 described above are stacked. Although the following description exemplifies a three-dimensional stacked device in which three semiconductor dies 12 are stacked, any three-dimensional stacked device in which two or more semiconductor dies 12 are stacked is also included in the present disclosure. In the following description, the numerals, such as semiconductor dies 12A, 12B, and 12C, are suffixed with "A," "B," or "C." This distinction is made for ease of explanation; the semiconductor dies 12A, 12B, and 12C each have the same configuration. Therefore, when there is no need to distinguish between them, they may simply be referred to as "semiconductor dies 12." For the same reason, the numerals of the components of the semiconductor dies 12A, 12B, and 12C are suffixed with "A," "B," or "C." Therefore, when there is no need to distinguish between them, they may be referred to without the suffix "A," "B," or "C."

[0105] In the following description, the location of the main heat source that generates heat in the semiconductor die 12 when the three-dimensional stacked device is operating is indicated as heat 20. The heat 20 indicated on the semiconductor die 12 is a mark indicating a location where a particularly large amount of heat is generated inside the semiconductor die 12. Therefore, when a three-dimensional stacked device in which multiple semiconductor dies 12 having the same configuration are stacked is operating, the locations of the heat sources on each of the multiple semiconductor dies 12 are the same when compared among the individual semiconductor dies 12. For ease of explanation, the heat 20 indicated on each of the semiconductor dies 12A, 12B, and 12C is indicated with a suffix "A," "B," or "C" next to the number. Therefore, when there is no need to distinguish between them, the heat 20 may be referred to without the suffix "A," "B," or "C."

[0106] An example of the structure of the three-dimensional stacked device 10 according to the second embodiment will be described with reference to Figures 9A and 9B. Figure 9A is a schematic diagram showing the structure of the three-dimensional stacked device 10 when viewed from a direction parallel to the Y direction. Figure 9B is a schematic diagram showing the structure of the three-dimensional stacked device 10 when viewed from a direction parallel to the Z direction. Note that Figure 9B is a schematic diagram of the three-dimensional stacked device 10 shown in Figure 9A when viewed from a direction parallel to the Z direction.

[0107] As shown in Figures 9A and 9B, when focusing on the positional relationship between the semiconductor die 12A and the semiconductor die 12B, the semiconductor die 12B is in a positional relationship rotated 90 degrees counterclockwise with respect to the semiconductor die 12A around line AA as the central axis.

[0108] Furthermore, when attention is paid to the positional relationship between the semiconductor die 12B and the semiconductor die 12C, the semiconductor die 12C is rotated 90 degrees counterclockwise around the central axis AA relative to the semiconductor die 12B.

[0109] 9A and 9B, the positions of the heat sources (i.e., heat sources 20A, 20B, and 20C) are shifted when viewed in a direction parallel to the Z direction (stacking direction) as shown in Fig. 9B. This allows the three-dimensional stacked device 10 to have a lower density of heat sources than the three-dimensional stacked device 100 of the comparative example.

[0110] 9B , when the shape of the semiconductor die 12 is not square when viewed in a direction parallel to the Z direction (stacking direction), there will be regions where the two semiconductor dies 12 connected by the bumps 30 do not overlap. This makes it easier for heat to be dissipated in the regions where the two semiconductor dies 12 do not overlap than in the regions where the two semiconductor dies overlap, allowing the three-dimensional stacked device 10 to dissipate heat more efficiently.

[0111] 9B , when the semiconductor die 12 has a square shape, the two semiconductor dies 12 connected by the bumps 30 overlap when viewed in a direction parallel to the Z direction (stacking direction). In other words, when viewed in a direction parallel to the Z direction, the two semiconductor dies are stacked so that the four vertices of each of the two semiconductor dies overlap. This three-dimensional stacked device 10 has the same shape as the three-dimensional stacked device 100 of the comparative example, and therefore, it is easy to change the design from the three-dimensional stacked device 100 of the comparative example.

[0112] Another example of the structure of the three-dimensional stacked device 10 according to the second embodiment will be described with reference to Fig. 10A and Fig. 10B. Fig. 10A is a schematic diagram showing the structure of the three-dimensional stacked device 10 when viewed from a direction parallel to the Y direction. Fig. 10B is a schematic diagram showing the structure of the three-dimensional stacked device 10 when viewed from a direction parallel to the Z direction. Fig. 10B is a schematic diagram of the three-dimensional stacked device 10 shown in Fig. 10A when viewed from a direction parallel to the Z direction.

[0113] As shown in Figures 10A and 10B, when focusing on the positional relationship between the semiconductor die 12A and the semiconductor die 12B, the semiconductor die 12B is in a positional relationship rotated 45 degrees counterclockwise with respect to the semiconductor die 12A around line AA as the central axis.

[0114] Furthermore, when attention is paid to the positional relationship between the semiconductor die 12B and the semiconductor die 12C, the semiconductor die 12C is rotated 45 degrees counterclockwise with respect to the semiconductor die 12B about the line AA as the central axis.

[0115] 10A and 10B, the positions of the heat sources (i.e., heat sources 20A, 20B, and 20C) are shifted when viewed in a direction parallel to the Z direction (stacking direction) as shown in Fig. 10B. This allows the three-dimensional stacked device 10 to have a lower density of heat sources than the three-dimensional stacked device 100 of the comparative example.

[0116] The angles shown in the explanation of FIGS. 9A to 10B are merely examples, and other angles such as 30° or 60° may also be used.

[0117] 9A to 10B, the rotation angles are all the same, but this is not limiting. For example, the semiconductor die 12B may be rotated 90 degrees counterclockwise around the line A-A relative to the semiconductor die 12A, and the semiconductor die 12C may be rotated 45 degrees counterclockwise around the line A-A relative to the semiconductor die 12B.

[0118] Next, the electrical connections of the three-dimensional stacked device 10 according to this embodiment will be described with reference to FIG. 11 . FIG. 11 is a schematic diagram illustrating the electrical connections of the three-dimensional stacked device 10 shown in FIGS. 9A and 9B . The positions of the first bonding pads 16 provided on the semiconductor die 12 used in the three-dimensional stacked device 10 shown in FIG. 11 are the same as the positions obtained by rotating the second bonding pads 17 90° counterclockwise around line A-A on the lower surface 15 while maintaining their relative positions, as viewed from a direction parallel to the Z direction (stacking direction). To avoid complicating the schematic diagram, FIG. 11 also illustrates an example of the structure of a semiconductor die 12 that does not include third bonding pads 18 and fourth bonding pads 19. FIG. 11 is a diagram illustrating the interior of the three-dimensional stacked device 10 to explain the electrical connections of the three-dimensional stacked device 10.

[0119] Also, in Figure 11, the lines extending from each bonding pad are lines that schematically indicate the electrical connection between the substrate 11 and the semiconductor die 12A, and the electrical connection between the three semiconductor dies 12, and do not indicate the exact wiring path.

[0120] As shown in FIG. 11, focusing on the connection relationship between the substrate 11 and the semiconductor die 12A, the plurality of second bonding pads 17A provided on the semiconductor die 12A are electrically connected to the substrate 11 via bumps 30.

[0121] Furthermore, when attention is paid to the connection relationship between the semiconductor die 12A and the semiconductor die 12B, the plurality of second bonding pads 17B provided on the semiconductor die 12B are electrically connected to the plurality of first bonding pads 16A provided on the semiconductor die 12A via bumps 30. In other words, the semiconductor die 12B is stacked on the semiconductor die 12A so that the positions of the plurality of second bonding pads 17B provided on the semiconductor die 12B and the positions of the plurality of first bonding pads 16A provided on the semiconductor die 12A coincide with and are electrically connected to each other when viewed from a direction perpendicular to the top surface 14 or the bottom surface 15.

[0122] Furthermore, when attention is paid to the connection relationship between the semiconductor die 12B and the semiconductor die 12C, the plurality of second bonding pads 17C provided on the semiconductor die 12C are electrically connected to the plurality of first bonding pads 16B provided on the semiconductor die 12B via bumps 30. In other words, the semiconductor die 12C is stacked on the semiconductor die 12B so that the positions of the plurality of second bonding pads 17C provided on the semiconductor die 12C and the positions of the plurality of first bonding pads 16B provided on the semiconductor die 12B coincide with and are electrically connected to each other when viewed from a direction perpendicular to the top surface 14 or the bottom surface 15.

[0123] The same applies to the case where the semiconductor die 12 includes a plurality of third bonding pads 18. For example, the semiconductor die 12B may be stacked on the semiconductor die 12A so that the positions of the plurality of second bonding pads 17B on the semiconductor die 12B and the positions of the plurality of third bonding pads 18A on the semiconductor die 12A coincide with and are electrically connected to each other when viewed from a direction perpendicular to the top surface 14 or the bottom surface 15. The same applies to the case where the semiconductor die 12 includes a plurality of fourth bonding pads 19.

[0124] [Modification of Three-Dimensional Stacked Device] Next, a modification of the three-dimensional stacked device 10 according to the second embodiment will be described with reference to Fig. 12A and Fig. 12B. Fig. 12A is a schematic diagram showing the structure of the three-dimensional stacked device 10 when viewed from a direction parallel to the Y direction. Fig. 12B is a schematic diagram showing the structure of the three-dimensional stacked device 10 when viewed from a direction parallel to the Z direction. Fig. 12B is a schematic diagram of the three-dimensional stacked device 10 shown in Fig. 12A when viewed from a direction parallel to the Z direction.

[0125] As shown in Figures 12A and 12B, when focusing on the positional relationship between the semiconductor die 12A and the semiconductor die 12B, the semiconductor die 12B is in a positional relationship in which it has moved parallel to the semiconductor die 12A in the direction of the arrow (a direction parallel to the X direction) and then rotated 90 degrees counterclockwise around line A-A as the central axis.

[0126] Furthermore, when attention is paid to the positional relationship between semiconductor die 12B and semiconductor die 12C, semiconductor die 12C is in a position where it has been translated in the direction of the arrow (parallel to the Y direction) relative to semiconductor die 12B, and then rotated 90 degrees counterclockwise around line A-A as the central axis.

[0127] 12A and 12B, the positions of the heat sources (i.e., heat sources 20A, 20B, and 20C) are shifted when viewed in a direction parallel to the Z direction (stacking direction) as shown in Fig. 12B. This allows the three-dimensional stacked device 10 to have a lower density of heat sources than the three-dimensional stacked device 100 of the comparative example.

[0128] The electrical connection relationships of the three-dimensional stacked device 10 shown in Figures 12A and 12B can be realized by combining the electrical connection relationships shown in Figures 4 to 6B with the electrical connection relationship shown in Figure 11.

[0129] [Effects, etc.] As described above, in the semiconductor die 12 according to this embodiment, the moved position is a position where the plurality of second bonding pads 17 are rotated around a predetermined point T located on the lower surface 15.

[0130] According to this, when viewed from a direction perpendicular to the top surface 14 or bottom surface 15, the semiconductor die 12 is arranged in a position where the plurality of first bonding pads 16 do not overlap with the plurality of second bonding pads 17, so that when the plurality of semiconductor dies 12 are stacked, the position of the main heat source that generates heat in each semiconductor die 12 can be shifted. Therefore, the semiconductor die 12 can more efficiently dissipate heat generated inside the three-dimensional stacked device 10 (i.e., SoC).

[0131] Furthermore, in the semiconductor die 12 according to this embodiment, if the semiconductor die 12 is rectangular, the predetermined point T may be the intersection of the diagonals of the rectangle.

[0132] According to this, when viewed from a direction perpendicular to the top surface 14 or bottom surface 15, the semiconductor die 12 is arranged in a position where the plurality of first bonding pads 16 do not overlap with the plurality of second bonding pads 17, so that when the plurality of semiconductor dies 12 are stacked, the position of the main heat source that generates heat in each semiconductor die 12 can be shifted. Therefore, the semiconductor die 12 can more efficiently dissipate heat generated inside the three-dimensional stacked device 10 (i.e., SoC).

[0133] Furthermore, in the semiconductor die 12 according to this embodiment, the moved position is a position where the plurality of second bonding pads 17 are moved parallel to the plurality of first bonding pads 16, and the plurality of second bonding pads 17 are rotated around a predetermined point T located on the lower surface 15.

[0134] According to this, when viewed from a direction perpendicular to the top surface 14 or bottom surface 15, the semiconductor die 12 is arranged in a position where the plurality of first bonding pads 16 do not overlap with the plurality of second bonding pads 17, so that when the plurality of semiconductor dies 12 are stacked, the position of the main heat source that generates heat in each semiconductor die 12 can be shifted. Therefore, the semiconductor die 12 can more efficiently dissipate heat generated inside the three-dimensional stacked device 10 (i.e., SoC).

[0135] Furthermore, the three-dimensional stacked device 10 according to this embodiment is a three-dimensional stacked device 10 having a structure in which a plurality of semiconductor dies 12 according to this embodiment are stacked, and the second semiconductor die 12 is stacked on the first semiconductor die 12 so that the positions of the plurality of second bonding pads 17 provided on the second semiconductor die 12 and the positions of the plurality of first bonding pads 16 provided on the first semiconductor die 12 coincide with each other when viewed from a direction perpendicular to the top surface 14 or the bottom surface 15.

[0136] As a result, the semiconductor dies 12 are stacked with the main heat source that generates heat in each semiconductor die 12 shifted in position, so the three-dimensional stacked device 10 can have a lower density of heat sources than the comparative three-dimensional stacked device 100. Therefore, the three-dimensional stacked device 10 (i.e., SoC) can more efficiently dissipate heat generated inside.

[0137] Furthermore, the three-dimensional stacked device 10 according to this embodiment is stacked so that a portion of the second semiconductor die 12 does not overlap with the first semiconductor die 12 when viewed from a direction perpendicular to the top surface 14 or bottom surface 15.

[0138] This allows the three-dimensional stacked device 10 (i.e., SoC) to more efficiently dissipate heat generated internally, since heat is more easily dissipated in areas where a portion of the second semiconductor die 12 does not overlap with the first semiconductor die 12 than in areas where the two semiconductor dies overlap.

[0139] Furthermore, the three-dimensional stacked device 10 according to this embodiment is a three-dimensional stacked device 10 having a structure in which a plurality of semiconductor dies 12 according to this embodiment are stacked, and the second semiconductor die 12 is stacked on the first semiconductor die 12 so that the positions of the plurality of second bonding pads 17 provided on the second semiconductor die 12 and the positions of the plurality of first bonding pads 16 provided on the first semiconductor die 12 coincide with each other when viewed from a direction perpendicular to the upper surface 14 or the lower surface 15, or so that the positions of the plurality of second bonding pads 17 provided on the second semiconductor die 12 coincide with the positions of the plurality of third bonding pads 18 provided on the first semiconductor die 12 when viewed from a direction perpendicular to the upper surface 14 or the lower surface 15.

[0140] This provides the same effects as the above-described three-dimensional stacked device 10. Furthermore, when stacking the second semiconductor die 12 on the first semiconductor die 12, the user can appropriately select the bonding pads to be connected to the second bonding pads 17 from the first bonding pads 16 and the third bonding pads 18. Therefore, the user can change the electrical connection paths of the semiconductor dies 12 depending on the amount of heat generated by each semiconductor die 12.

[0141] Furthermore, the three-dimensional stacked device 10 according to this embodiment is a three-dimensional stacked device 10 having a structure in which a plurality of semiconductor dies 12 according to this embodiment are stacked, and the second semiconductor die 12 is stacked on the first semiconductor die 12 so that the positions of the plurality of second bonding pads 17 provided on the second semiconductor die 12 and the positions of the plurality of first bonding pads 16 provided on the first semiconductor die 12 coincide with each other when viewed from a direction perpendicular to the upper surface 14 or the lower surface 15, or so that the positions of the plurality of fourth bonding pads 19 provided on the second semiconductor die 12 and the positions of the plurality of first bonding pads 16 provided on the first semiconductor die 12 coincide with each other when viewed from a direction perpendicular to the upper surface 14 or the lower surface 15.

[0142] This provides the same effects as the above-described three-dimensional stacked device 10. Furthermore, when stacking the second semiconductor die 12 on the first semiconductor die 12, the user can appropriately select the bonding pads to be connected to the plurality of first bonding pads 16 from the plurality of second bonding pads 17 and the plurality of fourth bonding pads 19. Therefore, the user can change the electrical connection paths of the plurality of semiconductor dies 12 depending on the amount of heat generated by each semiconductor die 12.

[0143] (Other Modifications) Although the semiconductor die and three-dimensional stacked device according to the present disclosure have been described above based on the embodiments, the present disclosure is not limited to the above-described embodiments.

[0144] In addition, this disclosure also includes forms obtained by making various modifications to the above embodiments that a person skilled in the art would think of, and forms realized by arbitrarily combining the components and functions in the embodiments within the scope of the present disclosure.

[0145] For example, in the first and second embodiments, the first and third bonding pads 16 and 18 on the top surface of the semiconductor die 12 and the second and fourth bonding pads 17 and 19 on the bottom surface of the semiconductor die 12 are described as being a set and are electrically connected inside the semiconductor die 12. However, the same effect can be achieved even if this limitation is not present. That is, the same effect can be achieved even if the first and third bonding pads 16 and 18 on the top surface of the semiconductor die 12 are not electrically connected to the second and fourth bonding pads 17 and 19 on the bottom surface of the semiconductor die 12, i.e., even if the second and fourth bonding pads 17 and 19 on the bottom surface of the semiconductor die 12 stacked above are simply connected to the first and third bonding pads 16 and 18 on the top surface of the semiconductor die 12 stacked below.

[0146] Examples of the semiconductor die and three-dimensional stacked device according to the present disclosure that have been described based on the above embodiments are shown below. The semiconductor die and three-dimensional stacked device according to the present disclosure are not limited to the following examples.

[0147] For example, a semiconductor die according to a first aspect of the present disclosure is a semiconductor die used in a three-dimensional stacked device having a plurality of semiconductor dies having the same configuration and stacked on top of each other, the semiconductor die comprising a main body having an upper surface and a lower surface, a plurality of first bonding pads arranged on the upper surface, and a plurality of second bonding pads arranged on the lower surface, the upper surface being one surface of the main body, the lower surface being a surface opposite to the upper surface, and the positions of the plurality of first bonding pads being positions that coincide with positions where the plurality of second bonding pads are moved within the plane of the lower surface while maintaining their relative positions relative to each other, when viewed from a direction perpendicular to the upper surface or the lower surface.

[0148] Also, for example, a semiconductor die according to a second aspect of the present disclosure is a semiconductor die according to the first aspect, and the moved position is a position where the plurality of second bonding pads are moved parallel to the plurality of first bonding pads.

[0149] Also, for example, a semiconductor die according to a third aspect of the present disclosure is a semiconductor die according to the first aspect, and the moved position is a position where the plurality of second bonding pads are rotated around a predetermined point located on the underside.

[0150] Also, for example, a semiconductor die according to a fourth aspect of the present disclosure is the semiconductor die according to the third aspect, and when the semiconductor die is rectangular, the predetermined point is an intersection of diagonals of the rectangle.

[0151] Also, for example, a semiconductor die according to a fifth aspect of the present disclosure is a semiconductor die according to the first aspect, and the moved position is a position obtained by moving the plurality of second bonding pads parallel to the plurality of first bonding pads and rotating the plurality of second bonding pads around a predetermined point located on the underside.

[0152] Furthermore, for example, a semiconductor die according to a sixth aspect of the present disclosure is a semiconductor die according to any one of the first to fifth aspects, further comprising a plurality of third bonding pads arranged on the upper surface of the main body, the positions of the plurality of third bonding pads being aligned with the positions of the plurality of second bonding pads moved within the plane of the lower surface while maintaining their relative positions relative to each other, when viewed from a direction perpendicular to the upper or lower surface, and the plurality of third bonding pads being electrically connected to the plurality of first bonding pads arranged on the same main body.

[0153] Also, for example, a semiconductor die according to a seventh aspect of the present disclosure is a semiconductor die according to any one of the first to sixth aspects, further comprising a plurality of fourth bonding pads arranged on the underside of the main body, the positions of the plurality of first bonding pads being aligned with the positions of the plurality of fourth bonding pads moved within the plane of the underside while maintaining their relative positions relative to each other, when viewed from the top surface or a direction perpendicular to the underside, and the plurality of fourth bonding pads being electrically connected to the plurality of second bonding pads arranged on the same main body, respectively.

[0154] Furthermore, for example, a three-dimensional stacked device according to an eighth aspect of the present disclosure is a three-dimensional stacked device in which a plurality of semiconductor dies according to any one of the first to seventh aspects are stacked, and the second semiconductor die is stacked on the first semiconductor die so that the positions of the plurality of second bonding pads on the second semiconductor die and the positions of the plurality of first bonding pads on the first semiconductor die coincide when viewed from a direction perpendicular to the top surface or the bottom surface.

[0155] Also, for example, a three-dimensional stacked device according to a ninth aspect of the present disclosure is a three-dimensional stacked device according to the eighth aspect, in which the second semiconductor die is stacked so that a portion of the second semiconductor die does not overlap with the first semiconductor die when viewed from a direction perpendicular to the top surface or the bottom surface.

[0156] Furthermore, for example, a three-dimensional stacked device according to a tenth aspect of the present disclosure is a three-dimensional stacked device in which a plurality of semiconductor dies according to the sixth aspect are stacked, and the second semiconductor die is stacked on the first semiconductor die so that the positions of the second bonding pads on the second semiconductor die and the positions of the first bonding pads on the first semiconductor die coincide with each other when viewed from a direction perpendicular to the top surface or the bottom surface, or so that the positions of the second bonding pads on the second semiconductor die and the positions of the third bonding pads on the first semiconductor die coincide with each other when viewed from a direction perpendicular to the top surface or the bottom surface.

[0157] Furthermore, for example, a three-dimensional stacked device according to an eleventh aspect of the present disclosure is a three-dimensional stacked device in which a plurality of semiconductor dies according to the seventh aspect are stacked, and the second semiconductor die is stacked on the first semiconductor die so that the positions of the plurality of second bonding pads on the second semiconductor die and the positions of the plurality of first bonding pads on the first semiconductor die coincide with each other when viewed from a direction perpendicular to the top surface or the bottom surface, or so that the positions of the plurality of fourth bonding pads on the second semiconductor die and the positions of the plurality of first bonding pads on the first semiconductor die coincide with each other when viewed from a direction perpendicular to the top surface or the bottom surface.

[0158] Furthermore, for example, a three-dimensional stacked device according to a twelfth aspect of the present disclosure is a three-dimensional stacked device according to the tenth or eleventh aspect, in which the second semiconductor die is stacked so that a portion of the second semiconductor die does not overlap with the first semiconductor die when viewed from a direction perpendicular to the top surface or the bottom surface.

[0159] The semiconductor die and the like according to the present disclosure can be used in various electrical devices that use semiconductor chips.

[0160] 10, 100 Three-dimensional stacked device 11, 101 Substrate 12, 12A, 12B, 12C, 102, 102A, 102B, 102C Semiconductor die 13, 13A, 13B, 13C Body 14, 14A, 14B, 14C Top surface 15, 15A, 15B, 15C Bottom surface 16, 16A, 16B, 16C First bonding pad 17, 17A, 17B, 17C Second bonding pad 18, 18A, 18B, 18C Third bonding pad 19, 19A, 19B, 19C Fourth bonding pad 20, 20A, 20B, 20C, 120A, 120B, 120C Heat 30, 130 Bump T Predetermined point

Claims

1. A semiconductor die used in a three-dimensional stacked device comprising a plurality of semiconductor dies having the same configuration and stacked on top of each other, comprising: a main body having an upper surface and a lower surface; a plurality of first bonding pads arranged on the upper surface; and a plurality of second bonding pads arranged on the lower surface, wherein the upper surface is one surface of the main body, and the lower surface is a surface opposite to the upper surface, and the positions of the plurality of first bonding pads are aligned with the positions of the plurality of second bonding pads moved within the plane of the lower surface while maintaining their relative positions, when viewed from a direction perpendicular to the upper surface or the lower surface.

2. The semiconductor die of claim 1, wherein the moved positions are positions obtained by translating the second plurality of bonding pads relative to the first plurality of bonding pads.

3. The semiconductor die according to claim 1, wherein the moved positions are positions obtained by rotating the plurality of second bonding pads about a predetermined point located on the lower surface.

4. The semiconductor die according to claim 3, wherein, when the semiconductor die is rectangular, the predetermined point is an intersection of diagonals of the rectangle.

5. The semiconductor die of claim 1, wherein the moved positions are obtained by translating the second bonding pads relative to the first bonding pads and by rotating the second bonding pads about a predetermined point on the lower surface.

6. The semiconductor die of claim 1, further comprising a plurality of third bonding pads arranged on the upper surface of said body, the positions of said third bonding pads being aligned with the positions of said second bonding pads moved within the plane of said lower surface while maintaining their relative positions, when viewed from a direction perpendicular to said upper surface or said lower surface, and said third bonding pads being electrically connected to said plurality of first bonding pads arranged on the same body.

7. The semiconductor die of claim 1, further comprising a plurality of fourth bonding pads arranged on the underside of said body, wherein the positions of said plurality of first bonding pads coincide with positions where said plurality of fourth bonding pads are moved within the plane of said underside while maintaining their relative positions relative to one another, as viewed from the top surface or a direction perpendicular to said underside, and said plurality of fourth bonding pads are each electrically connected to said plurality of second bonding pads arranged on the same body.

8. A three-dimensional stacked device having a structure in which a plurality of semiconductor dies according to any one of claims 1 to 5 are stacked, wherein the second semiconductor die is stacked on the first semiconductor die so that the positions of the plurality of second bonding pads on the second semiconductor die and the positions of the plurality of first bonding pads on the first semiconductor die are aligned when viewed from a direction perpendicular to the top surface or the bottom surface.

9. The three-dimensional stacked device according to claim 8, wherein the second semiconductor die is stacked so that a portion of the second semiconductor die does not overlap the first semiconductor die when viewed from a direction perpendicular to the top surface or the bottom surface.

10. A three-dimensional stacked device having a structure in which a plurality of semiconductor dies according to claim 6 are stacked, wherein the second semiconductor die is stacked on the first semiconductor die so that the positions of the second bonding pads on the second semiconductor die and the positions of the first bonding pads on the first semiconductor die coincide when viewed from a direction perpendicular to the top surface or the bottom surface, or so that the positions of the second bonding pads on the second semiconductor die and the positions of the third bonding pads on the first semiconductor die coincide when viewed from a direction perpendicular to the top surface or the bottom surface.

11. A three-dimensional stacked device having a structure in which a plurality of semiconductor dies according to claim 7 are stacked, wherein the second semiconductor die is stacked on the first semiconductor die so that the positions of the plurality of second bonding pads on the second semiconductor die and the positions of the plurality of first bonding pads on the first semiconductor die coincide when viewed from a direction perpendicular to the top surface or the bottom surface, or so that the positions of the plurality of fourth bonding pads on the second semiconductor die and the positions of the plurality of first bonding pads on the first semiconductor die coincide when viewed from a direction perpendicular to the top surface or the bottom surface.

12. The three-dimensional stacked device according to claim 10 or 11, wherein the second semiconductor die is stacked so that a portion of the second semiconductor die does not overlap the first semiconductor die when viewed from a direction perpendicular to the top surface or the bottom surface.

Images