Modular multi-level cascade converter and control method for same

Abstract

This modular multi-level cascade converter has a plurality of cells per phase, each cell comprising an AC-DC converter ACDC, a primary-side DC capacitor C1, an insulated DC-DC converter DCDC, and a secondary-side DC capacitor C2. The converter has a plurality of DC systems in each of which a plurality of secondary-side DC capacitors C2 are connected in parallel. The voltages of the plurality of DC systems are supplied to a load or a power supply. When a cell fails, a control unit for the AC-DC converter ACDC increases the output voltage on the AC system side of a cell connected to the same DC system as that of the failed cell, and reduces the output voltage on the AC system side of a cell connected to another DC system. A third harmonic is superimposed on the AC output voltage of the cell connected to the same DC system as that of the failed cell, and a reverse third harmonic is superimposed on the AC output voltage of the cell connected to the DC system different from that of the failed cell. This prevents the problem that, when an operation is continued in the event of failure of some of the cells, an SST cannot output a prescribed AC voltage required for system interconnection.

Description

Modular multilevel cascade converter and control method thereof

[0001] The present invention relates to a modular multilevel cascade converter (MMCC) of single star bridge cells (SSBC) connected to a three-phase AC system, in which a bidirectional isolated DC / DC converter (isolated DC / DC converter) or the like is connected to the DC side of the full bridge cells (AC / DC converter) that make up the converter, enabling multiple DC systems to be output.

[0002] A typical example of this configuration is a solid-state transformer (SST). Figure 1 shows an SST consisting of m = 4 cells per phase, which combines an MMCC-SSBC configured by cascading AC-DC converters ACDC with an isolated DC-DC converter DCDC using a dual active bridge (DAB) system. A cell consists of an AC-DC converter ACDC, an isolated DC-DC converter DCDC, and capacitors C1 and C2.

[0003] High-voltage AC power is converted into DC power using series-connected cells, and the DC power is converted into high-frequency AC power, which is then insulated and rectified using a transformer to convert back into DC power. Reverse power interchange is also possible. Because SST uses a high-frequency transformer, it can be made smaller than conventional commercial frequency transformers.

[0004] Isolated DC-DC converter DCDC: By connecting the output terminals of 3m / x (6 units) in parallel, it is possible to output x (2) isolated DC systems with the same capacity. By connecting multiple DC systems in series, it is also possible to obtain a high DC voltage.

[0005] In cases where high reliability is required, such as when important loads are connected to a DC system, it is necessary to realize a fault tolerance function that allows operation to continue even if some of the cells that make up the SST fail.

[0006] If a fault occurs inside a cell, such as an open or short circuit caused by a broken conductor, or an open or short circuit in one of the switching devices, the output terminal on the three-phase AC system side can be short-circuited using the remaining healthy switching devices or a separately provided mechanical switch, and the output terminal on the DC system side can be opened, thereby preventing the effects of the fault from spreading to other cells.

[0007] However, the next problem is balancing the voltage of the DC capacitor (primary DC voltage) connected to the AC grid side of the remaining cells' high-frequency transformers, and the voltage of each stage connected in series at the output. Also, as the ratio of faulty cells to the total number of cells increases, the MMCC-SSBC is more likely to be unable to output the AC voltage required for grid connection.

[0008] Patent Document 6 discloses a control method for uniformly maintaining the primary DC voltage inside the cell and the voltage of the output DC system in the SST shown in Fig. 1. The control method in Patent Document 6 is configured by the following feedback control.

[0009] (1) Primary side DC voltage average value control If the average value of the primary side DC voltage is lower than the command value, active power is input from the AC system; if it is higher, the AC output current of the MMCC-SSBC is adjusted so that active power is output to the AC system.

[0010] (2) Primary DC voltage intra-phase balance control The primary DC voltage of a cell connected to a phase of the AC system is compared with the average primary DC voltage of all cells connected to the same phase, and the AC output voltage of the AC-DC converter for that cell is adjusted. If the primary DC voltage of a cell is high and power is flowing in from the AC system, the AC voltage is reduced to suppress charging. If the power is flowing in the opposite direction to the AC system, the AC voltage is increased to encourage discharge.

[0011] (3) Individual primary DC voltage balance control: Current control of the isolated DC-DC converter DCDC is performed so that the primary DC voltages of all cells connected to a DC system are equal. Cells with high primary DC voltages increase the power transferred from the AC system to the DC system via the isolated DC-DC converter DCDC, while cells with low primary DC voltages reduce the power transferred from the AC system to the DC system via the isolated DC-DC converter DCDC.

[0012] (4) Individual control of secondary DC voltage The voltage of the DC capacitor inside the cell that is closer to the DC system than the high-frequency transformer, i.e., the voltage of the DC system (secondary DC voltage), is adjusted to be equal to the command value.

[0013] Patent Documents 1, 2, and 3 disclose a method in which, when a cell constituting a converter fails, a switch connected to one of the input / output terminals of the cell is turned on to short-circuit the terminals, thereby preventing the effects of the failure from spreading to other cells and allowing operation to continue.

[0014] In addition, Patent Document 1 assumes that either AC or DC power is input and DC power is output, and the cells on the output side are connected in series (the input side can be either parallel or series). If some cells fail, the DC capacitor voltage on the output side of the series-connected cells can be increased to obtain an output voltage from the converter with the same amplitude as before the failure.

[0015] Patent Document 2 describes a technology that assumes the mutual conversion of two AC power sources and applies it to a configuration in which both the input and output terminals of the cells are connected in series. If one of the cells fails, the switch on the failed side of the input and output terminals of the cell is short-circuited, and the other terminal is controlled to maintain a constant DC capacitor voltage inside the cell, thereby enabling the converter to obtain an output voltage with the same amplitude as before the failure.

[0016] Furthermore, in Patent Document 2, the waveform before the failure is shown in Figure 5, and the waveform after the failure is shown in Figure 6. The pulse width of the AC output voltages (Vo2 to Vo4) of the non-failed cells increases. In other words, the AC output voltage of the converter is made equal before and after the failure by operating with the highest priority on increasing amplitude even if the distortion of the AC output voltage of the non-failed cells worsens, and by removing the distortion of the failed cell.

[0017] Patent Document 3 describes a technology that assumes the mutual conversion of two DC power sources, and applies it to a configuration in which one cell is connected in parallel and the other in series within the unit that makes up the converter. If one cell fails, the voltage of the DC capacitor on the parallel-connected side of the cells remains unchanged, while the voltage of the DC capacitor on the series-connected side is increased. With Patent Document 3, the voltage of the DC system on the series-connected side does not change before and after the failure. Furthermore, the input and output power are equal, allowing for continued stable operation.

[0018] Non-Patent Document 1 and Patent Documents 4 and 5 disclose techniques for lowering the peak of a voltage command value by superimposing a third harmonic on an output phase voltage command value, thereby enabling an AC voltage of larger amplitude to be output, and preventing the superimposed third harmonic from affecting the line voltage.

[0019] Patent Documents 7 and 8 disclose techniques for superimposing a zero-phase sequence voltage of the fundamental wave so that the amplitude of the AC voltage output from the SST can be maintained even when some cells fail.

[0020] Patent No. 6476318 Publication Patent No. 6725758 Publication Patent No. 6976426 Publication JP-A-3-107373 Publication JP-A-2022-107230 Patent Application No. 2023-191251 Patent Application No. 2023-215645 Patent Application No. 2023-215646

[0021] "Sensorless Vector Control of AC Drive Systems," Institute of Electrical Engineers of Japan, Research Committee on Sensorless Vector Control, Ohmsha, pp. 54 (2016)

[0022] In order to operate the SST stably, it is necessary to improve the stability of the primary side DC voltage inside the cell and the voltage balance of the output DC system even when a power imbalance in each DC system, a sudden load change, or a cell failure occurs. One possible method for achieving this is the method described in Patent Document 6 (2) in which the AC output voltage of the AC-DC converter ACDC of the cell is adjusted by feedforward for the primary side DC voltage intra-phase balance control.

[0023] The following methods can also be considered to maintain an equal DC voltage in each DC system: ・Other cells connected to the DC system where the faulty cell is located have their AC output voltage set to be larger than the remaining cells. ・The amplitude ratio of the AC output voltages of other cells in the DC system where the faulty cell is located: remaining cells = 3m:3m-x (= 6:5).

[0024] As a result, the power transferred from the AC system to each DC system can be made equal, and the primary voltage inside the cell and the DC voltage of each secondary DC system are both balanced.

[0025] However, the above methods require increasing the AC output voltage of the cell's AC-DC converter ACDC. However, the maximum amplitude of the cell's AC output voltage is limited by the primary DC voltage. Therefore, there is a limit to how much the cell's AC output voltage can be increased. Lowering the AC output voltage of cells connected to a DC system without a faulty cell can also maintain the DC voltage of each DC system evenly, and is not limited by the primary DC voltage. However, when the AC output voltage of the entire MMCC-SSBC drops due to a cell failure, the AC output voltage of even more cells must be lowered, increasing the risk that the MMCC-SSBC will not be able to output the AC voltage required for grid connection.

[0026] One possible solution is to lower the AC system voltage by injecting reactive power into the AC system, thereby lowering the AC voltage required for grid interconnection. However, changing the AC system voltage will affect other devices connected to the same system. If a reactive power compensator is connected nearby, not only will it not be possible to lower the AC voltage, but unnecessary reactive power will be exchanged between the reactive power compensator and the system, resulting in losses.

[0027] By increasing the primary-side DC voltage in advance, the AC output voltage of the AC-DC converter can be freely increased. However, this requires a corresponding cell voltage resistance design, and components with high voltage resistance must be selected, which increases cost and size. Furthermore, switching losses also increase steadily. Methods such as those described in Patent Documents 1 and 3, which increase the cell primary-side DC voltage only when some cells fail, are also conceivable. However, this still requires a cell voltage resistance design, and switching losses in the event of a failure are unavoidable.

[0028] To apply the technology of Patent Document 2, it is necessary to keep the primary side DC voltage constant using the full-bridge inverter of the failed cell. Therefore, if a failure occurs in the full-bridge inverter, the technology of Patent Document 2 cannot be applied.

[0029] Furthermore, in Patent Document 2, the AC output voltage of all cells that are not failing is increased (the pulse width is increased). Considering the case of Figure 1, in order to maintain equal power in DC system 21 and DC system 22, the AC output voltage of cells V11 to W12 should be increased, but the AC output voltage of cells U21 to W22 should not be increased. In this respect, too, the technology of Patent Document 2 cannot be applied as is.

[0030] Non-Patent Document 1, Patent Document 4, and Patent Document 5 can also be applied to MMCC-SSBCs. However, there is a problem in that third-order harmonics are superimposed on the neutral point of an MMCC-SSBC. Fluctuations in the neutral point potential cause common-mode current to flow through stray capacitance, potentially resulting in false detection of ground faults and adversely affecting other devices connected to the same AC system. In particular, SSTs are designed to be directly connected to high-voltage AC systems, such as 6.6 kV or higher, without a transformer, so even small stray capacitances can result in large common-mode currents. Among these, the method of Patent Document 4 also superimposes many ninth-order and higher harmonics, further increasing the common-mode current and increasing the risk of problems.

[0031] The zero-phase voltage superimposed in Patent Documents 7 and 8 is a fundamental wave. Therefore, the common-mode current flowing out from the stray capacitance is one-third that of Non-Patent Document 1 and Patent Documents 4 and 5, thereby reducing the impact. However, Patent Documents 7 and 8 assume that all cells are connected in parallel on the DC system side. They do not mention maintaining voltage balance when connected in series.

[0032] As described above, when continuing operation in the event of a failure in one of the cells, the SST may be unable to output the specified AC voltage required for grid connection, making it impossible to transfer power according to the command value, outputting distorted current to the AC side, or requiring gate blocking due to overcurrent, which causes the device to stop, and the issue of how to prevent these problems becomes a challenge.

[0033] The present invention has been devised in view of the above-mentioned problems of the prior art, and one aspect thereof is a power supply system including m (m: an integer of 2 or more) cells per phase, each cell including an AC / DC converter connected to an AC system, a primary-side DC capacitor connected to the DC side of the AC / DC converter, an isolated DC / DC converter having one DC side connected to the primary-side DC capacitor, and a secondary-side DC capacitor connected to the other DC side of the isolated DC / DC converter, and x (x: an integer of 2 or more) DC systems in which a plurality of the secondary-side DC capacitors are connected in parallel, and a power supply system for supplying voltages of the plurality of DC systems to a load or a power source. a control unit of the AC-DC converter, when a cell fails, increases an output voltage on the AC system side of the cell connected to the same DC system as the failed cell, decreases an output voltage on the AC system side of the cell connected to the other DC system, superimposes a third harmonic on the AC output voltage of the cell connected to the same DC system as the failed cell, and superimposes an opposite third harmonic on the AC output voltage of the cell connected to the DC system different from the failed cell.

[0034] In one aspect, the control unit of the AC-DC converter includes a second multiplier that multiplies each phase voltage command value of the AC-DC converter by 3m / (3m-x+1) when one of the cells fails, by (3m-x) / (3m-x+1) when one of the cells fails, by 1 when one of the cells fails, by 3m / (3m-x) / (3m-x+1) when one of the cells fails, by 1 when there is no failed cell, and by 3m / (3m+1-x) when the cell is connected to the same DC system as the failed cell, by -3(m-x) / ((x-1)(3m+1-x)) when the cell is connected to the same phase as the failed cell, by -3(m-x) / ((x-1)(3m+1-x)), and by 1 when there is no failed cell. the primary side DC voltage intra-phase balance control unit outputs a primary side DC voltage intra-phase balance control value based on the primary side DC voltage intra-phase average value of each phase and the primary side DC voltage of each cell; and a first subtractor outputs each cell voltage command value by subtracting the primary side DC voltage intra-phase balance control value from the output of the first adder, and generates a gate signal for the AC-DC converter based on each cell voltage command value.

[0035] In one aspect, the control unit of the AC-DC converter is characterized by comprising: a dq inverse converter that converts a voltage command value on a rotating coordinate system into a voltage command value on a fixed coordinate system; a switch for each phase that outputs (3m-x+1) / (3m-x-2) as a coefficient for the phase to which the faulty cell is connected and 1 as a coefficient for the other phases; a fourth multiplier that multiplies the AC voltage of each phase by the output of the switch for each phase; a calculator that outputs a zero-phase voltage based on the output of the fourth multiplier and the coefficient; a third adder that adds the zero-phase voltage to the voltage command value on the fixed coordinate system; and a first multiplier that multiplies the output of the third adder by the reciprocal of the average value of the primary side DC voltages of all cells and outputs the result as the voltage command value for each phase.

[0036] In one aspect, when two of the cells connected to the same DC system in the same phase fail, the control unit of the AC-DC converter includes a dq inverse converter that converts a voltage command value on a rotating coordinate system into a voltage command value on a fixed coordinate system, a switch for each phase that outputs (3m-2x+2) / (3m-2x-4) as a coefficient for the phase to which the failed cell is connected and 1 as a coefficient for the other phases, a fourth multiplier that multiplies the AC voltage of each phase by the output of the switch for each phase, and a multiplier that converts the output of the fourth multiplier and the coefficient a third adder that adds the zero-phase voltage to the fixed coordinate voltage command value; a first multiplier that multiplies the output of the third adder by the reciprocal of an average value of the primary side DC voltages of all the cells and outputs the result as the voltage command value for each phase; a first multiplier that multiplies 3m / (3m+2-2x) for the cell connected to the same DC system as the failed cell, and (3m-2x) / (3m+2-2x) for the cell connected to a DC system different from the failed cell; a third multiplier that multiplies the third harmonic by 3m / (3m+2-2x) for the cell connected to the same DC system as the failed cell, by -3(m-2x) / ((x-1)(3m+2-2x)) for the cell connected to the same phase as the failed cell or to a different DC system, and by -3m / (x-1)(3m+2-2x) for the cell connected to a different phase than the failed cell or to a different DC system; a primary DC voltage intra-phase balance control unit that outputs a primary DC voltage intra-phase balance control value based on an average primary DC voltage intra-phase value of each phase and the primary DC voltage of each cell; and a first subtractor that subtracts the primary DC voltage intra-phase balance control value from the output of the first adder to output each cell voltage command value, and generates a gate signal for the AC-DC converter based on each cell voltage command value.

[0037] In one aspect, when two of the cells connected to different phases but the same DC system fail, the control unit of the AC-DC converter includes a dq inverse converter that converts a voltage command value on a rotating coordinate system into a voltage command value on a fixed coordinate system, a switch for each phase that outputs (3m-2x+2) / (3m-2x-1) as a coefficient for the phase to which the failed cell is connected and 1 as a coefficient for the other phases, a fourth multiplier that multiplies the AC voltage of each phase by the output of the switch for each phase, and a multiplier that converts the output of the fourth multiplier and the coefficient a third adder that adds the zero-phase voltage to the fixed coordinate voltage command value; a first multiplier that multiplies the output of the third adder by the reciprocal of an average value of the primary side DC voltages of all the cells and outputs the result as the voltage command value for each phase; a first multiplier that multiplies 3m / (3m+2-2x) for the cell connected to the same DC system as the failed cell, and (3m-2x) / (3m+2-2x) for the cell connected to a DC system different from the failed cell; a third multiplier that multiplies the third harmonic by 3m / (3m+2-2x) for the cell connected to the same DC system as the failed cell, by -3(m-x) / ((x-1)(3m+2-2x)) for the cell connected to the same phase as the failed cell but connected to a different DC system, and by -3m / (x-1)(3m+2-2x) for the cell connected to a different phase than the failed cell but connected to a different DC system; a primary DC voltage intra-phase balance control unit that outputs a primary DC voltage intra-phase balance control value based on an average primary DC voltage intra-phase value of each phase and the primary DC voltage of each cell; and a first subtractor that subtracts the primary DC voltage intra-phase balance control value from the output of the first adder to output each cell voltage command value, and generates a gate signal for the AC-DC converter based on each cell voltage command value.

[0038] In one aspect, when two cells connected to the same phase but different DC systems fail, the control unit of the AC-DC converter includes a dq inverse converter that converts a voltage command value on a rotating coordinate system into a voltage command value on a fixed coordinate system, a switch for each phase that outputs (3m-x+2) / (3m-x-4) as a coefficient for the phase to which the failed cell is connected and 1 as a coefficient for the other phases, a fourth multiplier that multiplies the AC voltage of each phase by the output of the switch for each phase, and a multiplier that converts the output of the fourth multiplier and the coefficient a third adder that adds the zero-phase voltage to the fixed coordinate voltage command value; a first multiplier that multiplies the output of the third adder by the reciprocal of an average value of the primary side DC voltages of all cells and outputs the result as the voltage command value for each phase; a first multiplier that multiplies 3m / (3m+2-x) for the cell connected to the same DC system as the failed cell, and (3m-x) / (3m+2-x) for the cell connected to a DC system different from that of the failed cell; a second multiplier that multiplies the phase voltage command value; a third multiplier that multiplies the third harmonic by 3m / (3m+2-x) for the cell connected to the same DC system as the failed cell, by -6(m-x) / ((x-2)(3m+2-x)) for the cell connected to the same phase as the failed cell but connected to a different DC system, and by -6m / (x-2)(3m+2-x) for the cell connected to a different phase than the failed cell but connected to a different DC system; a primary DC voltage intra-phase balance control unit that outputs a primary DC voltage intra-phase balance control value based on the primary DC voltage intra-phase average value of each phase and the primary DC voltage of each cell; and a first subtractor that subtracts the primary DC voltage intra-phase balance control value from the output of the first adder and outputs each cell voltage command value, and generates a gate signal for the AC-DC converter based on each cell voltage command value.

[0039] In one aspect, when two of the cells connected to different phases and different DC systems fail, the control unit of the AC-DC converter includes a dq inverse converter that converts a voltage command value on a rotating coordinate system into a voltage command value on a fixed coordinate system, a switch for each phase that outputs (3m-x+2) / (3m-x-1) as a coefficient for the phase to which the failed cell is connected and 1 as a coefficient for the other phases, a fourth multiplier that multiplies the AC voltage of each phase by the output of the switch for each phase, and a multiplier that converts the output of the fourth multiplier and the a computing unit that outputs a zero-phase sequence voltage based on a coefficient; a third adder that adds the zero-phase sequence voltage to the fixed coordinate voltage command value; a first multiplier that multiplies the output of the third adder by the reciprocal of an average value of primary side DC voltages of all cells and outputs the result as the each-phase voltage command value; a first multiplier that multiplies 3m / (3m+2-x) for the cell connected to the same DC system as the failed cell, and (3m-x) / (3m+2-x) for the cell connected to a DC system different from that of the failed cell; a third multiplier that multiplies the third harmonic by 3m / (3m+2-x) for the cell connected to the same DC system as the failed cell, by -3(2m-x) / ((x-2)(3m+2-x)) for the cell connected to the same phase as the failed cell and to a different DC system, and by -6m / (x-2)(3m+2-x) for the cell connected to a different phase than the failed cell and to a different DC system; and a primary DC voltage intra-phase balance control unit that outputs a primary DC voltage intra-phase balance control value based on an average primary DC voltage intra-phase value of each phase and the primary DC voltage of each cell; and a first subtractor that subtracts the primary DC voltage intra-phase balance control value from the output of the first adder to output each cell voltage command value, and generates a gate signal for the AC-DC converter based on each cell voltage command value.

[0040] According to the present invention, when continuing operation in the event of a failure in one of the cells, it is possible to prevent problems such as the inability to output the specified AC voltage required for grid connection from the SST, the inability to transfer power according to the command value, the output of distorted current to the AC side, and the need to apply a gate block due to an overcurrent, which causes the device to stop.

[0041] Fig. 1 is a diagram showing an example of a main circuit configuration of the modular multilevel cascade converter of embodiment 1. Fig. 2 is a diagram showing a main circuit configuration when a failure occurs in cell U11, causing the AC side to be short-circuited and the DC side to be open. Fig. 3 is a block diagram showing a control unit of the AC-DC converter of embodiment 1. Fig. 4 is a block diagram showing a voltage command value calculation unit of embodiment 2. Fig. 5 is a diagram showing an output voltage waveform of the AC-DC converter when embodiment 2 is applied.

[0042] Hereinafter, first to third embodiments of the modular multilevel cascade converter of the present invention will be described in detail with reference to FIGS.

[0043] [Embodiment 1] Here, m (m: an integer of 2 or more) is the number of cells per phase, and x (x: an integer of 2 or more) is the number of DC systems to output. In Fig. 1, m = 4 and x = 2.

[0044] Figure 1 shows the main circuit configuration of a modular multilevel cascade converter (SST) that generates multiple DC systems. As shown in Figure 1, the SST includes an AC-DC converter ACDC connected to a high-voltage AC system via reactors Lu, Lv, and Lw, a primary-side DC capacitor C1 connected to the DC side of the AC-DC converter ACDC, an isolated DC-DC converter DCDC having one DC side connected to the primary-side DC capacitor C1, and a secondary-side DC capacitor C2 connected to the other DC side of the isolated DC-DC converter DCDC. The AC-DC converter ACDC and the isolated DC-DC converter DCDC may be appropriately selected from conventionally known converters. Because the AC-DC converter ACDC and the isolated DC-DC converter DCDC are well known, detailed description thereof will be omitted here.

[0045] Here, the AC-DC converter ACDC, primary side DC capacitor C1, isolated DC-DC converter DCDC, and secondary side DC capacitor C2 constitute one cell. In FIG. 1, there are U-phase cells U11 to U22, V-phase cells V11 to V22, and W-phase cells W11 to W22. The AC sides of the cells of each phase are connected in series. Cells U11 to W12 are connected in parallel to form a DC system 21, and the DC sides of cells U21 to W22 are connected in parallel to form a DC system 22. The DC systems 21 and 22 are connected in series. V ＡＣＵ１１ ~V ＡＣＷ２２ indicates the AC output voltage of each cell, and VＤＣ２１ , V ＤＣ２２ indicates the DC system voltage detection value, and I ＤＣ２１ , I ＤＣ２２ indicates the detected DC system current value.

[0046] In the first embodiment, the secondary side DC capacitors C2 are connected in parallel to form one DC system V ｄｃ２１ or DC system V ｄｃ２２ In addition, the DC system V ｄｃ２１ , or V ｄｃ２２ , or V ｄｃ２１ +V ｄｃ２２ The power supply is supplied to a load or a power source. Each cell (AC-DC converter ACDC, isolated DC-DC converter DCDC) is equipped with a switching element. The voltage and current of each cell can be controlled by turning the switching element on and off.

[0047] In this embodiment, the above-mentioned (3) individual balance control of primary DC voltage and (4) individual control of secondary DC voltage are applied as they are. However, modifications are made to (1) average value control of primary DC voltage and (2) intra-phase balance control of primary DC voltage.

[0048] Here, (1) to (4) will be explained.

[0049] (1) The primary DC voltage average value control calculates the total primary DC voltage of all cells as the total primary DC voltage of all cells, and calculates the primary DC voltage all-cell average value from the product of the total primary DC voltage all-cell value and the reciprocal of the total number of cells. The deviation between the primary DC voltage average value command value and the primary DC voltage all-cell average value is amplified, and the d-axis current command value i ｄ＿ｒｅｆ Output as

[0050] In addition, the AC system voltage V ｕ , V ｖ , V ｗ The phase ωt is output based on the three-phase system current value i ｕ , i ｖ , i ｗ and the phase ωt, a d-axis current detection value id and a q-axis current detection value i on the rotating coordinate system synchronized with the grid are calculated. ｑ Output.

[0051] The grid current control unit calculates the d-axis current command value I ｄ＿ｒｅｆ to d-axis current detection value I ｄ is subtracted and amplified to obtain the d-axis voltage command value V ｄ＿ｒｅｆ The q-axis current command value I ｑ＿ｒｅｆ The q-axis current detection value Iq is subtracted from the q-axis voltage command value V ｑ＿ｒｅｆ Output as

[0052] (2) The primary DC voltage intra-phase balance control unit calculates the total value of the primary DC voltages in the phase as the primary DC voltage intra-phase total value, and calculates the primary DC voltage intra-phase average value for each phase from the product of the primary DC voltage intra-phase total value and the reciprocal of the number of cells in the phase.The primary DC voltage intra-phase average value for each phase is amplified, and the deviation between the primary DC voltage of each cell in the phase and the primary DC voltage of each cell is multiplied by the sign of the grid current value for each phase, and output as the primary DC voltage intra-phase balance control value.This value is used to calculate each cell voltage command value, as described below.

[0053] (3) The primary DC voltage individual balance control unit calculates the sum of the primary DC voltages of the cells connected to each DC system, multiplies the sum by the reciprocal of the number of cells connected to each DC system, and calculates the DC system primary DC voltage average value of the cells connected to each DC system. The deviation between the DC system primary DC voltage average value and the primary DC voltage of each cell in a phase is calculated, and after removing the system frequency double component superimposed on the deviation as necessary, the result is amplified by an amplifier, multiplied by the turns ratio of the transformer of the AC-DC converter and the transformer of the isolated DC-DC converter, and output as the primary DC voltage individual balance control value.

[0054] (4) The individual secondary DC voltage control unit amplifies the difference between the secondary DC voltage command value of each DC system and the secondary DC voltage, calculates the product by the reciprocal of the number of cells connected to the DC system, and outputs the result as an individual secondary DC voltage control value. The isolated DC-DC converter DCDC of each cell adds the corresponding individual primary DC voltage balance control value and individual secondary DC voltage control value to obtain a current command value, and performs power interchange based on this command.

[0055] 3 shows a block diagram of the control unit of the AC-DC converter ACDC of the first embodiment. In the first embodiment, when a cell fails, the output voltage on the AC system side of the cell connected to the same DC system as the failed cell is increased, and the output voltage on the AC system side of the cell connected to the other DC system is decreased. Then, a third harmonic is superimposed on the AC output voltage of the cell connected to the same DC system as the failed cell, and a third harmonic in the opposite direction is superimposed on the AC output voltage of the cell connected to a DC system other than the failed cell.

[0056] Specifically, the dq inverse converter 1 calculates the d-axis voltage command value V ｄ＿ｒｅｆ , q-axis voltage command value V ｑ＿ｒｅｆ and phase ωt are input, and the voltage command value on the rotating coordinate system synchronized with the grid is converted into a voltage command value on the fixed coordinate system. ｄ＿ｒｅｆ , q-axis voltage command value V ｑ＿ｒｅｆ The first multiplier 2 multiplies the output of the dq inverter 1 by the reciprocal 1 / V of the average value of the primary side DC voltage of all cells. ｄｃ１＿ａｖｅ The output of the first multiplier 2 is multiplied by the voltage command value V ｕ＿ｒｅｆ , V ｖ＿ｒｅｆ , V ｗ＿ｒｅｆ Let's say.

[0057] A fixed value of 3m / (3m+1-x) is input as a coefficient for increasing the output voltage on the AC grid side of the cell. In FIG. 1, m = 4 and x = 2, so 3m / (3m+1-x) = 12 / 11. A fixed value of (3m-x) / (3m+1-x) is input as a coefficient for decreasing the output voltage on the AC grid side of the cell. When applied to FIG. 1 as well, (3m-x) / (3m+1-x) = 10 / 11.

[0058] The switch SW1 outputs 3m / (3m+1-x) if a cell connected to the DC system 21 fails, and outputs (3m-x) / (3m+1-x) if not. The switch SW2 outputs (3m-x) / (3m+1-x) if a cell connected to the DC system 21 fails, and outputs 3m / (3m+1-x) if not.

[0059] If a faulty cell exists, switch SW3 outputs the output of switch SW1, and if not, it outputs 1. If there is no faulty cell, switch SW3 outputs 1, if a cell connected to DC system 21 has failed, it outputs 3m / (3m+1-x), and if a cell connected to DC system 22 has failed, it outputs (3m-x) / (3m+1-x).

[0060] If a faulty cell exists, switch SW4 outputs the output of switch SW2, and if not, it outputs 1. Switch SW4 outputs 1 if there is no faulty cell, (3m-x) / (3m+1-x) if a cell connected to DC system 21 has failed, and 3m / (3m+1-x) if a cell connected to DC system 22 has failed.

[0061] The second multiplier 3 calculates the phase voltage command value V ｕ＿ｒｅｆ , V ｖ＿ｒｅｆ , V ｗ＿ｒｅｆ is multiplied by the outputs of the switches SW3 and SW4. The number of second multipliers 3 is 3x, and six when applied to FIG. 1. For example, when the DC system is a three-stage series connection, if there is no faulty cell, it is 1, if there is a faulty cell in the DC system 23, it is 3m / (3m+1-x), and if there is a faulty cell in another stage, it is (3m-x) / (3m+1-x), and the voltage command value V for each phase is ｕ＿ｒｅｆ , V ｖ＿ｒｅｆ , V ｗ＿ｒｅｆ Three second multipliers 3 are added to calculate the product of

[0062] 3rd harmonic V ０３ is a value found in Non-Patent Document 1, Patent Documents 4 and 5, etc. The switch SW5 outputs 0 if there is no faulty cell, and the third harmonic V ０３ Output.

[0063] The third harmonic V superimposed on the AC output voltage of a cell connected to the same phase as the faulty cell but a different DC system ０３ A fixed value of -3(m-x) / ((x-1)(3m+1-x)) is input as a coefficient for determining the amplitude of the third harmonic V. In the example shown in Figure 1, it is -6 / 11. ０３A fixed value of -3m / ((x-1)(3m+1-x)) is input as a coefficient for determining the amplitude of the signal. In the example of FIG. 1, this is -12 / 11.

[0064] Switch SW6 outputs -3(m-x) / ((x-1)(3m+1-x)) if the faulty cell is in the U phase, and -3m / ((x-1)(3m+1-x)) otherwise. Switch SW7 outputs -3(m-x) / ((x-1)(3m+1-x)) if the faulty cell is in the V phase, and -3m / ((x-1)(3m+1-x)) otherwise. Switch SW8 outputs -3(m-x) / ((x-1)(3m+1-x)) if the faulty cell is in the W phase, and -3m / ((x-1)(3m+1-x)) otherwise.

[0065] The third harmonic V superimposed on the AC output voltage of the cell connected to the same DC system as the failed cell. ０３ A fixed value of 3m / (3m+1-x) is input as a coefficient for determining the amplitude of the signal. In the example of FIG. 1, where m=4 and x=2, the value is 12 / 11.

[0066] The switch SW9 outputs 3m / (3m+1-x) if the faulty cell is in the DC system 21, and outputs the output of the switch SW6 otherwise. The switch SW10 outputs 3m / (3m+1-x) if the faulty cell is in the DC system 22, and outputs the output of the switch SW6 otherwise. The switch SW11 outputs 3m / (3m+1-x) if the faulty cell is in the DC system 21, and outputs the output of the switch SW7 otherwise. The switch SW12 outputs 3m / (3m+1-x) if the faulty cell is in the DC system 22, and outputs the output of the switch SW7 otherwise. The switch SW13 outputs 3m / (3m+1-x) if the faulty cell is in the DC system 21, and outputs the output of the switch SW8 otherwise. The switch SW14 outputs 3m / (3m+1-x) if the faulty cell is in the DC system 22, and outputs the output of the switch SW8 otherwise.

[0067] The third multiplier 5 calculates the product of the output of the switch SW5 and the outputs of the switches SW9 to SW14. That is, the third multiplier 5 multiplies the third harmonic by 3m / (3m+1-x) for cells connected to the same DC system as the faulty cell, by -3(m-x) / ((x-1)(3m+1-x)) for cells connected to the same phase as the faulty cell or a different DC system, by -3m / (x-1)(3m+1-x) for cells connected to a different phase or a different DC system from the faulty cell, and by 0 if there is no faulty cell.

[0068] The first adder 6 adds the output of the third multiplier 5 to the respective phase voltage command values ​​V ｕ＿ｒｅｆ , V ｖ＿ｒｅｆ , V ｗ＿ｒｅｆ and the product of the switches SW3 and SW4 (the output of the second multiplier 3) are added together. Then, the first subtractor 4 subtracts the primary side DC voltage intra-phase balance control value calculated in (2) from the output of the first adder 6 to calculate each cell voltage command value. Based on each cell voltage command value, a gate signal for the AC-DC converter ACDC is generated by PWM modulation.

[0069] In the (2) primary side DC voltage intra-phase balance control of Patent Document 6, feedforward adjustment is performed on the AC output voltage of the AC-DC converter ACDC of the cell. The problem with this method is that if some of the cells constituting the SST fail, it is unable to output a voltage sufficient for connection to the AC grid. The reason why the amplitude of the AC side voltage output by the cell cannot be increased is that it is limited by the primary side DC voltage within the cell, and in order to maintain voltage balance at each stage of the DC grid, the amplitude of the AC side voltage of a cell connected to the DC grid without a failed cell must be smaller than the AC voltage of a cell connected to the DC grid with a failed cell.

[0070] In this embodiment, the third harmonic superposition technique described in Non-Patent Document 1, Patent Documents 5, and 6 is applied to the AC output voltage of the AC-DC converter ACDC of a cell connected to a DC system with a faulty cell, thereby enabling the AC output voltage of the AC-DC converter ACDC to be increased without increasing the primary-side DC voltage average value control. Furthermore, because the amplitude of the AC voltage must be reduced for cells connected to a DC system without a faulty cell, there is a margin in the limit of the AC voltage amplitude. Therefore, by superimposing a third harmonic in the opposite direction to that of the cell connected to the DC system with the faulty cell, the third harmonics cancel each other out, preventing the third harmonic from being superimposed on the neutral point of the MMCC-SSBC.

[0071] The amplitude of the superimposed third harmonic will be explained. Consider the case where one cell connected to both the U phase and the DC system 21 fails. Non-Patent Document 1 states that in order to minimize the voltage peak after superimposition, it is sufficient to superimpose a third harmonic whose amplitude is 1 / 6 of the voltage amplitude before superimposition. The third harmonic V in Figure 3 ０３ is assumed to be a third harmonic of the corresponding amplitude. Alternatively, each phase voltage command value V ｕ＿ｒｅｆ , V ｖ＿ｒｅｆ , V ｗ＿ｒｅｆ Patent Documents 4 and 5 are applied to the third harmonic V ０３ You may ask for:

[0072] When a fault occurs, the remaining cells connected to the DC grid 21 need to increase the AC output voltage of the AC-DC converter ACDC by 3m / (3m+1-x) times. Third-order harmonic superposition is applied to these cells. The amplitude of the third-order harmonic needs to be multiplied by 3m / (3m+1-x) in accordance with the increase in the AC output voltage of the AC-DC converter ACDC.

[0073] In the remaining cells, the superimposed third harmonic must be canceled. Focusing on the U phase, there are m / x-1 cells on which a third harmonic multiplied by 3m / (3m+1-x) is superimposed, one faulty cell, and m-m / x remaining cells. To cancel the third harmonic in these remaining cells, the amplitude of the third harmonic to be superimposed on the remaining cells is -3(m-x) / ((x-1)(3m+1-x)) times.

[0074] In the V and W phases, the cells onto which the third harmonic multiplied by 3m / (3m+1-x) is superimposed are in the m / x range, and the remaining cells are in the mm-m / x range. The amplitude of the third harmonic to be superimposed on the remaining cells is -3m / ((x-1)(3m+1-x)) times.

[0075] Taking m=4 and x=2 in FIG. 1 as an example, the remaining cells connected to the DC grid 21 have a third harmonic V ０３ This corresponds to one U-phase cell, and the remaining two U-phase cells are superimposed with the third harmonic V ０３ If you multiply it by -6 / 11 and superimpose it, the third harmonic will be zero in the U phase. ０３ The remaining two cells are multiplied by 12 / 11 and superimposed. ０３ By multiplying and superimposing the third harmonic V ０３ can be cancelled out.

[0076] By applying third-order harmonic superposition, the fundamental component of the output voltage amplitude can be increased by 2 / √3 ≒ 1.15 times. On the other hand, to restore the output voltage of a phase of a failed cell to the same level as before the failure, the AC output voltage of the AC-DC converter ACDC must be increased by (3m-x+1) / (3m-x-2) times.

[0077] In this embodiment, if x = 2 and m > 7.8, the AC output voltage of the AC-DC converter ACDC must be increased within 1.15 times. In the example of m = 4 in Figure 1, the AC output voltage of the AC-DC converter ACDC must be increased to 1 1 / 8 = 1.375, which exceeds 1.15 times. In such a case, it is necessary to design the primary-side DC voltage average value control to be high in advance. However, even in the example of m = 4 in Figure 1, if this embodiment is applied, the increase in the intra-cell primary-side DC voltage can be reduced to 1.2 times instead of 1.375 times.

[0078] According to the first embodiment, in a modular multilevel cascade converter (SST) that has output terminals connected in series to enable output of a higher DC voltage, the problem of a drop in the AC voltage output by the SST when some of the cells fail can be solved. This makes it possible to suppress phenomena such as an inability to transfer a predetermined amount of power, output of a distorted current to the AC side, and the occurrence of an overcurrent.

[0079] Furthermore, according to the first embodiment, if one cell fails, the cells connected in parallel to the same DC system as the failed cell can increase their AC voltage output by up to 1.15 times. This makes it possible to maintain both the balance of the DC voltage output and the AC system interconnection without increasing the DC capacitor voltage inside the cell. This is advantageous in terms of cost and size, as there is no need to strengthen the voltage resistance design of the cells or change to components compatible with high voltages. Increased switching losses can also be avoided.

[0080] [Embodiment 2] FIG. 4 shows the phase voltage command value V ｕ＿ｒｅｆ , V ｖ＿ｒｅｆ , V ｗ＿ｒｅｆ A block diagram of the calculation unit is shown.

[0081] AC system voltage detection value V ｕ , V ｖ , V ｗ Enter the fixed value (3m-x+1) / (3m-x-2). Assuming application to Figure 1, the number of cells per phase is m=4, and the number of DC systems is x=2, so (3m-x+1) / (3m-x-2)=11 / 8.

[0082] The switch SW15 sets (3m-x+1) / (3m-x-2) when a cell connected to the U phase fails, and sets 1 otherwise as a coefficient N / n ｕ If a cell connected to the V phase fails, the switch SW16 outputs (3m-x+1) / (3m-x-2), otherwise it outputs 1 as a coefficient N / n ｖ The switch SW17 outputs (3m-x+1) / (3m-x-2) if a cell connected to the W phase has failed, and outputs 1 otherwise as a coefficient N / n ｗ Output as

[0083] The numerator of the coefficient, N, is the number of cells in each phase, and N = m. The notation of N conforms to Patent Documents 7 and 8. The denominator of the coefficient, n ｕ , n ｖ , n ｗ is the number of cells in each phase that are operating without failure.

[0084] The fourth multiplier 7 multiplies the AC system voltage detection value V ｕ and coefficient N / n ｕ , AC system voltage detection value V ｖ and coefficient N / n ｖ , AC system voltage detection value V ｗ and coefficient N / n ｗ Find the product of

[0085] The computing unit 8 multiplies the output V of the fourth multiplier 7 by ｕ N / n ｕ , V ｖ N / n ｖ , V ｗ N / n ｗ , coefficient N / n ｕ , N / n ｖ , N / n ｗ is input, and the zero-phase voltage V ０ｑ sinωt, V ０ｄ cosωt is output.

[0086] Here, the method of calculating the zero-phase voltage of Patent Document 7, which is implemented inside the computing unit 8, will be described.

[0087] The corrected voltage command value generator outputs a phase ωt synchronized with the AC voltage of the grid. The first dq converter converts the phase voltage detection signal or voltage command value, or the phase voltage detection signal or voltage command value, multiplied by a coefficient obtained by dividing the number of cells in each phase by the number of cells in each phase that are operating without failure, into a value on a rotating coordinate system synchronized with the grid frequency. The second dq converter converts the phase voltage detection signal or voltage command value, or the phase voltage detection signal or voltage command value, multiplied by a coefficient obtained by dividing the number of cells in each phase by the number of cells in each phase that are operating without failure, into a value on a rotating coordinate system that rotates in the direction opposite to the grid frequency. The calculator extracts a DC component from the output of the first dq converter and converts it into a value on a rotating coordinate system that rotates in the direction opposite to the grid frequency. １ｄ , positive phase q-axis component V １ｑand the negative-phase d-axis component V extracted from the output of the second dq converter. ２ｄ , the negative phase q-axis component V ２ｑ Based on this, the zero-phase-sequence voltage d-axis component and the zero-phase-sequence voltage q-axis component that make the AC output voltage of each cell uniform are calculated using one of the following equations (1) to (3): ０ｄ is multiplied by cosωt. The zero-phase voltage q-axis component V ０ｑ is multiplied by sinωt.

[0088]

[0089]

[0090]

[0091] Next, a method for calculating the zero-phase voltage when the method disclosed in Patent Document 8 is implemented in the computing unit 8 will be described.

[0092] The correction voltage command value generator calculates the amplitude of the correction voltage command value for each phase. The amplitude may be, for example, the effective value of the voltage command value, the value obtained by extracting the amplitude of the fundamental wave component of the voltage command value, or the peak value per cycle of the voltage command value. The calculated amplitude is multiplied by a coefficient based on the number of failed cells. The deviation between the three-phase average value of the amplitude of the multiplied correction voltage command value and the amplitude of the multiplied correction voltage command value is amplified, and the result is multiplied by a sine wave in phase with the voltage command value. The multiplied values ​​for the three phases are added together and output as a zero-phase sequence voltage.

[0093] The zero-phase voltage V output from the calculator 8 ０ｑ sinωt, V ０ｄ cosωt is added by the second adder 9. The third adder 10 adds the zero-phase voltage V ０ｑ sinωt+V ０ｄ cosωt is added to the output of the dq inverter 1, and a corrected voltage command value for each phase is output.

[0094] The correction voltage command value of each phase is input to the first multiplier 2 and is also input again to the calculator 12, where it is again subjected to feedback control based on Patent Document 8 to calculate the zero-phase voltage V ０ｑ sinωt, V ０ｄ cosωt is calculated (when the calculation is performed based on Patent Document 7, the correction voltage command value for each phase does not need to be input to the calculator 8).

[0095] The first multiplier 2 multiplies the output of the third adder 10 by the reciprocal 1 / V of the average primary side DC voltage of all cells. ｄｃ１＿ａｖｅ and each phase voltage command value V ｕ＿ｒｅｆ , V ｖ＿ｒｅｆ , V ｗ＿ｒｅｆ Let's say.

[0096] The second embodiment is a combination of the first embodiment and Patent Documents 7 and 8.

[0097] In Patent Documents 7 and 8, a coefficient N / n is applied to the AC voltage of the phase including the failed cell. ｕ , N / n ｖ , N / n ｗ By multiplying this by 1 / 2, the voltage amplitude appears to be larger according to the number of faulty cells, and a zero-phase sequence voltage is calculated and superimposed to equalize the voltage amplitude. However, this can only be applied when the amplitude of the AC output voltage of the AC-DC converter ACDC of each cell is equal.

[0098] In the first embodiment, the AC output voltage of the AC-DC converter ACDC is multiplied by fixed values ​​3m / (3m+1-x) and (3m-x) / (3m+1-x), so the amplitudes of the AC output voltages of the AC-DC converter ACDC are not equal. ｕ , N / n ｖ , N / n ｗ adjustments need to be made.

[0099] Here, let us consider a case where the output voltage of the AC-DC converter ACDC for all cells before a cell failure is set to 1, and a cell connected to both the U phase and the DC system 21 fails. The remaining 3m / x-1 cells connected to the DC system 21 have an AC output voltage of 3m / (3m+1-x) based on embodiment 1. The AC output voltage of the AC-DC converter ACDC for the cells connected to the other DC systems 22 to 2x is (3m-x) / (3m+1-x).

[0100] Looking at the U phase, there are m / x-1 cells whose AC output voltage from the AC-DC converter ACDC has become 3m / (3m+1-x), m-m / x cells whose AC output voltage has become (3m-x) / (3m+1-x), and one cell that has failed and become 0. The total U phase AC output voltage of the AC-DC converter ACDC is m(3m-x-2) / (3m-x+1). Before the failure, there were m cells outputting 1, so the total U phase AC output voltage of the AC-DC converter ACDC changes by a factor of (3m-x-2) / (3m-x+1).

[0101] In the V and W phases, the number of cells where the AC output voltage of the AC-DC converter ACDC has become 3m / (3m+1-x) due to the failure is in the m / x range, and the number of cells where it has become (3m-x) / (3m+1-x) is in the mm-m / x range, the same as in the U phase. The total AC output voltage of the AC-DC converter ACDC for the V and W phases is m, and does not change before or after the failure. Therefore, the coefficient N / n ｕ may be set to (3m-x+1) / (3m-x-2), which is the reciprocal of the total amount of change in the U-phase AC output voltage of the AC-DC converter ACDC.

[0102] A case where a cell connected to both the U phase and the DC system 21 fails in the configuration of m = 4 and x = 2 in Figure 1 will be described again. According to the first embodiment, the output voltage of the AC-DC converter ACDC with five cells connected to the DC system 21 is 12 / 11 times. The output voltage of the AC-DC converter ACDC with six cells connected to the DC system 22 is 10 / 11 times. In the U phase, there is one cell that is 12 / 11 times and two cells that are 10 / 11 times. The total output voltage changes from 4 to 32 / 11, decreasing to 8 / 11 times. The number of cells is not simply reduced from four to three, resulting in a 3 / 4 times increase, but rather the decrease in the total output voltage is greater because there are more cells whose output voltage of the AC-DC converter ACDC has decreased. In the V phase and W phase, there are two cells that are 12 / 11 times and two cells that are 10 / 11 times, so the total output voltage remains 4. From the above, ｕ is multiplied by a coefficient of 11 / 8 to make the U-phase voltage amplitude appear larger.

[0103] FIG. 5 shows the AC output voltage waveform of the U-phase AC-DC converter ACDC when the second embodiment is applied. Initially, all cells normally output the AC voltage of the AC-DC converter ACDC. For example, the amplitude of the AC voltage is 1 / 1000 of the primary side DC voltage (V ｄｃ１ｕ１１ ~V ｄｃ１ｕ２２ ) is set to 0.9 times.

[0104] After two cycles, cell U11 fails and shorts the AC output terminal, so V ＡＣＵ１１ becomes zero. V ＡＣＵ１２ is the amplitude multiplied by 12 / 11, V ＡＣＵ２１ , V ＡＣＵ２２ is multiplied by 10 / 11.

[0105] Furthermore, by applying Patent Documents 7 and 8, a zero-phase sequence voltage is superimposed, and the AC voltage is three-phase balanced. At this time, the AC voltage of the AC-DC converter ACDC of all cells is multiplied by about 1.09. As a result, V ＡＣＵ１２ In reality, it is not possible to output such a voltage, which can cause distortion and overcurrent.

[0106] Four cycles later, this is the case where the second embodiment is applied. The fundamental wave component of the AC voltage of each AC-DC converter ACDC is not changed. ＡＣＵ１２ The third harmonic is added to V, reducing the peak, and the amplitude is contained within the primary side DC voltage, making it possible to avoid overmodulation. The superimposed third harmonic is reversed and divided into two equal parts to V ＡＣＵ２１ , V ＡＣＵ２２ V ＡＣＵ２１ , V ＡＣＵ２２ Although the distortion peak increases in a triangular wave shape, the amplitude is reduced before application, so there is a margin to avoid overmodulation. ＡＣＵ１２ , V ＡＣＵ２１ , V ＡＣＵ２２ The distortions cancel each other out, preventing the superposition of third harmonics on the neutral point.

[0107] However, for the V phase, ＡＣＶ１１ , V ＡＣＶ１２ The amplitude of both is multiplied by 12 / 11 x 1.09, and the third harmonic must be superimposed on both. This is shared and canceled by the two cells V21 and V22, so the V ＡＣＶ２１, V ＡＣＶ２２ A double third harmonic is superimposed on the W phase, increasing the risk of overmodulation. The same applies to the W phase. Here, we have used an example where m = 4, but in configurations where m is larger, the number of cells that can share the load by canceling out the third harmonic increases, making it possible to prevent overmodulation.

[0108] According to the second embodiment, even if one cell fails, the AC output voltages of the AC-DC converters ACDC of cells connected to the same DC system can be made equal. This prevents a chain reaction of failures caused by an excessive DC voltage being applied to other cells in the phase where the failed cell is located, or the AC output voltage of the phase where the failed cell is located is insufficient, making it impossible to maintain grid connection and causing overcurrent, and voltage and current distortion. Furthermore, as in Patent Documents 7 and 8, the effect of equalizing the AC output voltages of the cells can also be achieved even when an imbalance occurs in the AC voltage or when an unbalanced AC voltage is intentionally output.

[0109] [Embodiment 3] Table 1 shows the formulas for calculating the fixed values ​​used in this embodiment 3. The fixed values ​​used in embodiments 1 and 2 are changed to the values ​​found in Table 1 depending on the number and positions of the faulty cells.

[0110]

[0111] In this third embodiment, a case where two cells fail will be described. The voltage command value fault stage in Table 1 is the value input to the upper side of switch SW1 and the lower side of switch SW2. The voltage command value healthy stage is the value input to the lower side of switch SW1 and the upper side of switch SW2. The coefficient N / n faulty phase is the value input to the upper side of switch SW15, the middle of switch SW16, and the lower side of switch SW17. The third harmonic fault stage is the value input to the upper sides of switches SW9, SW11, and SW13, and the lower sides of switches SW10, SW12, and SW14. The third harmonic healthy stage fault phase is the value input to the upper side of switch SW6, the middle of switch SW7, and the lower side of switch SW8. The third harmonic healthy stage healthy phase is the value input to the middle and lower sides of switch SW6, the upper and lower sides of switch SW7, and the upper and middle sides of switch SW8.

[0112] (1) When two faulty cells are connected to the same phase and same DC system (stage) Consider the case where two faulty cells are connected to the U phase and DC system 21. The number of cells in DC system 21, excluding the faulty cell, is 3m / x-2, and the AC output voltage is increased by 3m / (3m+2-2x) times. The number of cells in DC systems 22 to 2x is a total of 3m-3m / x, and the AC output voltage is reduced by (3m-2x) / (3m+2-2x) times.

[0113] Excluding the faulty cell, there are m / x-2 cells connected to the DC system 21 at the U phase, and m-m / x cells connected to other DC systems. There are m / x cells connected to the DC system 21 at the V and W phases, and m-m / x cells connected to other DC systems.

[0114] Due to the failure, the AC output voltage of U phase will decrease by {(3m / (3m+2-2x))*(m / x-2)+((3m-2x) / (3m+2-2x))*(m-m / x)} / m=(3m-2x-4) / (3m-2x+2) times. The AC output voltage of V phase and W phase will decrease by {(3m / (3m+2-2x))*m / x+((3m-2x) / (3m+2-2x))(m-m / x)} / m=1 time, and will not change before or after the failure.

[0115] Therefore, the coefficient N / n ｕ is set to (3m-2x+2) / (3m-2x-4). Since the third harmonic superposition is performed to reduce the peak value of the cell that has increased the AC output voltage, the amplitude of the third harmonic superposed on the cell of the DC system 21 is set to 3m / (3m+2-2x) times.

[0116] The number of cells in which this third harmonic is superimposed on the U phase is m / x-2 units. Since the remaining cells m-m / x units cancel this, the amplitude of the third harmonic to be superimposed on the remaining cells is -3m / (3m+2-2x) * (m / x-2) / (m-m / x) = -3(m-2x) / ((x-1)(3m+2-2x)). The number of cells in which this third harmonic is superimposed on the V and W phases is m / x units. Since the remaining cells m-m / x units cancel this, the amplitude of the third harmonic to be superimposed on the remaining cells is -3m / (3m+2-2x) * (m / x) / (m-m / x) = -3m / ((x-1)(3m+2-2x)).

[0117] (2) When two faulty cells are connected to different phases and the same DC system (stage) Consider the case where two faulty cells, one in the U phase and one in the V phase, are connected to DC system 21. The number of cells in DC system 21, excluding the faulty cell, is 3m / x-2, and the AC output voltage is increased by 3m / (3m+2-2x) times. The number of cells in DC systems 22 to 2x is a total of 3m-3m / x, and the AC output voltage is reduced by (3m-2x) / (3m+2-2x) times.

[0118] The number of cells connected to the DC system 21 in the U and V phases is m / x-1, excluding the faulty cell, and the number of cells connected to the other DC systems is m-m / x. The number of cells connected to the DC system 21 in the W phase is m / x, and the number of cells connected to the other DC systems is m-m / x.

[0119] Due to the failure, the AC output voltages of the U and V phases will decrease by {(3m / (3m+2-2x))*(m / x-1)+((3m-2x) / (3m+2-2x))*(m-m / x)} / m=(3m-2x-1) / (3m-2x+2) times. The AC output voltage of the W phase will decrease by {(3m / (3m+2-2x))*m / x+((3m-2x) / (3m+2-2x))(m-m / x)} / m=1 time, and will not change before or after the failure.

[0120] Therefore, the coefficient N / n ｕ , N / n ｖ is set to (3m-2x+2) / (3m-2x-1). Since the third harmonic superposition is performed to reduce the peak value of the cell that has increased the AC output voltage, the amplitude of the third harmonic to be superposed is set to 3m / (3m+2-2x).

[0121] The number of cells in which this third harmonic is superimposed on the U and V phases is m / x-1 units. Since the remaining cells m-m / x units cancel this, the amplitude of the third harmonic to be superimposed on the remaining cells is -3m / (3m+2-2x) * (m / x-1) / (m-m / x) = -3(m-x) / ((x-1)(3m+2-2x)). The number of cells in which this third harmonic is superimposed on the W phase is m / x units. Since the remaining cells m-m / x units cancel this, the amplitude of the third harmonic to be superimposed on the remaining cells is -3m / (3m+2-2x) * (m / x) / (m-m / x) = -3m / ((x-1)(3m+2-2x)).

[0122] (3) When two faulty cells are connected to the same phase but different DC systems (stages) Consider the case where two faulty cells are connected to the U phase, and one each to DC system 21 and DC system 22. The number of cells in DC system 21 and DC system 22, excluding the faulty cell, is 3m / x-1 each, and the AC output voltage is increased by 3m / (3m+2-x) times. The number of cells in DC systems 23 to 2x is a total of 3m-6m / x, and the AC output voltage is reduced by (3m-x) / (3m+2-x) times.

[0123] In the U phase, the number of cells connected to the DC system 21 and the DC system 22 is a total of 2m / x-2, excluding the faulty cell, and the number of cells connected to the other DC systems is m-2m / x. In the V and W phases, the number of cells connected to the DC system 21 and the DC system 22 is a total of 2m / x, and the number of cells connected to the other DC systems is m-2m / x.

[0124] Due to the failure, the AC output voltage of U phase will decrease by {(3m / (3m+2-x)) (2m / x-2) + ((3m-x) / (3m+2-x)) (m-2m / x)} / m = (3m-x-4) / (3m-x+2) times. The AC output voltage of V and W phases will decrease by {(3m / (3m+2-x)) 2m / x + ((3m-x) / (3m+2-x)) (m-2m / x)} / m = 1 time, and will not change before or after the failure.

[0125] Therefore, the coefficient N / n ｕ is set to (3m-x+2) / (3m-x-4). Since the third harmonic superposition is performed to reduce the peak value of the cell that has increased the AC output voltage, the amplitude of the third harmonic to be superposed is set to 3m / (3m+2-x).

[0126] The number of cells in which this third harmonic is superimposed on the U phase is 2m / x-2 units. Since the remaining cells m-2m / x units cancel this, the amplitude of the third harmonic to be superimposed on the remaining cells is -3m / (3m+2-x) * (2m / x-2) / (m-2m / x) = -6(m-x) / ((x-2)(3m+2-x)). The number of cells in which this third harmonic is superimposed on the V and W phases is 2m / x units. Since the remaining cells m-2m / x units cancel this, the amplitude of the third harmonic to be superimposed on the remaining cells is -3m / (3m+2-x) * (2m / x) / (m-2m / x) = -6m / ((x-2)(3m+2-x)).

[0127] (4) When two faulty cells are connected to different phases and different DC systems (stages) Consider the case where one faulty cell each is connected to U phase and V phase, respectively, connected to DC system 21 and DC system 22. The number of cells in DC system 21 and DC system 22, excluding the faulty cell, is 3m / x-1 each, and the AC output voltage is increased by 3m / (3m+2-x) times. The number of cells in DC systems 23 to 2x is a total of 3m-6m / x, and the AC output voltage is reduced by (3m-x) / (3m+2-x) times.

[0128] The total number of cells connected to DC system 21 and DC system 22 in U phase and V phase is 2m / x-1 for each phase excluding the faulty cell, and the total number of cells connected to other DC systems is m-2m / x. The total number of cells connected to DC system 21 and DC system 22 in W phase is 2m / x, and the total number of cells connected to other DC systems is m-2m / x.

[0129] Due to the failure, the AC output voltage of U and V phases will decrease by {(3m / (3m+2-x))*(2m / x-1)+((3m-x) / (3m+2-x))*(m-2m / x)} / m=(3m-x-1) / (3m-x+2) times. The AC output voltage of W phase will decrease by {(3m / (3m+2-x))*2m / x+((3m-x) / (3m+2-x))(m-2m / x)} / m=1 time, and will not change before or after the failure.

[0130] Therefore, the coefficient N / n ｕ , N / n ｖis set to (3m-x+2) / (3m-x-1). Since the third harmonic superposition is performed to reduce the peak value of the cell that has increased the AC output voltage, the amplitude of the third harmonic to be superposed is set to 3m / (3m+2-x).

[0131] The number of cells with this third harmonic superimposed on the U and V phases is 2m / x-1 units. Since the remaining cells m-2m / x units cancel this, the amplitude of the third harmonic to be superimposed on the remaining cells is -3m / (3m+2-x) * (2m / x-1) / (m-2m / x) = -3(2m-x) / ((x-2)(3m+2-x)). The number of cells with this third harmonic superimposed on the W phase is 2m / x units. Since the remaining cells m-2m / x units cancel this, the amplitude of the third harmonic to be superimposed on the remaining cells is -3m / (3m+2-x) * (2m / x) / (m-2m / x) = -6m / ((x-2)(3m+2-x)).

[0132] Table 1 summarizes the above. From Table 1, the voltage command values ​​V for each phase according to the number and location of the faulty cells are calculated. ｕ＿ｒｅｆ , V ｖ＿ｒｅｆ , V ｗ＿ｒｅｆ A fixed value to be multiplied by, coefficient N / n ｕ , N / n ｖ , N / n ｗ By referring to and applying the value to be set and the amplitude of the third harmonic to be superimposed, operation can be continued if up to two units fail.

[0133] If m is sufficiently large and the modular multilevel cascade converter (SST) can output the AC voltage required for grid connection even when only one cell is faulty, it may be possible not to superimpose the third harmonic. In this case, the third embodiment is applied when the number of faulty cells reaches two. Alternatively, if only one cell is faulty, the third harmonic V ０３ The amplitude of the superimposed third harmonic may be reduced, for example, by multiplying by a coefficient 2 / 3 to superimpose a third harmonic having 1 / 9 of the voltage amplitude before superimposition.

[0134] By expanding the above, it is possible to deal with cases where three or more cells fail. However, as the number of failed cells increases, the case distinction becomes more complicated, and there is a high possibility that the AC output voltage of the cells connected to the same DC system as the failed cell will need to be increased by more than 1.15 times. In this case, it becomes necessary to increase the cell primary DC voltage in advance. However, even when increasing the cell primary DC voltage, by applying this embodiment 3, the increase can be limited to √3 / 2 ≒ 0.866 times.

[0135] According to the third embodiment, the effects of the first and second embodiments can be obtained even when two cells fail.

[0136] Although the present invention has been described in detail above only with respect to the specific examples, it will be apparent to those skilled in the art that various modifications and variations are possible within the scope of the technical concept of the present invention, and it is natural that such modifications and variations fall within the scope of the claims.

[0137] 1...dq inverse converter, 2...first multiplier, 3...second multiplier, 4...first subtractor, 5...third multiplier, 6...first adder, 7...fourth multiplier, 8...arithmetic unit, 9...second adder, 10...third adder, SW1 to SW17...switches, ACDC...AC-DC converter, C1...primary side DC capacitor, DCDC...isolated DC-DC converter, C2...secondary side DC capacitor

Claims

1. A modular multilevel cascade converter having m (m: an integer of 2 or more) cells per phase, each cell comprising an AC-DC converter connected to an AC system, a primary-side DC capacitor connected to the DC side of the AC-DC converter, an isolated DC-DC converter having one DC side connected to the primary-side DC capacitor, and a secondary-side DC capacitor connected to the other DC side of the isolated DC-DC converter, and having x (x: an integer of 2 or more) DC systems in which a plurality of the secondary-side DC capacitors are connected in parallel, and supplying voltages of a plurality of the DC systems to loads or power sources, wherein a control unit of the AC-DC converter, when a cell fails, increases the output voltage on the AC system side of the cell connected to the same DC system as the failed cell, and decreases the output voltage on the AC system side of the cell connected to the other DC system, A modular multilevel cascade converter, characterized in that a third harmonic is superimposed on the AC output voltage of the cell connected to the same DC system as the failed cell, and a third harmonic in the opposite direction is superimposed on the AC output voltage of the cell connected to a DC system different from that of the failed cell.

2. The control unit of the AC-DC converter comprises: a second multiplier that, when one of the cells fails, multiplies each phase voltage command value of the AC-DC converter by 3m / (3m-x+1) for the cell connected to the same DC system as the failed cell, by (3m-x) / (3m-x+1) for the cell connected to a DC system different from that of the failed cell, and by 1 if there is no failed cell; and a third multiplier that multiplies the third harmonic by 3m / (3m+1-x) for the cell connected to the same DC system as the failed cell, by -3(m-x) / ((x-1)(3m+1-x)) for the cell connected to the same phase as the failed cell or to a different DC system, by -3m / (x-1)(3m+1-x) for the cell connected to a different phase from that of the failed cell or to a different DC system, and by 0 if there is no failed cell; 2. The modular multilevel cascade converter according to claim 1, comprising: a first adder that adds an output of the third multiplier to an output of the second multiplier; a primary DC voltage intra-phase balance control unit that outputs a primary DC voltage intra-phase balance control value based on an average primary DC voltage intra-phase value of each phase and the primary DC voltage of each cell; and a first subtractor that subtracts the primary DC voltage intra-phase balance control value from the output of the first adder to output each cell voltage command value, and generates a gate signal for the AC-DC converter based on each cell voltage command value.

3. The modular multilevel cascade converter according to claim 2, wherein the control unit of the AC-DC converter comprises: a dq inverse converter that converts a voltage command value on a rotating coordinate system into a voltage command value on a fixed coordinate system; a switch for each phase that outputs (3m-x+1) / (3m-x-2) as a coefficient for the phase to which the faulty cell is connected and 1 as a coefficient for the other phases; a fourth multiplier that multiplies the AC voltage of each phase by the output of the switch for each phase; a calculator that outputs a zero-phase voltage based on the output of the fourth multiplier and the coefficient; a third adder that adds the zero-phase voltage to the voltage command value on the fixed coordinate system; and a first multiplier that multiplies the output of the third adder by the reciprocal of an average value of the primary side DC voltages of all cells and outputs the result as the voltage command value for each phase.

4. When two of the cells connected to the same phase and the same DC system fail, the control unit of the AC-DC converter comprises: a dq inverse converter that converts a voltage command value on a rotating coordinate system into a voltage command value on a fixed coordinate system; a switch for each phase that outputs (3m-2x+2) / (3m-2x-4) as a coefficient for the phase to which the failed cell is connected and 1 as a coefficient for the other phases; a fourth multiplier that multiplies the AC voltage of each phase by the output of the switch for each phase; a calculator that outputs a zero-phase voltage based on the output of the fourth multiplier and the coefficient; a third adder that adds the zero-phase voltage to the voltage command value on the fixed coordinate system; and a first multiplier that multiplies the output of the third adder by the reciprocal of the average value of the primary side DC voltage of all cells and outputs the result as the voltage command value for each phase. a second multiplier that multiplies the phase voltage command value of the AC-DC converter by 3m / (3m+2-2x) for the cell connected to the same DC system as the failed cell, and by (3m-2x) / (3m+2-2x) for the cell connected to a DC system different from that of the failed cell; a third multiplier that multiplies a third harmonic by 3m / (3m+2-2x) for the cell connected to the same DC system as the failed cell, by -3(m-2x) / ((x-1)(3m+2-2x)) for the cell connected to the same phase as the failed cell or to a different DC system, and by -3m / (x-1)(3m+2-2x) for the cell connected to a different phase than that of the failed cell or to a different DC system; a first adder that adds an output of the third multiplier to an output of the second multiplier; 2. The modular multilevel cascade converter according to claim 1, comprising: a primary DC voltage intra-phase balance control unit that outputs a primary DC voltage intra-phase balance control value based on an average primary DC voltage intra-phase value of each phase and the primary DC voltage of each cell; and a first subtractor that outputs each cell voltage command value by subtracting the primary DC voltage intra-phase balance control value from the output of the first adder, and generates gate signals for the AC-DC converter based on each cell voltage command value.

5. When two of the cells connected to different phases but the same DC system fail, the control unit of the AC-DC converter comprises: a dq inverse converter that converts a voltage command value on a rotating coordinate system into a voltage command value on a fixed coordinate system; a switch for each phase that outputs (3m-2x+2) / (3m-2x-1) as a coefficient for the phase to which the failed cell is connected and 1 as a coefficient for the other phases; a fourth multiplier that multiplies the AC voltage of each phase by the output of the switch for each phase; a calculator that outputs a zero-phase voltage based on the output of the fourth multiplier and the coefficient; a third adder that adds the zero-phase voltage to the voltage command value on the fixed coordinate system; and a first multiplier that multiplies the output of the third adder by the reciprocal of the average value of the primary side DC voltage of all cells and outputs the result as the voltage command value for each phase. a second multiplier that multiplies the phase voltage command value of the AC-DC converter by 3m / (3m+2-2x) for the cell connected to the same DC system as the failed cell, and by (3m-2x) / (3m+2-2x) for the cell connected to a DC system different from that of the failed cell; a third multiplier that multiplies a third harmonic by 3m / (3m+2-2x) for the cell connected to the same DC system as the failed cell, by -3(m-x) / ((x-1)(3m+2-2x)) for the cell connected to the same phase as the failed cell or to a different DC system, and by -3m / (x-1)(3m+2-2x) for the cell connected to a different phase than that of the failed cell or to a different DC system; a first adder that adds an output of the third multiplier to an output of the second multiplier; 2. The modular multilevel cascade converter according to claim 1, comprising: a primary DC voltage intra-phase balance control unit that outputs a primary DC voltage intra-phase balance control value based on an average primary DC voltage intra-phase value of each phase and the primary DC voltage of each cell; and a first subtractor that subtracts the primary DC voltage intra-phase balance control value from the output of the first adder to output the each cell voltage command value, and generates a gate signal for the AC-DC converter based on the each cell voltage command value.

6. When two cells connected to the same phase but different DC systems fail, the control unit of the AC-DC converter comprises: a dq inverse converter that converts a voltage command value on a rotating coordinate system into a voltage command value on a fixed coordinate system; a switch for each phase that outputs (3m-x+2) / (3m-x-4) as a coefficient for the phase to which the failed cell is connected and 1 as a coefficient for the other phases; a fourth multiplier that multiplies the AC voltage of each phase by the output of the switch for each phase; a calculator that outputs a zero-phase voltage based on the output of the fourth multiplier and the coefficient; a third adder that adds the zero-phase voltage to the voltage command value on the fixed coordinate system; and a first multiplier that multiplies the output of the third adder by the reciprocal of the average value of the primary side DC voltage of all cells and outputs the result as the voltage command value for each phase. a second multiplier that multiplies the phase voltage command value of the AC-DC converter by 3m / (3m+2-x) for the cell connected to the same DC system as the failed cell, and by (3m-x) / (3m+2-x) for the cell connected to a DC system different from that of the failed cell; a third multiplier that multiplies a third harmonic by 3m / (3m+2-x) for the cell connected to the same DC system as the failed cell, by -6(m-x) / ((x-2)(3m+2-x)) for the cell connected to the same phase as the failed cell or to a different DC system, and by -6m / (x-2)(3m+2-x) for the cell connected to a different phase than that of the failed cell or to a different DC system; a first adder that adds an output of the third multiplier to an output of the second multiplier; 2. The modular multilevel cascade converter according to claim 1, comprising: a primary DC voltage intra-phase balance control unit that outputs a primary DC voltage intra-phase balance control value based on an average primary DC voltage intra-phase value of each phase and the primary DC voltage of each cell; and a first subtractor that subtracts the primary DC voltage intra-phase balance control value from the output of the first adder to output the each cell voltage command value, and generates a gate signal for the AC-DC converter based on the each cell voltage command value.

7. When two of the cells connected to different phases and different DC systems fail, the control unit of the AC-DC converter comprises: a dq inverse converter that converts a voltage command value on a rotating coordinate system into a voltage command value on a fixed coordinate system; a switch for each phase that outputs (3m-x+2) / (3m-x-1) as a coefficient for the phase to which the failed cell is connected and 1 as a coefficient for the other phases; a fourth multiplier that multiplies the AC voltage of each phase by the output of the switch for each phase; a calculator that outputs a zero-phase voltage based on the output of the fourth multiplier and the coefficient; a third adder that adds the zero-phase voltage to the voltage command value on the fixed coordinate system; and a first multiplier that multiplies the output of the third adder by the reciprocal of the average value of the primary side DC voltage of all cells and outputs the result as the voltage command value for each phase. a second multiplier that multiplies the phase voltage command value of the AC-DC converter by 3m / (3m+2-x) for the cell connected to the same DC system as the failed cell, and by (3m-x) / (3m+2-x) for the cell connected to a DC system different from that of the failed cell; a third multiplier that multiplies a third harmonic by 3m / (3m+2-x) for the cell connected to the same DC system as the failed cell, by -3(2m-x) / ((x-2)(3m+2-x)) for the cell connected to the same phase as the failed cell or to a different DC system, and by -6m / (x-2)(3m+2-x) for the cell connected to a different phase than that of the failed cell or to a different DC system; a first adder that adds an output of the third multiplier to an output of the second multiplier; 2. The modular multilevel cascade converter according to claim 1, comprising: a primary DC voltage intra-phase balance control unit that outputs a primary DC voltage intra-phase balance control value based on an average primary DC voltage intra-phase value of each phase and the primary DC voltage of each cell; and a first subtractor that subtracts the primary DC voltage intra-phase balance control value from the output of the first adder to output the each cell voltage command value, and generates a gate signal for the AC-DC converter based on the each cell voltage command value.

8. A control method for a modular multilevel cascade converter having m (m: an integer of 2 or more) cells per phase, each cell comprising an AC-DC converter connected to an AC system, a primary-side DC capacitor connected to the DC side of the AC-DC converter, an isolated DC-DC converter having one DC side connected to the primary-side DC capacitor, and a secondary-side DC capacitor connected to the other DC side of the isolated DC-DC converter, and having x (x: an integer of 2 or more) DC systems in which a plurality of the secondary-side DC capacitors are connected in parallel, and supplying voltages of a plurality of the DC systems to a load or a power source, wherein, when a cell fails, the control unit of the AC-DC converter increases the output voltage on the AC system side of the cell connected to the same DC system as the failed cell, and decreases the output voltage on the AC system side of the cell connected to the other DC system, A method for controlling a modular multilevel cascade converter, comprising: superimposing a third harmonic on the AC output voltage of a cell connected to the same DC system as the failed cell; and superimposing an opposite third harmonic on the AC output voltage of a cell connected to a DC system different from the failed cell.

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