Thin-film solar cell device, thin-film solar cell module, and manufacturing method thereof

Abstract

A thin-film solar cell device according to an embodiment of the present invention may comprise: a substrate; a solar cell including a first lower conductive layer, a first lower semiconductor layer, a first intermediate conductive layer, a first upper semiconductor layer, and a first upper conductive layer sequentially laminated upwardly on the substrate; a connection part including a second lower conductive layer connected to the first lower conductive layer and a second lower semiconductor layer, a second intermediate conductive layer, a second upper semiconductor layer, and a second upper conductive layer sequentially laminated upwardly on the second lower conductive layer; and a bypass diode including a third upper conductive layer connected to the second upper conductive layer and a third upper semiconductor layer, a third intermediate conductive layer, a third lower semiconductor layer, and a third lower conductive layer sequentially laminated downwardly from the third upper conductive layer. Therefore, the thin-film solar cell device and a thin-film solar cell module according to embodiments of the present invention may have a bypass diode embedded therein.

Description

Thin-film solar cell devices, thin-film solar cell modules, and methods for manufacturing them

[0001] The present invention relates to a thin film solar cell device, a thin film solar cell module, and a method for manufacturing the same, and more particularly, to a thin film solar cell device with a built-in bypass diode, a thin film solar cell module, and a method for manufacturing the same.

[0002] A solar cell module includes a plurality of solar cells connected in series and a bypass diode connected in parallel to one or more solar cells. When sunlight falls on the solar cells, photoelectric conversion generates and causes current to flow. At this time, a reverse voltage is applied to the bypass diode connected to the solar cells, so the bypass diode remains turned off. On the other hand, if some of the solar cells are defective and do not operate normally, or if some of the solar cells are shaded (shading), a forward voltage is applied to the bypass diode, turning it on and allowing current to flow through the bypass diode.

[0003] Accordingly, the current applied to the solar cell module is not applied to the solar cell that is not operating normally, but flows along the bypass diode connected to the solar cell that is not operating normally. Accordingly, even if a problem occurs in some of the multiple solar cells, the current generated in the remaining functioning solar cells is prevented from flowing and being blocked, thereby preventing the occurrence of solar cell module failure.

[0004] Solar cell modules including bypass diodes are divided into a type in which the solar cell and bypass diode are provided separately and the bypass diode is attached to the solar cell (external type), and a type in which the solar cell and bypass diode are formed together on the same substrate (built-in type).

[0005] In the case of the external type, the solar cell and bypass diode must be manufactured separately and then connected to the solar cell, which causes the process to be complicated and increases the cost.

[0006] Additionally, for embedded types, a bypass diode is manufactured simultaneously with the solar cell. Specifically, a lower conductive layer, a photoelectric conversion semiconductor layer, and an upper conductive layer are sequentially layered on a substrate, then etched using a photolithography process to form the solar cell and bypass diode. However, the photolithography process is extremely expensive. Consequently, the cost of forming a solar cell module increases.

[0007] (Prior art document) (Patent document 1) Korean registered patent KR2271899

[0008] The present invention provides a thin film solar cell device with a built-in bypass diode, a thin film solar cell module, and a method for manufacturing the same.

[0009] The present invention provides a thin-film solar cell device with a built-in bypass diode, a solar cell module, and a method for manufacturing the same, which can be manufactured at low cost.

[0010] The present invention provides a thin-film solar cell device, a solar cell module, and a method for manufacturing the same, which have a built-in bypass diode and can operate the bypass diode at a low voltage.

[0011] A thin film solar cell device according to an embodiment of the present invention may include a substrate; a solar cell including a first lower conductive layer, a first lower semiconductor layer, a first intermediate conductive layer, a first upper semiconductor layer, and a first upper conductive layer sequentially stacked upward on the substrate; a connecting portion including a second lower conductive layer connected to the first lower conductive layer, and a second lower semiconductor layer, a second intermediate conductive layer, a second upper semiconductor layer, and a second upper conductive layer sequentially stacked upward on the second lower conductive layer; and a bypass diode including a third upper conductive layer connected to the second upper conductive layer, and a third upper semiconductor layer, a third intermediate conductive layer, a third lower semiconductor layer, and a third lower conductive layer sequentially stacked downward on the third upper conductive layer.

[0012] The solar cell may include: a first lower pattern formed to penetrate the first lower conductive layer in the thickness direction and formed of a material for the first lower semiconductor layer; an intermediate pattern formed to penetrate the first intermediate conductive layer in the thickness direction to connect the first lower semiconductor layer and the first upper semiconductor layer and formed of a material for the first upper semiconductor layer; a first upper pattern formed to penetrate the first upper semiconductor layer, the first intermediate conductive layer, and the first lower semiconductor layer in the thickness direction to connect the first lower conductive layer, the first intermediate conductive layer, and the first upper conductive layer and formed of a material for the first upper conductive layer; and a first insulating pattern formed to penetrate the first upper conductive layer, the first upper semiconductor layer, the first intermediate conductive layer, and the first lower semiconductor layer in the thickness direction and formed on an upper side of the first lower conductive layer.

[0013] Based on the first horizontal direction of the substrate, when one end of the one end and the other end of the substrate are referred to as one side and the other end as the other side, the first insulating pattern, the first upper pattern, the first lower pattern, and the middle pattern may be arranged in the following order from one end of the substrate to the other end.

[0014] Among the first lower conductive layers, a region located on one side of the first lower pattern may be connected to the first upper conductive layer by the first upper pattern and may be connected to the third lower conductive layer of the bypass diode.

[0015] The connecting portion may include: a second lower pattern formed to penetrate the second lower conductive layer in the thickness direction and formed of a material for the second lower semiconductor layer; a second upper pattern formed to penetrate the second upper semiconductor layer, the second intermediate conductive layer, and the second lower semiconductor layer in the thickness direction and formed of a material for the second upper conductive layer to connect the second lower conductive layer, the second intermediate conductive layer, and the second upper conductive layer; and a second insulating pattern formed to penetrate the second upper conductive layer, the second upper semiconductor layer, the second intermediate conductive layer, and the second lower semiconductor layer in the thickness direction and formed on an upper side of the second lower conductive layer.

[0016] From one end of the above substrate to the other end, the second lower pattern, the second upper pattern, and the second insulating pattern may be arranged in that order.

[0017] The second lower conductive layer of the above-mentioned connecting portion is connected to the second upper conductive layer by the second upper pattern, and is connected to an area of ​​the first lower conductive layer of the solar cell located on the other side of the first lower pattern, and the second lower conductive layer can be spaced apart from the third lower conductive layer of the bypass diode by the second lower pattern.

[0018] The bypass diode is formed on one side of the third lower semiconductor layer, the third intermediate conductive layer, the third upper semiconductor layer, and the third upper conductive layer, and includes a third insulating pattern formed on an upper side of the third lower conductive layer, and the bypass diode can be connected to the connecting portion so as to be positioned on one side of the second lower pattern.

[0019] The first to third insulating patterns may be formed as empty spaces or formed of an insulating material.

[0020] The solar cell may extend in the first horizontal direction on the substrate, the connecting portion and the bypass diode may be arranged in the first horizontal direction, and the connecting portion and the bypass diode and the solar cell may be arranged in the second horizontal direction intersecting the first horizontal direction.

[0021] A thin film solar cell device according to an embodiment of the present invention includes a split pattern extending in the first horizontal direction so as to be positioned between the connecting portion and the bypass diode and the solar cell, wherein the split pattern may be formed as an empty space or formed of an insulating material.

[0022] The above split pattern is formed in a plurality, the plurality of split patterns are arranged in the second horizontal direction, and the connecting portion and bypass diode can be arranged between the plurality of split patterns arranged in the second horizontal direction.

[0023]

[0024] A thin film solar cell module according to an embodiment of the present invention may include a substrate; a solar cell formed on the substrate and having a plurality of semiconductor layers capable of converting received sunlight into photoelectric energy; a connecting portion formed on the substrate such that a lower conductive layer is connected to a lower conductive layer of the solar cell; and a battery portion including a bypass diode formed on the substrate such that an upper conductive layer is connected to a lower conductive layer of the connecting portion.

[0025] The plurality of semiconductor layers of the solar cell include a first lower semiconductor layer and a first upper semiconductor layer formed on an upper side of the first lower semiconductor layer, the lower conductive layer of the solar cell includes a first lower conductive layer formed between the substrate and the first lower semiconductor layer, the solar cell includes a first intermediate conductive layer formed between the first lower semiconductor layer and the first upper semiconductor layer, and a first upper conductive layer formed on the first upper semiconductor, the lower conductive layer of the connecting portion includes a second lower conductive layer formed on the substrate and connected to the first lower conductive layer, the connecting portion includes a second lower semiconductor layer, a second intermediate conductive layer, a second upper semiconductor layer, and a second upper conductive layer sequentially stacked in an upward direction on the second lower conductive layer, the upper conductive layer of the bypass diode includes a third upper conductive layer connected to the second lower conductive layer, the bypass diode includes a third lower conductive layer, and the plurality of semiconductor layers of the bypass diode are formed on the third lower conductive layer. The bypass diode may include a third lower semiconductor layer and a third upper semiconductor layer formed on an upper side of the third lower semiconductor layer, and a third intermediate conductive layer formed between the third lower semiconductor layer and the third upper semiconductor layer and a third upper conductive layer formed on the third upper semiconductor layer.

[0026] The solar cell may include: a first lower pattern formed to penetrate the first lower conductive layer in the thickness direction and formed of a material for the first lower semiconductor layer; an intermediate pattern formed to penetrate the first intermediate conductive layer in the thickness direction and formed of a material for the first upper semiconductor layer; a first upper pattern formed to penetrate the first upper semiconductor layer, the first intermediate conductive layer, and the first lower semiconductor layer in the thickness direction and formed of a material for the first upper conductive layer; and a first insulating pattern formed to penetrate the first upper conductive layer, the first upper semiconductor layer, the first intermediate conductive layer, and the first lower semiconductor layer in the thickness direction and formed on an upper side of the first lower conductive layer.

[0027] Based on the first horizontal direction of the substrate, when one end of the one end and the other end of the substrate are referred to as one side and the other end as the other side, the first insulating pattern, the first upper pattern, the first lower pattern, and the middle pattern may be arranged in the following order from one end of the substrate to the other end.

[0028] Among the first lower conductive layers, a region located on one side of the first lower pattern may be connected to the first upper conductive layer by the first upper pattern and may be connected to the third lower conductive layer of the bypass diode.

[0029] The connecting portion includes: a second lower pattern formed to penetrate the second lower conductive layer in the thickness direction and formed of a material for the second lower semiconductor layer; a second upper pattern formed to penetrate the second upper semiconductor layer, the second intermediate conductive layer, and the second lower semiconductor layer in the thickness direction and formed of a material for the second upper conductive layer to connect the second lower conductive layer, the second intermediate conductive layer, and the second upper conductive layer; and a second insulating pattern formed to penetrate the second upper conductive layer, the second upper semiconductor layer, the second intermediate conductive layer, and the second lower semiconductor layer in the thickness direction and formed on an upper side of the second lower conductive layer; and the second lower pattern, the second upper pattern, and the second insulating pattern may be arranged in this order from one end of the substrate to the other end.

[0030] The second lower conductive layer of the above-mentioned connecting portion is connected to the second upper conductive layer by the second upper pattern, and is connected to an area of ​​the first lower conductive layer of the solar cell located on the other side of the first lower pattern, and the second lower conductive layer can be spaced apart from the third lower conductive layer of the bypass diode by the second lower pattern.

[0031] The bypass diode is formed on one side of the third lower semiconductor layer, the third intermediate conductive layer, the third upper semiconductor layer, and the third upper conductive layer, and includes a third insulating pattern formed on an upper side of the third lower conductive layer, and the bypass diode can be connected to the connecting portion so as to be positioned on one side of the second lower pattern.

[0032] The first to third insulating patterns may be formed as empty spaces or formed of an insulating material.

[0033] The solar cell may extend in the first horizontal direction on the substrate, the connecting portion and the bypass diode may be arranged in the first horizontal direction, and the connecting portion and the bypass diode and the solar cell may be arranged in a second horizontal direction intersecting the first horizontal direction.

[0034] A thin film solar cell module according to an embodiment of the present invention includes a split pattern extending in the first horizontal direction so as to be positioned between the connecting portion and the bypass diode and the solar cell, wherein the split pattern may be formed as an empty space or formed of an insulating material.

[0035] The above split pattern is formed in a plurality, the plurality of split patterns are arranged in the second horizontal direction, and the connecting portion and bypass diode can be arranged between the plurality of split patterns arranged in the second horizontal direction.

[0036]

[0037] An embodiment of the present invention is a method for manufacturing a solar cell device, comprising: a solar cell formed on a substrate and having a plurality of semiconductor layers capable of converting received sunlight into photoelectric energy; a connecting portion formed on the substrate such that a lower conductive layer is connected to a lower conductive layer of the solar cell; and a bypass diode formed on the substrate such that an upper conductive layer is connected to a lower conductive layer of the connecting portion, wherein the process for manufacturing the solar cell, the connecting portion, and the bypass diode may include a scribing process.

[0038] A method for manufacturing a thin-film solar cell device according to an embodiment of the present invention comprises the steps of preparing a substrate extending in a first horizontal direction and a second horizontal direction intersecting the first horizontal direction, and the steps of manufacturing the solar cell, the connecting portion, and the bypass diode include the steps of forming a lower conductive layer on the substrate; etching the lower conductive layer in a thickness direction using a scribing process to form a lower groove; forming a lower semiconductor layer capable of converting received sunlight into electricity on the lower conductive layer, and filling the lower groove with a material for the lower semiconductor layer to form a lower pattern; forming an intermediate conductive layer on the lower semiconductor layer and the lower pattern; etching the intermediate conductive layer in a thickness direction using a scribing process to form an intermediate groove so that the intermediate groove has a different position in the first horizontal direction from the lower pattern; forming an upper semiconductor layer capable of converting received sunlight into electricity on the intermediate conductive layer, and filling the intermediate groove with a material for the upper semiconductor layer to form an intermediate pattern; The method may include: a process of forming an upper groove by etching the upper semiconductor layer, the middle conductive layer, and the lower semiconductor layer in the thickness direction using a scribing process so that the first horizontal direction positions are different from those of the lower pattern and the middle pattern; a process of forming an upper conductive layer on the upper semiconductor layer, and filling the upper groove with a material for the upper conductive layer to form an upper pattern;

[0039] The process of forming the lower groove may include a process of forming a first lower groove extending from one end of the substrate to the other end with respect to the second horizontal direction, and a process of forming a second lower groove extending from the other end of the substrate to the one end, and when one end of the one end and the other end of the substrate, which are both ends with respect to the first horizontal direction, is referred to as one side and the other end is referred to as the other side, in forming the first and second lower grooves, the first lower groove may be formed so as to be disposed on one side of the second lower groove, and the process of forming the lower pattern may include a process of forming the first and second lower patterns by filling the material for the lower semiconductor layer into the first and second lower grooves.

[0040] The process of forming the intermediate groove may include a process of forming the intermediate groove so as to extend from one end of the substrate to the other end based on the second horizontal direction; and in forming the intermediate groove, the intermediate groove may be formed so as to be positioned on the other side of the first lower groove based on the first horizontal direction, and the process of forming the intermediate pattern may include a process of forming the intermediate pattern by filling the semiconductor layer material into the intermediate groove.

[0041] The process of forming the upper groove may include a process of forming a first upper groove extending from one end of the substrate to the other end, based on the second horizontal direction, and a process of forming a second upper groove extending from the other end of the substrate to the one end; and in forming the first and second upper grooves, the first upper groove may be arranged on one side of the first lower groove, and the second upper groove may be arranged on the other side of the second lower groove, based on the first horizontal direction; and the process of forming the upper pattern may include a process of forming the first and second upper patterns by filling the upper conductive layer material into the first and second upper grooves.

[0042] A method for manufacturing a thin-film solar cell device according to an embodiment of the present invention includes: a process of forming an insulating pattern on one side of the first upper pattern, the insulating pattern penetrating through the upper conductive layer, the upper semiconductor layer, the intermediate conductive layer, and the lower semiconductor layer in the thickness direction and positioned on the upper side of the lower conductive layer; and a process of forming an insulating pattern on the other side of the second upper pattern, the insulating pattern penetrating through the upper conductive layer, the upper semiconductor layer, the intermediate conductive layer, and the lower semiconductor layer in the thickness direction and positioned on the upper side of the lower conductive layer; wherein the process of forming the insulating pattern may include a process of forming a void by etching the upper conductive layer, the upper semiconductor layer, the intermediate conductive layer, and the lower semiconductor layer in the thickness direction using a scribing process.

[0043] The process of forming the above insulating pattern may include a process of filling the empty space with an insulating material.

[0044] A method for manufacturing a thin film solar cell module according to an embodiment of the present invention may include a method for forming a plurality of solar cell devices.

[0045] Thin-film solar cell devices and thin-film solar cell modules according to embodiments of the present invention can incorporate bypass diodes. Furthermore, thin-film solar cell devices and thin-film solar cell modules including bypass diodes can be manufactured simply and at low cost. Furthermore, the operating voltage of the bypass diode can be lowered, allowing the bypass diode to operate at low voltages.

[0046] FIG. 1 is a three-dimensional diagram illustrating a thin-film solar cell module according to a first embodiment of the present invention.

[0047] FIG. 2 is a drawing illustrating a solar cell according to a first embodiment of the present invention by cutting through area E of FIG. 1 to explain the solar cell in more detail.

[0048] FIG. 3 is a drawing for explaining the polarity of the solar cell, connection part, and bypass diode of the second battery unit illustrated in FIG. 2.

[0049] Figure 4 is a cross-sectional view taken along line B-B' of Figure 1.

[0050] Fig. 5 is a cross-sectional view taken along line C-C' of Fig. 1.

[0051] Figure 6 is a cross-sectional view taken along line D-D' of Figure 1.

[0052] Figures 7 to 15 are process diagrams sequentially showing a method for manufacturing a thin film solar cell module according to the first embodiment of the present invention.

[0053] Figure 16 is a plan view of Figure 9.

[0054] Figure 17 is a plan view of Figure 12.

[0055] Figure 18 is a plan view of Figure 14.

[0056] Figure 19 is a plan view of Figure 15.

[0057] Fig. 20 is a plan view of Fig. 1.

[0058] FIG. 21 is a three-dimensional diagram illustrating a thin-film solar cell module according to a second embodiment of the present invention.

[0059] FIG. 22 is a drawing illustrating a cutaway view of area E of FIG. 21 to more specifically explain a solar cell according to a second embodiment of the present invention.

[0060] Hereinafter, embodiments of the present invention will be described in more detail with reference to the attached drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention. To illustrate the embodiments of the present invention, the drawings may be exaggerated, and like reference numerals in the drawings represent like components.

[0061] FIG. 1 is a three-dimensional view illustrating a thin-film solar cell module according to a first embodiment of the present invention. FIG. 2 is a diagram illustrating a section E of FIG. 1 in order to explain the solar cell according to the first embodiment of the present invention in more detail. FIG. 3 is a diagram for explaining the polarity of the solar cell, the connecting portion, and the bypass diode of the second battery unit illustrated in FIG. 2. FIG. 4 is a cross-sectional view taken along line B-B' of FIG. 1, FIG. 5 is a cross-sectional view taken along line C-C' of FIG. 1, and FIG. 6 is a cross-sectional view taken along line D-D' of FIG. 1.

[0062] The present invention relates to a thin-film solar cell device and a thin-film solar cell module, and more particularly, to a thin-film solar cell device and a thin-film solar cell module including a bypass diode. In other words, the present invention relates to a thin-film solar cell device and a thin-film solar cell module with a built-in bypass diode.

[0063] In addition, the thin film solar cell device and thin film solar cell module according to embodiments of the present invention may be of a tandem type including a plurality of semiconductor layers capable of generating current using received sunlight.

[0064] And, embodiments of the present invention may relate to a thin film solar cell device and a thin film solar cell module in which a bypass diode can be driven at a low voltage.

[0065] The thin-film solar cell device and thin-film solar cell module may be components of an artificial satellite. That is, the thin-film solar cell device and thin-film solar cell module according to an embodiment of the present invention may be installed in an artificial satellite. The artificial satellite may be a military satellite, for example, a reconnaissance satellite.

[0066] Hereinafter, a thin-film solar cell module according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 6. For convenience of explanation, the term "thin-film solar cell module" will be referred to as "solar cell module."

[0067] Referring to FIGS. 1 and 2, a solar cell module according to a first embodiment of the present invention may include a thin film type battery unit (200: 200a, 200b, 200c) having a substrate (100) and solar cells (SC: SC1, SC2, SC3) formed on the substrate (100) to generate current or electricity using received sunlight.

[0068] These solar cell modules can be connected to a battery (not shown), and the current generated by the solar cell modules can be stored in the battery.

[0069] The thin film type battery unit (200: 200a, 200b, 200c) may include a solar cell (SC: SC1, SC2, SC3), and a bypass unit (BP: BP1, BP2, BP3) connected to the solar cell (SC: SC1, SC2, SC3). In addition, the battery unit (200: 200a, 200b, 200c) may further include a blocking unit (not shown) installed on the upper portion of the bypass unit (BP: BP1, BP2, BP3) to block sunlight from entering. Accordingly, sunlight may enter the solar cell (SC: SC1, SC2, SC3), and the sunlight may be blocked from entering the bypass unit (BP: BP1, BP2, BP3).

[0070] The thin film cell unit (200: 200a, 200b, 200c) may be referred to as a thin film solar cell device. For convenience of explanation, the thin film cell unit (200: 200a, 200b, 200c) is referred to simply as the 'cell unit (200: 200a, 200b, 200c)' below.

[0071] The substrate (100) may be, for example, a substrate made of polyimide (PI). Of course, the substrate (100) is not limited to the above-described examples, and various substrates may be applied. For example, the substrate may be made of at least one of glass, ultra-thin glass (UTG), and space coverglass. Of course, the substrate is not limited to these, and various insulating materials may be used.

[0072] A solar cell module may include a plurality of cell sections (200: 200a, 200b, 200c). In addition, the plurality of cell sections (200: 200a, 200b, 200c) may be arranged in at least one direction, for example, the plurality of cell sections (200: 200a, 200b, 200c) may be arranged in a first horizontal direction (X-axis direction).

[0073] In the above, it has been described that a plurality of battery parts (200: 200a, 200b, 200c) are arranged in a first horizontal direction (X-axis direction), for example. However, this is not limited to the embodiment, and a plurality of battery parts (200: 200a, 200b, 200c) may be arranged in a second horizontal direction (Y-axis direction) that intersects or is perpendicular to the first horizontal direction (X-axis direction).

[0074] Hereinafter, the three battery sections (200a, 200b, 200c) are referred to as the first battery section (200a), the second battery section (200b), and the third battery section (200c) from one end of the substrate (100) to the other end. It is merely an example that the solar cell module includes three battery sections (200a, 200b, 200c), and the battery sections may be provided in various numbers. That is, the solar cell module may be provided with a plurality of battery sections exceeding three, or may be provided with two or one battery section.

[0075] Hereinafter, as illustrated in FIGS. 1 to 6, a solar cell module including three cell sections (200a, 200b, 200c) will be described as an example. And, with reference to FIGS. 1 to 6, the left end of the substrate (100) is defined as one end, and the right end is defined as the other end, based on the first horizontal direction (X-axis direction) of the substrate (100). In addition, with respect to a reference target, one end of the substrate (100) is defined as one side, and the other end of the substrate (100) is defined as the other end.

[0076] Each of the first to third battery sections (200: 200a, 200b, 200c) includes a solar cell (SC: SC1, SC2, SC3) that can receive sunlight and convert it into electricity (photoelectric conversion), a bypass section (BP: BP1, BP2, BP3) connected to the solar cell (SC: SC1, SC2, SC3), and a partition pattern (P) that is an empty space that can spatially divide the space between the solar cell (SC: SC1, SC2, SC3) and the bypass section (BP: BP1, BP2, BP3). d ) may be included.

[0077] As described above, each of the plurality of battery sections (200: 200a, 200b, 200c) includes a solar cell (SC: SC1, SC2, SC3), a bypass section (BP: BP1, BP2, BP3), and a split pattern (P d ) is included. To explain this again based on the solar cell module, the solar cell module includes a plurality of solar cells (SC: SC1, SC2, SC3), a plurality of bypass sections (BP: BP1, BP2, BP3), and a plurality of split patterns (P d ) may be included.

[0078] A plurality of solar cells (SC: SC1, SC2, SC3) can be connected in series. In addition, in each battery section (200: 200a, 200b, 200c), the solar cells (SC: SC1, SC2, SC3) and the bypass section (BP: BP1, BP2, BP3) can be connected in parallel. And in each battery section (200: 200a, 200b, 200c), the solar cells (SC: SC1, SC2, SC3) and the bypass section (BP: BP1, BP2, BP3) can be arranged in the second horizontal direction (Y-axis direction), for example. That is, the first solar cell (SC1) and the first bypass section (BP1) can be arranged in the second horizontal direction (Y-axis direction) and connected in parallel. In the case of the second and third battery units (200b, 200c), the second and third solar cells (SC1, SC2) and the second and third bypass units (BP1, BP2) can be connected in parallel and arranged in the second horizontal direction (Y-axis direction).

[0079]

[0080] Hereinafter, referring to FIGS. 1 to 6, solar cells constituting the battery section (200: 200a, 200b, 200c), (SC: SC1, SC2, SC3), bypass section (BP: BP1, BP2, BP3), and split pattern (P d ) is explained.

[0081] Referring to FIGS. 1 to 6, the solar cell (SC: SC1, SC2, SC3) may include a first lower conductive layer (210a), a first lower semiconductor layer (220a) formed on the first lower conductive layer (210a), a first intermediate conductive layer (230a) formed on the first lower semiconductor layer (220a), a first upper semiconductor layer (240a) formed on the first intermediate conductive layer (230a), and a first upper conductive layer (250a) formed on the first upper semiconductor layer (240a). In addition, the solar cell (SC: SC1, SC2, SC3) may include a first lower pattern (P) formed of a material for the first lower semiconductor layer (220a) and connecting the first lower conductive layer (210a) and the first lower semiconductor layer (220a). b1), connecting the first lower semiconductor layer (220a) and the first upper semiconductor layer (240a), and an intermediate pattern (P) formed of a material for the first upper semiconductor layer (240a) c ) and the first lower conductive layer (210a), the first middle conductive layer (230a), and the first upper conductive layer (250a) are connected, and the first upper pattern (P) is formed of a material for the first upper conductive layer (250a). t1 ), a first insulating pattern (P), which is an empty space arranged on one side of the first lower semiconductor layer (220a), the first middle conductive layer, the first upper semiconductor layer (240a), and the first upper conductive layer (250a) based on the first horizontal direction (X-axis direction) h1 ) may be included.

[0082] The first lower semiconductor layer (220a) and the first upper semiconductor layer (240a) of the solar cell (SC: SC1, SC2, SC3) are layers that can convert sunlight into electric current when sunlight is received, and may be referred to as light absorption layers. In addition, since the solar cell (SC: SC1, SC2, SC3) according to the embodiments includes a plurality of semiconductor layers (220a, 240a), it may be a tandem solar cell. In addition, the tandem solar cell includes a first intermediate conductive layer (230a) disposed between the first lower semiconductor layer (220a) and the first upper semiconductor layer (240a), as described above.

[0083] Referring to FIG. 1, the solar cells (SC: SC1, SC2, SC3) may include a first region (A1) extending in a first horizontal direction (X-axis direction) on a substrate (100) and a second region (A2) extending in a second horizontal direction (Y-axis direction) from an edge of the first region (A1) in the first horizontal direction (X-axis direction). At this time, the second region (A2) may be arranged at the other edge of the first region (A1). Accordingly, in each battery section (200a, 200b, 200c), the solar cells (SC1, SC2, SC3) may have a shape like the Korean consonant 'ㄱ'. The shapes of the solar cells (SC: SC1, SC2, SC3) described above are merely examples, and the shapes of the solar cells (SC: SC1, SC2, SC3) may be variously changed.

[0084] First insulation pattern (P h1 ) may be a hollow space or groove shape extending in the second horizontal direction (Y-axis direction). In addition, the first insulating pattern (P h1 ) can be formed to extend from one end of the second horizontal direction (Y-axis direction) of the substrate (100) to the other end. When described based on the up-down direction, the first insulating pattern (P h1 ) may be a hollow space or groove shape located on the upper side of the first lower conductive layer (210a). That is, the first insulating pattern (P h1 ) may be an empty space extending from the upper surface of the first lower conductive layer (210a) to the upper surface of the first upper conductive layer (250a). In terms of the first horizontal direction (X-axis direction), the first insulating pattern (P h1 ) may be an empty space provided on one side of the first lower semiconductor layer (220a), the first middle conductive layer (230a), the first upper semiconductor layer (240a), and the first upper conductive layer (250a). Accordingly, the first insulating pattern (P h1 ) may be a first lower semiconductor layer (220a), a first middle conductive layer (230a), a first upper semiconductor layer (240a), and a first lower conductive layer (210a) protruding to one side of the first upper conductive layer (250a).

[0085] The first sub-pattern (P) of the solar cell (SC: SC1, SC2, SC3) b1 ), intermediate pattern (P c ), first upper pattern (P t1 ), first insulation pattern (P h1 ) can be formed in the first region (A1) as shown in Fig. 2. And, the first lower pattern (P b1 ), intermediate pattern (P c ), first upper pattern (P t1 ), first insulation pattern (P h1 ) can be listed in the first horizontal direction (X-axis direction). At this time, the first lower pattern (P b1 ) on one side of the first upper pattern (P t1 ) is placed, and the first sub-pattern (P b1 ) on the other side of the middle pattern (P c ) are placed, and the first upper pattern (P t1 ) on one side of the first insulating pattern (P h1 ) can be arranged. When described from one end to the other end of the substrate (100), the first insulating pattern (P h1 ), first upper pattern (P t1 ), first sub-pattern (P b1 ), intermediate pattern (P c ) can be listed in order.

[0086] In the first region (A1) of the solar cell (SC: SC1, SC2, SC3), the first lower conductive layer (210a) is formed of a first lower pattern (P b1 ) can be divided into regions. That is, the first lower conductive layer (210a) is divided into the first lower pattern (P b1 ) and the first sub-pattern (P b1 ) can be separated into areas arranged on the other side. And, the first lower pattern (P b1 ) and the first lower conductive layer (210a) and the first lower pattern (P) are arranged on one side of the b1 ) is arranged on the other side of the first lower conductive layer (210a) and the first lower pattern (P b1) can be separated by a first sub-pattern (P). In addition, in the first region (A1) of each solar cell (SC1, SC2, SC3), a first sub-pattern (P b1 ) can be connected to the first lower conductive layer (210a) of another solar cell disposed on one side. In addition, in the first region (A1) of the solar cell (SC1, SC2, SC3), the first lower pattern (P b1 ) can be connected to the third lower conductive layer (210c) of the bypass diode (BD: BD1 to BD3). In addition, in the first region (A1) of each solar cell (SC1, SC2, SC3), the first lower pattern (P b1 ) can be connected to the first lower conductive layer (210a) of another solar cell disposed on the other side. In addition, in the first region (A1) of the solar cell (SC1, SC2, SC3), the first lower pattern (P b1 ) can be connected to the second lower conductive layer (210b) of the connecting portion (IC: IC1 to IC3).

[0087] In the first region (A1) of the solar cell (SC: SC1, SC2, SC3), the first intermediate conductive layer (230a) is an intermediate pattern (P c ) can be divided into areas. That is, the first intermediate conductive layer (230a) is an intermediate pattern (P c ) and the area placed on one side of the middle pattern (P c ) can be separated into areas arranged on the other side. And, the middle pattern (P c ) and the first intermediate conductive layer (230a) and the intermediate pattern (P) are arranged on one side of the c ) is arranged on the other side of the first intermediate conductive layer (230a) and the intermediate pattern (P c ) can be separated by.

[0088] In the first region (A1) of the solar cell (SC: SC1, SC2, SC3), the first lower semiconductor layer (220a) is formed on the first upper pattern (P t1 ) can be divided into regions. That is, the first lower semiconductor layer (220a) is divided into the first upper pattern (P t1 ) and the first upper pattern (P t1 ) can be separated into areas arranged on the other side. And, the first upper pattern (P t1 ) and the first lower semiconductor layer (220a) and the first upper pattern (P) are arranged on one side of the t1 ) is arranged on the other side of the first lower semiconductor layer (220a) and the first upper pattern (P t1 ) can be separated by.

[0089] In the first region (A1) of the solar cell (SC: SC1, SC2, SC3), the first upper semiconductor layer (240a) is formed of a first upper pattern (P t1 ) can be divided into regions. That is, the first upper semiconductor layer (240a) is divided into the first upper pattern (P t1 ) and the first upper pattern (P t1 ) can be separated into areas arranged on the other side. And, the first upper pattern (P t1 ) and the first upper semiconductor layer (240a) and the first upper pattern (P) are arranged on one side of the t1 ) is arranged on the other side of the first upper semiconductor layer (240a) and the first upper pattern (P t1 ) can be separated by.

[0090] Among the first region (A1) of the solar cell (SC: SC1, SC2, SC3), the first insulating pattern (P h1 ) from the area where the intermediate pattern (P) is formed c ) may be a dead area. That is, among the first region (A1) of the solar cell (SC: SC1, SC2, SC3), the first insulating pattern (P h1 ) from the area where the intermediate pattern (P) is formed c) may not cause photoelectric conversion in some areas where the first insulating pattern (P) is formed, and in other areas, photoelectric conversion may occur and current may be generated, but the current may be short-circuited and not flow to the battery and may be dissipated. This is because the first insulating pattern (P) h1 ) from the area where the intermediate pattern (P) is formed c ) is formed, the first upper pattern (P t1 ) by the first lower conductive layer (210a) and the first upper conductive layer (P h1 ) because they are connected.

[0091] In the second region (A2) of the solar cell (SC: SC1, SC2, SC3), the first lower conductive layer (210a) can be connected to the lower conductive layer (210b) of the connecting portion (IC: IC1, IC2, IC3) arranged on one side, and can be connected to the lower conductive layer (210c) of the bypass diode (BD: BD1, BD2, BD3) arranged on the other side.

[0092]

[0093] The bypass section (BP: BP1, BP2, BP3) may include a bypass diode (BD: BD1, BD2, BD3) arranged in parallel with the solar cell (SC: SC1, SC2, SC3), a first lower conductive layer (210a) of the solar cell (SC: SC1, SC2, SC3) and a connection section (IC: IC1, IC2, IC3) connected to the first upper conductive layer (250a) of the bypass diode (BD: BD1, BD2, BD3).

[0094] The second region (A2) of the solar cells (SC: SC1, SC2, SC3), the connecting portions (IC: IC1, IC2, IC3) and the bypass diodes (BD: BD1, BD2, BD3) may be arranged, for example, in the first horizontal direction (X-axis direction). Then, the connecting portions (IC: IC1, IC2, IC3) may be arranged on the other side of the bypass diodes (BD: BD1, BD2, BD3), and the second region (A2) of the solar cells (SC: SC1, SC2, SC3) may be arranged on the other side of the connecting portions (IC: IC1, IC2, IC3).

[0095] The first region (A1) and the bypass portion (BP: BP1, BP2, BP3) of the solar cells (SC: SC1, SC2, SC3) can be arranged in the second horizontal direction (Y-axis direction). And, a split pattern (P) is provided between the first region (A1) and the bypass portion (BP: BP1, BP2, BP3) of the solar cells (SC: SC1, SC2, SC3). d ) can be placed.

[0096] When sunlight is received by solar cells (SC: SC1, SC2, SC3), current is generated and flows through photoelectric conversion. At this time, a reverse voltage is applied to the bypass diodes (BD: BD1, BD2, BD3) connected to the solar cells (SC: SC1, SC2, SC3), so the bypass diodes (BD: BD1, BD2, BD3) are kept turned off. On the other hand, if some of the plurality of solar cells (SC: SC1, SC2, SC3) are shaded or some of them do not operate normally, a forward voltage higher than the operating voltage is applied to the bypass diodes (BD: BD1, BD2, BD3) by other solar cells that are operating normally. Accordingly, the bypass diodes to which the forward voltage is applied are turned on, and current flows through the turned-on bypass diodes. In other words, current is not applied to the malfunctioning solar cell, but instead flows through the bypass diode connected to the malfunctioning solar cell. Accordingly, even if a problem occurs in some of the multiple solar cells, the phenomenon of the malfunctioning solar cell blocking the flow of current can be suppressed or prevented, thereby preventing the occurrence of solar cell module failure.

[0097]

[0098] The connecting portion (IC: IC1, IC2, IC3) may include a second lower conductive layer (210b) connected to a first lower conductive layer (210a) of a solar cell (SC: SC1, SC2, SC3), a second lower semiconductor layer (220b) formed on the second lower conductive layer (210b), a second middle conductive layer (230b) formed on the second lower semiconductor layer (220b), a second upper semiconductor layer (240b) formed on the second middle conductive layer (230b), and a second upper conductive layer (250b) formed on the second upper semiconductor layer (240b).

[0099] In addition, the connecting portion (IC: IC1, IC2, IC3) connects the second lower conductive layer (210b) and the second lower semiconductor layer (220b) and is formed of a material for the second lower semiconductor layer (220b) and is formed of a second lower pattern (P b2 ), the second lower conductive layer (210b), the second middle conductive layer (230b), and the second upper conductive layer (250b) are connected, and the second upper pattern (P) is formed of a material for the second upper conductive layer (250b). t2 ), a second insulating pattern (P), which is an empty space provided on the outside of the second lower semiconductor layer (220b), the second upper semiconductor layer (240b), and the second upper conductive layer (250b) h2 ) may be included.

[0100] The second sub-pattern (P) of the connection (IC: IC1, IC2, IC3) b2 ), second upper pattern (P t2 ), second insulation pattern (P h2 ) can be arranged in the first horizontal direction (X-axis direction). And, the solar cells (SC: SC1 to SC3) have an intermediate pattern (P) connecting the first lower semiconductor layer (220a) and the first upper semiconductor layer (240a). c ), but the connecting portion (IC: IC1, IC2, IC3) may not include an intermediate pattern connecting the second lower semiconductor layer (220b) and the second upper semiconductor (240b) layer. That is, the solar cell (SC: SC1 to SC3) may include four patterns (the first lower pattern (P b1 ), intermediate pattern (P c ), first upper pattern (P t1 ) and the first insulation pattern (P h1 )) and the connection part (IC: IC1, IC2, IC3) includes three patterns (second lower pattern (P b2 ), second upper pattern (P t2 ), second insulation pattern (P h2 )) may be included. And, the second sub-pattern (P b2 ), second upper pattern (P t2 ), second insulation pattern (P h2) are listed in the order of the first sub-pattern (P) of the solar cell (SC: SC1, SC2, SC3). b1 ), intermediate pattern (P c ), first upper pattern (P t1 ), first insulation pattern (P h1 ) may be in the opposite direction to the listed direction. That is, in the case of the connection (IC: IC1, IC2, IC3), the second sub-pattern (P b2 ) on the other side of the second upper pattern (P t2 ) is placed, and the second upper pattern (P t2 ) on the other side of the second insulating pattern (P h2 ) can be arranged. When described from one end of the substrate (100) to the other end, when described from one end of the substrate (100) to the other end, the second lower pattern (P b2 ), second upper pattern (P t2 ), second insulation pattern (P h2 ) can be listed in order.

[0101] Second insulation pattern (P h2 ) can mean empty space. When explained based on the vertical direction, the second insulating pattern (P h2 ) may be an empty space provided on the upper side of the second lower conductive layer (210b). That is, the second insulating pattern (P h2 ) may be an empty space extending from the upper surface of the second lower conductive layer (210b) to the upper surface of the second upper conductive layer (250b). In other words, the second insulating pattern (P h2 ) may be an empty space arranged on the other side of the second lower semiconductor layer (220b), the second intermediate conductive layer (230b), the second upper semiconductor layer (240b), and the second upper conductive layer (250b). Accordingly, the second insulating pattern (P h2 ) may be a second lower semiconductor layer (220b), a second middle conductive layer (230b), a second upper semiconductor layer (240b), and a second lower conductive layer (210b) protruding from the other side of the second upper conductive layer (250b).

[0102] In each battery section (200: 200a, 200b, 200c), the second region (A2) and the connection section (IC: IC1, IC2, IC3) of the solar cell (SC: SC1, SC2, SC3) are formed with a second insulating pattern (P h2 ) can be spatially separated. That is, the second region (A2) and the connection portion (IC: IC1, IC2, IC3) of the adjacently arranged solar cells (SC: SC1, SC2, SC3) can be separated by the remaining layers except for the lower conductive layer. To be more specific, in the second region (A2) and the connection portion (IC: IC1, IC2, IC3) of the adjacently arranged solar cells (SC: SC1, SC2, SC3), the first lower semiconductor layer (220a), the first intermediate conductive layer (230a), the first upper semiconductor layer (240a), the first upper conductive layer (250a) of the solar cells (SC: SC1, SC2, SC3) and the second lower semiconductor layer (220b), the second intermediate conductive layer (230b), the second upper semiconductor layer (240b), and the second upper conductive layer (250b) of the connection portion (IC: IC1, IC2, IC3) can be separated. And, in the second region (A2) and the connection part (IC: IC1, IC2, IC3) of the adjacently arranged solar cells (SC: SC1, SC2, SC3), the first lower conductive layer (210a) of the solar cells (SC: SC1, SC2, SC3) and the second lower conductive layer (210b) of the connection part (IC: IC1, IC2, IC3) can be connected. That is, the second insulating pattern (P h2 ) and the first lower conductive layer (210a) of the solar cell (SC: SC1, SC2, SC3) can be connected.

[0103] The second lower challenge layer (210b) is a second lower pattern (P b2 ) can be divided into regions. That is, the second lower conductive layer (210b) is divided into the second lower pattern (P b2 ) and the second lower pattern (P b2 ) can be separated into areas arranged on the other side. And, the second lower pattern (Pb2 ) and the second lower conductive layer (210b) and the second lower pattern (P) are arranged on one side of the b2 ) is arranged on the other side of the second lower conductive layer (210b) and the second lower pattern (P b2 ) can be separated by a second sub-pattern (P b2 ) can be connected to the first lower conductive layer (210a) of the solar cell (SC: SC1, SC2, SC3).

[0104] The second lower semiconductor layer (220b) is formed by the second upper pattern (P t2 ) can be divided into regions. That is, the second lower semiconductor layer (220b) is divided into the second upper pattern (P t2 ) and the second upper pattern (P t2 ) can be separated into areas arranged on the other side. And, the second upper pattern (P t2 ) and the second lower semiconductor layer (220b) and the second upper pattern (P) are arranged on one side of the t2 ) is arranged on the other side of the second lower semiconductor layer (220b) and the second upper pattern (P t2 ) can be separated by.

[0105] The second upper semiconductor layer (240b) is a second upper pattern (P t2 ) can be divided into regions. That is, the second upper semiconductor layer (240b) is divided into the second upper pattern (P t2 ) and the second upper pattern (P t2 ) can be separated into areas arranged on the other side. And, the second upper pattern (P t2 ) and the second upper semiconductor layer (240b) arranged on one side of the second upper pattern (P t2 ) is arranged on the other side of the second upper semiconductor layer (240b) and the second upper pattern (P t2 ) can be separated by.

[0106] As described above, the connecting portion (IC: IC1 to IC3) does not include an intermediate pattern connecting the second lower semiconductor layer and the second upper semiconductor layer (240b). That is, there is no separate pattern formed of a semiconductor layer material between the second lower semiconductor layer (220b) and the second upper semiconductor layer (240b). In addition, the connecting portion (IC: IC1 to IC3) does not include an intermediate pattern connecting the second upper pattern (P t2 ) extends from the second lower conductive layer (210b) to the second upper conductive layer (250b).

[0107] Therefore, the second upper semiconductor layer (240b) of the connection portion (IC: IC1 to IC3) may be short-circuited. As a result, a potential difference does not occur between the second lower semiconductor layer (220b) and the second upper semiconductor layer (240b) of the connection portion (IC: IC1 to IC3). In other words, the second upper semiconductor layer (240b) of the connection portion (IC: IC1 to IC3) may be short-circuited, resulting in a second upper pattern (P t2 ) flows directly to the second lower semiconductor layer (220b). For example, when an intermediate pattern formed of a semiconductor layer material is provided to connect the second lower semiconductor layer (220b) and the second upper semiconductor layer (240b), current can flow to the second lower semiconductor layer (220b) via the second upper semiconductor layer (240b). However, in the embodiment, there is no intermediate pattern formed of a semiconductor layer material between the second lower semiconductor layer (220b) and the second upper semiconductor layer (240b). Therefore, a potential difference may not be generated from the second upper semiconductor layer of the connection portion (IC: IC1 to IC3) to the second lower semiconductor layer.

[0108]

[0109] The bypass diode (BD: BD1, BD2, BD3) may include a third lower conductive layer (210c), a third lower semiconductor layer (220c) formed on the third lower conductive layer (210c), a third intermediate conductive layer (230c) formed on the third lower semiconductor layer (220c), a third upper semiconductor layer (240c) formed on the third intermediate conductive layer (230c), and a third upper conductive layer (250c) formed on the third upper semiconductor layer (240c). In addition, the bypass diode (BD: BD1, BD2, BD3) may include a third insulating pattern (P), which is an empty space provided on one side of the third lower semiconductor layer (220c), the third intermediate conductive layer (230c), the third upper semiconductor layer (240c), and the third upper conductive layer (250c). h3 ) may be included.

[0110] If we explain based on the vertical direction, the third insulation pattern (P h3 ) may be an empty space provided on the upper side of the third lower conductive layer (210c). That is, the third insulating pattern (P h3 ) may be an empty space extending from the upper surface of the third lower conductive layer (210c) to the upper surface of the third upper conductive layer (250c). Accordingly, the third insulating pattern (P h3 ) may be a third lower conductive layer (210c). That is, a third insulating pattern (P h3 ) may be a third lower semiconductor layer (220c), a third intermediate conductive layer (230c), a third upper semiconductor layer (240c), and a first lower conductive layer (210a) protruding to one side of the third upper conductive layer (250c).

[0111] The third lower conductive layer (210c) of the bypass diode (BD: BD1, BD2, BD3) can be connected to the first lower conductive layer (210a) of the solar cell (SC: SC1, SC2, SC3). That is, the first lower conductive layer (210a) of the first region (A1) of the solar cell (SC: SC1, SC2, SC3) and the third lower conductive layer (210c) of the bypass diode (BD: BD1, BD2, BD3) can be connected. In addition, the third lower conductive layer (210c) of the bypass diode (BD: BD1, BD2, BD3) and the second lower conductive layer (210b) of the connection portion (IC: IC1, IC2, IC3) are connected to the second lower pattern (P b2 ) are separated by a third upper conductive layer (250c) of the bypass diode (BD: BD1, BD2, BD3) is connected to the second upper conductive layer (250b) of the connecting portion (IC: IC1, IC2, IC3).

[0112] As described above, the connecting portion (IC: IC1 to IC3) does not include an intermediate pattern connecting the second lower semiconductor layer and the second upper semiconductor layer (240b). Therefore, a potential difference may not be generated between the second lower semiconductor layer (220b) and the second upper semiconductor layer (240b) of the connecting portion (IC: IC1 to IC3).

[0113] Accordingly, the bypass diodes (BD: BD1 to BD3) may not generate a potential difference between the third lower semiconductor layer (220c) and the third upper semiconductor layer (240c) in the same manner as the connection portions (IC: IC1 to IC3). In other words, current may not flow from the third upper semiconductor layer (240c) of the bypass diodes (BD: BD1 to BD3) to the third lower semiconductor layer (220c).

[0114]

[0115] Hereinafter, with reference to FIGS. 4 and 6, when a failure occurs in any one of a plurality of solar cells (SC: SC1, SC2, SC3), the flow of current in the solar cells (SC: SC1, SC2, SC3), the connectors (IC: IC1, IC2, IC3), and the bypass diodes (BP: BP1, BP2, BP3) will be described. At this time, a situation in which a second solar cell (SC2) among the plurality of solar cells (SC: SC1, SC2, SC3) fails will be described as an example. In FIGS. 4 and 6, arrows (→, ←, ↑, ↓, etc.) indicate a situation in which current flows, and the direction of the arrows means the direction in which the current flows. In addition, 'X' in FIGS. 4 and 6 indicates that the movement of current is blocked.

[0116] Referring to Fig. 4, the current can flow from the third solar cell (SC3) to the second solar cell (SC2). That is, the current can flow through the first lower conductive layer (210a), the first lower semiconductor layer (220a), the first middle conductive layer (230a), the first upper semiconductor layer (240a), the first upper conductive layer (250a), and the first upper pattern (P) of the third solar cell (SC3). t1 ) and moves to the first lower conductive layer (210a) of the second solar cell (SC2).

[0117] At this time, since the second solar cell (SC2) is in an abnormal state, the current flow from the first lower conductive layer (210a) to the first lower semiconductor layer (220a) is blocked, and the current flows to the first solar cell (SC1) by bypassing the second bypass diode (BD2). More specifically, since a reverse voltage is applied to the first and third bypass diodes (BD1, BD2) connected to the first and third solar cells (SC1, SC3) that are operating normally, the first and third bypass diodes (BD1, BD2) are maintained in a turned-off state. On the other hand, since the second solar cell (SC2) is not operating normally, a forward voltage higher than the operating voltage is applied to the second bypass diode (BD2) by the first and third solar cells (SC1, SC3) that are operating normally. Accordingly, the second bypass diode (BD2) to which the forward voltage is applied is turned on, and current flows through the turned-on second bypass diode (BD2). That is, the current is not applied to the second solar cell (SC2) that is not operating normally, but bypasses the second bypass diode (BD2) connected to the second solar cell (SC2) and moves to the first lower conductive layer (210a) of the first solar cell (SC1). This will be described in more detail with reference to FIGS. 4 and 6. The current that has moved to the first lower conductive layer (210a) of the second solar cell (SC2) does not move to the first lower semiconductor layer (220a), but moves along the second connector (IC2) and the second bypass diode (BD2) connected to the second solar cell (SC2) and moves to the first lower conductive layer (210a) of the first solar cell (SC1). Accordingly, even if a problem occurs in some of the plurality of solar cells, the phenomenon of the solar cell in which the problem occurred blocking the flow of current can be suppressed or prevented, and thus, the occurrence of a defect in the solar cell module can be prevented.

[0118] And, the bypass portion (BP: BP1, BP2, BP3) according to the embodiment does not include an intermediate pattern as described above. That is, the connection portion (IC: IC1 to IC3) does not include an intermediate pattern connecting the second lower semiconductor layer (220b) and the second upper semiconductor layer (240b). Therefore, the bypass diode (BD: BD1 to BD3) may not generate a potential difference between the third lower semiconductor layer (220c) and the third upper semiconductor layer (240c). Accordingly, when the current moves along the bypass diode (BD: BD1, BD2, BD3), it may flow without passing through the third upper semiconductor layer (240c). That is, the second upper pattern (P) of the connection portion (IC: IC1, IC2, IC3) t2 ) may or may not flow along the second intermediate conductive layer (230b) and move to the third lower semiconductor layer (220c).

[0119] Referring to Fig. 6, an example will be described in which the first and third solar cells (SC1, SC3) operate normally and the second solar cell (SC2) does not operate normally.

[0120] Since the first and third solar cells (SC1, SC2) operate normally, the first and third bypass diodes (BD1, BD3) remain turned off. Accordingly, the current that moves along the first lower conductive layer (210a) of the third solar cell (BD3) to the second lower conductive layer (210b) of the third connector (IC3) flows to the second upper pattern (P t2 ) moves along. And, the second upper pattern (P t2 ) flows along the third intermediate conductive layer (230c) of the third bypass diode (BD3), and movement to the third lower semiconductor layer (220c) is blocked. Similarly, the current that moves along the first lower conductive layer (210a) of the first solar cell (SC1) to the second lower conductive layer (210b) of the first connector (SC1) flows along the second upper pattern (P t2) moves along. And, the second upper pattern (P t2 ) flows along the third intermediate conductive layer (230c) of the first bypass diode (BP1), and movement to the third lower semiconductor layer (220c) is blocked.

[0121] And, since the second solar cell (SC2) does not operate normally, a forward voltage higher than the operating voltage is applied to the second bypass diode (BD2) by the first and third solar cells (SC1, SC3) that operate normally. Accordingly, the second bypass diode (BD2) to which the forward voltage is applied is turned on, and current flows through the turned-on second bypass diode (BD2).

[0122] That is, the current that moves along the first lower conductive layer (210a) of the second solar cell (SC2) to the second lower conductive layer (210b) of the second connector (IC2) flows through the second upper pattern (P t2 ) moves along. And, the second upper pattern (P t2 ) flows along the third intermediate conductive layer (230c), the third lower semiconductor layer (220c), and the third lower conductive layer (210c) of the second bypass diode (BD2) and moves to the first solar cell (SC1). That is, when the second solar cell (SC2) is not operating normally and the current flows bypassing the second bypass diode (BD2), the current can flow along the third intermediate conductive layer (230c), the third lower semiconductor layer (220c), and the third lower conductive layer (210c) without passing through the third upper semiconductor layer (240c) of the second bypass diode (BD2).

[0123] In this way, as the current flows without passing through the third upper semiconductor layer (240c) of the second bypass diode (BD2), the operating voltage of the second bypass diode (BD2) can be lowered. That is, when a forward voltage higher than the operating voltage is applied to the second bypass diode (BD2) to turn on the second bypass diode (BD2), the current does not flow to the third upper semiconductor layer (240c), but flows along the third lower semiconductor layer (220c), so that the second bypass diode (BD2) can be turned on at a low voltage.

[0124] Here, the operating voltage of the bypass diode (BD: BD1, BD2, BD3) may mean the voltage consumed by the bypass diode when the bypass diode (BD: BD1, BD2, BD3) is operated or turned on.

[0125] Meanwhile, in the case of a tandem solar cell module, the band gap of the upper semiconductor layers (240a to 240c) is higher than the band gap of the lower semiconductor layers (220a to 220c). That is, the upper semiconductor layers (240a to 240c) are formed of a material having a relatively high band gap, and the lower semiconductor layers (220a to 220c) are formed of a material having a relatively lower band gap than the upper semiconductor layers (240a to 240c). In general, when a photon is converted into an electron in a semiconductor having a higher band gap, a higher potential difference is generated, so the voltage value of the solar cell is high and the operating voltage as a diode is also high. Therefore, when a current passes through the upper semiconductor layers (240a to 240c) having a high band gap, the power consumed is large.

[0126] In the embodiment, the current does not flow through the third upper semiconductor layer (240c) among the third upper semiconductor layer (240c) and the third lower semiconductor layer (220c), but flows along the third lower semiconductor layer (220c). In this way, since the current flows along one of the two semiconductor layers (220c, 240c), the bypass diodes (BD: BD1, BD2, BD3) can be turned on even at a relatively low voltage, thereby bypassing the current. That is, when a forward voltage higher than the operating voltage is applied to the bypass diodes (BD: BD1, BD2, BD3) to turn on the bypass diodes (BD: BD1, BD2, BD3), the bypass diodes (BD: BD1, BD2, BD3) can be turned on at a low voltage as the current flows along the third lower semiconductor layer (220c) instead of flowing to the third upper semiconductor layer (240c).

[0127]

[0128] Split pattern (P d ) may be a groove that penetrates the five layers formed on the substrate (100) in the thickness direction (Z-axis direction) and extends in the first horizontal direction (X-axis direction). That is, the split pattern (P d ) may be a groove formed to extend in the first horizontal direction (X-axis direction) while penetrating the upper conductive layer, the upper semiconductor layer, the middle conductive layer, the lower semiconductor layer, and the lower conductive layer in the thickness direction (Z-axis direction). And the split pattern (P d ) is based on the first horizontal direction (X-axis direction), the first and third insulation patterns (P h1 , P h3 ) and the second insulation pattern (P h2 ) is formed to be located between the split pattern (P d ) is the first and third insulation patterns (P h1 , P h3 ) and is connected to the split pattern (P d ) is the second insulating pattern (P h2 ) can be connected.

[0129]

[0130] The first to third lower conductive layers (210a, 210b, 210c) may be formed of a material having electrical conductivity. And the first to third lower conductive layers (210a, 210b, 210c) may be formed of the same material. For example, the first to third lower conductive layers (210a, 210b, 210c) may be formed of a metal, for example, molybdenum (Mo). Of course, the first to third lower conductive layers (210a, 210b, 210c) are not limited to the above-described examples and may be formed of various materials that can reflect light and have electrical conductivity. For example, the first to third lower conductive layers (210a, 210b, 210c) may be formed of a material having light transmittance and electrical conductivity. That is, the first to third lower conductive layers (210a, 210b, 210c) may be formed of a TCO (Transparent Conductive Oxide), and may be formed of, for example, at least one of ITO (Indium tin oxide) and IZO (Indium Zinc Oxide).

[0131] The first to third lower conductive layers (210a, 210b, 210c) can be formed using at least one of, for example, a sputtering deposition method, a thermal evaporation method, a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, a coating method, a printing method, and an inkjet method. In addition, the coating method can use, for example, a slot-die coating method. Of course, the first to third lower conductive layers (210a, 210b, 210c) are not limited to the above-described examples, and can be formed using various methods.

[0132]

[0133] The first to third lower semiconductor layers (220a, 220b, 220c) are layers that can absorb sunlight and convert it into electricity, and may have a structure in which multiple layers are stacked. That is, the first to third lower semiconductor layers (220a, 220b, 220c) may have a structure in which a p-type semiconductor layer and an n-type semiconductor layer are stacked. At this time, the first to third lower semiconductor layers (220a, 220b, 220c) may have a PN stacked structure in which a p-type semiconductor layer is an upper layer and an n-type semiconductor layer is a lower layer, or an NP stacked structure in which an n-type semiconductor layer is an upper layer and a p-type semiconductor layer is a lower layer. As another example, the first to third lower semiconductor layers (220a, 220b, 220c) may have a structure in which an i-type semiconductor layer is inserted between a p-type semiconductor layer and an n-type semiconductor layer. At this time, the first to third lower semiconductor layers (220a, 220b, 220c) may be a PiN stacked structure in which a p-type semiconductor layer is an upper layer and an n-type semiconductor layer is a lower layer, or a NiP stacked structure in which an n-type semiconductor layer is an upper layer and a p-type semiconductor layer is a lower layer. The first to third lower semiconductor layers (220a, 220b, 220c) may be made of a CIGS compound, which is a compound containing copper (Cu), indium (In), gallium (Ga), and selenium (Se).

[0134] The first to third lower semiconductor layers (220a, 220b, 220c) may be formed, for example, by using at least one of a thermal evaporation method, a chemical vapor deposition (CVD), an atomic layer deposition (ALD) method, a sputtering deposition method, a coating method, a printing method, and an inkjet method. In addition, a slot-die coating method may be used as the coating method. Of course, the semiconductor layers are not limited to the examples described above, and may be formed using various methods. The first to third lower semiconductor layers (220a, 220b, 220c) may be formed with the same structure and material.

[0135]

[0136] The first to third intermediate conductive layers (230a to 230c) may be formed using at least one of, for example, a sputtering deposition method, a thermal evaporation method, a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, a coating method, a printing method, and an inkjet method. In addition, the coating method may use, for example, a slot-die coating method. Of course, the first to third intermediate conductive layers (230a to 230c) are not limited to the above-described examples, and may be formed using various methods.

[0137]

[0138] The first to third upper semiconductor layers (240a to 240c) are layers that can absorb sunlight and convert it into electricity, and may have a structure in which multiple layers are stacked. That is, the first to third upper semiconductor layers (240a to 240c) may have a structure in which a p-type semiconductor layer and an n-type semiconductor layer are stacked. In this case, the first to third upper semiconductor layers (240a to 240c) may have a PN stacked structure in which a p-type semiconductor layer is an upper layer and an n-type semiconductor layer is a lower layer, or an NP stacked structure in which an n-type semiconductor layer is an upper layer and a p-type semiconductor layer is a lower layer. As another example, the first to third upper semiconductor layers (240a to 240c) may have a structure in which an i-type semiconductor layer is inserted between a p-type semiconductor layer and an n-type semiconductor layer. At this time, the first to third upper semiconductor layers (240a to 240c) may be a PiN stacked structure in which a p-type semiconductor layer is an upper layer and an n-type semiconductor layer is a lower layer, or a NiP stacked structure in which an n-type semiconductor layer is an upper layer and a p-type semiconductor layer is a lower layer. The first to third upper semiconductor layers (240a to 240c) may be formed of a material having a higher band gap than the first to third lower semiconductor layers (220a to 220c). For example, the first to third upper semiconductor layers (240a to 240c) may be formed of, for example, a perovskite structure semiconductor.

[0139] The first to third upper semiconductor layers (240a to 240c) can be formed using at least one method selected from the group consisting of a thermal evaporation method, a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, a sputtering deposition method, a coating method, a printing method, and an inkjet method. In addition, a slot-die coating method, for example, can be used as the coating method. Of course, the semiconductor layers are not limited to the examples described above, and can be formed using various methods. The first to third upper semiconductor layers (240a to 240c) can be formed using the same structure and material.

[0140]

[0141] The first to third upper conductive layers (250a to 250c) may be formed of a material that is transparent to sunlight and has electrical conductivity. In addition, the first to third upper conductive layers (250a to 250c) may be formed of the same material. For example, the first to third upper conductive layers (250a to 250c) may be formed of either IZO (Indium Zinc Oxide) or ITO (Indium Tin Oxide). Of course, the first to third upper conductive layers (250a to 250c) are not limited to the above-described examples and may be formed of various materials that are transparent to sunlight and have electrical conductivity.

[0142] The first to third upper conductive layers (250a to 250c) can be formed using at least one of, for example, a sputtering deposition method, a thermal evaporation method, a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, a coating method, a printing method, and an inkjet method. In addition, the coating method can use, for example, a slot-die coating method. Of course, the first to third upper conductive layers (250a to 250c) are not limited to the above-described examples, and can be formed using various methods.

[0143] In manufacturing a solar cell module, the first to third lower conductive layers (210a, 210b, 210c) are formed simultaneously or together, and the first to third lower semiconductor layers (220a to 220c) and the first and second lower patterns (P b1 , P b2 ) can be formed simultaneously or together. In addition, the first to third intermediate conductive layers (230a to 230c) can be formed simultaneously or together, and the first to third upper semiconductor layers (240a to 240c) and the intermediate pattern (P c ) can be formed simultaneously or together. In addition, the first to third upper conductive layers (250a to 250c) and the first and second upper patterns (P t1 , P t2 ) can be formed simultaneously or together. Here, forming simultaneously or together can mean forming through the same process at the same time.

[0144]

[0145] In the solar cell section, the solar cells (SC: SC1, SC2, SC3) and the bypass section (BP: BP1, BP2, BP3) must be connected with opposite polarities. To this end, in the first embodiment, a connection section (IC: IC1, IC2, IC3) connecting the solar cells (SC: SC1, SC2, SC3) and the bypass diode (BD: BD1, BD2, BD3) is formed. That is, a connection section (IC: IC1, IC2, IC3) connecting the first lower conductive layer (210a) of the solar cells (SC: SC1, SC2, SC3) and the second upper conductive layer (250b) of the bypass diode (BP: BP1, BP2, BP3) is formed between the solar cells (SC: SC1, SC2, SC3) and the bypass diode (BP: BP1, BP2, BP3).

[0146] For this connection structure, the first insulating pattern (P) of the solar cell (SC: SC1, SC2, SC3) h1 ), first upper pattern (P t1 ), first sub-pattern (P b1 ), intermediate pattern (P c ) and the second insulation pattern (P) of the connection part (IC: IC1, IC2, IC3) in the listed direction h2 ), second upper pattern (P t2 ) and the second sub-pattern (P b2 ) are formed so that the listed directions are opposite. That is, in the case of solar cells (SC: SC1, SC2, SC3), the first insulating pattern (P) is formed from one end of the substrate (100) to the other end. h1 ), first upper pattern (P t1 ), first sub-pattern (P b1 ), intermediate pattern (P c ) are listed in order. On the other hand, in the case of the connection part (IC: IC1, IC2, IC3), the second lower pattern (P) is located from one end of the substrate (100) to the other end. b2 ), second upper pattern (P t2 ), second insulation pattern (P h2 ) are listed in order.

[0147] By arranging the patterns in this manner, the first lower conductive layer (210a) of the second region (A2) of the solar cell (SC: SC1, SC2, SC3) and the first lower conductive layer (210a) of the connection portion (IC: IC1, IC2, IC3) can be connected, and the third upper conductive layer (250c) of the bypass diode (BD: BD1, BD2, BD3) and the second upper conductive layer (250b) of the connection portion (IC: IC1, IC2, IC3) can be connected. In addition, the first lower conductive layer (210a) of the solar cell (SC: SC1, SC2, SC3) and the third upper conductive layer (250c) of the bypass diode (BD: BD1, BD2, BD3) can be connected via the connection portion (IC: IC1, IC2, IC3). Additionally, the solar cells (SC: SC1, SC2, SC3) and bypass diodes (BD: BD1, BD2, BD3) can be made to have opposite polarities.

[0148]

[0149] The first lower semiconductor layer (220a) and the first upper semiconductor layer (240a) described above may be named as any one of a solar cell layer, a photoelectric conversion layer, or a light absorption layer.

[0150] And, as described above, the second lower semiconductor layer (220b) of the connecting portion (IC: IC1 to IC3) and the third lower conductive layer (220c) of the bypass diode (BD: BD1 to BD3) are formed of the same material as the first lower semiconductor layer (220a) of the solar cell. In addition, the second upper semiconductor layer (240b) of the connecting portion (IC: IC1 to IC3) and the third upper conductive layer (240c) of the bypass diode (BD: BD1 to BD3) are formed of the same material as the first upper semiconductor layer (240a) of the solar cell (SC: SC1 to SC3).

[0151] Accordingly, the second lower semiconductor layer (220b), the second upper semiconductor layer (240b) of the connecting portion (IC: IC1 to IC3), the third lower semiconductor layer (220c) of the bypass diode (BD: BD1 to BD3), and the third upper semiconductor layer (240c) of the bypass diode may each be named as a solar cell layer, a photovoltaic layer, or a light absorption layer. However, the second lower semiconductor layer (220b), the second upper semiconductor layer (240b) of the connecting portion (IC: IC1 to IC3), and the third lower semiconductor layer (220c) of the bypass diode (BD: BD1 to BD3) may be layers that do not function as solar cells due to reasons such as blocking sunlight or an electrical short circuit.

[0152]

[0153]

[0154] The second battery unit (200b) will be described in more detail with reference to FIGS. 1 to 6 as an example.

[0155] The second battery part (200b) is the first insulation pattern (P h1 ) and the third insulation pattern (P h3 ) are spatially separated from the first battery unit (200a) and the third battery unit (200c) which are arranged adjacent to each other. In addition, referring to FIG. 3, the first lower conductive layer (210a) of the second solar cell (SC2) is formed by the first lower pattern (P b1 ) is divided into two regions, and the two regions are connected to different lower conductive layers. That is, the first lower pattern (P) of the first lower conductive layer (210a) of the second solar cell (SC2) b1 ) is connected to the first lower conductive layer (210a) of the first solar cell (SC1). In addition, the first lower pattern (P) of the first lower conductive layer (210a) of the second solar cell (SC2) b1 ) is connected to the second lower conductive layer (210b) of the second connecting portion (IC2) and the first lower conductive layer (210a) of the third solar cell (SC3).

[0156] The second lower semiconductor layer (220b), the second middle conductive layer (230b), the second upper semiconductor layer (240b) and the second upper conductive layer (250b) of the second connection part (IC2) are formed by a second insulating pattern (P h2 ) is separated from the first lower semiconductor layer (220a), the first middle conductive layer (230a), the first upper semiconductor layer (240a), and the first upper conductive layer (250a) of the second solar cell (SC2). In addition, the second upper conductive layer (250b) of the second connecting portion (IC2) is separated from the second upper pattern (P t2 ) is connected to the second lower conductive layer (210b). In addition, the second upper conductive layer (250b) of the second connecting portion (IC2) is connected to the third upper conductive layer (250c) of the second bypass diode (BD2).

[0157] The third lower conductive layer (210c) of the second bypass diode (BD2) is connected to the first lower conductive layer (210a) of the first solar cell (SC1). In addition, the third lower conductive layer (210c) of the second bypass diode (BD2) is connected to the second lower pattern (P b2 ) can be separated from the first lower conductive layer (210a) of the third solar cell (SC2).

[0158] Accordingly, the polarity of the second solar cell (SC2) and the polarity of the second bypass diode (BD2) may be opposite. More specifically, referring to Fig. 3, when sunlight is received by the second solar cell (SC2), the first lower pattern (P) of the second solar cell (SC2) b1 ) may have a positive (+) polarity, and the first upper conductive layer (230a) may have a negative (-) polarity. More specifically, the first lower pattern (P) of the first lower conductive layer (210a) may have a positive (+) polarity. b1 ) may have a positive (+) polarity. And, the first upper pattern (P) connected to the first upper conductive layer (250a) of the second solar cell (SC2) t1 ) and the first upper pattern (P t1) and is connected to the first sub-pattern (P b1 ) may have a negative (-) polarity. And, the first lower conductive layer disposed on one side of the first lower pattern (P b1 ) connected to the first lower conductive layer (210a) arranged on the other side of the second connection part (IC2) has a positive (+) polarity, and the second upper conductive layer (250b) connected to the second lower conductive layer (210b) also has a positive (+) polarity. The second upper conductive layer (250b) of the second connection part (IC2) and the third upper conductive layer (250c) of the second bypass diode (BD2) are connected. Accordingly, the third upper conductive layer (230c) of the second bypass diode (BD2) has a positive (+) polarity. On the other hand, the first lower pattern (P) of the second solar cell (SC) b1 ) connected to the first lower conductive layer (210a) arranged on one side of the second bypass diode (BD2) has a negative (-) polarity.

[0159] In this way, the first sub-pattern (P) of the second solar cell (SC2) b1 ) has a positive (+) polarity, and the third lower conductive layer (210c) of the second bypass diode (BD2) has a negative (-) polarity, so the polarities are opposite. In addition, the first upper conductive layer (230a) of the second solar cell (SC2) has a negative (-) polarity, and the third upper conductive layer (250c) of the second bypass diode (BD2) has a positive (+) polarity, so the polarities are opposite.

[0160] And, the first sub-pattern (P) of the second solar cell (SC2) b1 ) both have a negative polarity. Accordingly, among the second solar cells (SC2), the first insulating pattern (P h1 ) to the intermediate pattern (P c ) may be a dead area. That is, among the second solar cells (SC2), the first insulating pattern (Ph1 ) to the intermediate pattern (P c ) may not cause photoelectric conversion in some areas, and in other areas, photoelectric conversion may occur and current may be generated, but may be short-circuited and the current may not flow to the battery and may be dissipated.

[0161] The polarities of the first and third solar cells (SC1, SC2) of the first and third battery units (200a, 200c) may be the same as the polarity of the second solar cell (SC2), the polarities of the first and third connectors (IC1, IC2) may be the same as the polarity of the second connector (IC2), and the polarities of the first and third bypass diodes (BD1, BD3) may be the same as the polarity of the second bypass diode (BD2). Therefore, description of the polarities of the first and third battery units (200a, 200c) is omitted.

[0162]

[0163] In this way, the first insulating pattern (P) of the solar cell (SC: SC1, SC2, SC3) h1 ), first upper pattern (P t1 ), first sub-pattern (P b1 ) and intermediate pattern (P c ) and the second insulation pattern (P) of the connection part (IC: IC1, IC2, IC3) in the listed direction h2 ), second upper pattern (P t2 ) and the second sub-pattern (P b2 ) are formed so that the listed directions are opposite. Then, the first lower conductive layer (210a) of the solar cell (SC: SC1, SC2, SC3) and the second lower conductive layer (210b) of the connection part (IC: IC1, IC2, IC3) are connected, and the third upper conductive layer (250c) of the bypass diode (BD: BD1, BD2, BD3) and the second upper conductive layer (250b) of the connection part (IC: IC1, IC2, IC3) are connected.

[0164] Therefore, as described above, the first lower conductive layer (210a) of the solar cell (SC: SC1, SC2, SC3) and the second lower conductive layer (210b) of the connection part (IC: IC1, IC2, IC3), the second upper pattern (P t2 ), the second upper conductive layer (250b) may have the same polarity. As a result, the third upper conductive layer (250c) of the bypass diode (BD: BD1, BD2, BD3) may have the same polarity as the second upper conductive layer (250b) of the connection (IC: IC1, IC2, IC3) but may have the opposite polarity to the first upper conductive layer (230a) of the solar cell (SC: SC1, SC2, SC3). Accordingly, the polarity of the third lower conductive layer (210c) of the bypass diode (BD: BD1, BD2, BD3) and the polarity of the first lower conductive layer (210a) of the solar cell (SC: SC1, SC2, SC3) may be opposite. Additionally, the polarity of the third upper conductive layer (250c) of the bypass diode (BD: BD1, BD2, BD3) and the polarity of the first upper conductive layer (230a) of the solar cell (SC: SC1, SC2, SC3) may be opposite.

[0165] Here, the region of the solar cell (SC: SC1, SC2, SC3) whose polarity is opposite to that of the bypass diode (BD: BD1, BD2, BD3) is the first insulating pattern (P) of the solar cell (SC: SC1, SC2, SC3). h1 ) from the area where the intermediate pattern (P) is formed c ) may be an area excluding the area where the formation of the .

[0166] In addition, when current flows through the bypass diodes (BD: BD1, BD2, BD3), the current does not flow through the third upper semiconductor layer (240c) among the third upper semiconductor layer (240c) and the third lower semiconductor layer (220c) which has a large band gap or a relatively large operating voltage, and as the current flows through the third lower semiconductor layer (220c), there is an advantage in that the bypass diodes (BD: BD1, BD2, BD3) can be operated or turned on at a low voltage.

[0167] In this way, the solar cell module according to the first embodiment may be formed by integrating solar cells (SC: SC1, SC2, SC3) and bypass diodes (BD: BD1, BD2, BD3).

[0168]

[0169] In the above, the first to third insulating patterns (P h1 , P h2 , P h2 ), split pattern (P d ) is formed as an empty space. That is, the first to third insulating patterns (P h1 , P h2 , P h2 ), split pattern (P d ) is an example of an empty space that is not filled with a separate material or filled with air. However, the first to third insulating patterns (P h1 , P h2 , P h2 ), split pattern (P d ) can be formed of an insulating material. That is, the first to third insulating patterns (P h1 , P h2 , P h2 ), split pattern (P d ) can be formed by filling, depositing, or applying an insulating material in the empty space as described above. The first to third insulating patterns (P h1 , P h2 , P h2 ), split pattern (P d) is not particularly limited, and various materials having insulating properties can be used.

[0170]

[0171]

[0172] Figures 7 to 15 are process diagrams sequentially showing a method for manufacturing a thin film solar cell module according to a first embodiment of the present invention. Figure 16 is a plan view of Figure 9, Figure 17 is a plan view of Figure 12, Figure 18 is a plan view of Figure 14, Figure 19 is a plan view of Figure 15, and Figure 20 is a plan view of Figure 1.

[0173] Hereinafter, a method for manufacturing a solar cell module according to a first embodiment of the present invention will be described with reference to FIGS. 1 and 2, and FIGS. 7 to 20. Any content that overlaps with the previously described content will be omitted or briefly described.

[0174] First, a substrate (100) is prepared. For example, a substrate (100) made of polyimide (PI) is prepared. Then, a lower conductive layer (210) is formed on the substrate (100). For example, molybdenum (Mo) can be deposited on the substrate (100) to form the lower conductive layer (210).

[0175] Next, as shown in Fig. 8, a plurality of lower grooves (H) are formed that penetrate the lower conductive layer (210) in the thickness direction (Z-axis direction). b ) is formed. That is, the first lower groove (H) extends from one end to the other end based on the second horizontal direction (Y-axis direction) of the lower conductive layer (210). b1 ) is provided, and the second lower groove (H) is extended from the other end to one end. b2 ) is provided. And in the second horizontal direction (Y-axis direction), the first lower groove (H) is provided in the extended length. b1 ) is the length of the second lower groove (H b1 ) is formed to be longer than the first lower groove (H). Of course, the first lower groove (H) b1 ) compared to the extended length of the second lower groove (Hb1 ) is long in length or the first lower groove (H) b1 ) and the second lower groove (H b1 ) may have the same extension length.

[0176] First lower home (H b1 ) and the second lower groove (H b2 ) are provided in multiples, and can be provided in the same number. In addition, the first lower groove (H b1 ) and the second lower groove (H b2 ) can be formed to be alternately arranged. Based on the first horizontal direction (X-axis direction) of the substrate (100), the first lower groove (H) is formed toward the other end. b1 ), second lower groove (H b2 ), first lower groove (H b1 ), second lower groove (H b2 ), first lower groove (H b1 ), second lower groove (H b2 ) are formed in the order of . In addition, two first lower grooves (H) are formed based on the first horizontal direction (X-axis direction). b1 ) located between the second lower groove (H b2 ) is a first lower groove (H) arranged relatively adjacent to one end of the substrate (100). b1 ) can be formed to be positioned more closely.

[0177] First and second lower grooves (H b1 , H b2 ) can be formed using a scribing method, for example, can be formed using a scribing etching method using a laser. That is, the first and second lower grooves (H) are formed by etching the lower conductive layer (210) using a laser scribing etching method. b1 , H b2 ) can be formed. At this time, for example, etching can be performed using a laser of 500 nm to 1100 nm or a laser of 200 nm to less than 500 nm. More specifically, a laser of 532 nm wavelength, a laser of 1064 nm wavelength, or a laser of 266 nm wavelength can be used.

[0178] Next, a lower semiconductor layer (220) is formed on the lower conductive layer (210) as shown in FIGS. 9 and 16. At this time, for example, the lower semiconductor layer (220) may be formed using a CIGS compound, which is a compound containing copper (Cu), indium (In), gallium (Ga), and cerium (Se). In addition, the lower semiconductor layer (220) may be formed in a PN stacked structure in which an n-type semiconductor layer is an upper layer and a p-type semiconductor layer is a lower layer.

[0179] When the lower semiconductor layer (220) is formed on the lower conductive layer (210), the material for the lower semiconductor layer (220) is formed in a plurality of first lower grooves (H) provided in the lower conductive layer (210). b1 ) and multiple second lower grooves (H b1 ) can also be filled or introduced into the interior. In this way, a plurality of first lower grooves (H b1 ) is formed by filling or introducing a material for the lower semiconductor layer (220) into the first lower pattern (P b1 ) and multiple second lower grooves (H b2 ) is formed by filling or introducing a material for the lower semiconductor layer (220) into the second lower pattern (P b2 )am.

[0180] Here, when the lower semiconductor layer (220) is formed on the lower conductive layer (210), the material for the lower semiconductor layer (220) is formed in the first lower groove (H b1 ) and the second lower groove (H b1 ) is not a separately performed process. That is, when the lower semiconductor layer (220) is formed on the lower conductive layer (210), the material for the lower semiconductor layer (220) is not only formed on the lower conductive layer (210) but also on the first lower groove (H b1 ) and the second lower groove (H b1 ) are filled with the first and second sub-patterns (P b1 , P b2 ) is formed.

[0181] Next, an intermediate conductive layer (230) is formed on the lower semiconductor layer (220) as shown in Fig. 10. For example, the intermediate conductive layer (230) can be formed by depositing IZO (Indium Zinc Oxide) on the lower semiconductor layer (220).

[0182] Afterwards, as shown in Fig. 11, a plurality of grooves (hereinafter, intermediate grooves (H)) are formed to penetrate the intermediate conductive layer (230) in the thickness direction (Z-axis direction). c )) is formed. That is, the intermediate groove (H) extends from one end to the other end based on the second horizontal direction (Y-axis direction) of the intermediate conductive layer (230). c ) is provided. And, the middle home (H c ) are provided in multiple pieces. In the second horizontal direction (Y-axis direction), the middle groove (H) is provided in a length extended in the second horizontal direction (Y-axis direction). c ) is the length of the first lower pattern (H b1 ) is preferably formed to be the same length.

[0183] Middle home (H c ), the first sub-pattern (P) is arranged adjacently to form b1 ) and the second sub-pattern (P b2 ) is formed to be located between the middle groove (H c ) is the first sub-pattern (P b1 ) is formed on the other side. At this time, the middle groove (H c ) is the second sub-pattern (P b2 ) compared to the first sub-pattern (P b1 ) is formed adjacent to it.

[0184] Middle home (H c ) can be formed using a scribing method, for example, can be formed by a scribing etching method using a laser. That is, the intermediate conductive layer (230) is etched using a laser scribing etching method to form an intermediate groove (H c) can be formed. At this time, for example, etching can be performed using a laser of 500 nm to 1100 nm or a laser of 200 nm to less than 500 nm. More specifically, a laser of 532 nm wavelength, a laser of 1064 nm wavelength, or a laser of 266 nm wavelength can be used.

[0185] Next, as shown in FIGS. 12 and 17, an upper semiconductor layer (240) is formed on the intermediate conductive layer (230). At this time, for example, the upper semiconductor layer (240) may be formed by forming a semiconductor layer with a perovskite structure on the intermediate conductive layer (230).

[0186] When the upper semiconductor layer (240) is formed on the intermediate conductive layer (230), the material for the upper semiconductor layer (240) is formed in a plurality of intermediate grooves (H) formed in the intermediate conductive layer (230). c ) is also filled or introduced into the interior. In this way, multiple intermediate grooves (H) are formed. c ) is formed by filling or introducing a material for the upper semiconductor layer (240) into the intermediate pattern (P c ) is. Accordingly, as shown in Fig. 17, the first lower pattern (P) is arranged adjacently. b1 ) and the second sub-pattern (P b2 ) between the intermediate patterns (P c ) is formed. Also, the intermediate pattern (P c ) is the first sub-pattern (P b1 ) is formed on the other side. At this time, the middle pattern (P c ) is the second sub-pattern (P b2 ) compared to the first sub-pattern (P b1 ) is formed adjacent to it.

[0187] Here, when the upper semiconductor layer (240) is formed on the intermediate conductive layer (230), the material for the upper semiconductor layer (240) is formed in the intermediate groove (H c) is not a separately performed process. That is, when the upper semiconductor layer (240) is formed on the intermediate conductive layer (230), the material for the upper semiconductor layer (240) is not only in the intermediate conductive layer (230) but also in the intermediate groove (H c ) is filled with an intermediate pattern (P c ) is formed.

[0188] Next, as shown in Fig. 13, a plurality of grooves (hereinafter referred to as upper grooves (H)) are formed through the upper semiconductor layer (240), the middle conductive layer (230), and the lower semiconductor layer (220) in the thickness direction (Z-axis direction). t )) is formed. That is, the first upper groove (H) extends from one end to the other end based on the second horizontal direction (Y-axis direction) of the substrate (100). t1 ) is formed, and the second upper H extends from the other end to one end. t2 ) are formed. In addition, the first and second upper grooves (H) are formed to penetrate the three layers (upper semiconductor layer (240), middle conductive layer (230), and lower semiconductor layer (220)). t1 , H t2 ) is formed. The first upper groove (H t1 ) and the second upper groove (H t2 ) are provided in multiples, and can be provided in the same number. And in the length extended in the second horizontal direction (Y-axis direction), the first upper groove (H t1 ) is the length of the middle pattern (H c1 ) is preferably formed to be the same length.

[0189] Below are multiple first sub-patterns (P b1 ), multiple intermediate patterns (P c ) and multiple second sub-patterns (P b2 ), one 'first sub-pattern (P)' is placed adjacently or adjacently. b1 ), intermediate pattern (P c ) and the second sub-pattern (P b2 )' as a group of 'pattern sets (S p) is named as '(see Fig. 18). In the first embodiment, three first sub-patterns (P b1 ), 3 intermediate patterns (P c ) and three second sub-patterns (P b2 ) is formed, so three sets of patterns (1S p , 2S p , 3S p ) is formed. Below, for the three lower pattern sets, the first pattern set (1S) is formed in order from one end to the other end of the substrate (100). p ), second pattern set (2S p ), 3rd pattern set (3S p ) is named.

[0190]

[0191] 1st upper groove (H t1 ) is a set of patterns (S p :1S p , 2S p , 2S p ) is formed to be located on one side of the second upper groove (H t2 ) is a set of patterns (S p :1S p , 2S p , 2S p ) is formed to be located on the other side. Accordingly, the first upper groove (H t1 ) is the first sub-pattern (P b1 ) is located on one side of the second upper groove (H t2 ) is the second sub-pattern (P b2 ) is located on the other side.

[0192] First and second upper grooves (H t1 , H t2 ) can be formed using a scribing method, for example, can be formed by a scribing etching method using a laser. That is, the upper semiconductor layer (240), the middle conductive layer (230), and the lower semiconductor layer (220) are etched using a laser scribing etching method to form the first and second upper grooves (H t1 , H t2) can be formed. At this time, for example, etching can be performed using a laser of 500 nm to 1100 nm or a laser of 200 nm to less than 500 nm. More specifically, a laser of 532 nm wavelength, a laser of 1064 nm wavelength, or a laser of 266 nm wavelength can be used.

[0193] Next, as shown in FIG. 14 and FIG. 18, an upper conductive layer (250) is formed on the upper semiconductor layer (240). For example, the upper conductive layer (250) can be formed by depositing IZO (Indium Zinc Oxide) on the upper semiconductor layer (240).

[0194] When the upper conductive layer (250) is formed on the upper semiconductor layer (240), the material for the upper conductive layer (250) has a plurality of first upper grooves (H t1 ) and multiple second upper grooves (H t1 ) is also filled or introduced into the interior. In this way, a plurality of first upper grooves (H t1 ) is formed by filling or introducing a material for the upper conductive layer (250) into the first upper pattern (P t1 ) and a plurality of second upper grooves (H t2 ) is formed by filling or introducing a material for the upper conductive layer (250) into the second upper pattern (P t2 ) is. Accordingly, as shown in Fig. 18, the pattern set (S p : 1S p , 2S p , 2S p ) on one side of the first upper pattern (P t1 ) is formed, and a pattern set (S p :1S p , 2S p , 2S p ) on the other side of the second upper pattern (P t2 ) is formed. That is, the first upper pattern (P t1 ) is the first sub-pattern (P b1 ) is located on one side of the second upper pattern (P t2 ) is the second sub-pattern (P b2) is located on the other side.

[0195] Here, when the upper conductive layer (250) is formed on the upper semiconductor layer (240), the material for the upper conductive layer (250) is formed in the first upper groove (H t1 ) and the second upper groove (H t1 ) is not a separately performed process. That is, when the upper conductive layer (250) is formed on the upper semiconductor layer (240), the material for the upper conductive layer (250) is not only formed on the upper semiconductor layer (240) but also on the first upper groove (H t1 ) and the second upper groove (H t1 ) are filled with the first and second upper patterns (P t1 , P t2 ) is formed.

[0196] Below are multiple first upper patterns (P t1 ), multiple first sub-patterns (P b1 ), multiple intermediate patterns (P c ), multiple second sub-patterns (P b2 ) and multiple second upper patterns (P t1 ), one 'first upper pattern (P)' is placed adjacently or adjacently. t1 ), first sub-pattern (P b1 ), intermediate pattern (P c ), second sub-pattern (P b2 ) and the second upper pattern (P t2 )' as a group of 'pattern sets (S p : 1S p , 2S p , 3S p ) is named as '(see Fig. 19). In the first embodiment, three first upper patterns (P t1 ), three first sub-patterns (P b1 ), 3 intermediate patterns (P c ), three second sub-patterns (P b2 ) and the second upper pattern (P t2 ) is formed, so three sets of patterns (1S p , 2S p , 3Sp ) is formed. Below, for the three lower pattern sets, the first pattern set (1S) is formed in order from one end to the other end of the substrate (100). p ), second pattern set (2S p ), 3rd pattern set (3S p ) is named.

[0197] Thereafter, as shown in FIGS. 15 and 19, a plurality of grooves are formed that penetrate the upper conductive layer (250), the upper semiconductor layer (240), the middle conductive layer (230), and the lower semiconductor layer (220) in the thickness direction (Z-axis direction). More specifically, a first groove (H1) is formed to extend from one end to the other end based on the second horizontal direction (Y-axis direction) of the substrate (100). At this time, the first groove (H1) is formed to extend from one end to the other end in the second horizontal direction (Y-axis direction). In addition, a second groove (H2) is formed to extend from the other end to one end based on the second horizontal direction (Y-axis direction) of the substrate (100). At this time, the second groove (H2) is formed to extend from the other end in the second horizontal direction (Y-axis direction) to one end, but the length of the second groove (H2) extended in the second horizontal direction (Y-axis direction) may be smaller than that of the first groove (H1). That is, the second groove (H2) extends from the other end in the second horizontal direction (Y-axis direction) to one end, but does not extend to the first end.

[0198] The first home (H1) is a pattern set (S p :1S p , 2S p , 3S p ) is located on one side of the pattern set, and the second groove (H2) is located on the other side (S) of the pattern set. p :1S p , 2S p , 3S p ) is formed to be located at the first upper pattern (P). Accordingly, the first groove (H1) is formed at the first upper pattern (P t1 ) is located on one side of the second upper pattern (H2), and the second groove (H2) is located on the other side of the second upper pattern (H2). Each of the first groove (H1) and the second groove (H2) may be provided in multiple numbers, and may be provided in the same number.

[0199] Next, as shown in FIG. 1 and FIG. 20, a groove (hereinafter referred to as a split pattern (P)) extending in the first horizontal direction (X-axis direction) penetrates the upper conductive layer (250), the upper semiconductor layer (240), the middle conductive layer (230), the lower semiconductor layer (220), and the lower conductive layer (210) in the thickness direction (Z-axis direction) d )) is formed. That is, the split pattern (P d ) is a pattern formed by penetrating five layers formed on a substrate (100), and is a pattern extending in the first horizontal direction (X-axis direction).

[0200] Split pattern (P d ) is the first lower pattern (P) based on the second horizontal direction (Y-axis direction). b1 ), intermediate pattern (P c ) and the first upper pattern (P t1 ) and the second sub-pattern (P b2 ) and the second upper pattern (P t2 ) is formed to be located between them. In addition, the split pattern (P d ) is formed to be located between the first groove (H1) and the second groove (H1) based on the first horizontal direction (Y-axis direction).

[0201] Here, some of the first home (H1) is formed by the first insulating pattern (P) of the solar cell (SC: SC1, SC2, SC3). h1 ) and some others are the third insulation pattern (P) of the bypass diode (BD: BD1, BD2, BD3). h3 ) (see Fig. 1, Fig. 19 and Fig. 20). That is, based on the second horizontal direction (Y-axis direction), a split pattern (P) is formed from one end of the first groove (H1) among the first grooves (H1). d ) The area before is the first insulating pattern (P) of the solar cell (SC: SC1, SC2, SC3) h1 ) may be. And, among the first grooves (H1), a split pattern (P) may be formed from the other end of the first groove (H1). d) The area before is the third insulation pattern (P) of the bypass diode (BD: BD1, BD2, BD3) h3 ) may be.

[0202] Split pattern (P d ) can be formed using a scribing method, for example, can be formed using a scribing etching method using a laser. That is, the upper conductive layer (250), the upper semiconductor layer (240), the middle conductive layer (230), the lower semiconductor layer (220), and the lower conductive layer (210) are etched using a laser scribing etching method to form a split pattern (P d ) can be formed. At this time, for example, etching can be performed using a laser of 500 nm to 1100 nm or a laser of 200 nm to less than 500 nm. More specifically, a laser of 532 nm wavelength, a laser of 1064 nm wavelength, or a laser of 266 nm wavelength can be used.

[0203] The above describes scribing using a laser etching method. However, this is not limited to this method and etching can also be performed using a needle.

[0204] In this way, the first sub-pattern (P b1 ), intermediate pattern (P c ), first upper pattern (P t1 ), first insulation pattern (P h1 ), second sub-pattern (P b2 ), second upper pattern (P t2 ), second insulation pattern (P h2 ), third insulation pattern (P h3 ) and split pattern (P d), the battery unit (200: 200a, 200b, 200c) can include a solar cell (SC: SC1, SC2, SC3), a bypass diode (BD: BD1, BD2, BD3) and a connection unit (IC: IC1, IC2, IC3). That is, a battery unit (200: 200a, 200b, 200c) in which a solar cell (SC: SC1, SC2, SC3) and a bypass diode (BD: BD1, BD2, BD3) are provided as an integral unit can be manufactured.

[0205] In addition, a solar cell module in which solar cells (SC: SC1, SC2, SC3) and bypass diodes (BD: BD1, BD2, BD3) are formed as an integral part can be manufactured. That is, the solar cells (SC: SC1, SC2, SC3) and bypass diodes (BD: BD1, BD2, BD3) can be formed as an integral part on one substrate (100). In addition, when forming the solar cells (SC: SC1, SC2, SC3), the bypass diodes (BD: BD1, BD2, BD3) can be formed simultaneously with or together with the solar cells (SC: SC1, SC2, SC3). Therefore, the cost and time for manufacturing the battery unit (200: 200a, 200b, 200c) including the bypass diodes (BD: BD1, BD2, BD3) and the solar cell module can be saved.

[0206] And, the middle groove (H) extends from one end to the other end based on the second horizontal direction (Y-axis direction). c ) is formed, an intermediate groove extending from one end to the other end is not formed. Accordingly, when forming an upper semiconductor layer (140) on an intermediate conductive layer (230), an intermediate pattern (P) is formed extending from one end to the other end based on the second horizontal direction (Y-axis direction). c) is provided, and an intermediate pattern extending from one end to the other end is not provided. Therefore, when current flows to the bypass diode (BD: BD1, BD2, BD3), the current does not flow to the third upper semiconductor layer (240c) having a relatively high operating voltage among the third upper semiconductor layer (240c) and the third lower semiconductor layer (220c), and as the current flows to the third lower semiconductor layer (220c), there is an advantage in that the bypass diode (BD: BD1, BD2, BD3) can be operated or turned on at a low voltage.

[0207]

[0208] Fig. 21 is a three-dimensional view illustrating a thin-film solar cell module according to a second embodiment of the present invention. Fig. 22 is a cross-sectional view of area E of Fig. 21 to explain the solar cell according to the second embodiment of the present invention in more detail.

[0209] The solar cell module according to the first embodiment illustrated in FIG. 1 is arranged such that bypass diodes (BD: BD1, BD2, BD3) are formed at edges in the second horizontal direction (Y-axis direction). More specifically, the bypass diodes (BD: BD1, BD2, BD3) are arranged such that one end in the second horizontal direction (Y-axis direction) is closer to the other end. However, the present invention is not limited thereto, and the bypass diodes (BD: BD1, BD2, BD3) may be arranged at the center in the second horizontal direction, as illustrated in FIGS. 21 and 22.

[0210] Hereinafter, with reference to FIGS. 21 and 22, a solar cell module according to a second embodiment of the present invention will be described. The solar cell module according to the second embodiment has the same or similar configuration and pattern arrangement structure as the solar cell module according to the first embodiment described above. However, the solar cell module according to the second embodiment may have a bypass diode (BD: BD1, BD2, BD3) arranged at the center in the second horizontal direction (Y-axis direction), and the shape of the solar cell may be different from that of the first embodiment.

[0211] Therefore, in the following description, the solar cell module according to the second embodiment will be described with a focus on the differences from the first embodiment.

[0212] The solar cell (SC: SC1, SC2, SC3) according to the second embodiment may include a first region (A1) extending in a first horizontal direction (X-axis direction) on a substrate (100), a second region (A2) extending in a second horizontal direction (Y-axis direction) from the other edge of the first region (A1) based on the first horizontal direction (X-axis direction) and having one end connected to the first region (A1), and a third region (A3) extending in the first horizontal direction (X-axis direction) from the other end of the second region (A2) so as to face the first region (A1) in the second horizontal direction (Y-axis direction). Accordingly, in each battery section (200a, 200b, 200c), the solar cell (SC1, SC2, SC3) may have a shape similar to the Korean consonant 'ㄷ'.

[0213] First sub-pattern (P b1 ), intermediate pattern (P c ), first upper pattern (P t1 ), first insulation pattern (P h1 ) can be formed in the first and third regions (A1, A3) of the solar cell (SC: SC1, SC2, SC3) as shown in Fig. 22. And, the first lower pattern (P b1 ) on one side of the first upper pattern (P t1 ) is placed, and the first sub-pattern (P b1 ) on the other side of the middle pattern (P c ) is placed, and the first upper pattern (P t1 ) on one side of the first insulating pattern (P h1 ) can be arranged. When described from one end to the other end of the substrate (100), the first insulating pattern (P h1 ), first upper pattern (P t1 ), first sub-pattern (P b1 ), intermediate pattern (P c ) can be listed in order.

[0214] The bypass section (BP: BP1, BP2, BP3) can be arranged to face the second region (A2) of the solar cell (SC: SC1, SC2, SC3) in the first horizontal direction (X-axis direction).

[0215]

[0216] The second sub-pattern (P) of the connection (IC: IC1, IC2, IC3) b2 ), second upper pattern (P t2 ), second insulation pattern (P h2 ) are listed in the order of the first sub-pattern (P) of the solar cell. b1 ), intermediate pattern (P c ), first upper pattern (P t1 ), first insulation pattern (P h1 ) may be in the opposite direction to the direction in which they are listed. That is, the second sub-pattern (P b2 ) on the other side of the second upper pattern (P t2 ) is placed, and the second upper pattern (P t2 ) on the other side of the second insulating pattern (P h2 ) can be arranged. When described from one end to the other end of the substrate (100), the second lower pattern (P b2 ), second upper pattern (P t2 ), second insulation pattern (P h2 ) can be listed in order.

[0217] The second lower challenge layer (210b) is a second lower pattern (P b2 ) can be divided into regions. That is, the second lower conductive layer (210b) is divided into the second lower pattern (P b2 ) and the second lower pattern (P b2 ) can be separated into areas arranged on the other side. And, the second lower pattern (P b2 ) and the second lower conductive layer (210b) and the second lower pattern (P) are arranged on one side of the b2 ) is arranged on the other side of the second lower conductive layer (210b) and the second lower pattern (P b2 ) can be separated by the second sub-pattern (P b2) can be connected to the first lower conductive layer (210a) of the solar cell (SC: SC1, SC2, SC3).

[0218] The second lower semiconductor layer (220b) is formed by the second upper pattern (P t2 ) can be divided into regions. That is, the second lower semiconductor layer (220b) is divided into the second upper pattern (P t2 ) and the second upper pattern (P t2 ) can be separated into areas arranged on the other side. And, the second upper pattern (P t2 ) and the second lower semiconductor layer (220b) and the second upper pattern (P) are arranged on one side of the t2 ) is arranged on the other side of the second lower semiconductor layer (220b) and the second upper pattern (P t2 ) can be separated by.

[0219] The second upper semiconductor layer (240b) is a second upper pattern (P t2 ) can be divided into regions. That is, the second upper semiconductor layer (240b) is divided into the second upper pattern (P t2 ) and the second upper pattern (P t2 ) can be separated into areas arranged on the other side. And, the second upper pattern (P t2 ) and the second upper semiconductor layer (240b) arranged on one side of the second upper pattern (P t2 ) is arranged on the other side of the second upper semiconductor layer (240b) and the second upper pattern (P t2 ) can be separated by.

[0220]

[0221] The third lower conductive layer (210c) of the bypass diode (BD: BD1, BD2, BD3) can be connected to the first lower conductive layer (210a) of the solar cell (SC: SC1, SC2, SC3). That is, the first lower conductive layer (210a) of the first and third regions (A1, A3) of the solar cell (SC: SC1, SC2, SC3) and the third lower conductive layer (210c) of the bypass diode (BD: BD1, BD2, BD3) can be connected. In addition, the third lower conductive layer (210c) of the bypass diode (BD: BD1, BD2, BD3) and the second lower conductive layer (210b) of the connection portion (IC: IC1, IC2, IC3) can be connected to the second lower pattern (P b2 ) are separated by a third upper conductive layer (250c) of the bypass diode (BD: BD1, BD2, BD3) and is connected to the second upper conductive layer (250b) of the connecting portion (IC: IC1, IC2, IC3).

[0222]

[0223] Split pattern (P d ) may be a groove that penetrates the five layers formed on the substrate (100) in the thickness direction (Z-axis direction) and extends in the first horizontal direction (X-axis direction). That is, the split pattern (P d ) may be a groove formed to extend in the first horizontal direction (X-axis direction) while penetrating the upper conductive layer, the upper semiconductor layer, the middle conductive layer, the lower semiconductor layer, and the lower conductive layer in the thickness direction (Z-axis direction). And the split pattern (P d ) is based on the first horizontal direction (X-axis direction), the first and third insulation patterns (P h1 , P h3 ) and the second insulation pattern (P h2 ) is formed to be located between them. At this time, the split pattern (P d ) is the first and third insulation patterns (P h1 , P h3 ) and is connected to the split pattern (P d ) is the second insulating pattern (P h2 ) can be connected.

[0224] Split pattern (P d ) are arranged in multiples to be arranged in the second horizontal direction (Y-axis direction). That is, the first division pattern (P) is provided between the first region (A1) of the solar cell (SC: SC1, SC2, SC3) and the bypass section (BP: BP1, BP2, BP3). d ) is formed, and a second segmentation pattern (P) is formed between the third region (A3) of the solar cell (SC: SC1, SC2, SC3) and the bypass section (BP: BP1, BP2, BP3). d ) is formed.

[0225]

[0226] The method for manufacturing a solar cell module according to the second embodiment is compared with the method for manufacturing a solar cell module according to the first embodiment in that the second insulating pattern (P h2 ) formation location, split pattern (P d ) formation location and division pattern (P d ) may be different, but the other processes may be the same.

[0227] Second insulation pattern (P) according to the second embodiment h2 ) is formed by penetrating the upper conductive layer, the upper semiconductor layer, the middle conductive layer, and the lower semiconductor layer in the thickness direction, which is the same as the first embodiment. However, the second insulating pattern (P) according to the second embodiment h2 ) can be formed to be located at the center of the second horizontal direction (Y-axis direction).

[0228] Split pattern (P) according to the second embodiment d ) penetrates the upper conductive layer, the upper semiconductor layer, the middle conductive layer, the lower semiconductor layer, and the lower conductive layer in the thickness direction, and the first and third insulating patterns (P h1 , P h3 ) and the second insulation pattern (P h2 ) is the same as the first embodiment in that it extends in the first horizontal direction (X-axis direction) to be located between them. However, the split pattern (P) according to the second embodiment d) are formed in multiples to be arranged in the second horizontal direction (Y-axis direction) as described above. That is, the second insulating pattern (P) is formed based on the second horizontal direction (Y-axis direction). h2 ) on one side of the first division pattern (P d ) is formed, and a second division pattern (P) is formed on the other side. d ) is formed.

[0229] Accordingly, the solar cell (SC: SC1, SC2, SC3) according to the second embodiment may have a shape including the first to third regions (A1, A2, A3) as described above. In addition, the bypass portion (BP: BP1, BP2, BP3) may be arranged to face the second region (A2) of the solar cell in the first horizontal direction (X-axis direction). That is, the bypass portion (BP: BP1, BP2, BP3) may be arranged at the center in the second horizontal direction (Y-axis direction). In other words, the bypass portion (BP: BP1, BP2, BP3) may be arranged between the first region (A1) and the second region (A2) of the solar cell (SC: SC1, SC2, SC3).

[0230]

[0231]

[0232] Accordingly, the polarity of the solar cells (SC: SC1, SC2, SC3) and the polarity of the bypass section (BP: BP1, BP2, BP3) can be opposite. More specifically, when sunlight is received by the solar cells (SC: SC1, SC2, SC3), the first sub-pattern (P) among the solar cells (SC: SC1, SC2, SC3) b1 ) may have a positive (+) polarity, and the first upper conductive layer (230a) may have a negative (-) polarity. More specifically, the first lower pattern (P) of the first lower conductive layer (210a) may have a positive (+) polarity. b1) may have a positive (+) polarity. And, among the solar cells (SC: SC1, SC2, SC3), the first upper pattern (P) connected to the first upper conductive layer (250a) t1 ) and the first upper pattern (P t1 ) and is connected to the first sub-pattern (P b1 ) may have a negative (-) polarity. And, the first lower conductive layer disposed on one side of the first lower pattern (P b1 ) connected to the first lower conductive layer (210a) arranged on the other side of the solar cell (SC: IC1, IC2, SC3) has a positive (+) polarity, and the second upper conductive layer (250b) connected to the second lower conductive layer (210b) also has a positive (+) polarity. The second upper conductive layer (250b) of the connecting portion (IC: IC1, IC2, IC3) and the third upper conductive layer (250c) of the bypass diode (BD: BD1, BD2, BD3) are connected. Accordingly, the third upper conductive layer (230c) of the bypass diode (BD: BD1, BD2, BD3) has a positive (+) polarity. On the other hand, the first lower pattern (P) of the solar cell (SC: SC1, SC2, SC3) b1 ) connected to the first lower conductive layer (210a) arranged on one side of (BD: BD1, BD2, BD3) has a negative (-) polarity.

[0233] In each solar cell (SC: SC1, SC2, SC3), the first insulating pattern (P h1 ) to the intermediate pattern (P c ) may be a dead area. That is, the first insulating pattern (P h1 ) to the intermediate pattern (P c ) may not cause photoelectric conversion in some areas, and in other areas, photoelectric conversion may occur and current may be generated, but may be short-circuited and the current may not flow to the battery and may be dissipated.

[0234] In addition, when current flows through the bypass diodes (BD: BD1, BD2, BD3), the current does not flow through the third upper semiconductor layer (240c) having a relatively high operating voltage among the third upper semiconductor layer (240c) and the third lower semiconductor layer (220c), and as the current flows through the third lower semiconductor layer (220c), the bypass diodes (BD: BD1, BD2, BD3) can be operated or turned on at a low voltage.

[0235] The solar cell module according to the second embodiment described above may be one in which solar cells (SC: SC1, SC2, SC3) and bypass diodes (BD: BD1, BD2, BD3) are provided as an integral unit. That is, the second embodiment may be a solar cell module with a built-in bypass diode (BD: BD1, BD2, BD3).

[0236] Thin-film solar cell devices and thin-film solar cell modules according to embodiments of the present invention can incorporate bypass diodes. Furthermore, thin-film solar cell devices and thin-film solar cell modules including bypass diodes can be manufactured simply and at low cost. Furthermore, the operating voltage of the bypass diode can be lowered, allowing the bypass diode to operate at low voltages.

Claims

1. Substrate; A solar cell comprising a first lower conductive layer, a first lower semiconductor layer, a first middle conductive layer, a first upper semiconductor layer, and a first upper conductive layer sequentially stacked in an upward direction on the substrate; A connecting portion including a second lower conductive layer connected to the first lower conductive layer and a second lower semiconductor layer, a second intermediate conductive layer, a second upper semiconductor layer, and a second upper conductive layer sequentially stacked in an upward direction on the second lower conductive layer; and A thin film solar cell device comprising a bypass diode including a third upper conductive layer connected to the second upper conductive layer, a third upper semiconductor layer sequentially stacked downward from the third upper conductive layer, a third intermediate conductive layer, a third lower semiconductor layer, and a third lower conductive layer.

2. In claim 1, The above solar cell, A first lower pattern formed so as to penetrate the first lower conductive layer in the thickness direction and formed of a material for the first lower semiconductor layer; An intermediate pattern formed to penetrate the first intermediate conductive layer in the thickness direction to connect the first lower semiconductor layer and the first upper semiconductor layer, and formed of a material for the first upper semiconductor layer; A first upper pattern formed of a material for the first upper conductive layer, which is formed to penetrate the first upper semiconductor layer, the first intermediate conductive layer, and the first lower semiconductor layer in the thickness direction to connect the first lower conductive layer, the first intermediate conductive layer, and the first upper conductive layer; and A thin film solar cell device comprising a first insulating pattern formed on the upper side of the first lower conductive layer, the first upper semiconductor layer, the first middle conductive layer, and the first lower semiconductor layer in the thickness direction.

3. In claim 2, A thin film solar cell device in which, with respect to the first horizontal direction of the substrate, one end of the substrate and the other end are referred to as one side and the other end as the other side, a first insulating pattern, a first upper pattern, a first lower pattern, and a middle pattern are arranged in the order from one end of the substrate to the other end.

4. In claim 3, A thin film solar cell device, wherein a region located on one side of the first lower pattern among the first lower conductive layers is connected to the first upper conductive layer by the first upper pattern and is connected to the third lower conductive layer of the bypass diode.

5. In claim 3, The above connection part, A second lower pattern formed so as to penetrate the second lower conductive layer in the thickness direction and formed of a material for the second lower semiconductor layer; A second upper pattern formed of a material for the second upper conductive layer, which is formed to penetrate the second upper semiconductor layer, the second intermediate conductive layer, and the second lower semiconductor layer in the thickness direction to connect the second lower conductive layer, the second intermediate conductive layer, and the second upper conductive layer; and A thin film solar cell device comprising a second insulating pattern formed so as to penetrate the second upper conductive layer, the second upper semiconductor layer, the second middle conductive layer, and the second lower semiconductor layer in the thickness direction, and formed on the upper side of the second lower conductive layer.

6. In claim 5, A thin film solar cell device in which a second lower pattern, a second upper pattern, and a second insulating pattern are arranged in the order from one end to the other end of the above substrate.

7. In claim 6, The second lower conductive layer of the above connecting portion is connected to the second upper conductive layer by the second upper pattern, and is connected to an area of ​​the first lower conductive layer of the solar cell located on the other side of the first lower pattern, A thin film solar cell device in which the second lower conductive layer is separated from the third lower conductive layer of the bypass diode by the second lower pattern.

8. In claim 7, The above bypass diode is, It includes a third insulating pattern formed on one side of the third lower semiconductor layer, the third intermediate conductive layer, the third upper semiconductor layer, and the third upper conductive layer, and formed on the upper side of the third lower conductive layer. A thin film solar cell device connected to the connecting portion so that the above bypass diode is located on one side of the second lower pattern.

9. In claim 8, A thin film solar cell device in which the first to third insulating patterns are formed as empty spaces or formed of an insulating material.

10. In any one of claims 3 to 9, The solar cell extends in the first horizontal direction on the substrate, The above connecting portion and bypass diode are arranged in the first horizontal direction, A thin film solar cell device in which the above connecting portion and bypass diode and the above solar cell are arranged in a second horizontal direction intersecting the first horizontal direction.

11. In claim 10, Including a split pattern extending in the first horizontal direction so as to be positioned between the connecting portion and the bypass diode and the solar cell, The above split pattern is formed as a thin film solar cell device formed of an empty space or an insulating material.

12. In claim 11, The above split pattern is formed in multiple pieces, A plurality of the above-described split patterns are arranged in the second horizontal direction, A thin film solar cell device in which the connecting portion and bypass diode are arranged between a plurality of the split patterns arranged in the second horizontal direction.

13. Substrate; A thin film solar cell module comprising a plurality of solar cells formed on the substrate and having a plurality of semiconductor layers capable of converting received sunlight into photoelectric energy, a connecting portion formed on the substrate such that a lower conductive layer is connected to a lower conductive layer of the solar cell, and a battery portion including a plurality of semiconductor layers and a bypass diode formed on the substrate such that an upper conductive layer is connected to a lower conductive layer of the connecting portion.

14. In claim 13, The plurality of semiconductor layers of the solar cell include a first lower semiconductor layer and a first upper semiconductor layer formed on an upper side of the first lower semiconductor layer, The lower conductive layer of the solar cell includes a first lower conductive layer formed between the substrate and the first lower semiconductor layer, The solar cell includes a first intermediate conductive layer formed between the first lower semiconductor layer and the first upper semiconductor layer, and a first upper conductive layer formed on the first upper semiconductor layer. The lower conductive layer of the above connecting portion is formed on the substrate and includes a second lower conductive layer connected to the first lower conductive layer, The above connecting portion includes a second lower semiconductor layer, a second intermediate conductive layer, a second upper semiconductor layer, and a second upper conductive layer sequentially stacked in an upward direction on the second lower conductive layer, The upper conductive layer of the above bypass diode includes a third upper conductive layer connected to the second lower conductive layer, The above bypass diode includes a third lower conductive layer, and the plurality of semiconductor layers of the bypass diode include a third lower semiconductor layer formed on the third lower conductive layer and a third upper semiconductor layer formed on an upper side of the third lower semiconductor layer. The above bypass diode is a thin film solar cell module including a third intermediate conductive layer formed between the third lower semiconductor layer and the third upper semiconductor layer and a third upper conductive layer formed on the third upper semiconductor layer.

15. In claim 14, The above solar cell, A first lower pattern formed so as to penetrate the first lower conductive layer in the thickness direction and formed of a material for the first lower semiconductor layer; An intermediate pattern formed so as to penetrate the first intermediate conductive layer in the thickness direction and formed of a material for the first upper semiconductor layer; A first upper pattern formed so as to penetrate the first upper semiconductor layer, the first middle conductive layer, and the first lower semiconductor layer in the thickness direction, and formed of a material for the first upper conductive layer; and A first insulating pattern formed on the upper side of the first lower conductive layer, which is formed to penetrate the first upper conductive layer, the first upper semiconductor layer, the first middle conductive layer, and the first lower semiconductor layer in the thickness direction; A thin film solar cell module in which, with respect to the first horizontal direction of the substrate, one end of the substrate and the other end are referred to as one side and the other end as the other side, the first insulating pattern, the first upper pattern, the first lower pattern, and the middle pattern are arranged in the order from one end to the other end of the substrate.

16. In claim 15, A thin film solar cell module, wherein a region located on one side of the first lower pattern among the first lower conductive layers is connected to the first upper conductive layer by the first upper pattern and is connected to the third lower conductive layer of the bypass diode.

17. In claim 15, The above connection part, A second lower pattern formed so as to penetrate the second lower conductive layer in the thickness direction and formed of a material for the second lower semiconductor layer; A second upper pattern formed of a material for the second upper conductive layer, which is formed to penetrate the second upper semiconductor layer, the second intermediate conductive layer, and the second lower semiconductor layer in the thickness direction to connect the second lower conductive layer, the second intermediate conductive layer, and the second upper conductive layer; and A second insulating pattern formed on the upper side of the second lower conductive layer, which is formed to penetrate the second upper conductive layer, the second upper semiconductor layer, the second middle conductive layer, and the second lower semiconductor layer in the thickness direction; A thin film solar cell module in which a second lower pattern, a second upper pattern, and a second insulating pattern are arranged in the order from one end to the other end of the above substrate.

18. In claim 17, The second lower conductive layer of the above connecting portion is connected to the second upper conductive layer by the second upper pattern, and is connected to an area of ​​the first lower conductive layer of the solar cell located on the other side of the first lower pattern, A thin film solar cell module in which the second lower conductive layer is separated from the third lower conductive layer of the bypass diode by the second lower pattern.

19. In claim 18, The above bypass diode is, It is formed on one side of the third lower semiconductor layer, the third intermediate conductive layer, the third upper semiconductor layer and the third upper conductive layer, and includes a third insulating pattern formed on the upper side of the third lower conductive layer. A thin film solar cell module connected to the connecting portion so that the above bypass diode is located on one side of the second lower pattern.

20. In claim 19, A thin film solar cell module in which the first to third insulating patterns are formed as empty spaces or formed of an insulating material.

21. In any one of claims 15 to 20, The solar cell extends in the first horizontal direction on the substrate, The above connecting portion and bypass diode are arranged in the first horizontal direction, A thin film solar cell module in which the above connecting portion and bypass diode and the above solar cell are arranged in a second horizontal direction intersecting the first horizontal direction.

22. In claim 21, Including a split pattern extending in the first horizontal direction so as to be positioned between the connecting portion and the bypass diode and the solar cell, The above split pattern is formed as a thin film solar cell module formed of an empty space or an insulating material.

23. In claim 22, The above split pattern is formed in multiple pieces, A plurality of the above-described split patterns are arranged in the second horizontal direction, A thin film solar cell module in which the connecting portion and bypass diode are arranged between a plurality of the split patterns arranged in the second horizontal direction.

24. A method for manufacturing a solar cell device, comprising: a solar cell formed on a substrate and having a plurality of semiconductor layers capable of converting received sunlight into photoelectric energy; a connecting portion formed on the substrate so that a lower conductive layer is connected to the lower conductive layer of the solar cell; and a bypass diode formed on the substrate so that an upper conductive layer is connected to the lower conductive layer of the connecting portion, the method comprising: A method for manufacturing a thin film solar cell device, the process comprising manufacturing a solar cell, a connector, and a bypass diode, the method comprising a scribing process.

25. In claim 24, A process for preparing a substrate extending in a first horizontal direction and a second horizontal direction intersecting the first horizontal direction, The process for manufacturing the above solar cell, connector, and bypass diode is as follows: A process of forming a lower conductive layer on the above substrate; A process of forming a lower groove by etching the lower conductive layer in the thickness direction using a scribing process; A process of forming a lower semiconductor layer capable of converting sunlight received on the lower conductive layer into photoelectric energy, and filling the lower groove with a material for the lower semiconductor layer to form a lower pattern; A process of forming an intermediate conductive layer on the lower semiconductor layer and lower pattern; A process of forming an intermediate groove by etching the intermediate conductive layer in the thickness direction using a scribing process so that the first horizontal direction position is different from that of the lower pattern; A process of forming an upper semiconductor layer capable of converting sunlight received on the intermediate conductive layer into photoelectricity, and filling the intermediate groove with a material for the upper semiconductor layer to form an intermediate pattern; A process of forming an upper groove by etching the upper semiconductor layer, the middle conductive layer, and the lower semiconductor layer in the thickness direction using a scribing process so that the first horizontal direction position is different from that of the lower pattern and the middle pattern; A method for manufacturing a thin film solar cell device, comprising: forming an upper conductive layer on the upper semiconductor layer, and filling the upper groove with a material for the upper conductive layer to form an upper pattern.

26. In claim 25, The process of forming the above lower groove is: It includes a process of forming a first lower groove extending from one end of the substrate to the other end based on the second horizontal direction, and forming a second lower groove extending from the other end of the substrate to one end. When one end of the substrate is referred to as one side and the other end is referred to as the other side based on the first horizontal direction, In forming the first and second lower grooves, the first lower groove is formed so as to be positioned on one side of the second lower groove, A method for manufacturing a thin film solar cell device, wherein the process of forming the lower pattern includes a process of filling the first and second lower grooves with a material for the lower semiconductor layer to form the first and second lower patterns.

27. In claim 26, The process of forming the above intermediate groove is: A process of forming an intermediate groove extending from one end of the substrate to the other end based on the second horizontal direction; In forming the above intermediate groove, the intermediate groove is formed so as to be positioned on the other side of the first lower groove based on the first horizontal direction. A method for manufacturing a thin film solar cell device, wherein the process of forming the intermediate pattern includes a process of filling the intermediate groove with the material for the semiconductor layer to form the intermediate pattern.

28. In claim 27, The process of forming the upper groove is as follows: A process of forming a first upper groove extending from one end of the substrate to the other end based on the second horizontal direction, and forming a second upper groove extending from the other end of the substrate to one end; In forming the first and second upper grooves, the first upper groove is formed to be arranged on one side of the first lower groove and the second upper groove is formed to be arranged on the other side of the second lower groove with respect to the first horizontal direction. A method for manufacturing a thin film solar cell device, wherein the process of forming the upper pattern includes a process of filling the upper conductive layer material into the first and second upper grooves to form the first and second upper patterns.

29. In claim 28, A process of forming an insulating pattern that penetrates the upper conductive layer, the upper semiconductor layer, the middle conductive layer, and the lower semiconductor layer in the thickness direction on one side of the first upper pattern and is located on the upper side of the lower conductive layer; and A process of forming an insulating pattern on the other side of the second upper pattern, penetrating the upper conductive layer, the upper semiconductor layer, the middle conductive layer, and the lower semiconductor layer in the thickness direction and positioned on the upper side of the lower conductive layer; A method for manufacturing a thin film solar cell device, wherein the process of forming the insulating pattern includes a process of forming a void space by etching the upper conductive layer, the upper semiconductor layer, the middle conductive layer, and the lower semiconductor layer in the thickness direction using a scribing process.

30. In claim 29, A method for manufacturing a thin film solar cell device, wherein the process of forming the insulating pattern includes a process of filling the empty space with an insulating material.

31. In any one of claims 24 to 30, A method for manufacturing a thin film solar cell module comprising a plurality of the above solar cell devices.

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