Display device and method for manufacturing same

Abstract

Provided are a display device and a method for manufacturing same. A display device according to an embodiment may comprise: a substrate; a pixel electrode disposed on the substrate; an organic layer disposed on the pixel electrode; a light emitting element disposed on the organic layer and including a semiconductor stack, a first protective layer, a contact electrode, and a second protective layer; and a connection electrode connecting the light emitting element and the pixel electrode, wherein the first protective layer is an insulating protective layer, the second protective layer is a conductive protective layer, and the connection electrode and the second protective layer are etched using the same etchant.

Description

Display device and method of manufacturing the same

[0001] The present invention relates to a display device and a method for manufacturing the same.

[0002] As the information society develops, demand for display devices for displaying images is increasing in various forms. Display devices can be flat panel displays such as liquid crystal displays (LCDs), field emission displays (FEDs), and light emitting displays (LEDs).

[0003] The light-emitting display device may include an organic light-emitting display device including an organic light-emitting diode element as a light-emitting element, and an ultra-small light-emitting display device including a micro light-emitting diode element (hereinafter referred to as a micro light-emitting element) as a light-emitting element. Since the ultra-small light-emitting diode element is made of an inorganic material, it has the advantage of having a longer lifespan due to fewer deterioration issues compared to an organic light-emitting diode element.

[0004] The problem to be solved by the present invention is to provide a display device and a manufacturing method thereof that facilitates the process while increasing the brightness of a light-emitting element.

[0005] The tasks of the present invention are not limited to the technical tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0006] According to one embodiment of the present invention for solving the above problem, a display device includes a substrate, a pixel electrode disposed on the substrate, an organic layer disposed on the pixel electrode, a light-emitting element disposed on the organic layer and including a semiconductor stack, a first protective layer, a contact electrode, and a second protective layer, and a connection electrode connecting the light-emitting element and the pixel electrode, wherein the first protective layer is an insulating protective layer, the second protective layer is a conductive protective layer, and the connection electrode and the second protective layer can be etched with the same etchant.

[0007] The second protective layer may be a conductive light-transmitting material.

[0008] The contact electrode may include aluminum, the second protective layer may include IZO (Indium Zinc Oxide), and the connection electrode may include ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

[0009] The above contact electrode may be arranged on one surface of the semiconductor stack to surround the side surface, but may be arranged spaced apart from the upper surface of the semiconductor stack by a first distance.

[0010] The second protective layer is disposed on one surface of the contact semiconductor stack to surround a side surface, but is disposed further outward from the semiconductor stack than the contact electrode and is disposed spaced apart from the upper surface of the semiconductor stack by a second distance, and the second distance may be longer than the first distance.

[0011]

[0012] The connecting electrode surrounds a side surface of the semiconductor stack, is disposed further outward from the semiconductor stack than the second protective layer, and is disposed at a third distance from the upper surface of the semiconductor stack, wherein the third distance may be longer than the first distance.

[0013] The second distance and the third distance may be the same, and the thicknesses of the second protective layer and the connecting electrode may be the same.

[0014] The second distance may be closer than the third distance, and the thickness of the second protective layer may be thicker than the thickness of the connecting electrode.

[0015] The third distance may be closer than the second distance, and the thickness of the connecting electrode may be thicker than the thickness of the second protective layer.

[0016] The second protective layer is disposed on one surface of the contact semiconductor stack to surround a side surface, is disposed further outward from the semiconductor stack than the contact electrode, covers an upper surface of the contact electrode, and is disposed at a second distance from the upper surface of the semiconductor stack, wherein the second distance may be closer than the first distance.

[0017] The connecting electrode surrounds a side surface of the semiconductor stack, is disposed further outward from the semiconductor stack than the second protective layer, and is disposed at a third distance from the upper surface of the semiconductor stack, wherein the third distance may be the same as the second distance.

[0018] The above connecting electrode may be electrically connected through the second protective layer without directly contacting the contact electrode.

[0019] The above second protective layer can be in direct contact with the above organic layer.

[0020] The semiconductor stack may further include a first semiconductor layer disposed on the organic layer and including a semiconductor material layer doped with a first conductive dopant, an active layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the active layer and including a semiconductor material layer doped with a second conductive dopant.

[0021] A method for manufacturing a display device according to one embodiment of the present invention may include the steps of forming a light-emitting element including a semiconductor stack, a first protective layer, a contact electrode, and a second protective layer on a semiconductor substrate, wherein the first protective layer is an insulating protective layer and the second protective layer is a conductive protective layer, bonding the light-emitting element on a circuit board including the pixel electrode, and depositing an electrode material layer on the entire surface of the circuit board and then etching a portion of the electrode material layer and a portion of the second protective layer with the same etchant using a mask pattern.

[0022] The step of bonding the light-emitting element may include forming an organic layer on the pixel electrode and performing primary curing, transferring the light-emitting element onto the organic layer and performing secondary curing, and the second protective layer may have a crystallization temperature higher than the secondary curing temperature of the organic layer.

[0023] The above secondary curing temperature is a temperature of 200℃ or higher and 250℃ or lower, and the second protective layer may be IZO (Indium Zinc Oxide).

[0024] The step of bonding the light-emitting element may include transferring the light-emitting element formed on the semiconductor substrate to a relay substrate, transferring the light-emitting element on the relay substrate to a transfer substrate, and then transferring the light-emitting element on the transfer substrate to the circuit board.

[0025] The transfer substrate onto which the light-emitting element is transferred is cleaned with a chemical solution, and the chemical solution peels off the contact electrode and may not react with the second protective layer.

[0026] The step of etching a portion of the electrode material layer and a portion of the second protective layer with the same etchant includes forming a mask pattern so that the photoresist covers a side surface of the contact electrode, and etching the electrode material layer and the second protective layer on the upper portion of the light-emitting element exposed by the mask pattern, wherein the height of the second protective layer and the height of the connection electrode can be determined according to the height of the photoresist.

[0027] An electronic device including a display device for displaying an image according to one embodiment for solving a problem, the display device including a substrate, a pixel electrode disposed on the substrate, an organic layer disposed on the pixel electrode, a light-emitting element disposed on the organic layer and including a semiconductor stack, a first protective layer, a contact electrode, and a second protective layer, and a connection electrode connecting the light-emitting element and the pixel electrode, wherein the first protective layer is an insulating protective layer, the second protective layer is a conductive protective layer, and the connection electrode and the second protective layer can be etched with the same etchant.

[0028] Specific details of other embodiments are included in the detailed description and drawings.

[0029] According to the display device and its manufacturing method according to the embodiments, the reflectivity of light emitted from the lower surface of the light-emitting element can be increased, thereby increasing the light output of the light-emitting element and increasing the brightness of the display device.

[0030] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0031] Figure 1 is a perspective view showing a display device according to one embodiment.

[0032] FIG. 2 is a layout diagram showing a display device according to one embodiment.

[0033] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0034] Fig. 4 is an equivalent circuit diagram showing a sub-pixel according to one embodiment.

[0035] FIG. 5 is a layout diagram showing pixels of a display area according to one embodiment.

[0036] Fig. 6 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I-I' of Fig. 5.

[0037] Figure 7 is a cross-sectional view showing in detail an example of area A1 of Figure 6.

[0038] Figure 8 is a cross-sectional view showing in detail an example of area B of Figure 7.

[0039] Figure 9 is a cross-sectional view showing another example of area B of Figure 7 in detail.

[0040] Figure 10 is a cross-sectional view showing another example of area B of Figure 7 in detail.

[0041] Figure 11 is a cross-sectional view showing another example of area B of Figure 7 in detail.

[0042] FIG. 12 is a drawing schematically showing light emitted from a light-emitting element in one embodiment of FIG. 7.

[0043] Figure 13 is a graph showing the reflectance of aluminum, chromium, and gold against wavelength.

[0044] Fig. 14 is a flowchart showing a method for manufacturing a display device according to one embodiment.

[0045] FIGS. 15 to 33 are exemplary drawings for explaining a method of manufacturing a display device according to one embodiment.

[0046] FIG. 34 is an exemplary drawing showing a smartwatch including a display device according to one embodiment.

[0047] FIGS. 35 and 36 are exemplary drawings showing a virtual reality device including a display device according to one embodiment.

[0048] FIG. 37 is an exemplary drawing showing a virtual reality device including a display device according to another embodiment.

[0049] FIG. 38 is an exemplary drawing showing an automobile instrument panel and center fascia including display devices according to one embodiment.

[0050] FIG. 39 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0051] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0052] When elements or layers are referred to as being "on" another element or layer, this includes both cases where the other element or layer is directly on top of the other element or layer, or where the other layer or layer is interposed therebetween. Like reference numerals refer to like elements throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are illustrative and therefore the present invention is not limited to the matters illustrated.

[0053] The individual features of the various embodiments of the present invention can be partially or fully combined or combined with one another, enabling various technically feasible interconnections and operations. Each embodiment may be implemented independently of the others, or may be implemented together in a related manner.

[0054] Specific embodiments are described below with reference to the attached drawings.

[0055] Figure 1 is a perspective view showing a display device according to one embodiment.

[0056] Referring to FIG. 1, the display device (10) is a device that displays a moving image or a still image, and can be used as a display screen for various products such as a mobile phone, a smart phone, a tablet personal computer, a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation system, an Ultra Mobile PC (UMPC), etc., as well as a television, a laptop, a monitor, a billboard, an Internet of Things (IOT), etc.

[0057] The display device (10) may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and an ultra-small light-emitting display device using an ultra-small light-emitting diode (micro or nano light emitting diode (micro LED or nano LED)). Hereinafter, the display device (10) is described mainly as an ultra-small light-emitting display device, but the present invention is not limited thereto. Meanwhile, for the convenience of explanation, an ultra-small light-emitting diode is described as a light-emitting element below.

[0058] The display device (10) includes a display panel (100), a display driving circuit (250), a circuit board (300), and a power supply circuit (500).

[0059] The display panel (100) may be formed as a rectangular plane having a short side in a first direction (DR1) and a long side in a second direction (DR2) intersecting the first direction (DR1). A corner where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet may be formed to be rounded to have a predetermined curvature or formed at a right angle. The plane shape of the display panel (100) is not limited to a square, and may be formed in another polygonal, circular, or oval shape. The display panel (100) may be formed to be flat or substantially flat, but is not limited thereto. For example, the display panel (100) may include curved portions formed at left and right ends and having a constant curvature or a varying curvature. (For example, the left and / or right end portions of the display panel (100) may be curved.) In one embodiment, the display panel (100) may be formed flexibly so as to be able to be bent, curved, bent, folded, or rolled.

[0060] The substrate (SUB) of the display panel (100) may include a main area (MA) and a sub area (SBA).

[0061] The main area (MA) may include a display area (DA) that displays an image and a non-display area (NDA) that is a surrounding area of ​​the display area (DA). The display area (DA) may include a plurality of pixels that display an image. Each of the pixels may include a plurality of sub-pixels. For example, each of the pixels may include a first sub-pixel that emits light of a first color, a second sub-pixel that emits light of a second color, and a third sub-pixel that emits light of a third color, but the embodiments of the present specification are not limited thereto.

[0062] The sub-area (SBA) may protrude in a second direction (DR2) from one side of the main area (MA). In FIG. 1, the sub-area (SBA) is illustrated as being unfolded, but the sub-area (SBA) may be bent, in which case it may be disposed on the lower surface of the display panel (100). When the sub-area (SBA) is bent, it may overlap with the main area (MA) in the third direction (DR3), which is the thickness direction of the display panel (100). A display driving circuit (250) may be disposed in the sub-area (SBA).

[0063] The display driving circuit (250) can generate signals and voltages for driving the display panel (100). The display driving circuit (250) can be formed as an integrated circuit (IC) and attached to the display panel (100) using a COG (chip on glass) method, a COP (chip on plastic) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit (250) can be attached to the circuit board (300) using a COF (chip on film) method.

[0064] The circuit board (300) may be attached to one end of the sub-area (SBA) of the display panel (100). As a result, the circuit board (300) may be electrically connected to the display panel (100) and the display driving circuit (250). The display panel (100) and the display driving circuit (250) may receive digital video data, timing signals, and driving voltages through the circuit board (300). The circuit board (300) may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0065] The power supply circuit (500) can generate multiple panel driving voltages according to an external power voltage. The power supply circuit (500) can be formed as an integrated circuit (IC) and attached to a circuit board (300) using a COF method.

[0066] Fig. 2 is a layout diagram showing a display device according to one embodiment. Fig. 2 illustrates that the sub-area (SBA) is unfolded rather than bent.

[0067] Referring to FIG. 2, the display panel (100) may include a main area (MA) and a sub area (SBA).

[0068] The main area (MA) may include a display area (DA) that displays an image and a non-display area (NDA) surrounding the display area (DA). The display area (DA) may occupy most of the area of ​​the main area (MA). The display area (DA) may be positioned at the center of the main area (MA).

[0069] The display area (DA) includes a plurality of pixels (PX) for displaying an image, and each of the plurality of pixels (PX) may include a plurality of sub-pixels (SPX). A pixel (PX) may be defined as a sub-pixel group that is the smallest unit capable of expressing white gradation.

[0070] A non-display area (NDA) may be positioned adjacent to a display area (DA). The non-display area (NDA) may be an area outside the display area (DA). The non-display area (NDA) may be positioned to surround the display area (DA). The non-display area (NDA) may be an edge area of ​​the display panel (100).

[0071] The first scan driver (SDC1) and the second scan driver (SDC2) may be positioned in the non-display area (NDA). The first scan driver (SDC1) may be positioned on one side (e.g., the left side) of the display panel (100), and the second scan driver (SDC2) may be positioned on the other side (e.g., the right side) of the display panel, but the embodiments of the present specification are not limited thereto.

[0072] Each of the first scan driving unit (SDC1) and the second scan driving unit (SDC2) can be electrically connected to the display driving circuit (250) via scan fan out lines. Each of the first scan driving unit (SDC1) and the second scan driving unit (SDC2) can receive a scan control signal from the display driving circuit (250), generate scan signals according to the scan control signal, and output the scan signals to the scan lines.

[0073] The sub-area (SBA) may protrude from one side of the main area (MA) in a second direction (DR2). The length of the sub-area (SBA) in the second direction (DR2) may be shorter than the length of the main area (MA) in the second direction (DR2). The length of the sub-area (SBA) in the first direction (DR1) may be shorter than the length of the main area (MA) in the first direction (DR1) or may be substantially the same as the length of the main area (MA) in the first direction (DR1). The sub-area (SBA) may be curved and may be disposed at a lower portion of the display panel (100). In this case, the sub-area (SBA) may overlap the main area (MA) in the third direction (DR3).

[0074] The sub-area (SBA) may include a connection area (CA), a pad area (PA), and a bending area (BA).

[0075] The connection area (CA) is an area that protrudes in the second direction (DR2) from one side of the main area (MA). One side of the connection area (CA) may be in contact with the non-display area (NDA) of the main area (MA), and the other side of the connection area (CA) may be in contact with the bending area (BA).

[0076] The pad area (PA) is an area where pads (PD) and a display driving circuit (250) are arranged. The display driving circuit (250) can be attached to the driving pads of the pad area (PA) using a conductive adhesive such as an anisotropic conductive film. The circuit board (300) can be attached to the pads (PD) of the pad area (PA) using a conductive adhesive such as an anisotropic conductive film. One side of the pad area (PA) can be in contact with the bending area (BA).

[0077] The bending area (BA) is a bending area. When the bending area (BA) is bent, the pad area (PA) can be positioned below the connection area (CA) and below the main area (MA). The bending area (BA) can be positioned between the connection area (CA) and the pad area (PA). One side of the bending area (BA) can be in contact with the connection area (CA), and the other side of the bending area (BA) can be in contact with the pad area (PA).

[0078] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0079] Referring to FIG. 3, the display area (DA) includes a plurality of pixels (PX), a plurality of scan lines (SL), a plurality of emission control lines (EL), and a plurality of data lines (DL).

[0080] A plurality of pixels (PX) can be arranged in a matrix form in a first direction (DR1) and a second direction (DR2). A plurality of scan lines (SL) and a plurality of emission control lines (EL) can extend in the first direction (DR1) and be arranged in the second direction (DR2). A plurality of data lines (DL) can extend in the second direction (DR2) and be arranged in the first direction (DR1). The plurality of scan lines (SL) include a plurality of write scan lines (GWL), a plurality of control scan lines (GCL), a plurality of initialization scan lines (GIL), and a plurality of bias scan lines (GBL).

[0081] Each of the plurality of sub-pixels (SPX) may be connected to one of the plurality of write scan lines (GWL), one of the plurality of control scan lines (GCL), one of the plurality of initialization scan lines (GIL), one of the plurality of bias scan lines (GBL), one of the plurality of emission control lines (EL), and one of the plurality of data lines (DL). Each of the plurality of sub-pixels (SPX) may be supplied with a data voltage of the data line (DL) according to a write scan signal of the write scan line (GWL), and may emit light through a light-emitting element according to the data voltage.

[0082] The non-display area (NDA) includes a first scan driver (SDC1), a second scan driver (SDC2), and a display driver circuit (250).

[0083] Each of the first scan driving unit (SDC1) and the second scan driving unit (SDC2) may include a write scan signal output unit (611), an initialization scan signal output unit (612), a bias scan signal output unit (613), and an emission control signal output unit (614). Each of the write scan signal output unit (611), the initialization scan signal output unit (612), the bias scan signal output unit (613), and the emission control signal output unit (614) may receive a scan timing control signal (SCS) from a timing control circuit (251).

[0084] The write scan signal output unit (611) can generate write scan signals according to the scan timing control signal (SCS) of the timing control circuit (251) and sequentially output them to write scan lines (GWL).

[0085] The initialization scan signal output unit (612) can generate initialization scan signals according to a scan timing control signal (SCS) and sequentially output them to initialization scan lines (GIL).

[0086] The bias scan signal output unit (613) can generate bias scan signals according to a scan timing control signal (SCS) and sequentially output them to bias scan lines (GBL). The light emission control signal output unit (614) can generate light emission control signals according to a scan timing control signal (SCS) and sequentially output them to light emission control lines (EL).

[0087] The display driving circuit (250) includes a timing control circuit (251) and a data driving circuit (252).

[0088] The data driving circuit (252) can receive digital video data (DATA) and a data timing control signal (DCS) from the timing control circuit (251). The data driving circuit (252) converts the digital video data (DATA) into analog data voltages according to the data timing control signal (DCS) and outputs the converted data voltages to the data lines (DL). In this case, the sub-pixels (SPX) are selected by the write scan signals of the first scan driving unit (SDC1) and the second scan driving unit (SDC2), and the data voltages can be supplied to the selected sub-pixels (SPX).

[0089] The timing control circuit (251) can receive digital video data (DATA) and timing signals from the outside. The timing control circuit (251) can generate a scan timing control signal (SCS) and a data timing control signal (DCS) for controlling the display panel (100) according to the timing signals. The timing control circuit (400) can output the scan timing control signal (SCS) to the first scan driving unit (SDC1) and the second scan driving unit (SDC2). The timing control circuit (251) can output digital video data (DATA) and a data timing control signal (DCS) to the data driving circuit (252).

[0090] The power supply circuit (500) can generate a plurality of panel driving voltages according to a power voltage supplied from an external source. For example, the power supply circuit (500) can generate a first power voltage (VDD), a second power voltage (VSS), a third power voltage (VINT), and a fourth power voltage (VAINT) and supply them to the display panel (100).

[0091] Fig. 4 is an equivalent circuit diagram showing a sub-pixel according to one embodiment.

[0092] Referring to FIG. 4, a sub-pixel (SPX) according to one embodiment may be connected to scan lines (GWL, GIL, GBL), an emission control line (EL), and a data line (DL). For example, the sub-pixel (SPX) may be connected to a write scan line (GWL), an initialization scan line (GIL), a bias scan line (GBL), an emission control line (EL), and a data line (DL).

[0093] A sub-pixel (SPX) according to one embodiment includes a driving transistor (DT), switch elements, a capacitor (C1), and a light-emitting element (LE). The switch elements include first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6).

[0094] A driving transistor (DT) includes a gate electrode, a first electrode, and a second electrode. The driving transistor (DT) controls a drain-source current (Ids, hereinafter referred to as “driving current”) flowing between the first electrode and the second electrode according to a data voltage applied to the gate electrode.

[0095] The light emitting element (LE) may be a micro light emitting diode.

[0096] The light emitting element (LE) emits light according to the driving current (Ids). The amount of light emitted by the light emitting element (LE) may be proportional to the driving current (Ids). The anode electrode of the light emitting element (LE) may be connected to the first electrode of the fourth transistor (ST4) and the second electrode of the sixth transistor (ST6), and the cathode electrode may be connected to the second power line (VSL) to which the second power voltage is applied.

[0097] A capacitor (C1) is formed between the gate electrode of the driving transistor (DT) and a first power line (VDL) to which a first power voltage is applied. The first power voltage may be a voltage of a higher level than the second power voltage. One electrode of the capacitor (C1) may be connected to the gate electrode of the driving transistor (DT), and the other electrode may be connected to the first power line (VDL).

[0098] As shown in Fig. 4, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can all be formed as p-type MOSFETs (metal-oxide-semiconductor field-effect transistors). In this case, the active layers of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can be formed of polysilicon.

[0099] The gate electrode of the first transistor (ST1) and the gate electrode of the second transistor (ST2) may be connected to a write scan line (GWL), the gate electrode of the third transistor (ST3) may be connected to an initialization scan line (GIL), and the gate electrode of the fourth transistor (ST4) may be connected to a bias scan line (GBL). Since the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, and ST6) are formed of p-type MOSFETs, they may be turned on when a scan signal of a gate low voltage and an emission control signal are applied to the initialization scan line (GIL), the write scan line (GWL), the bias scan line (GBL), and the emission line (EL), respectively. One electrode of the third transistor (ST3) may be connected to a first initialization voltage line (VIL) to which a third power supply voltage (VINT of FIG. 3) is applied, and one electrode of the fourth transistor (ST4) may be connected to a second initialization voltage line (VAIL) to which a fourth power supply voltage (VAINT of FIG. 3) is applied. The third power supply voltage (VINT of FIG. 3) and the fourth power supply voltage (VAINT of FIG. 3) may be different voltages. In addition, the third power supply voltage (VINT of FIG. 3) and the fourth power supply voltage (VAINT of FIG. 3) may be a voltage at a lower level than the first power supply voltage (VDD) and a voltage at a higher level than the second power supply voltage (VSS).

[0100] Alternatively, the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) may be formed as p-type MOSFETs, and the first transistor (ST1) and the third transistor (ST3) may be formed as n-type MOSFETs. In this case, the active layers of each of the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) formed as p-type MOSFETs may be formed of polysilicon, and the active layers of each of the first transistor (ST1) and the third transistor (ST3) formed as n-type MOSFETs may be formed of oxide semiconductors. In addition, since the first transistor (ST1) and the third transistor (ST3) are formed as n-type MOSFETs, the first transistor (ST1) may be turned on when a scan signal of a gate high voltage is applied, and the third transistor (ST3) may be turned on when an initialization scan signal of a gate high voltage is applied. In comparison, the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) are formed as p-type MOSFETs, and thus can be turned on when a scan signal of a gate low voltage and a light emission control signal are applied.

[0101] Alternatively, when the fourth transistor (ST4) is formed as an n-type MOSFET and the remaining transistors (DT, ST1, ST2, ST3, ST5, ST6) are formed as p-type MOSFETs, the active layer of the fourth transistor (ST4) may be formed of an oxide semiconductor, and the active layers of each of the remaining transistors (DT, ST1, ST2, ST3, ST5, ST6) may be formed of polysilicon. In addition, the fourth transistor (ST4) may be turned on when a scan signal of a gate high voltage is applied, whereas the remaining transistors (DT, ST1, ST2, ST3, ST5, ST6) may be turned on when a scan signal of a gate low voltage and a light emission control signal are applied.

[0102] Alternatively, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) may all be formed as n-type MOSFETs. In this case, the active layers of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) are formed of an oxide semiconductor and can be turned on when a scan signal of a gate high voltage and a light emission control signal are applied.

[0103] FIG. 5 is a layout diagram showing pixels of a display area according to one embodiment.

[0104] Referring to FIG. 5, each of the plurality of pixels (PX) of the display area (DA) may include three sub-pixels (SPX1, SPX2, SPX3), but the embodiment of the present specification is not limited thereto and may include four sub-pixels. When each of the plurality of pixels (PX) includes three sub-pixels (SPX1, SPX2, SPX3), it may include a first sub-pixel (SPX1), a second sub-pixel (SPX2), and a third sub-pixel (SPX3).

[0105] A plurality of pixels (PX) can be arranged in a matrix form. In each of the plurality of pixels (PX), a first sub-pixel (SPX1), a second sub-pixel (SPX2), and a third sub-pixel (SPX3) can be arranged in a first direction (DR1).

[0106] When each of the plurality of pixels (PX) includes three sub-pixels (SPX1, SPX2, SPX3), the first sub-pixel (SPX1) can emit first light, the second sub-pixel (SPX2) can emit second light, and the third sub-pixel (SPX3) can emit third light. Here, the first light may be light in a blue wavelength band, the second light may be light in a green wavelength band, and the third light may be light in a red wavelength band. For example, the blue wavelength band may refer to a light whose main peak wavelength is included in a wavelength band of approximately 370 nm to 460 nm, the green wavelength band may refer to a light whose main peak wavelength is included in a wavelength band of approximately 480 nm to 560 nm, and the red wavelength band may refer to a light whose main peak wavelength is included in a wavelength band of approximately 600 nm to 750 nm.

[0107] Alternatively, when each of the plurality of pixels (PX) includes four sub-pixels, the first sub-pixel may emit a first light, the second and fourth sub-pixels may emit a second light, and the third sub-pixel may emit a third light. Alternatively, the first sub-pixel may emit a first light, the second sub-pixel may emit a second light, the third sub-pixel may emit a third light, and the fourth sub-pixel may emit a fourth light. In this case, the fourth light may be white light.

[0108] The first sub-pixel (SPX1) includes a first pixel electrode (PXE1), a plurality of light-emitting elements (LEs), and a first light conversion layer (QDL1). The second sub-pixel (SPX2) includes a second pixel electrode (PXE2), a plurality of light-emitting elements (LEs), and a second light conversion layer (QDL2). The third sub-pixel (SPX3) includes a third pixel electrode (PXE3), a plurality of light-emitting elements (LEs), and a light-transmitting layer (or third light conversion layer) (TPL).

[0109] Each of the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) may have a rectangular planar shape having a short side in the first direction (DR1) and a long side in the second direction (DR2). The area of ​​the first sub-pixel (SPX1), the area of ​​the second sub-pixel (SPX2), and the area of ​​the third sub-pixel (SPX3) may be set according to the light conversion efficiency of the first light conversion layer (QDL1) and the light conversion efficiency of the second light conversion layer (QDL2). For example, the lower the light conversion efficiency, the larger the area of ​​the sub-pixel.

[0110] For example, as shown in FIG. 5, when the light conversion efficiency of the second light conversion layer (QDL2) is lower than the light conversion efficiency of the first light conversion layer (QDL1), the area of ​​the second pixel electrode (PXE2) may be larger than the area of ​​the first pixel electrode (PXE1). In addition, since the light transmitting layer (TPL) directly transmits the light of the light emitting element (LE), whereas the first light conversion layer (QDL1) must convert the light, the area of ​​the first pixel electrode (PXE1) may be larger than the area of ​​the third pixel electrode (PXE3).

[0111] Each of the pixel electrodes (PXE1, PXE2, PXE3) can be electrically connected to at least one transistor through a pixel connection hole (CT1 / CT2 / CT3). For example, each of the pixel electrodes (PXE1, PXE2, PXE3) can be electrically connected to a second electrode of a fourth transistor (ST4 of FIG. 4) and a second electrode of a sixth transistor (ST6 of FIG. 4) of the corresponding sub-pixel.

[0112] A plurality of light emitting elements (LE) may be disposed on each of the pixel electrodes (PXE1, PXE2, PXE3). The same number of light emitting elements (LE) may be disposed on each of the pixel electrodes (PXE1, PXE2, PXE3). For example, two light emitting elements (LE) may be disposed on each of the pixel electrodes (PXE1, PXE2, PXE3). The plurality of light emitting elements (LE) may emit a third light, for example, light in a blue wavelength band, but the embodiment of the present specification is not limited thereto. When the light emitting element (LE) of the first sub-pixel (SPX1) emits a first light, the light emitting element (LE) of the second sub-pixel (SPX2) emits a second light, and the light emitting element (LE) of the third sub-pixel (SPX3) emits a third light, the light conversion layers (QDL1, QDL2) and the light transmitting layer (TPL) may be omitted.

[0113] The first light conversion layer (QDL1) can completely overlap the first pixel electrode (PXE1) and the plurality of light emitting elements (LEs) of the first sub-pixel (SPX1). The area of ​​the first light conversion layer (QDL1) can be larger than the area of ​​the first pixel electrode (PXE1). The first light conversion layer (QDL1) can convert or shift the peak wavelength of incident light into light of another specific peak wavelength and emit the light. For example, the first light conversion layer (QDL1) can convert or shift third light emitted from the plurality of light emitting elements (LEs) of the first sub-pixel (SPX1) into first light.

[0114] The second light conversion layer (QDL2) can completely overlap the second pixel electrode (PXE2) and the plurality of light emitting elements (LEs) of the second sub-pixel (SPX2). The area of ​​the second light conversion layer (QDL2) can be larger than the area of ​​the second pixel electrode (PXE2). The second light conversion layer (QDL2) can convert or shift the peak wavelength of incident light into light of another specific peak wavelength and emit the light. For example, the second light conversion layer (QDL2) can convert or shift third light emitted from the plurality of light emitting elements (LEs) of the second sub-pixel (SPX2) into second light.

[0115] The light transmitting layer (TPL) can completely overlap the third pixel electrode (PXE3) and the plurality of light emitting elements (LEs) of the third sub-pixel (SPX3). The light transmitting layer (TPL) can directly transmit incident light. For example, the light transmitting layer (TPL) can directly transmit the third light emitted from the plurality of light emitting elements (LEs) of the third sub-pixel (SPX3).

[0116] Fig. 6 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I-I' of Fig. 5. Fig. 7 is a cross-sectional view showing in detail an example of area A1 of Fig. 6.

[0117] Referring to FIGS. 6 and 7, the substrate (SUB) may be made of an insulating material such as glass or a polymer resin. If the substrate (SUB) is made of a polymer resin, it may be a flexible substrate that can be stretched. The polymer resin may be an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0118] A barrier film (BR) may be disposed on the substrate (SUB). The barrier film (BR) is a film for protecting the transistors of the thin film transistor layer (TFTL) and the light emitting elements (LE) disposed on the thin film transistor layer (TFTL) from moisture penetrating through the substrate (SUB) which is vulnerable to moisture permeation. The barrier film (BR) may be formed of a plurality of inorganic films that are alternately laminated.

[0119] A thin film transistor (TFT1) may be arranged on the barrier film (BR). The thin film transistor (TFT1) may be either the fourth transistor (ST4) or the sixth transistor (ST6) illustrated in FIG. 4. The thin film transistor (TFT1) may include a first active layer (ACT1) and a first gate electrode (G1).

[0120] A first active layer (ACT1) of a thin film transistor (TFT1) may be disposed on the barrier film (BR). The first active layer (ACT1) of the thin film transistor (TFT1) may include polycrystalline silicon, single-crystalline silicon, low-temperature polycrystalline silicon, or amorphous silicon. Alternatively, the first active layer (ACT1) of the thin film transistor (TFT1) may be formed of an oxide semiconductor including IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0121] The first active layer (ACT1) may include a first channel region (CHA1), a first source region (S1), and a first drain region (D1). The first channel region (CHA1) may be a region overlapping the first gate electrode (G1) in a third direction (DR3) that is a thickness direction of the substrate (SUB). The first source region (S1) may be disposed on one side of the first channel region (CHA1), and the first drain region (D1) may be disposed on the other side of the first channel region (CHA1). The first source region (S1) and the first drain region (D1) may be regions that do not overlap the first gate electrode (G1) in the third direction (DR3). The first source region (S1) and the first drain region (D1) may be regions in which ions are doped into a semiconductor material to have conductivity.

[0122] A first gate insulating film (131) may be disposed on the first channel region (CHA1), the first source region (S1), and the first drain region (D1) of the thin film transistor (TFT1).

[0123] A first gate metal layer may be disposed on the first gate insulating film (131). The first gate metal layer may include a first gate electrode (G1) of a thin film transistor (TFT1) and a first capacitor electrode (CAE1). The first gate electrode (G1) may overlap the first active layer (ACT1) in the third direction (DR3). Although FIG. 6 illustrates that the first gate electrode (G1) and the first capacitor electrode (CAE1) are disposed apart from each other, when the thin film transistor (TFT1) is the driving transistor (DT) of FIG. 4, the first gate electrode (G1) and the first capacitor electrode (CAE1) may be electrically or physically connected to each other. Alternatively, when the thin film transistor (TFT1) is any one of the first to sixth transistors (ST1 to ST6) of FIG. 4, the first gate electrode (G1) and the first capacitor electrode (CAE1) may not be electrically or physically connected to each other.

[0124] A second gate insulating film (132) may be disposed on the first gate electrode (G1) and the first capacitor electrode (CAE1) of the thin film transistor (TFT1).

[0125] A second gate metal layer may be disposed on the second gate insulating film (132). The second gate metal layer may include a second capacitor electrode (CAE2). The second capacitor electrode (CAE2) may overlap the first capacitor electrode (CAE1) of the thin film transistor (TFT1) in the third direction (DR3). Since the second gate insulating film (132) has a predetermined dielectric constant, a capacitor (C1 in FIG. 4) may be formed by the first capacitor electrode (CAE1), the second capacitor electrode (CAE2), and the second gate insulating film (132) disposed therebetween.

[0126] A first interlayer insulating film (141) may be placed on the second capacitor electrode (CAE2).

[0127] A first data metal layer may be disposed on a first interlayer insulating film (141). The first data metal layer may include a first source connection electrode (PCE1). The first source connection electrode (PCE1) may be connected to a first drain region (D1) of a first active layer (ACT1) through a first source contact hole (PCT1) penetrating the first gate insulating film (131), the second gate insulating film (132), and the first interlayer insulating film (141).

[0128] A first planarization film (160) may be placed on the first source connection electrode (PCE1) to planarize the step caused by the thin film transistor (TFT1).

[0129] A second data metal layer may be disposed on the first planarization film (160). The second data metal layer may include a second source connection electrode (PCE2). The second source connection electrode (PCE2) may be connected to the first source connection electrode (PCE1) through a second source contact hole (PCT2) penetrating the first planarization film (160).

[0130] A second planarization film (180) may be placed on the second source connection electrode (PCE2).

[0131] The barrier film (BR), the first gate insulating film (131), the second gate insulating film (132), and the interlayer insulating film (141) may be formed of an inorganic film, for example, silicon nitride (SiNx), silicon nitride oxide (SiON), silicon oxide (SiOx), titanium oxide (TiOx), or aluminum oxide (AlOx).

[0132] The first gate metal layer, the second gate metal layer, the first data metal layer, and the second data metal layer may be formed as a single layer or multiple layers made of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0133] The first flattening film (160) and the second flattening film (180) can be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0134] A light-emitting element layer may be arranged on the second planarization film (180). The light-emitting element layer may include pixel electrodes (PXE1, PXE2, PXE3), light-emitting elements (LE), a common electrode (CE), and an organic film (191, 192, 210).

[0135] A pixel electrode layer may be disposed on the second planarization film (180). The pixel electrode layer may include a first pixel electrode (PXE1), a second pixel electrode (PXE2), and a third pixel electrode (PXE3). Each of the pixel electrodes (PXE1, PXE2, PXE3) may be connected to a second source connection electrode (PCE2) through a pixel connection hole (CT1 / CT2 / CT3 of FIG. 5) penetrating the second planarization film (180). Each of the pixel electrodes (PXE1, PXE2, PXE3) may be connected to a first source region (S1) or a first drain region (D1) of a thin film transistor (TFT1) through the first source connection electrode (PCE1) and the second source connection electrode (PCE2). Therefore, a voltage controlled by the thin film transistor (TFT1) may be applied to each of the pixel electrodes (PXE1, PXE2, PXE3).

[0136] The pixel electrode layer may be formed as a single layer or multiple layers made of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). For example, the pixel electrodes (PXE1, PXE2, and PXE3) may include a first layer made of titanium (Ti), a second layer made of aluminum (Al), and a third layer made of titanium (Ti).

[0137] A first organic layer (210) may be disposed on each of the pixel electrodes (PXE1, PXE2, PXE3). For example, at least a portion of the pixel electrodes (PXE1, PXE2, PXE3) may be disposed on the first organic layer (210). The first organic layer (210) serves to temporarily fix or adhere the plurality of light emitting elements (LEs) to prevent the plurality of light emitting elements (LEs) from tilting and falling over or tipping over during the process of transferring the plurality of light emitting elements (LEs) to the display panel (100). That is, the first organic layer (210) may be a film for temporarily adhering the plurality of light emitting elements (LEs) to each of the pixel electrodes (PXE1, PXE2, PXE3). To facilitate the temporary adhering, the thickness of the first organic layer (210) may be greater than the thickness of each of the pixel electrodes (PXE1, PXE2, PXE3).

[0138] The first organic layer (210) may be a photosensitive organic film such as a photoresist. Alternatively, the first organic layer (210) may be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0139] A plurality of light emitting elements (LE) may be arranged on the first organic layer (210). In Fig. 6, it is exemplified that each of the plurality of light emitting elements (LE) is a vertical type micro LED extending in a third direction (DR3). The vertical type micro LED refers to an LED having a structure in which a first semiconductor layer (SEM1), an active layer (MQW), and a second semiconductor layer (SEM2) are sequentially arranged in the third direction (DR3), which is a vertical direction.

[0140] Each of the plurality of light emitting elements (LEs) may have a rectangular cross-section. For example, each of the plurality of light emitting elements (LEs) may have substantially the same width at the top and bottom, but is not limited thereto. For example, each of the plurality of light emitting elements (LEs) may have an inverted trapezoidal shape in which the width at the top is narrower than the width at the bottom.

[0141] Each of the plurality of light emitting elements (LE) may be formed of an inorganic material such as gallium nitride (GaN). Each of the plurality of light emitting elements (LE) may have a length in a first direction (DR1), a length in a second direction (DR2), and a length in a third direction (DR3) of several to several hundred μm, respectively. For example, each of the plurality of light emitting elements (LE) may have a length in the first direction (DR1), a length in the second direction (DR2), and a length in the third direction (DR3) of approximately 100 μm or less, respectively.

[0142] Each of the plurality of light emitting elements (LEs) can be grown and formed on a semiconductor substrate such as a silicon substrate or a sapphire substrate. The plurality of light emitting elements (LEs) can be transferred directly from the semiconductor substrate onto the pixel electrodes (PXE1, PXE2, PXE3) of the display panel (100). Alternatively, the plurality of light emitting elements (LEs) can be transferred onto the pixel electrodes (PXE1, PXE2, PXE3) of the display panel (100) through an electrostatic method using an electrostatic head or a stamp method using an elastic polymer material such as PDMS or silicon as a transfer substrate.

[0143] A light emitting element (LE) may include a conductive layer (E1), a semiconductor stack (STC), a contact electrode (CTE), and a first passivation layer (INS1). The semiconductor stack (STC) may include a first semiconductor layer (SEM1), an active layer (MQW), and a second semiconductor layer (SEM2) sequentially arranged in a third direction (DR3).

[0144] The conductive layer (E1) may be disposed on the lower surface of the first semiconductor layer (SEM1). In Fig. 7, the conductive layer (E1) covers the entire lower surface of the first semiconductor layer (SEM1), but the embodiment of the present specification is not limited thereto. For example, the conductive layer (E1) may be disposed on a portion of the lower surface of the first semiconductor layer (SEM1). The conductive layer (E1) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0145] The first semiconductor layer (SEM1) may be disposed on the contact electrode (CTE). The length of the lower surface of the first semiconductor layer (SEM1) in the first direction (DR1) or the length of the lower surface of the first semiconductor layer (SEM1) in the second direction (DR2) may be smaller than the length of the contact electrode (CTE) in the first direction (DR1) or the length of the contact electrode (CTE) in the second direction (DR2). The first semiconductor layer (SEM1) may be formed of a semiconductor material layer doped with a first conductive dopant such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), or the like, for example, gallium nitride (GaN).

[0146] The active layer (MQW) may be disposed on the first semiconductor layer (SEM1). The active material layer (MQWL) may include the same semiconductor material layer as the first semiconductor material layer (SEML1) and the second semiconductor material layer (SEML2). For example, when the first semiconductor material layer (SEML1) and the second semiconductor material layer (SEML2) include gallium nitride (GaN), the active material layer (MQWL) may also include gallium nitride (GaN). For example, the active material layer (MQWL) may include at least one of gallium nitride (GaN), indium gallium nitride (InGaN), and aluminum gallium nitride (AlGaN). The active layer (MQW) may emit light by the combination of electron-hole pairs in response to an electric signal applied through the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2).

[0147] The active layer (MQW) may include a material having a single or multiple quantum well structure. When the active layer (MQW) includes a material having a multiple quantum well structure, it may have a structure in which a plurality of well layers and barrier layers are alternately stacked. In this case, the well layers may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but is not limited thereto. Alternatively, the active layer (MQW) may have a structure in which a semiconductor material having a large band gap energy and a semiconductor material having a small band gap energy are alternately stacked, or may include different group III to group V semiconductor materials depending on the wavelength of the emitted light.

[0148] When the active layer (MQW) includes indium gallium nitride (InGaN), the color of the emitted light may vary depending on the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of the light emitted by the active layer may shift toward a red wavelength band, and as the content of indium (In) decreases, the wavelength band of the light emitted by the active layer may shift toward a blue wavelength band. For example, the content of indium (In) in the active layer (MQW) of the light-emitting element (LE) that emits the third light (light in the blue wavelength band) may be approximately 10 wt% to 20 wt%.

[0149] A second semiconductor layer (SEM2) may be disposed on the active layer (MQW). The second semiconductor layer (SEM2) may be a semiconductor material layer doped with a second conductive dopant, such as silicon (Si), germanium (Ge), or tin (Sn), for example, gallium nitride (GaN).

[0150] An electron blocking layer may be positioned between the first semiconductor layer (SEM1) and the active layer (MQW). The electron blocking layer may be a layer that suppresses or prevents excessive electrons from flowing into the active layer (MQW). For example, the electron blocking layer may be AlGaN or p-AlGaN doped with p-type Mg. The electron blocking layer may be omitted.

[0151] The superlattice layer may be positioned between the active layer (MQW) and the second semiconductor layer (SEM2). The superlattice layer may be a layer for relieving stress between the second semiconductor layer (SEM2) and the active layer (MQW). For example, the superlattice layer may be formed of InGaN or GaN. The superlattice layer may be omitted.

[0152] The first protective layer (INS1) may be disposed on the side of the first conductive layer (E1), the side of the first semiconductor layer (SEM1), the side of the active layer (MQW), and the side of the second semiconductor layer (SEM2). The first protective layer (INS1) may be a film made of an insulating material for protecting the side of the light emitting element (LE). The first protective layer (INS1) may be formed of an inorganic film, for example, silicon nitride (SiNx), silicon nitride oxide (SiON), silicon oxide (SiOx), titanium oxide (TiOx), or aluminum oxide (AlOx).

[0153] In another embodiment, the first protective layer (INS1) may expose at least a portion of a side surface of the second semiconductor layer (SEM2). For example, it may be positioned spaced apart from the top of the light emitting element (LE).

[0154] Additionally, the first protective layer (INS1) may be disposed only on the side of the first conductive layer (E1), the side of the first semiconductor layer (SEM1), the side of the active layer (MQW), and the side of the second semiconductor layer (SEM2), and may not be disposed on one side of the first conductive layer (E1).

[0155] In addition, the first protective layer (INS1) may be disposed not only on the side of the first conductive layer (E1), the side of the first semiconductor layer (SEM1), the side of the active layer (MQW), and the side of the second semiconductor layer (SEM2), but also on a part of the first conductive layer (E1). However, the first protective layer (INS1) must expose at least a part of the first conductive layer (E1).

[0156] The contact electrode (CTE) may be disposed on the first protective layer (INS1). The contact electrode (CTE) may be disposed between the first organic layer (210) and the first protective layer (INS1). The contact electrode (CTE) may be in contact with the first organic layer (210).

[0157] Although FIGS. 6 and 7 illustrate that the contact electrode (CTE) of each of the light-emitting elements (LE) is disposed on the first organic layer (210), the embodiments of the present specification are not limited thereto. For example, the first organic layer (210) may be disposed on the lower surface and a portion of the side surface of the contact electrode (CTE) of each of the light-emitting elements (LE). Alternatively, the first organic layer (210) may be disposed on the side surface of the conductive layer (E1) of each of the light-emitting elements (LE). Alternatively, the first organic layer (210) may be disposed on the side surface of the first semiconductor layer (SEM1), the side surface of the active layer (MQW), and the side surface of the second semiconductor layer (SEM2) of each of the light-emitting elements (LE). In this case, the first organic layer (210) may be disposed on a portion of the side surface of the second semiconductor layer (SEM2).

[0158] The contact electrode (CTE) can be connected to the exposed conductive layer (E1) that is not covered by the first protective layer (INS1).

[0159] When the contact electrode (CTE) is formed of a metal with high reflectivity, light emitted from the active layer (MQW) of the light emitting element (LE) and traveling in the lateral direction of the light emitting element (LE) can be reflected by the contact electrode (CTE) and emitted to the upper surface of the light emitting element (LE). Therefore, since light loss of the light emitting element (LE) can be reduced, the light efficiency of the light emitting element (LE) can be increased. Therefore, in order to increase the light efficiency of the light emitting element (LE), it is preferable that the contact electrode (CTE) be arranged to cover most of the lateral surface of the semiconductor stack (STC).

[0160] A contact electrode (CTE) may be disposed on a side surface of a semiconductor stack (STC). An area adjacent to a top surface of the semiconductor stack (STC) on the side surface of the semiconductor stack (STC) is covered by a protective film (INS), but may be exposed without being covered by a plurality of contact electrodes (CTEs). For example, it may be disposed spaced apart from the top surface of the semiconductor stack (STC) in a third direction (DR3). Here, the third direction (DR3) may be substantially the same as the height direction (or thickness direction) of the light emitting element (LE). In this way, when the contact electrode (CTE) is spaced apart from the top surface of the semiconductor stack (STC), the contact electrode (CTE) exposed on the top surface of the semiconductor stack (STC) can be prevented from being peeled off by a chemical solution or the like during a manufacturing process.

[0161] The contact electrode (CTE) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Specifically, the contact electrode (CTE) may be formed as a two-layer structure of chromium (Cr) and gold (Au), a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), or a three-layer structure of indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO) to increase reflectivity.

[0162] However, the reflectivity of aluminum (Al) can be about twice as high as that of chromium (Cr), silver (Ag), or gold (Au). Therefore, in one embodiment of the present invention, the contact electrode (CTE) adopts aluminum (Al) with high reflectivity. In this way, when aluminum (Al), which is relatively inexpensive, is adopted instead of gold (Au) as the contact electrode (CTE), the manufacturing cost of the light emitting element (LE) can be reduced.

[0163] The second protective layer (INS2) is a conductive material that serves to protect the contact electrode (CTE). For example, the second protective layer (INS2) can prevent peeling by chemicals or other agents during the process. This will be described in detail in the processing method described below.

[0164] The second protective layer (INS2) may be disposed on the side and one surface of the light emitting element (LE) on the contact electrode (CTE). The second protective layer (INS2) may not be disposed in an area adjacent to the upper surface of the semiconductor stack (STC) on the side of the light emitting element (LE). For example, it may be disposed spaced apart from the upper surface of the light emitting element (LE) in a third direction (DR3). Here, the third direction (DR3) may be substantially the same as the height direction (or thickness direction) of the light emitting element (LE).

[0165] The second protective layer (INS2) is a conductive, transparent material, capable of sputtering, and capable of being wet-etched with the same material as the connecting electrode (BE). The second protective layer (INS2) may be formed of the same material as the connecting electrode (BE), but is not limited thereto. For example, the second protective layer (INS2) may be IZO (Indium Zinc Oxide).

[0166] Since the first protective layer (INS1) is insulating and the second protective layer (INS2) is conductive, the first protective layer (INS1) may be referred to as an insulating protective layer, and the second protective layer (INS2) may be referred to as a conductive protective layer or a conductive electrode protective layer.

[0167] The connecting electrode (BE) connects the contact electrode (CTE) of the light emitting element (LE) and one of the pixel electrodes (PXE1, PXE2, PXE3). The connecting electrode (BE) may be disposed on a portion of a side surface of the light emitting element (LE), and may be disposed on the pixel electrodes (PXE1, PXE2, PXE3) along the upper surface and side surface of the first organic layer (210). In FIG. 7, the connecting electrode (BE) is disposed on the upper surface of the pixel electrodes (PXE1, PXE2, PXE3) and is not disposed on the side surface of the pixel electrodes (PXE1, PXE2, PXE3), but is not limited thereto. For example, the connecting electrode (BE) may be disposed on a portion of the side surface of the light-emitting element (LE), so as to be disposed on the upper surface and side surface of the pixel electrodes (PXE1, PXE2, PXE3) along the upper surface and side surface of the first organic layer (210), as well as on a portion of the side surface of the light-emitting element (LE), so as to be disposed on the upper surface and side surface of the pixel electrodes (PXE1, PXE2, PXE3) along the upper surface and side surface of the first organic layer (210). In addition, the connecting electrode (BE) may be disposed on a portion of the side surface of the light-emitting element (LE), so as to be disposed on the upper surface and side surface of the pixel electrodes (PXE1, PXE2, PXE3) along the upper surface and side surface of the first organic layer (210) or on a portion of the second planarizing organic film (180).

[0168] The connecting electrode (BE) may not be in direct contact with the contact electrode (CTE), but may be electrically connected through the second protective layer (INS2).

[0169] The connecting electrode (BE) is a material that can be sputtered and wet-etched with the same material as the connecting electrode (BE). For example, the connecting electrode (BE) may be made of a transparent conductive material (TCO), such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0170] In one embodiment, the connecting electrode (BE) may be made of the same Indium Zinc Oxide (IZO) as the second protective layer (INS2).

[0171] The second organic layer (211) may be arranged to cover a portion of a side surface of a plurality of light-emitting elements (LE). In addition, the second organic layer (211) may be arranged to cover the connection electrode (BE), but a portion of the connection electrode (BE) may be exposed and not covered by the second organic layer (211).

[0172] The third organic layer (212) may be disposed on the second organic layer (211). The third organic layer (212) may be disposed to cover a portion of a side surface of each of the plurality of light-emitting elements (LE). The third organic layer (212) may be disposed on at least a portion of the connection electrode (BE) that is exposed and not covered by the second organic layer (211). The upper surface of each of the plurality of light-emitting elements (LE) may be exposed and not covered by the third organic layer (212).

[0173] The second organic layer (211) and the third organic layer (212) can be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0174] The second organic layer (211) and the third organic layer (212) are layers for leveling the steps caused by the plurality of light-emitting elements (LE). If the height of the second organic layer (211) is arranged to cover most of the side surfaces of each of the plurality of light-emitting elements (LE), the third organic layer (212) may be omitted.

[0175] A common electrode (CE) may be disposed on the upper surface of each of the plurality of light emitting elements (LE) and the upper surface of the third organic layer (212). The common electrode (CE) may be a common layer formed in common on the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3). The common electrode (CE) may be made of a transparent metal material (TCO, Transparent Conductive Material), such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide), which can transmit light.

[0176] The common electrode (CE) is not in contact with the connecting electrode (BE), the second protective layer (INS2), and the contact electrode (CTE).

[0177] Meanwhile, the pixel electrodes (PXE1, PXE2, PXE3) may be referred to as anode electrodes or first electrodes, and the common electrode (CE) may be referred to as cathode electrodes or second electrodes.

[0178] The first capping layer (CAP1) can be disposed on the common electrode (CE).

[0179] A light-shielding layer (BM), a first light conversion layer (QDL1), a second light conversion layer (QDL2), and a light-transmitting layer (TPL) may be disposed on the first capping layer (CAP1). The first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light-transmitting layer (TPL) may be formed by the partitioning of the light-shielding layer (BM). Therefore, in the first sub-pixel (SPX1), the first light conversion layer (QDL1) may be disposed on the first capping layer (CAP1), in the second sub-pixel (SPX2), the second light conversion layer (QDL2) may be disposed on the first capping layer (CAP1), and in the third sub-pixel (SPX3), the light-transmitting layer (TPL) may be disposed on the first capping layer (CAP1). The light-shielding layer (BM) may overlap the second organic layer (211) and the third organic layer (212) in the third direction (DR3), and may not overlap the plurality of light-emitting elements (LE).

[0180] The first light conversion layer (QDL1) can convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element (LE) into first light (light in the red wavelength band). The first light conversion layer (QDL1) can include a first base resin (BRS1) and a first wavelength conversion particle (WCP1). The first base resin (BRS1) can include a light-transmitting organic material. The first wavelength conversion particle (WCP1) can convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element (LE) into first light (light in the red wavelength band).

[0181] The second light conversion layer (QDL2) can convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element (LE) into second light (light in the green wavelength band). The second light conversion layer (QDL2) can include a second base resin (BRS2) and second wavelength conversion particles (WCP2). The second base resin (BRS2) can include a light-transmitting organic material. The second wavelength conversion particles (WCP2) can convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element (LE) into second light (light in the green wavelength band).

[0182] The optically transparent layer (TPL) may include a light-transmitting organic material.

[0183] For example, the first base resin (BRS1), the second base resin (BRS2), and the light transmitting layer (TPL) may include an epoxy-based resin, an acrylic-based resin, a cardo-based resin, or an imide-based resin. The first and second wavelength conversion particles (WCP1, WCP2) may be quantum dots (QDs), quantum rods, fluorescent materials, or phosphorescent materials.

[0184] The light-blocking layer (BM) may include a first light-blocking layer (BM1) and a second light-blocking layer (BM2) that are sequentially laminated. The length of the first light-blocking layer (BM1) in the first direction (DR1) or the length of the second direction (DR2) may be wider than the length of the second light-blocking layer (BM2) in the first direction (DR1) or the length of the second light-blocking layer (BM2) in the second direction (DR2). The first light-blocking layer (BM1) and the second light-blocking layer (BM2) may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The first light-blocking layer (BM1) and the second light-blocking layer (BM2) may include a light-blocking material to prevent light from a light-emitting element (LE) of a sub-pixel from propagating to an adjacent sub-pixel. For example, the first shading layer (BM1) and the second shading layer (BM2) may include an inorganic black pigment such as carbon black or an organic black pigment.

[0185] The second capping layer (CAP2) may be disposed on the first capping layer (CAP1) and the light-shielding layer (BM). The second capping layer (CAP2) may be disposed on the side surface and the upper surface of the light-shielding layer (BM). For example, the second capping layer (CAP2) may be disposed on the side surface of the first light-shielding layer (BM1) and the side surface and the upper surface of the second light-shielding layer (BM2).

[0186] A reflective film (RF) may be disposed between a light-shielding layer (BM) and a first light conversion layer (QDL1), between a light-shielding layer (BM) and a second light conversion layer (QDL2), and between a light-shielding layer (BM) and a light-transmitting layer (TPL). The reflective film (RF) may be disposed on a second capping layer (CAP2) disposed on a side surface of the first light-shielding layer (BM1) and a side surface of the second light-shielding layer (BM2). The reflective film (RF) serves to reflect light that propagates in a lateral direction in the first light-conversion layer (QDL1), the second light-conversion layer (QDL2), and the light-transmitting layer (TPL).

[0187] The reflective film (RF) may include a highly reflective metal material, such as aluminum (Al). The thickness of the reflective film (RF) may be approximately 0.1 μm.

[0188] Alternatively, the reflective film (RF) may include M pairs of first and second layers having different refractive indices (M is an integer greater than or equal to 2) to function as Distributed Bragg Reflectors (DBR). In this case, the M first layers and the M second layers may be arranged alternately. The first and second layers may be formed of an inorganic film, for example, silicon nitride (SiNx), silicon nitride oxide (SiON), silicon oxide (SiOx), titanium oxide (TiOx), or aluminum oxide (AlOx).

[0189] The third capping layer (CAP3) can be disposed on the second capping layer (CAP2), the first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light transmitting layer (TPL).

[0190] The first capping layer (CAP1), the second capping layer (CAP2), and the third capping layer (CAP3) may be formed of an inorganic film, such as silicon nitride (SiNx), silicon nitride oxide (SiON), silicon oxide (SiOx), titanium oxide (TiOx), or aluminum oxide (AlOx). The first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light transmitting layer (TPL) may be encapsulated by the first capping layer (CAP1), the second capping layer (CAP2), and the third capping layer (CAP3).

[0191] A fifth organic layer (213) may be disposed on the third capping layer (CAP3). A plurality of color filters (CF1, CF2, CF3) may be disposed on the fifth organic layer (213). The plurality of color filters (CF1, CF2, CF3) may include first color filters (CF1), second color filters (CF2), and third color filters (CF3).

[0192] The first color filter (CF1) arranged in the first sub-pixel (SPX1) can transmit the first light (light in the red wavelength band) and absorb or block the third light (light in the blue wavelength band). Therefore, the first color filter (CF1) can transmit the first light (light in the red wavelength band) converted by the first light conversion layer (QDL1) among the third light (light in the blue wavelength band) emitted from the light-emitting element (LE), and absorb or block the third light (light in the blue wavelength band) not converted by the first light conversion layer (QDL1). Therefore, the first sub-pixel (SPX1) can emit the first light (light in the red wavelength band).

[0193] The second color filter (CF2) arranged in the second sub-pixel (SPX2) can transmit the second light (light in the green wavelength band) and absorb or block the third light (light in the blue wavelength band). Therefore, the second color filter (CF2) can transmit the second light (light in the green wavelength band) converted by the first light conversion layer (QDL1) among the third light (light in the blue wavelength band) emitted from the light-emitting element (LE), and absorb or block the third light (light in the blue wavelength band) not converted by the first light conversion layer (QDL1). Therefore, the second sub-pixel (SPX2) can emit the second light (light in the green wavelength band).

[0194] The third color filter (CF3) arranged in the third sub-pixel (SPX3) can transmit the third light (light in the blue wavelength band). Therefore, the third color filter (CF3) can transmit the third light (light in the blue wavelength band) emitted from the light-emitting element (LE) passing through the light-transmitting layer (TPL). Therefore, the third sub-pixel (SPX3) can emit the third light (light in the blue wavelength band).

[0195] The first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) overlapping in the third direction (DR3) can overlap the light-shielding layer (BM) in the third direction (DR3).

[0196] A fifth organic layer (214) for planarization may be placed on a plurality of color filters (CF1, CF2, CF3).

[0197] The fourth organic layer (213) and the fifth organic layer (214) can be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0198] Figure 8 is a cross-sectional view showing in detail an example of area B of Figure 7.

[0199] Referring to Fig. 8, the side surface of the semiconductor stack (STC) is surrounded by a first passivation layer (INS1). A contact electrode (CTE) surrounds a portion of the side surface of the semiconductor stack (STC) on the first passivation layer (INS1). An area adjacent to the upper surface of the semiconductor stack (STC) on the side surface of the semiconductor stack (STC) is covered by the passivation layer (INS), but may be exposed without being covered by a plurality of contact electrodes (CTEs).

[0200] The second passivation layer (INS2) and the connection electrode (BE) surround a portion of the side surface of the light emitting element (LE). The second passivation layer (INS2) is positioned closer to the light emitting element (LE) than the connection electrode (BE). For example, the second passivation layer (INS2) is in contact with the contact electrode (CTE), and the connection electrode (BE) is in contact with the second passivation layer (INS2). Since the second passivation layer (INS2) is a conductive passivation layer, it electrically connects the contact electrode (CTE) and the connection electrode (BE).

[0201] From the side of the light emitting element (LE), an area adjacent to the upper surface of the light emitting element (LE) may be exposed without being covered by the second protective layer (INS2) and the connecting electrode (BE).

[0202] In the third direction (DR3), the height of the second passivation layer (INS2) and the connection electrode (BE) may be greater than the height of the contact electrode (CTE). For example, in the third direction (DR3), a distance (DS1) between the upper surface of the light-emitting element (LE) (or the upper surface of the semiconductor stack (STC)) and the contact electrode (CTE) is smaller than a distance (DS2) between the upper surface of the light-emitting element (LE) and the second passivation layer (INS2), and smaller than a distance (DS3) between the upper surface of the light-emitting element (LE) and the connection electrode (BE). In addition, the distance (DS2) between the upper surface of the light-emitting element (LE) and the second passivation layer (INS2) is the same as the distance (DS3) between the upper surface of the light-emitting element (LE) and the connection electrode (BE). The third direction (DR3) may be a thickness direction of the light-emitting element (LE) and a stacking direction of the semiconductor layer.

[0203] The thickness (W1) of the second protective layer (INS2) and the thickness (W2) of each connecting electrode (BE) are the same. The thickness (W1) of the second protective layer (INS2) and the thickness (W2) of each connecting electrode (BE) are the widths in the outward direction from the surface of the light emitting element (LE).

[0204] Figure 9 is a cross-sectional view showing another example of area B of Figure 7 in detail.

[0205] Referring to FIG. 9, the second protective layer (INS2) and the connection electrode (BE) are formed higher than the contact electrode (CTE), and the upper portion of the second protective layer (INS2) surrounds the contact electrode (CTE), which is different from FIG. 8.

[0206] From the side of the light emitting element (LE), an area adjacent to the upper surface of the light emitting element (LE) may be exposed without being covered by the second protective layer (INS2) and the connecting electrode (BE).

[0207] In the third direction (DR3), the height of the second passivation layer (INS2) and the connection electrode (BE) may be lower than the contact electrode (CTE). For example, in the third direction (DR3), a distance (DS1) between the upper surface of the light-emitting element (LE) (or the upper surface of the semiconductor stack (STC)) and the contact electrode (CTE) is smaller than a distance (DS2) between the upper surface of the light-emitting element (LE) and the second passivation layer (INS2), and smaller than a distance (DS3) between the upper surface of the light-emitting element (LE) and the connection electrode (BE). In addition, a distance (DS2) between the upper surface of the light-emitting element (LE) and the second passivation layer (INS2) and a distance (DS3) between the upper surface of the light-emitting element (LE) and the connection electrode (BE) may be the same. The third direction (DR3) may be a thickness direction of the light-emitting element (LE) and a stacking direction of the semiconductor layer.

[0208] The second protective layer (INS2) can cover one end of the contact electrode (CTE). The one end of the contact electrode (CTE) is surrounded by the second protective layer (INS2) and the first protective layer (INS1) and is not exposed.

[0209] The thickness (W1) of the second protective layer (INS2) and the thickness (W2) of each connecting electrode (BE) are the same. The thickness (W1) of the second protective layer (INS2) and the thickness (W2) of each connecting electrode (BE) are the widths in the outward direction from the surface of the light emitting element (LE).

[0210] Figure 10 is a cross-sectional view showing another example of area B of Figure 7 in detail.

[0211] Referring to FIG. 10, it is different from FIG. 8 in that the height of the connecting electrode (BE) is lower than the height of the second protective layer (INS2).

[0212] Referring to Fig. 10, the side surface of the semiconductor stack (STC) is surrounded by a first passivation layer (INS1). A contact electrode (CTE) surrounds a portion of the side surface of the semiconductor stack (STC) on the first passivation layer (INS1). An area adjacent to the upper surface of the semiconductor stack (STC) on the side surface of the semiconductor stack (STC) is covered by the passivation layer (INS), but may be exposed without being covered by a plurality of contact electrodes (CTEs).

[0213] The second passivation layer (INS2) and the connection electrode (BE) surround a portion of the side surface of the light emitting element (LE). The second passivation layer (INS2) is positioned closer to the light emitting element (LE) than the connection electrode (BE). For example, the second passivation layer (INS2) is in contact with the contact electrode (CTE), and the connection electrode (BE) is in contact with the second passivation layer (INS2). Since the second passivation layer (INS2) is a conductive passivation layer, it electrically connects the contact electrode (CTE) and the connection electrode (BE).

[0214] From the side of the light emitting element (LE), an area adjacent to the upper surface of the light emitting element (LE) may be exposed without being covered by the second protective layer (INS2) and the connecting electrode (BE).

[0215] In the third direction (DR3), the height of the second passivation layer (INS2) and the connection electrode (BE) may be lower than the contact electrode (CTE). For example, in the third direction (DR3), a distance (DS1) between the upper surface of the light-emitting element (LE) (or the upper surface of the semiconductor stack (STC)) and the contact electrode (CTE) is smaller than a distance (DS2) between the upper surface of the light-emitting element (LE) and the second passivation layer (INS2), and smaller than a distance (DS3) between the upper surface of the light-emitting element (LE) and the connection electrode (BE). In addition, a distance (DS2) between the upper surface of the light-emitting element (LE) and the second passivation layer (INS2) is smaller than a distance (DS3) between the upper surface of the light-emitting element (LE) and the connection electrode (BE). The third direction (DR3) may be a thickness direction of the light-emitting element (LE) and a stacking direction of the semiconductor layer.

[0216] The thickness (W1) of the second protective layer (INS2) is thicker than the thickness (W2) of the connecting electrode (BE). In addition, the thickness (W1) of the second protective layer (INS2) is thicker than the thickness (W0) of the contact electrode (CTE).

[0217] Figure 11 is a cross-sectional view showing another example of area B of Figure 7 in detail.

[0218] Referring to FIG. 11, it is different from FIG. 8 in that the height of the connecting electrode (BE) is higher than the height of the second protective layer (INS2).

[0219] Referring to Fig. 11, a side surface of a semiconductor stack (STC) is surrounded by a first passivation layer (INS1). A contact electrode (CTE) surrounds a portion of the side surface of the semiconductor stack (STC) on the first passivation layer (INS1). Among the side surfaces of the semiconductor stack (STC), an area adjacent to the upper surface of the semiconductor stack (STC) is covered by the passivation layer (INS), but may be exposed without being covered by a plurality of contact electrodes (CTEs).

[0220] The second passivation layer (INS2) and the connection electrode (BE) surround a portion of the side surface of the light emitting element (LE). The second passivation layer (INS2) is positioned closer to the light emitting element (LE) than the connection electrode (BE). For example, the second passivation layer (INS2) is in contact with the contact electrode (CTE), and the connection electrode (BE) is in contact with the second passivation layer (INS2). Since the second passivation layer (INS2) is a conductive passivation layer, it electrically connects the contact electrode (CTE) and the connection electrode (BE).

[0221] From the side of the light emitting element (LE), an area adjacent to the upper surface of the light emitting element (LE) may be exposed without being covered by the second protective layer (INS2) and the connecting electrode (BE).

[0222] In the third direction (DR3), the height of the second passivation layer (INS2) and the connection electrode (BE) may be lower than the contact electrode (CTE). For example, in the third direction (DR3), a distance (DS1) between the upper surface of the light-emitting element (LE) (or the upper surface of the semiconductor stack (STC)) and the contact electrode (CTE) is smaller than a distance (DS2) between the upper surface of the light-emitting element (LE) and the second passivation layer (INS2), and smaller than a distance (DS3) between the upper surface of the light-emitting element (LE) and the connection electrode (BE). In addition, the distance (DS2) between the upper surface of the light-emitting element (LE) and the second passivation layer (INS2) is longer than a distance (DS3) between the upper surface of the light-emitting element (LE) and the connection electrode (BE). The third direction (DR3) may be a thickness direction of the light-emitting element (LE) and a stacking direction of the semiconductor layer.

[0223] The thickness (W2) of the connecting electrode (BE) is thicker than the thickness (W1) of the second protective layer (INS2). The thickness (W2) of the connecting electrode (BE) is thicker than the thickness (W0) of the contact electrode.

[0224] FIG. 12 is a drawing schematically showing light emitted from a light emitting element (LE) in one embodiment of FIG. 7.

[0225] Referring to Fig. 12, it can be seen that light emitted from the active layer (MQW) of the light emitting element (LE) travels downward as well as upward. It can be seen that the light (L1, L2, L3) traveling downward is reflected by a contact electrode (CTE) including a metal with a high reflectivity, for example, aluminum (Al), and travels upward. On the other hand, when the contact electrode (CTE) is formed of a metal with a relatively low reflectivity, for example, chromium (Cr) or gold (Au), the reflectivity of light emitted downward from the light emitting element (LE) may be reduced, which may lower the luminous efficiency of the display device.

[0226] Figure 13 is a graph showing the reflectance of aluminum (Al), chromium (Cr), and gold (Au) with respect to wavelength.

[0227] Referring to Fig. 13, it can be seen that the reflectivity of aluminum (Al) is about 92% or more at most wavelengths. On the other hand, it can be seen that gold (Au) has a reflectivity of less than 38% from 200 nm to 500 nm, and silver (Ag) has a reflectivity of less than 25% from 200 nm to 350 nm. Therefore, it can be seen that when the contact electrode (CTE of Fig. 12) adopts aluminum (Al), the reflectivity of light emitted in a downward direction can be improved by about 2.5 to 3 times. Ultimately, when the contact electrode (CTE of Fig. 12) adopts aluminum (Al), it can increase the brightness of the display device by contributing to the light extraction of the light emitting element (LE).

[0228] Fig. 14 is a flowchart showing a method for manufacturing a display device according to one embodiment. Figs. 15 to 33 are exemplary drawings for explaining a method for manufacturing a display device according to one embodiment.

[0229] Hereinafter, FIGS. 15 to 33 illustrate cross-sectional views of the structure of each layer of the display device according to the formation order. FIGS. 14 to 33 focus on the formation of the light-emitting element (LE) and the light-emitting element layer. Below, the manufacturing method of the display device illustrated in FIGS. 15 to 33 will be described in conjunction with FIG. 14.

[0230] First, a light emitting element (LE) including a semiconductor stack (STC), a first protective layer (INS1), a contact electrode (CTE), and a second protective layer (INS2) is formed on a semiconductor substrate (BSUB). (S110 of FIG. 14)

[0231] For example, referring to FIG. 15, a semiconductor substrate (BSUB) is prepared. The semiconductor substrate (BSUB) may be a sapphire substrate (Al2O3) or a transparent silicon wafer containing silicon. However, the present invention is not limited thereto, and in one embodiment, a case in which the semiconductor substrate (BSUB) is a sapphire substrate is described as an example.

[0232] A plurality of semiconductor material layers (SEM3L, SEM2L, SLTL, MQWL, EBLL, SEM1L) are formed on a semiconductor substrate (BSUB). The plurality of semiconductor material layers grown by an epitaxial method can be formed by growing a seed crystal. Here, a method for forming the semiconductor material layers may be electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, metal-organic chemical vapor deposition (MOCVD), etc., and preferably, it can be formed by metal-organic chemical vapor deposition (MOCVD). However, it is not limited thereto.

[0233] The precursor material for forming multiple semiconductor material layers is not particularly limited within a range that can be typically selected to form the target material. For example, the precursor material may be a metal precursor containing an alkyl group, such as a methyl group or an ethyl group. Examples thereof include, but are not limited to, compounds such as trimethyl gallium (Ga(CH3)3), trimethyl aluminum (Al(CH3)3), and triethyl phosphate ((C2H5)3PO4).

[0234] Specifically, a third semiconductor material layer (SEM3L) is formed on a semiconductor substrate (BSUB). The drawing illustrates that the third semiconductor material layer (SEM3L) is laminated in one layer, but this is not limited thereto and multiple layers may be formed.

[0235] The third semiconductor material layer (SEM3L) may be arranged to reduce the lattice constant difference between the second semiconductor material layer (SEM2L) and the semiconductor substrate (BSUB). For example, the third semiconductor material layer (SEM3L) may include an undoped semiconductor and may be an n-type or p-type undoped material. In an exemplary embodiment, the third semiconductor material layer (SEM3L) may be at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, but is not limited thereto.

[0236] Using the above-described method, a second semiconductor material layer (SEM2L), an active material layer (MQWL), and a first semiconductor material layer (SEM1L) are sequentially formed on a third semiconductor material layer (SEM3L). In another variation, a superlattice material layer may be formed between the second semiconductor material layer (SEM2L) and the active material layer (MQWL). In addition, an electron blocking material layer may be formed between the active material layer (MQWL) and the first semiconductor material layer (SEM1L). A conductive material layer (E1L) may further be formed on the first semiconductor material layer (SEM1L). The conductive material layer (E1L) may be made of a transparent metal material (TCO, Transparent Conductive Material) such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide) that can transmit light, but is not limited thereto. In another embodiment, the conductive material layer (E1L) may be omitted.

[0237] Referring to FIG. 16, after forming a mask pattern on a conductive material layer (E1L), a third semiconductor material layer (SEM3L), a second semiconductor material layer (SEM2L), an active material layer (MQWL), a first semiconductor material layer (SEM1L), and a conductive material layer (E1L) are etched according to the first mask pattern to form semiconductor stacks. The first mask pattern can be removed after forming a plurality of light-emitting elements (LE).

[0238] The etching process can be performed by dry etching, wet etching, reactive ion etching (RIE), deep reactive ion etching (DRIE), inductively coupled plasma reactive ion etching (ICP-RIE), etc. In the case of dry etching, anisotropic etching is possible, so it may be suitable for vertical etching. When dry etching is used, the etching gas may be Cl2 or O2, but is not limited thereto.

[0239] Then, referring to FIG. 17, a first protective layer (INS1) may be formed that covers side surfaces of the first semiconductor layer (SEM1), the active layer (MQW), the second semiconductor layer (SEM2), and the third semiconductor layer (SEM3) in each of the plurality of semiconductor stacks (STC). Meanwhile, the third semiconductor layer (SEM3) may be referred to as an undoped semiconductor layer. The first protective layer (INS1) may cover a portion of the conductive layer (E1). Even in this case, the first protective layer (INS1) must expose at least a portion of the conductive layer (E1).

[0240] Referring to FIG. 18, a second mask pattern (PR) can be formed on a portion of one side of each semiconductor stack (STC) and between the semiconductor stacks (STC).

[0241] A contact electrode layer (CTEL) is deposited on one side of a semiconductor substrate (BSUB).

[0242] A contact electrode layer (CTEL) may be formed to cover one surface and side surfaces of the light emitting elements (LE). The contact electrode layer (CTEL) may be arranged to cover the second mask pattern (PR). The contact electrode layer (CTEL) may be formed on one surface of the semiconductor substrate (BSUB) exposed between the light emitting elements (LE).

[0243] Referring to Fig. 19, the second mask pattern (PR) is removed and a contact electrode (CTE) is formed. The contact electrode (CTE) can be formed to include aluminum (Al) having a high reflectivity.

[0244] For example, the second mask pattern (PR) can be removed using a lift-off process. To remove the second mask pattern (PR) using a lift-off process, the second mask pattern (PR) can be formed using a negative photoresist. In this case, only the second mask pattern (PR) and the contact electrode layer (CTEL) disposed on the second mask pattern (PR) can be removed using a solvent ashing process using alcohol.

[0245] When the second mask pattern (PR) is removed, the contact electrode (CTE) can be exposed without covering the first protective layer (INS1) disposed on the side of the third semiconductor layer (SEML3).

[0246] Meanwhile, by reducing the thickness of the second mask pattern (PR) disposed between the light emitting elements (LE), the area that the contact electrode (CTE) covers the first passivation layer (INS1) disposed on the side surface of the semiconductor stack (STC) can be increased. As a result, the contact electrode (CTE) can reflect light emitted from the active layer (MQW) of the light emitting element (LE) and propagate in the side direction of the light emitting element (LE), thereby emitting light to the upper surface of the light emitting element (LE). Therefore, since the loss of light from the light emitting element (LE) can be reduced, the light efficiency of the light emitting element (LE) can be increased. The first passivation layer (INS1) can be formed of an insulating material, for example, silicon nitride (SiNx), silicon nitride oxide (SiON), silicon oxide (SiOx), titanium oxide (TiOx), or aluminum oxide (AlOx).

[0247] Then, referring to FIG. 20, a conductive second protective layer (INS2) is formed. The second protective layer (INS2) can completely surround the contact electrode (CTE). The second protective layer (INS2) is a conductive material that does not react with the etchant described below. For example, the second protective layer (INS2) can be formed of IZO (Indium Zinc Oxide).

[0248] This can protect the contact electrode (CTE) from being exposed to the chemical solution used in the cleaning process described later.

[0249] The above-described chemical solution may be tetramethylammonium hydroxide (TMAH), but the embodiments of the present disclosure are not limited thereto. When aluminum is exposed to tetramethylammonium hydroxide (TMAH), a peel-off phenomenon may occur in a contact electrode (CTE) including aluminum. In one embodiment, a second protective layer (INS2) that does not react with the chemical solution is formed to completely surround the contact electrode (CTE), so that the contact electrode (CTE) does not come into contact with the chemical solution. Accordingly, the contact electrode (CTE) can be formed to include aluminum having a high reflectivity without substantial damage by the chemical solution.

[0250] Second, the light emitting element (LE) is transferred and bonded onto the substrate (SUB). (S120 in Fig. 14)

[0251] To clearly distinguish the substrate (SUB) from the aforementioned semiconductor substrate (BSUB), it can be referred to as a circuit board (SUB).

[0252] For example, referring to FIG. 21, a plurality of light emitting elements (LE) of a semiconductor substrate (BSUB) are moved to a first adhesive layer (ADL1) disposed on a first relay substrate (SPL1). The first relay substrate (SPL1) may be made of a transparent material that allows light to pass through. For example, the first relay substrate (SPL1) may include a transparent polymer such as polyimide, polyester, polyacrylic, polyepoxy, polyethylene, polystyrene, polyethylene terephthalate, or the like. The first adhesive layer (ADL1) disposed on one surface of the first relay substrate (SPL1) may include an adhesive material for adhering the plurality of light emitting elements (LE). For example, the adhesive material may include urethane acrylate, epoxy acrylate, polyester acrylate, or the like.

[0253] A second protective layer (INS2) of each of the plurality of light emitting elements (LE) can be adhered to a first adhesive layer (ADL1) disposed on a first relay substrate (SPL1).

[0254] Then, referring to FIG. 22, a plurality of light emitting elements (LE) can be separated from the semiconductor substrate (BSUB) by a laser lift off (LLO) process of irradiating a laser onto the semiconductor substrate (BSUB).

[0255] As shown in Fig. 23, a plurality of light-emitting elements (LE) of the first relay substrate (SPL1) are moved onto the first transfer substrate (SPL2).

[0256] The first transfer substrate (SPL2) may be made of a transparent material that allows light to pass through. For example, the first transfer substrate (SPL2) may include a transparent polymer such as polyimide, polyester, polyacrylic, polyepoxy, polyethylene, polystyrene, polyethylene terephthalate, or the like.

[0257] One side of each of the plurality of light emitting elements (LE) can be placed on a first transfer substrate (SPL2). An adhesive layer having adhesive properties can also be further included on the first transfer substrate (SPL2). For example, the adhesive layer is a layer that can be separated by laser irradiation, and may include, for example, a transparent polymer such as polyimide.

[0258] When heat is applied while one surface of each of the plurality of light-emitting elements (LE) is in contact with the adhesive layer as shown in Fig. 24, each of the plurality of light-emitting elements (LE) can be adhered or fixed to the adhesive layer, and as the adhesive strength of the adhesive layer is weakened, each of the plurality of light-emitting elements (LE) can be separated from the first adhesive layer (ADL1). One surface of each of the plurality of light-emitting elements (LE) in contact with the adhesive layer on the first transfer substrate (SPL2) may be the opposite surface of the other surface on which the second protective layer (INS2) is disposed on each of the plurality of light-emitting elements (LE). Thereafter, the second transfer substrate (SPL2) can be removed. After the light-emitting elements (LE) are transferred in this manner, a cleaning process can be performed. Contaminants including the adhesive layer on the light-emitting elements (LE) can be removed by the cleaning process. As described above, the first transfer substrate (SPL2) can be cleaned with a chemical solution. The chemical solution may be tetramethylammonium hydroxide (TMAH), but the embodiments of the present disclosure are not limited thereto. The contact electrode (CTE) may be a material that is susceptible to chemical damage, but is protected from the chemical solution because it is surrounded by a second protective layer (INS2) that does not react with the chemical solution.

[0259] Meanwhile, as shown in Fig. 25, a circuit board (SUB) on which pixel electrodes (PXE1, PXE2, PXE3) are arranged is prepared. Here, the circuit board may be a circuit board (SUB) included in the transistor layer (TFTL) described with reference to Fig. 6.

[0260] As shown in FIG. 26, a first organic layer (210) is formed on the pixel electrodes (PXE1, PXE2, PXE3). The light emitting elements (LEs) can be moved onto the first organic layer (210). At this time, the light emitting elements (LEs) can be temporarily fixed by being embedded in the first organic layer (210). For example, although the second protective layer (INS2) is exemplified as being disposed on the first organic layer (210), the embodiment of the present specification is not limited thereto. For example, the first organic layer (210) can be disposed on a portion of the lower surface and side surface of the second protective layer (INS2) of each of the light emitting elements (LEs) and a portion of the lower surface and side surface of the contact electrode (CTE). Alternatively, the first organic layer (210) can be disposed on the side surfaces of the conductive layer (E1) of each of the light emitting elements (LEs). Alternatively, the first organic layer (210) may be disposed on the side surfaces of the first semiconductor layer (SEM1), the side surfaces of the active layer (MQW), and the side surfaces of the second semiconductor layer (SEM2) of each of the light emitting elements (LE). In this case, the first organic layer (210) may be disposed on a portion of each of the side surfaces of the second semiconductor layer (SEM2).

[0261] When the fluidity of the first organic layer (210) is low or the first organic layer (210) is solid, the depth at which the light-emitting element (LE) is inserted or embedded in the first organic layer (210) may be very small, or the light-emitting element (LE) may be placed on the first organic layer (210) without being inserted or embedded in the first organic layer (210).

[0262] When the first organic layer (210) is a photosensitive organic film such as a photoresist, after the first organic layer (210) is cured (soft baked) at a first temperature, at least a portion of each of the plurality of light-emitting elements (LE) is inserted into the first organic layer (210). Then, the first organic layer (210) can be completely cured at a second temperature higher than the first temperature. The first temperature may be approximately 100°C, and the second temperature may be approximately 230°C, but the embodiments of the present specification are not limited thereto. In addition, the process of completely curing the first organic layer (210) at the second temperature may be performed for approximately 30 minutes.

[0263] Meanwhile, when the second protective layer (INS2) is formed of ITO (Indium Tin Oxide) instead of IZO (Indium Zinc Oxide), ITO crystallizes at around 200°C, so wet etching cannot be performed in the subsequent etching process. Therefore, in one embodiment, the second protective layer (INS2) is formed of IZO having a crystallization temperature of about 600°C or higher, so that the second protective layer (INS2) can be etched in the subsequent wet etching process.

[0264] Third, a connecting electrode is formed. (S130 of FIG. 14) A connecting electrode (BE) is formed to connect the second protective layer (INS2) of the light-emitting element (LE) disposed on the first organic layer (210) and the pixel electrode (PXE).

[0265] For example, a connection electrode material layer (BEL) is formed on the front surface of the circuit board (SUB) as shown in Fig. 27. For example, the connection electrode material layer (BEL) may be a material that can be etched by the same etchant as the second protective layer (INS2). For example, when formed as the second protective layer (INS2), the connection electrode material layer (BEL) may include IZO (Indium Zinc Oxide). In addition, the connection electrode material layer (BEL) may include ITO (Indium Tin Oxide) (since there is no heat treatment process of 200°C or higher in the subsequent process).

[0266] As shown in Fig. 28, a third mask pattern (PR2) is formed using a photoresist, and the exposed connection material layer (BEL) that is not covered by the third mask pattern (PR2) is etched using an etchant. At this time, when the connection material layer (BEL) is etched, a portion of the second protective layer (INS2) is exposed, and the exposed second protective layer (INS2) can be etched.

[0267] Afterwards, the third mask pattern (PR2 of FIG. 28) can be removed by an ashing process, as shown in FIG. 29.

[0268] At this time, the height of the connection electrode (BE) and the second protective layer (INS2) may vary depending on the formation height of the third mask pattern (PR2).

[0269] For example, referring to FIG. 30, when the third mask pattern (PR2) is formed lower than the height of the contact electrode (CTE), the height of the connection electrode (BE) and the second protective layer (INS2) can be formed lower than the height of the second contact electrode (CTE).

[0270] Meanwhile, when the third mask pattern (PR2) is formed with a first height lower than the height of the contact electrode (CTE), the heights of the second protective layer (INS2) and the connection electrode (BE) may vary depending on the thickness of the second protective layer (INS2) and the connection electrode (BE). This is because the difference in etching time occurs depending on the thickness of the second protective layer (INS2) and the connection electrode (BE), and the thicker the thickness, the more difficult the etching is and the higher the electrode may be formed. For example, as illustrated in FIG. 10, when the thickness (W1) of the second protective layer (INS2) is thicker than the thickness (W2) of the connection electrode (BE), the height of the connection electrode (BE) may be formed lower. In addition, as illustrated in FIG. 11, when the thickness (W1) of the second protective layer (INS2) is thinner than the thickness (W2) of the connection electrode (BE), the height of the second protective layer (INS2) may be formed lower.

[0271] As another example, referring to FIG. 31, when the formation height of the third mask pattern (PR2) is formed higher than the contact electrode (CTE), the height of the second protective layer (INS2) and the connection electrode (BE) can be formed higher than the height of the contact electrode (CTE).

[0272] Additionally, a second protective layer (INS2) can be formed to cover the upper portion of the contact electrode (CTE).

[0273] However, since the second protective layer (INS2) is a conductive protective layer, it must be positioned so as to be spaced apart from the upper surface of the light-emitting element (LE) so as not to come into contact with the subsequently formed common electrode (CE). Therefore, the third mask pattern (PR2) must be formed lower than the upper surface of the light-emitting element (LE).

[0274] Fourth, a common electrode (CE) is formed. (S140 in Fig. 14)

[0275] A second organic layer (211) and a third organic layer (212) are formed to fix the light emitting elements (LEs) and to level out the steps caused by the light emitting elements (LEs). The third organic layer (212) is not formed to completely cover the light emitting elements (LEs). For example, the third organic layer (212) may expose the upper surface of the light emitting elements (LEs).

[0276] Thereafter, a common electrode (CE) is formed on the third organic layer (212) and the light-emitting element (LE). The common electrode (CE) can be electrically connected to the second semiconductor layer (SEM2) of the light-emitting element (LE).

[0277] Fifth, a light-shielding layer, a wavelength conversion layer, a light-transmitting layer, and a color filter layer are formed sequentially. (S150 in Fig. 14)

[0278] A first capping layer (CAP1) is formed on the third organic layer (212) and the light-emitting elements (LE), and a first light-blocking layer (BM1) and a second light-blocking layer (BM2) are formed on the first capping layer (CAP1) so as not to overlap with the light-emitting elements (LE) in the third direction (DR3). Then, a second capping layer (CAP2) covering the first light-blocking layer (BM1), the second light-blocking layer (BM2), and the first capping layer (CAP1) is formed. Then, a reflective film (RF) is formed covering the second capping layer (CAP2) disposed on the first light-blocking layer (BM1) and the second light-blocking layer (BM2).

[0279] Then, a first light conversion layer (QDL1) is formed on each of the first sub-pixels (SPX1), a second light conversion layer (QDL2) is formed on each of the second sub-pixels (SPX2), and a light transmitting layer (TPL) is formed on each of the third sub-pixels (SPX3). Then, a third capping layer (CAP3) is formed to cover the first light conversion layers (QDL1), the second light conversion layers (QDL2), and the light transmitting layers (TPL). Then, a fourth organic layer (213) is formed on the third capping layer (CAP3).

[0280] Then, a first color filter (CF1) is formed on the fourth organic layer (213) to overlap the first light conversion layers (QDL1) in the third direction (DR3), a second color filter (CF2) is formed to overlap the second light conversion layers (QDL2) in the third direction (DR3), and a third color filter (CF3) is formed to overlap the light transmitting layers (TPL) in the third direction (DR3). The first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) can all be formed in the region overlapping the first light-blocking layer (BM1) and the second light-blocking layer (BM2) in the third direction (DR3).

[0281] Then, a fifth organic layer (214) is formed on the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3).

[0282] FIG. 34 is an exemplary drawing showing a smartwatch including a display device according to one embodiment.

[0283] Referring to FIG. 34, a display device (10_1) according to one embodiment can be applied to a smart watch (1000_1), which is one of the smart devices.

[0284] FIGS. 35 and 36 are exemplary drawings showing a virtual reality device including a display device according to one embodiment.

[0285] Referring to FIGS. 35 and 36, a head-mounted display device (1000_2) according to one embodiment includes a first display device (10_2), a second display device (10_3), a display device storage unit (1100), a storage unit cover (1200), a first eyepiece lens (1210), a second eyepiece lens (1220), a head-mounted band (1300), a middle frame (1400), a first optical member (1510), a second optical member (1520), and a control circuit board (1600).

[0286] The first display device (10_2) provides an image to the user's left eye, and the second display device (10_3) provides an image to the user's right eye. Since each of the first display device (10_2) and the second display device (10_3) is substantially the same as the display device (10) described in conjunction with FIGS. 1 and 2, descriptions of the first display device (10_2) and the second display device (10_3) are omitted.

[0287] The first optical member (1510) may be positioned between the first display device (10_2) and the first eyepiece lens (1210). The second optical member (1520) may be positioned between the second display device (10_3) and the second eyepiece lens (1220). Each of the first optical member (1510) and the second optical member (1520) may include at least one convex lens.

[0288] The middle frame (1400) is disposed between the first display device (10_2) and the control circuit board (1600), and may be disposed between the second display device (10_3) and the control circuit board (1600). The middle frame (1400) serves to support and fix the first display device (10_2), the second display device (10_3), and the control circuit board (1600).

[0289] The control circuit board (1600) may be placed between the middle frame (1400) and the display device housing (1100). The control circuit board (1600) may be connected to the first display device (10_2) and the second display device (10_3) via connectors. The control circuit board (1600) may convert an image source input from the outside into digital video data (DATA) and transmit the digital video data (DATA) to the first display device (10_2) and the second display device (10_3) via the connectors.

[0290] The control circuit board (1600) can transmit digital video data (DATA) corresponding to a left-eye image optimized for the user's left eye to the first display device (10_2) and digital video data (DATA) corresponding to a right-eye image optimized for the user's right eye to the second display device (10_3). Alternatively, the control circuit board (1600) can transmit the same digital video data (DATA) to the first display device (10_2) and the second display device (10_3).

[0291] The display device storage unit (1100) serves to store the first display device (10_2), the second display device (10_3), the middle frame (1400), the first optical member (1510), the second optical member (1520), and the control circuit board (1600). The storage unit cover (1200) is arranged to cover an open surface of the display device storage unit (1100). The storage unit cover (1200) may include a first eyepiece (1210) for the user's left eye and a second eyepiece (1220) for the user's right eye. In FIGS. 33 and 34, the first eyepiece (1210) and the second eyepiece (1220) are separately arranged, but the embodiment of the present specification is not limited thereto. The first eyepiece (1210) and the second eyepiece (1220) may be combined into one.

[0292] The first eyepiece (1210) can be aligned with the first display device (10_2) and the first optical member (1510), and the second eyepiece (1220) can be aligned with the second display device (10_3) and the second optical member (1520). Accordingly, the user can view the image of the first display device (10_2) enlarged into a virtual image by the first optical member (1510) through the first eyepiece (1210), and can view the image of the second display device (10_3) enlarged into a virtual image by the second optical member (1520) through the second eyepiece (1220).

[0293] The head-mounted band (1300) serves to secure the display device storage unit (1100) to the user's head so that the first eyepiece (1210) and the second eyepiece (1220) of the storage unit cover (1200) can be positioned respectively for the user's left and right eyes. If the display device storage unit (1200) is implemented in a lightweight and compact form, the head-mounted display device (1000) may be equipped with a glasses frame as shown in FIG. 35 instead of the head-mounted band (800).

[0294] In addition, the head-mounted display device (1000) may further include a battery for supplying power, an external memory slot for storing external memory, and an external connection port and wireless communication module for receiving a video source. The external connection port may be a USB (universe serial bus) terminal, a display port, or an HDMI (high-definition multimedia interface) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0295] Fig. 37 is an exemplary drawing showing a virtual reality device including a display device according to another embodiment. Fig. 37 shows a virtual reality device (1000_3) to which a display device (10_4) according to one embodiment is applied.

[0296] Referring to FIG. 37, a virtual reality device (1000_3) according to one embodiment may be a device in the form of glasses. The virtual reality device (1000_3) according to one embodiment may include a display device (10_4), a left-eye lens (10a), a right-eye lens (10b), a support frame (20), eyeglass frame legs (30a, 30b), a reflective member (40), and a display device storage unit (50).

[0297] In Fig. 37, it is exemplified that the virtual reality device (1000_3) is a glasses-type display device including glasses frame legs (30a, 30b). That is, the virtual reality device (1000_3) according to one embodiment is not limited to that illustrated in Fig. 36, and can be applied in various forms in various other electronic devices.

[0298] The display device housing (50) may include a display device (10_4) and a reflective member (40). An image displayed on the display device (10_4) may be reflected by the reflective member (40) and provided to the user's right eye through the right eye lens (10b). As a result, the user may view a virtual reality image displayed on the display device (10_4) through the right eye.

[0299] In FIG. 37, the display device housing (50) is exemplified as being arranged at the right end of the support frame (20), but the embodiment of the present specification is not limited thereto. For example, the display device housing (50) may be arranged at the left end of the support frame (20), in which case the image displayed on the display device (10_4) may be reflected by the reflective member (40) and provided to the user's left eye through the left eye lens (10a). As a result, the user may view the virtual reality image displayed on the display device (10_4) through the left eye. Alternatively, the display device housing (50) may be arranged at both the left end and the right end of the support frame (20), in which case the user may view the virtual reality image displayed on the display device (10_4) through both the left eye and the right eye.

[0300] Fig. 38 is an exemplary drawing showing an automobile instrument panel and center fascia including display devices according to one embodiment. Fig. 38 shows an automobile to which display devices (10_a, 10_b, 10_c, 10_d, 10_e) according to one embodiment are applied.

[0301] Referring to FIG. 38, display devices (10_a, 10_b, 10_c) according to one embodiment may be applied to a dashboard of a vehicle, a center fascia of a vehicle, or a CID (Center Information Display) placed on a dashboard of a vehicle. In addition, display devices (10_d, 10_e) according to one embodiment may be applied to a room mirror display that replaces a side mirror of a vehicle.

[0302] FIG. 39 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0303] Referring to FIG. 39, a display device (10_5) according to one embodiment can be applied to a transparent display device. The transparent display device can display an image (IM) and transmit light at the same time. Therefore, a user positioned at the front of the transparent display device can not only view the image (IM) displayed on the display device (10_5), but also view an object (RS) or background positioned at the back of the transparent display device. When the display device (10_5) is applied to a transparent display device, the substrate of the display device (10_5) can include a light-transmitting portion that can transmit light or can be formed of a material that can transmit light.

[0304] Although embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

Claims

1. Substrate; A pixel electrode disposed on a substrate; An organic layer disposed on a pixel electrode; A light emitting element disposed on the organic layer and including a semiconductor stack, a first protective layer, a contact electrode, and a second protective layer; and Including a connecting electrode connecting the light-emitting element and the pixel electrode, The above first protective layer is an insulating protective layer, and the above second protective layer is a conductive protective layer. A display device in which the above-mentioned connecting electrode and the second protective layer can be etched with the same etchant.

2. In paragraph 1, A display device wherein the second protective layer is a conductive light-transmitting material.

3. In paragraph 2, The above contact electrode comprises aluminum, The second protective layer comprises IZO (Indium Zinc Oxide), A display device in which the above connecting electrode includes at least one of ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

4. In paragraph 1, A display device in which the contact electrode is arranged on one surface of the semiconductor stack, surrounding the side surface, and spaced apart from the upper surface of the semiconductor stack by a first distance.

5. In paragraph 4, A display device in which the second protective layer is disposed on one surface of the contact semiconductor stack to surround a side surface, is disposed further outward from the semiconductor stack than the contact electrode, and is disposed at a second distance from the upper surface of the semiconductor stack, wherein the second distance is further than the first distance.

6. In paragraph 5, A display device in which the connecting electrode surrounds a side surface of the semiconductor stack, is disposed further outward from the semiconductor stack than the second protective layer, and is disposed at a third distance from the upper surface of the semiconductor stack, the third distance being further than the first distance.

7. In paragraph 6, A display device in which the second distance and the third distance are the same and the thicknesses of the second protective layer and the connecting electrode are the same.

8. In paragraph 6, A display device wherein the second distance is closer than the third distance and the thickness of the second protective layer is thicker than the thickness of the connecting electrode.

9. In paragraph 6, A display device in which the third distance is closer than the second distance and the thickness of the connecting electrode is thicker than the thickness of the second protective layer.

10. In paragraph 4, A display device in which the second protective layer is disposed on one surface of the contact semiconductor stack to surround a side surface, is disposed further outward from the semiconductor stack than the contact electrode, covers an upper surface of the contact electrode, and is disposed spaced apart from the upper surface of the semiconductor stack by a second distance, the second distance being closer than the first distance.

11. In paragraph 10, The connecting electrode surrounds the side surface of the semiconductor stack, is disposed further outward from the semiconductor stack than the second protective layer, and is disposed at a third distance from the upper surface of the semiconductor stack, the third distance being the same as the second distance.

12. In paragraph 1, A display device in which the above-mentioned connecting electrode is electrically connected to the above-mentioned contact electrode through the second protective layer without directly contacting the above-mentioned contact electrode.

13. In paragraph 10, The second protective layer is a display device in direct contact with the organic layer.

14. In paragraph 1, The above semiconductor stack, A first semiconductor layer disposed on the organic layer and including a semiconductor material layer doped with a first conductive dopant; An active layer disposed on the first semiconductor layer; and A display device further comprising a second semiconductor layer disposed on the active layer and including a semiconductor material layer doped with a second conductive dopant.

15. A step of forming a light-emitting element including a semiconductor stack, a first protective layer, a contact electrode, and a second protective layer on a semiconductor substrate, wherein the first protective layer is an insulating protective layer, and the second protective layer is a conductive protective layer; A step of bonding the light emitting element onto a circuit board including a pixel electrode; A method for manufacturing a display device, comprising the step of depositing an electrode material layer on the entire surface of the circuit board and then etching a portion of the electrode material layer and a portion of the second protective layer with the same etchant using a mask pattern.

16. In paragraph 15, The step of bonding the above light-emitting element is: An organic layer is formed on the pixel electrode and cured for the first time, the light-emitting element is transferred onto the organic layer and cured for the second time, The second protective layer has a crystallization temperature higher than the secondary curing temperature of the organic layer, The above secondary curing temperature is a temperature of 200℃ or higher and 250℃ or lower, A method for manufacturing a display device in which the second protective layer is IZO (Indium Zinc Oxide).

17. In paragraph 15, The step of bonding the above light-emitting element is: A method for manufacturing a display device, comprising: transferring the light-emitting element formed on the semiconductor substrate to a relay substrate, transferring the light-emitting element on the relay substrate to a transfer substrate, and then transferring the light-emitting element on the transfer substrate to the circuit board.

18. A method for manufacturing a display device in which the transfer substrate to which the light-emitting element is transferred is cleaned with a chemical solution in the 17th paragraph, and the chemical solution peels off the contact electrode and does not react with the second protective layer.

19. In the 15th paragraph, the step of etching a part of the electrode material layer and a part of the second protective layer with the same etchant is as follows: Forming a mask pattern so as to cover the side of the contact electrode with a photoresist, and etching the electrode material layer and the second protective layer on the upper portion of the light emitting element exposed by the mask pattern, The above etched electrode material layer forms a connecting electrode, A method for manufacturing a display device in which the height of the second protective layer and the height of the connecting electrode are determined according to the height of the above photoresist.

20. In an electronic device including a display device for displaying an image, The above display device, substrate; A pixel electrode disposed on a substrate; An organic layer disposed on a pixel electrode; A light emitting element disposed on the organic layer and including a semiconductor stack, a first protective layer, a contact electrode, and a second protective layer; Including a connecting electrode connecting the light-emitting element and the pixel electrode, The above first protective layer is an insulating protective layer, and the above second protective layer is a conductive protective layer. An electronic device wherein the above connecting electrode and the second protective layer can be etched with the same etchant.

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