Display substrate and display device

Abstract

Provided is a display substrate, comprising a base substrate; and a drive circuit layer, which comprises a drive circuit and an initialization signal input structure. The initialization signal input structure comprises a second initialization signal portion, the second initialization signal portion comprising a plurality of signal sub-portions, and the plurality of signal sub-portions being arranged in an array in a first direction and a second direction. The drive circuit comprises a first transistor, the first transistor comprising a first gate, wherein the orthographic projection of the signal sub-portions on the base substrate partially overlaps the orthographic projection of the first gate on the base substrate. Each signal sub-portion comprises a second signal segment extending in the first direction, and a third signal segment extending in the second direction, wherein the orthographic projection of the second signal segment on the base substrate partially overlaps the orthographic projection of a second gate signal line on the base substrate; and the second signal segment comprises a first portion and a second portion located on two sides of the third signal segment in the first direction, the length of the first portion in the first direction being less than the length of the second portion in the first direction.

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display substrate and a display device. BACKGROUND

[0002] Micro Organic Light-Emitting Diode (Micro-OLED) is a micro display developed in recent years, and silicon-based OLED is one of them. Silicon-based OLED is prepared by mature Complementary Metal Oxide Semiconductor (CMOS) integrated circuit process, has the advantages of small size, high resolution (Pixels Per Inch, PPI), high refresh rate, and is widely used in near-eye display fields such as Virtual Reality (VR) or Augmented Reality (AR).

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure, and therefore, the above information can contain information that does not constitute prior art.

[0004] SUMMARY

[0005] In one aspect, a display substrate is provided, comprising:

[0006] a substrate substrate;

[0007] a drive circuit layer located on the substrate substrate, the drive circuit layer comprising a drive circuit, an initialization signal input structure for accessing an initialization signal to the drive circuit;

[0008] wherein the drive circuit layer comprises at least two conductive layers, the at least two conductive layers comprising a first conductive layer and a second conductive layer located on a side of the first conductive layer away from the substrate substrate, the initialization signal input structure comprising a second initialization signal part, the second initialization signal part being located on the second conductive layer, the second initialization signal part comprising a plurality of signal sub-parts, the plurality of signal sub-parts being arranged in an array along a first direction and a second direction, the first direction intersecting the second direction;

[0009] the drive circuit comprises a first transistor, the first transistor comprising a first gate, the drive circuit layer comprises a gate layer located on a side of the first conductive layer close to the substrate substrate, and the first gate is located on the gate layer; and

[0010] A normal projection of the signal sub-portion on the substrate and a normal projection of the first gate on the substrate partially overlap, the signal sub-portion includes a second signal segment extending along a first direction and a third signal segment extending along a second direction, and the second signal segment includes a first portion and a second portion located on both sides of the third signal segment along the first direction, a length of the first portion along the first direction is less than a length of the second portion along the first direction.

[0011] According to some exemplary embodiments, normal projections of two first gates adjacent along the first direction on the substrate and a normal projection of the same signal sub-portion on the substrate respectively overlap, and an overlapping area of the normal projection of one first gate on the substrate and the normal projection of the signal sub-portion on the substrate is substantially equal to an overlapping area of the normal projection of the other first gate on the substrate and the normal projection of the signal sub-portion on the substrate.

[0012] According to some exemplary embodiments, a normal projection of one first gate on the substrate and a normal projection of the second portion of the second signal segment on the substrate overlap and is spaced apart from a normal projection of the third signal segment on the substrate, a normal projection of the other first gate on the substrate and a normal projection of the first portion of the second signal segment on the substrate and a normal projection of the third signal segment on the substrate respectively overlap; and

[0013] An overlapping area of the normal projection of one first gate on the substrate and the normal projection of the second portion of the second signal segment on the substrate is substantially equal to a sum of overlapping areas of the normal projection of the other first gate on the substrate and the normal projection of the first portion of the second signal segment and the normal projection of the third signal segment on the substrate.

[0014] According to some exemplary embodiments, an overlapping area of the normal projection of the first gate on the substrate and the normal projection of the first portion of the second signal segment on the substrate is greater than an overlapping area of the normal projection of the first gate on the substrate and the normal projection of the third signal segment on the substrate.

[0015] According to some exemplary embodiments, the driving circuit includes a second transistor, the second transistor includes a second gate, one second gate is between two first gates adjacent along the first direction, and normal projections of the two first gates and one second gate on the substrate respectively overlap a normal projection of the same second signal segment on the substrate.

[0016] According to some exemplary embodiments, a projection of the third signal segment on the substrate substrate intersects with a projection of two first gates adjacent to each other along the second direction on the substrate substrate respectively.

[0017] According to some exemplary embodiments, the driving circuit layer further comprises a plurality of second gate signal lines for accessing a second gate signal to the driving circuit, the second gate signal lines are located in the first conductive layer, the plurality of second gate signal lines extend along a first direction and are arranged along a second direction, a projection of the second signal segment on the substrate substrate partially overlaps with a projection of the second gate signal lines on the substrate substrate,

[0018] According to some exemplary embodiments, a width of the second signal segment along the second direction is greater than or equal to a width of the second gate signal lines along the second direction.

[0019] According to some exemplary embodiments, the first conductive layer comprises a sixth connection structure located on one side of the second gate signal lines along the second direction, the driving circuit comprises a second transistor comprising a second active region, the driving circuit layer further comprises a first insulating layer located between the second active region and the first conductive layer, the first insulating layer has a ninth via, and the sixth connection structure is electrically connected to a first electrode of the second active region through the ninth via; and

[0020] The second conductive layer comprises a twenty-fourth connection structure, at least one of the twenty-fourth connection structures is located on one side of the second signal segment along the second direction, the driving circuit layer further comprises a second insulating layer located between the first conductive layer and the second conductive layer, the second insulating layer has a twenty-fifth via, and the twenty-fourth connection structure is electrically connected to the sixth connection structure through the twenty-fifth via.

[0021] Wherein, a distance between a projection of the second gate signal lines on the substrate substrate and a projection of adjacent ninth vias on the substrate substrate along the second direction is a first distance, a distance between a projection of the second signal segment on the substrate substrate and a projection of adjacent twenty-fifth vias on the substrate substrate along the second direction is a second distance, and the first distance is greater than the second distance.

[0022] According to some exemplary embodiments, the driving circuit layer further comprises a first power signal input structure for accessing a first power signal to the driving circuit, the first power signal input structure comprises a first power signal part of the second conductive layer, the first power signal part comprises a plurality of third power signal lines, the plurality of third power signal lines extend along the second direction and are arranged along the first direction, the signal subpart is between two adjacent third power signal lines.

[0023] According to some exemplary embodiments, the second conductive layer comprises a first capacitor electrode between the adjacent third power signal line and the third signal segment, the first capacitor electrode has a third distance to the adjacent third power signal line along the first direction, the first capacitor electrode has a fourth distance to the adjacent third signal segment along the first direction; and

[0024] The second signal segment has a fifth distance to the adjacent third power signal line along the first direction, the third distance is greater than the fifth distance, and / or the fourth distance is greater than the fifth distance.

[0025] According to some exemplary embodiments, the first conductive layer comprises a first conductive connection part, a sixth connection structure and a seventh connection structure, the driving circuit comprises a first transistor and a second transistor, the first transistor comprises a first gate and a first active region, the second transistor comprises a second active region, the first conductive connection part is electrically connected with the first gate, the sixth connection structure is electrically connected with a first pole of the second active region, and the seventh connection structure is electrically connected with a first pole of the first active region.

[0026] The second conductive layer comprises a second conductive connection part, a twenty-fourth connection structure and a twenty-fifth connection structure, the second conductive connection part, the twenty-fourth connection structure and the twenty-fifth connection structure are between the adjacent third signal segment and third power signal line.

[0027] The driving circuit layer further comprises a second insulating layer between the first conductive layer and the second conductive layer, the second insulating layer comprises a twenty-first via, a twenty-fifth via and a twenty-sixth via, the twenty-first via is between the twenty-fifth via and the twenty-sixth via, the second conductive connection part is electrically connected with the first conductive connection part through the twenty-first via, the twenty-fourth connection structure is electrically connected with the sixth connection structure through the twenty-fifth via, and the twenty-fifth connection structure is electrically connected with the seventh connection structure through the twenty-sixth via.

[0028] At least one of the twenty-sixth via is disposed adjacent to the third signal segment along the first direction, and a distance between a projection of the twenty-sixth via on the substrate and a projection of the adjacent third signal segment on the substrate along the first direction is a sixth distance;

[0029] At least one of the twenty-fifth via is disposed adjacent to the third signal segment along the first direction, and a distance between a projection of the twenty-fifth via on the substrate and a projection of the adjacent third signal segment on the substrate along the first direction is a ninth distance; and

[0030] A distance between a projection of the twenty-first via on the substrate and a projection of the twenty-sixth via on the substrate along the first direction is a seventh distance, and a distance between a projection of the twenty-first via on the substrate and a projection of the twenty-fifth via on the substrate along the first direction is an eighth distance;

[0031] Wherein, at least two of the sixth distance, the seventh distance, the eighth distance and the ninth distance are not equal to each other.

[0032] According to some exemplary embodiments, the sixth distance ≤ the seventh distance, and / or the sixth distance ≤ the eighth distance, and / or the eighth distance ≤ the seventh distance, and / or the sixth distance ≤ the ninth distance, and / or the seventh distance ≤ the ninth distance, and / or the eighth distance ≤ the ninth distance.

[0033] According to some exemplary embodiments, at least one of the twenty-fourth connection structure is located on one side of the second signal segment along the second direction, and on one side of the third signal segment along the first direction;

[0034] Wherein, a distance between the twenty-fourth connection structure and the second signal segment is greater than or equal to 0.15 μm; and / or

[0035] A distance between the twenty-fourth connection structure and the third signal segment is greater than or equal to 0.15 μm.

[0036] According to some exemplary embodiments, the at least two conductive layers further comprise a third conductive layer located on a side of the second conductive layer away from the substrate, the third conductive layer comprising a second power signal part and a second capacitor electrode, the second power signal part transmitting a first power signal;

[0037] The second power signal portion includes a fourth power signal line extending along the first direction and a plurality of fifth power signal segments connected to the fourth power signal line, the plurality of fifth power signal segments extending along the second direction and arranged along the first direction; and

[0038] The second capacitor electrode is located between two adjacent fifth power signal segments and is spaced apart from the adjacent fourth power signal lines.

[0039] According to some exemplary embodiments, a spacing between the second capacitor electrode and an adjacent fourth power signal line along the second direction is an eleventh spacing, and a spacing between the second capacitor electrode and an adjacent fifth power signal segment along the first direction is a twelfth spacing, wherein the twelfth spacing is greater than the eleventh spacing.

[0040] According to some exemplary embodiments, the second conductive layer includes a twenty-fourth connection structure, at least one of the twenty-fourth connection structures is located on one side of the second signal segment along the second direction, the driving circuit layer further includes a second insulating layer between the first conductive layer and the second conductive layer, the second insulating layer has a twenty-fifth via hole, the twenty-fourth connection structure is electrically connected to the sixth connection structure through the twenty-fifth via hole, and the driving circuit includes a second transistor, the second transistor includes a second active region, and the sixth connection structure is electrically connected to a first electrode of the second active region.

[0041] A projection of the second capacitor electrode on the substrate is spaced apart from a projection of the second signal segment on the substrate;

[0042] The second capacitor electrode is located between two adjacent fifth power signal segments and is spaced apart from the adjacent fourth power signal lines.

[0043] According to some exemplary embodiments, a spacing between the second capacitor electrode and an adjacent fourth power signal line along the second direction is an eleventh spacing, and the eleventh spacing is greater than the second spacing.

[0044] According to some exemplary embodiments, the fourth power signal line includes a fourth power signal line main portion extending along the first direction and a fourth power signal line connection portion located on one side of the fourth power signal line main portion along the second direction and connected to the fourth power signal line main portion.

[0045] The driving circuit layer further comprises a third insulating layer between the third conductive layer and the second conductive layer, the third insulating layer has a thirty-sixth via hole, and the fourth power signal line body part is electrically connected with the twenty-fourth connecting structure through the thirty-sixth via hole;

[0046] The geometric center of the orthogonal projection of the twenty-fifth via hole on the substrate substrate and the orthogonal projection of the adjacent second signal segment on the substrate substrate along the second direction has a thirteenth interval, and the geometric center of the orthogonal projection of the thirty-sixth via hole on the substrate substrate and the orthogonal projection of the adjacent fourth power signal line body part on the substrate substrate along the second direction has a fourteenth interval, and the fourteenth interval is smaller than the thirteenth interval; or

[0047] The geometric center of the orthogonal projection of the twenty-fifth via hole on the substrate substrate and the orthogonal projection of the adjacent second signal segment on the substrate substrate along the second direction has a thirteenth interval, and the geometric center of the orthogonal projection of the thirty-sixth via hole on the substrate substrate is located within the orthogonal projection of the adjacent fourth power signal line body part on the substrate substrate.

[0048] According to some exemplary embodiments, at least a portion of the orthogonal projection of the fourth power signal line body part on the substrate substrate is spaced apart from the orthogonal projection of the second signal segment on the substrate substrate.

[0049] According to some exemplary embodiments, the first power signal part further comprises a plurality of second power signal lines, the plurality of second power signal lines extend along the first direction and are arranged along the second direction, the plurality of second power signal lines and the plurality of third power signal lines are interlaced to form a grid structure, and the first power signal part comprises a plurality of hollow parts, and the plurality of signal sub-parts are respectively located in the plurality of hollow parts of the first power signal part.

[0050] According to some exemplary embodiments, the plurality of signal sub-parts arranged along the first direction and the plurality of third power signal lines are alternately arranged along the first direction; and / or

[0051] The plurality of signal sub-parts arranged along the second direction and the plurality of second power signal lines are alternately arranged along the second direction.

[0052] According to some exemplary embodiments, the interval between the second part of the second signal segment and the adjacent third power signal line is greater than or equal to 0.15 μm; and / or

[0053] The interval between the third signal segment and the adjacent second power signal line is greater than or equal to 0.15 μm.

[0054] According to some exemplary embodiments, the initialization signal input structure further comprises a first initialization signal part, the first initialization signal part is located in the first conductive layer, the first initialization signal part comprises a plurality of first initialization signal lines, the plurality of first initialization signal lines extend along a first direction and are arranged along a second direction, and two adjacent first initialization signal lines are electrically connected by at least one signal subpart.

[0055] According to some exemplary embodiments, the first initialization signal part further comprises at least one first signal segment electrically connected to the first initialization signal line, the first signal segment extends along the second direction, one end of the first signal segment is electrically connected to the first initialization signal line and the other end of the first signal segment is spaced apart from the adjacent second gate signal line; and

[0056] The orthographic projection of the third signal segment on the substrate and the orthographic projection of two adjacent and spaced first signal segments along the second direction on the substrate respectively partially overlap, and the two adjacent and spaced first signal segments along the second direction are electrically connected by the third signal segment.

[0057] According to some exemplary embodiments, the driving circuit comprises a third transistor, and the orthographic projection of the first signal segment on the substrate is located between the orthographic projections of two adjacent third transistors along a first direction on the substrate.

[0058] According to some exemplary embodiments, the orthographic projections of two adjacent third transistors along the first direction on the substrate are located between the orthographic projections of two adjacent first signal segments along the first direction on the substrate.

[0059] According to some exemplary embodiments, the driving circuit layer further comprises a plurality of first gate signal lines, the plurality of first gate signal lines extend along a first direction and are arranged along a second direction, the first gate signal lines are used for transmitting first gate signals, and the driving circuit comprises a third transistor.

[0060] Among one driving circuit, the first gate signal line and the second gate signal line electrically connected to the driving circuit respectively, the orthographic projection of the first gate signal line on the substrate and the orthographic projection of the second gate signal line on the substrate are located on the same side of the orthographic projection of the third transistor on the substrate, and the first gate signal line and the second gate signal line are respectively located in different conductive layers.

[0061] According to some exemplary embodiments, the at least two conductive layers further include a third conductive layer located on a side of the second conductive layer distal to the substrate, and the first gate signal line is located on the third conductive layer.

[0062] According to some exemplary embodiments, a projection of the second gate signal line on the substrate is spaced apart from a projection of the first gate signal line on the substrate.

[0063] The second conductive layer includes a shielding trace, and a projection of the shielding trace on the substrate at least partially overlaps a projection of the second gate signal line on the substrate.

[0064] A projection of the shielding trace on the substrate is spaced apart from a projection of the first gate signal line on the substrate.

[0065] According to some exemplary embodiments, the second conductive layer includes a second conductive connection, the driving circuit layer further includes a third insulating layer located between the second conductive layer and the third conductive layer, the third insulating layer includes a thirty-first via, and the first gate signal line is electrically connected to the second conductive connection through the thirty-first via.

[0066] The first gate signal line is a zigzag trace extending along the first direction, the first gate signal line includes a corner portion, and a projection of the thirty-first via on the substrate is located within a projection of the corner portion on the substrate.

[0067] According to some exemplary embodiments, the driving circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor, and the display substrate further includes a light emitting element electrically connected to the driving circuit.

[0068] The first electrode of the first transistor is configured to access a data signal, the second electrode of the first transistor is electrically connected to the third gate electrode of the third transistor, and the first gate electrode of the first transistor is configured to access a first gate signal.

[0069] The first electrode of the second transistor is configured to access a first power signal, the second electrode of the second transistor is electrically connected to the first electrode of the third transistor, and the second gate electrode of the second transistor is configured to access a second gate signal.

[0070] The second electrode of the third transistor is electrically connected to a first electrode of the light emitting element.

[0071] The first electrode of the fourth transistor is configured to access the initialization signal, the second electrode of the fourth transistor is electrically connected with the first electrode of the light emitting element, and the fourth gate of the fourth transistor is configured to access a fourth gate signal.

[0072] The second electrode of the light emitting element is configured to access a second power signal.

[0073] According to some exemplary embodiments, a projection of the third signal segment on the substrate is spaced apart from or tangent to a projection of the second gate on the substrate; and / or

[0074] A projection of the third signal segment on the substrate is spaced apart from or tangent to a projection of the third gate on the substrate; and / or

[0075] A projection of the third signal segment on the substrate is spaced apart from or tangent to a projection of the fourth gate on the substrate.

[0076] According to some exemplary embodiments, a width of the third signal segment along the first direction is greater than a width of the second signal segment along the second direction.

[0077] In still another aspect, a display substrate is provided, comprising:

[0078] A substrate is a silicon-based substrate, the substrate includes a first active region, a second active region and a third active region, a first electrode of the first active region is configured to access a data signal, a first electrode of the second active region is configured to access a first power signal, and a second electrode of the second active region is electrically connected with a first electrode of the third transistor;

[0079] A gate layer is located on the substrate and includes a first gate, a second gate and a third gate, a projection of the first gate on the substrate partially overlaps with a projection of the first active region on the substrate, a projection of the second gate on the substrate partially overlaps with a projection of the second active region on the substrate, and a projection of the third gate on the substrate partially overlaps with a projection of the third active region on the substrate, and the third gate is electrically connected with a second electrode of the first active region.

[0080] A first conductive layer is located on a side of the gate layer away from the substrate, and the first conductive layer includes a first conductive connection portion, and the first conductive connection portion is electrically connected with the first gate.

[0081] a second conductive layer located on a side of the first conductive layer away from the substrate, the second conductive layer including a second conductive connection portion, the second conductive connection portion being electrically connected with the first conductive connection portion; and

[0082] a third conductive layer located on a side of the second conductive layer away from the substrate, the third conductive layer including a first gate signal line, the first gate signal line being electrically connected with the second conductive connection portion, the first gate signal line accessing the first gate signal through the second conductive connection portion and the first conductive connection portion.

[0083] In yet another aspect, there is provided a display device comprising the display substrate as in any of the preceding aspects. BRIEF DESCRIPTION OF DRAWINGS

[0084] The features and advantages of the present disclosure will become more apparent from the detailed description of example embodiments of the present disclosure with reference to the attached drawings.

[0085] FIG. 1 is a plan view of a display substrate according to some embodiments of the present disclosure.

[0086] FIGS. 2A-2G schematically show plan views of some film layers in a display substrate according to some embodiments of the present disclosure, wherein FIG. 2A shows a combination of a substrate and a gate layer; FIG. 2B shows a combination of an active region in the substrate, the gate layer, a first insulating layer, and a first conductive layer; FIG. 2C shows a combination of the first insulating layer and the first conductive layer; FIG. 2D shows a combination of the first conductive layer, a second insulating layer, and a second conductive layer; FIG. 2E shows a combination of the second conductive layer, a third insulating layer, and a third conductive layer; FIG. 2F shows a combination of a fourth conductive layer, a fifth insulating layer, and a fifth conductive layer; and FIG. 2G shows a combination of a sixth conductive layer, a seventh insulating layer, and a seventh conductive layer.

[0087] FIG. 3 schematically shows a circuit schematic of a drive circuit in a display substrate according to some embodiments of the present disclosure.

[0088] FIG. 4A schematically shows an improved schematic of a drive circuit in a display substrate according to some embodiments of the present disclosure.

[0089] FIG. 4B schematically shows a waveform comparison schematic of a first gate signal and a second gate signal in a display substrate before and after improvement according to some embodiments of the present disclosure.

[0090] FIG. 5 schematically shows a cross-sectional view taken along AA' in FIG. 1, in which the substrate, the gate insulating layer, the gate layer, the first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer, the third insulating layer, the third conductive layer, the fourth insulating layer, the fourth conductive layer, the fifth insulating layer, the fifth conductive layer, the sixth insulating layer, the sixth conductive layer, the seventh insulating layer, and the seventh conductive layer are schematically shown.

[0091] FIG. 6 schematically shows a cross-sectional view taken along BB' in FIG. 2D of the first conductive layer to the third conductive layer in a display substrate according to some embodiments of the present disclosure.

[0092] FIGS. 7A-7C schematically show plan views of some film layers in a display substrate in a display area according to some embodiments of the present disclosure, in which FIG. 7A shows the combination of the first conductive layer, the second insulating layer, and the second conductive layer; FIG. 7B shows the combination of the substrate, the gate layer, the first insulating layer, the first conductive layer, the second insulating layer, and the second conductive layer; and FIG. 7C shows the combination of the second conductive layer, the third insulating layer, and the third conductive layer.

[0093] FIG. 8 schematically shows a cross-sectional view taken along CC' in FIG. 7C of the first conductive layer to the third conductive layer in a display substrate according to some embodiments of the present disclosure.

[0094] FIG. 9A schematically shows an enlarged view of the area Al in FIG. 2C.

[0095] FIG. 9B schematically shows an enlarged view of the area Al in FIG. 7A.

[0096] FIG. 9C schematically shows an enlarged view of the area A3 in FIG. 7C. DETAILED DESCRIPTION

[0097] In order to make the objects, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the protection scope of the present disclosure.

[0098] It should be noted that in the drawings, the size and relative size of the elements can be exaggerated for clarity and / or descriptive purposes. Thus, the size and relative size of the elements in the drawings should not be construed as being to scale. In the description and drawings, identical or similar reference signs indicate identical or similar components.

[0099] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, it can be directly on, directly connected to, or directly coupled to the other element, or intervening elements can be present. In contrast, when an element is described as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements present. Other terms of description used herein, such as "between," "directly between," "adjacent to," "directly adjacent to," or "on" can be interpreted in a like fashion. In addition, the term "connected" can refer to physical or electrical connectivity, communicative connectivity, and / or fluidic connectivity. Furthermore, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of the present disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted to include only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and XZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated items.

[0100] It should be noted that, although the terms "first," "second," etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer and / or section from another element, component, region, layer and / or section. Thus, a first element, component, region, layer and / or section discussed below could be termed a second element, component, region, layer and / or section without departing from the teachings of the present disclosure.

[0101] Spatially relative terms, such as "on", "above", "left", "right", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device described is turned over, elements described as "below" or "under" other elements or features would then be oriented "above" the other elements or features. Likewise, if devices are turned over, elements described as "above" other elements or features would then be oriented "below" the other elements or features.

[0102] In this document, the terms“substantially,”“approximately,”“near,”“about,” and other similar terms are used as terms of approximation and not as terms of degree, and they are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. Considering, for example, process variations, measurement difficulties, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system),“about” or“approximately,” as used herein includes the stated value and means a range of values determined to be acceptable by one of ordinary skill in the art to a particular value. For example,“about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0103] It should be noted that, in this document, the expression“same layer” refers to a layer structure formed by using a same film forming process to form a film layer for forming a specific pattern, and then patterning the film layer by a one-time patterning process using a same mask plate. Depending on the specific pattern, the one-time patterning process can include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. That is, the multiple elements, components, structures and / or parts located in the“same layer” are composed of the same material and formed by the same one-time patterning process, and generally, the multiple elements, components, structures and / or parts located in the“same layer” have substantially the same thickness.

[0104] It should be understood by those skilled in the art that, in this document, the expression“height” or“thickness” refers to a dimension along a surface of each film layer disposed perpendicularly to the display substrate, i.e., a dimension along the light-out direction of the display substrate, or a dimension along the normal direction of the display device, unless otherwise specified.

[0105] In this document, the expression“transistor” can be a triode, a thin-film transistor or a field effect transistor or other devices with the same characteristics. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the control pole, one of the poles is referred to as the first pole and the other is referred to as the second pole. In actual operation, when the transistor is a thin-film transistor or a field effect transistor, the first pole can be the drain and the second pole can be the source, or the first pole can be the source and the second pole can be the drain.

[0106] FIG. 1 schematically shows a plan view of a display substrate according to some embodiments of the present disclosure, where FIG. 1 only schematically shows a substrate and a driving circuit on the substrate. FIGS. 2A-2G schematically show plan views of some film layers in a display substrate according to some embodiments of the present disclosure, where FIG. 2A shows a combination of a substrate and a gate layer; FIG. 2B shows a combination of an active region in the substrate, the gate layer, a first insulating layer, and a first conductive layer; FIG. 2C shows a combination of the first insulating layer and the first conductive layer; FIG. 2D shows a combination of the first conductive layer, a second insulating layer, and a second conductive layer; FIG. 2E shows a combination of the second conductive layer, a third insulating layer, and a third conductive layer; FIG. 2F shows a combination of a fourth conductive layer, a fifth insulating layer, and a fifth conductive layer; and FIG. 2G shows a combination of a sixth conductive layer, a seventh insulating layer, and a seventh conductive layer. FIG. 3 schematically shows a circuit schematic of a driving circuit in a display substrate according to some embodiments of the present disclosure. FIG. 4A schematically shows an improved schematic of a driving circuit in a display substrate according to some embodiments of the present disclosure. FIG. 4B schematically shows a waveform comparison schematic of a first gate signal and a second gate signal in a display substrate before and after improvement according to some embodiments of the present disclosure.

[0107] Referring to FIG. 1, the display substrate includes a substrate 100 and a plurality of sub-pixels SP arranged in an array on the substrate 100, where one sub-pixel SP includes one light emitting element and a driving circuit electrically connected to the light emitting element, and the driving circuit is configured to drive the light emitting element to emit light.

[0108] Referring to FIGS. 2A and 3, the driving circuit includes at least a first transistor M1, a second transistor M2, and a third transistor M3. The first transistor M1 includes a first active region 111 and a first gate 121, where an overlapping portion of the first active region 111 and the first gate 121 is a channel region, and two ends of the first active region 111 and the first gate 121 that are not overlapping are a first electrode 111S and a second electrode 111D. The second transistor M2 includes a second active region 112 and a second gate 122, where an overlapping portion of the second active region 112 and the second gate 122 is a channel region, and two ends of the second active region 112 and the second gate 122 that are not overlapping are a first electrode 112S and a second electrode 112D. The third transistor M3 includes a third active region 113 and a third gate 123, where an overlapping portion of the third active region 113 and the third gate 123 is a channel region, and two ends of the third active region 113 and the third gate 123 that are not overlapping are a first electrode 113S and a second electrode 113D.

[0109] With reference to FIGS. 2A-3, the first electrode 111S of the first transistor M1 is electrically connected to the data line DATA and inputs a data signal, the second electrode 111D of the first transistor M1 is electrically connected to the third gate 123 of the third transistor M3, and the first gate 121 of the first transistor M1 is electrically connected to the first gate signal line GM1 and inputs a first gate signal. The first electrode 112S of the second transistor M2 is configured to input a first power supply signal Vdd, the second electrode 112D of the second transistor M2 is electrically connected to the first electrode 113S of the third transistor M3, and the second gate 122 of the second transistor M2 is electrically connected to the second gate signal line GM2 and inputs a second gate signal.

[0110] With reference to FIGS. 2A-3, the first electrode of the light emitting element EM is electrically connected to the second electrode 113D of the third transistor M3, thereby achieving electrical connection between the light emitting element EM and the driving circuit, and the second electrode of the light emitting element EM is configured to input a second power supply signal Vss.

[0111] According to some exemplary embodiments, with reference to FIGS. 2A, 2B, 2C, and 2E, the display substrate includes a plurality of first gate signal lines GM1 and a plurality of second gate signal lines GM2. The plurality of first gate signal lines GM1 extend along the first direction X and are arranged along the second direction Y, one first gate signal line GM1 is electrically connected to the gate of each of the plurality of first transistors M1 arranged in a row along the first direction X, and the first gate signal line GM1 is configured to input a first gate signal to the gate of the first transistor M1. The plurality of second gate signal lines GM2 extend along the first direction X and are arranged along the second direction Y, one second gate signal line GM2 is electrically connected to the gate of each of the plurality of second transistors M2 arranged in a row along the first direction X, and the second gate signal line GM2 is configured to input a second gate signal to the gate of the second transistor M2. In any one driving circuit and the first gate signal line and the second gate signal line electrically connected thereto, respectively, the orthogonal projection of the first gate signal line GM1 on the substrate is on the same side of the orthogonal projection of the third transistor M3 on the substrate as the orthogonal projection of the second gate signal line GM2 on the substrate.

[0112] Further, the display substrate includes at least two conductive layers, and the first gate signal line GM1 and the second gate signal line GM2 are located in different conductive layers. By arranging the first gate signal line GM1 and the second gate signal line GM2 in different conductive layers, the mutual influence between the alternating current signal in the first gate signal line GM1 and the alternating current signal in the second gate signal line GM2 is weakened, and the coupling capacitance Cpd formed between the first gate signal line GM1 and the second gate signal line GM2 is reduced, as shown in FIG. 4A. Consequently, as shown in FIG. 4B, the upper part of the arrow in FIG. 4B schematically shows the waveform diagram of the first gate signal VGM1 and the second gate signal VGM2 when the first gate signal line and the second gate signal line are located in the same conductive layer, and the part pointed by the arrow in FIG. 4B schematically shows the waveform diagram of the first gate signal VGM1 and the second gate signal VGM2 when the first gate signal line and the second gate signal line are located in different conductive layers. By comparison, it can be found that when the first gate signal line and the second gate signal line are located in different conductive layers, the signal switching speed of the first gate signal VGM1 and the second gate signal VGM2 is improved, and the effective signal width of the first gate signal VGM1 and the second gate signal VGM2 is significantly increased, thereby improving the adjustable space of the signal, and finally improving the driving capability of the driving circuit.

[0113] FIG. 5 schematically shows a cross-sectional view taken along AA' in FIG. 1, wherein the substrate, the gate insulating layer, the gate layer, the first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer, the third insulating layer, the third conductive layer, the fourth insulating layer, the fourth conductive layer, the fifth insulating layer, the fifth conductive layer, the sixth insulating layer, the sixth conductive layer, the seventh insulating layer, and the seventh conductive layer are schematically shown.

[0114] According to some exemplary embodiments, as shown in FIGS. 2B, 2C, and 5, the display substrate includes a first conductive layer MT1 located on the side of each transistor away from the substrate 100. The first conductive layer MT1 includes a second gate signal line GM2 electrically connected to the second gate 122 of each of the plurality of second transistors M2 arranged in a row along the first direction X. The second gate signal line GM2 is located on the side of the third transistor M3 along the second direction Y, and the orthogonal projection of the second gate signal line GM2 on the substrate partially overlaps the orthogonal projection of the second transistor M2 on the substrate. In one driving circuit and the second gate signal line GM2 electrically connected to the driving circuit, the second gate signal line GM2 and the second transistor M2 are located on the same side of the third transistor M3 along the second direction Y.

[0115] According to some exemplary embodiments, referring to FIG. 2E, FIG. 5, the display substrate further comprises a third conductive layer MT3, which is located on the side of the first conductive layer MT1 away from the substrate 100. Referring to FIG. 2E, the third conductive layer MT3 comprises a first gate signal line GM1, which is electrically connected to the first gate 121 of each of the plurality of first transistors M1 arranged in a row along the first direction X, in combination with FIG. 2B. The first gate signal line GM1 is located on one side of the third transistor M3 along the second direction Y, and the orthogonal projection of the first gate signal line GM1 on the substrate partially overlaps the orthogonal projection of the first transistor M1 on the substrate. In one driving circuit and the first gate signal line GM1 electrically connected to the driving circuit, the first gate signal line GM1 is located on the same side of the third transistor M3 along the second direction Y as the first transistor M1.

[0116] According to some exemplary embodiments, referring to FIG. 2A, in one driving circuit, the first transistor M1 and the second transistor M2 are located on the same side of the third transistor M3 along the second direction Y, in combination with FIG. 2A, FIG. 2B and FIG. 2E, in one driving circuit and the first gate signal line GM1 and the second gate signal line GM2 electrically connected to the driving circuit, the first gate signal line GM1 and the second gate signal line GM2 are located on the same side of the third transistor M3 along the second direction Y in the driving circuit.

[0117] According to some exemplary embodiments, referring to FIG. 2A, the first active region 111 has a shape of an elongated rectangle extending along the second direction Y, and the orthogonal projections of the first pole 111S and the second pole 111D of the first active region 111 on the substrate are respectively located on both sides of the orthogonal projection of the first gate 121 on the substrate along the second direction Y. The second active region 112 has a shape of an elongated rectangle extending along the second direction Y, and the orthogonal projections of the first pole 112S and the second pole 112D of the second active region 112 on the substrate are respectively located on both sides of the orthogonal projection of the second gate 122 on the substrate along the second direction Y. The third active region 113 has a shape of an elongated rectangle extending along the second direction Y, and the orthogonal projections of the first pole 113S and the second pole 113D of the third active region 113 on the substrate are respectively located on both sides of the orthogonal projection of the third gate 123 on the substrate along the second direction Y.

[0118] According to some exemplary embodiments, referring to FIG. 2A, in one driving circuit, the second pole 112D of the second active region 112 and the first pole 113S of the third active region 113 are directly connected, and the second active region 112 and the third active region 113 are connected as an integral structure.

[0119] According to some exemplary embodiments, referring to FIG. 2A, in two driving circuits adjacent in the second direction Y, two first active regions 111 are connected in one body, i.e., the first pole 111S of one first active region 111 is directly connected with the first pole 111S of another first active region 111.

[0120] The "one body" in the embodiments of the present disclosure refers to structures connected with each other formed by the same deposition process and patterned by the same patterning process, and the materials thereof can be the same or different.

[0121] The transistors used in the embodiments of the present disclosure can all be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the embodiments of the present disclosure are described by taking metal-oxide semiconductor field effect transistors as an example. The source and drain of the transistor used herein can be symmetrical in structure, so that the source and drain can be indistinguishable in structure. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one pole is directly described as the first pole and the other pole is directly described as the second pole. In addition, the transistors can be divided into N-type and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltage), and the off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltage); when the transistor is an N-type transistor, the on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltage), and the off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltage).

[0122] The light emitting element used in the embodiments of the present disclosure can be an organic light emitting diode (OLED). For example, the light emitting element can be an OLED with a top emission structure, and can emit red light, green light, blue light or white light, etc. For example, the light emitting element is a Micro OLED. The embodiments of the present disclosure do not limit the specific structure of the light emitting element. For example, the first electrode of the light emitting element is the anode of the OLED, and the second electrode is the cathode of the OLED, i.e., the pixel circuit is a common cathode structure. However, the embodiments of the present disclosure do not limit this, and according to the change of the circuit structure, the pixel circuit can also be a common anode structure.

[0123] The display substrate employed in the embodiments of the present disclosure can employ a rigid substrate such as a glass substrate, a silicon substrate, etc., or can be formed of a flexible material having excellent heat resistance and durability such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), cellulose triacetate (TAC), cyclic olefin polymer (COP), and cyclic olefin copolymer (COC), etc. The embodiments of the present disclosure are described by way of example with a silicon substrate, i.e., the pixel structure is prepared on a silicon substrate, however, the embodiments of the present disclosure are not limited thereto.

[0124] For example, the pixel circuit includes a complementary metal-oxide-semiconductor circuit (CMOS circuit), i.e., the pixel circuit is prepared on a single-crystal silicon substrate. Thanks to mature CMOS integrated circuit technology, a silicon-based process can achieve high precision (e.g., PPI can reach 6500 or even more than ten thousand).

[0125] According to some exemplary embodiments, referring to FIG. 5, the substrate 100 is a silicon substrate, and the active regions AA of the transistors in the pixel circuit are located in the substrate 100, i.e., the first active region, the second active region, and the third active region are located in the substrate. FIG. 5 schematically shows the third active region 113 located in the substrate 100.

[0126] According to some exemplary embodiments, referring to FIG. 5, the substrate 100 further has a gate insulating layer 231 and a gate layer GT located on the side of the gate insulating layer 231 away from the substrate 100. In combination with FIG. 2A, the gate layer GT includes the first gate 121, the second gate 122, and the third gate 123. The orthogonal projection of the first gate 121 on the substrate partially overlaps the orthogonal projection of the first active region 111 on the substrate, the orthogonal projection of the second gate 122 on the substrate partially overlaps the orthogonal projection of the second active region 112 on the substrate, and the orthogonal projection of the third gate 123 on the substrate partially overlaps the orthogonal projection of the third active region 113 on the substrate.

[0127] According to some exemplary embodiments, referring to FIG. 5, the at least two conductive layers further include a second conductive layer MT2 located between the first conductive layer MT1 and the third conductive layer MT3. For example, the second conductive layer MT2 includes a shielding trace, and the orthogonal projection of the shielding trace on the substrate at least partially overlaps the orthogonal projection of at least one of the first gate signal line and the second gate signal line on the substrate. By arranging the shielding trace between the first gate signal line and the second gate signal line, the coupling capacitance formed between the first gate signal line and the second gate signal line can be further reduced.

[0128] According to some exemplary embodiments, referring to FIG. 2C and FIG. 2D in combination, the orthogonal projection of the shielding trace ST on the substrate substrate partially overlaps with the orthogonal projection of the second gate signal line GM2 on the substrate substrate. The second gate signal line GM2 comprises a second gate signal main trace GM2a extending along the first direction X and a plurality of connection portions GM2b connected to the second gate signal main trace GM2a, the connection portions GM2b are in the shape of long rectangular extending along the second direction Y, and the plurality of connection portions GM2b are respectively electrically connected to the plurality of second gate electrodes. The orthogonal projection of the shielding trace ST on the substrate substrate covers the orthogonal projection of the second gate signal main trace GM2a on the substrate substrate.

[0129] According to some exemplary embodiments, referring to FIG. 2D and FIG. 2E in combination, the orthogonal projection of the shielding trace ST on the substrate substrate is spaced apart from the orthogonal projection of the first gate signal line GM1 on the substrate substrate. That is, the orthogonal projection of the shielding trace ST on the substrate substrate does not overlap with the orthogonal projection of the first gate signal line GM1 on the substrate substrate.

[0130] According to some exemplary embodiments, referring to FIG. 2B and FIG. 2E in combination, the orthogonal projection of the second gate signal line GM2 on the substrate substrate is spaced apart from the orthogonal projection of the first gate signal line GM1 on the substrate substrate, that is, the orthogonal projection of the second gate signal line GM2 on the substrate substrate does not overlap with the orthogonal projection of the first gate signal line GM1 on the substrate substrate. Exemplarily, among one driving circuit and the second gate signal line GM2 and the first gate signal line GM1 electrically connected to the driving circuit respectively, the second gate signal line GM2 is closer to the third transistor M3 than the first gate signal line GM1.

[0131] According to some exemplary embodiments, referring to FIG. 2B and FIG. 2C in combination, the first conductive layer has a first conductive connection portion 141, and the first conductive connection portion 141 is electrically connected to the first gate electrode 121. Referring to FIG. 2D and FIG. 2C in combination, the second conductive layer has a second conductive connection portion 142, and the second conductive connection portion 142 is electrically connected to the first conductive connection portion 141. Referring to FIG. 2E and FIG. 2D in combination, the first gate signal line GM1 is electrically connected to the second conductive connection portion 142. That is, the first gate signal line GM1 is electrically connected to the first gate electrode 121 through the second conductive connection portion 142 and the first conductive connection portion 141 in sequence, so as to realize the transfer of the first gate signal to the first gate electrode 121.

[0132] According to some exemplary embodiments, referring to FIG. 5, the first insulating layer 221 is arranged between the gate layer GT and the first conductive layer MT1, the second insulating layer 222 is arranged between the first conductive layer MT1 and the second conductive layer MT2, and the third insulating layer 223 is arranged between the second conductive layer MT2 and the third conductive layer MT3. Referring to FIG. 2B and FIG. 2C, the first insulating layer has a first via V01, and the first conductive connection 141 is electrically connected to the first gate 121 through the first via V01. Referring to FIG. 2D, the second insulating layer has a twenty-first via V21, and the second conductive connection 142 is electrically connected to the first conductive connection 141 through the twenty-first via V21. Referring to FIG. 2E, the third insulating layer has a thirty-first via V31, and the first gate signal line GM1 is electrically connected to the second conductive connection 142 through the thirty-first via V31.

[0133] According to some exemplary embodiments, the via in each insulating layer can be conductive by filling with additional conductive material (such as tungsten).

[0134] According to some exemplary embodiments, referring to FIG. 2A and FIG. 3, the driving circuit further includes a fourth transistor M4, the first pole 114S of the fourth transistor M4 is configured to access the initialization signal Vinit, the second pole 114D of the fourth transistor M4 is electrically connected to the first electrode of the light emitting element EM, and the gate 124 of the fourth transistor M4 is electrically connected to the fourth gate signal line GM4 and accesses the fourth gate signal.

[0135] According to some exemplary embodiments, referring to FIG. 2A, the fourth transistor M4 includes a fourth active region 114 in the substrate substrate and a fourth gate 124 in the gate layer, and the orthogonal projection of the fourth gate 124 on the substrate substrate partially overlaps with the orthogonal projection of the fourth active region 114 on the substrate substrate. The part of the fourth active region 114 overlapping with the fourth gate 124 is the channel region, and the two ends of the fourth active region 114 not overlapping with the fourth gate 124 are the first pole 114S and the second pole 114D respectively.

[0136] According to some exemplary embodiments, referring to FIG. 2A, the shape of the fourth active region 114 is a long rectangular shape extending along the first direction X, and the orthogonal projections of the first pole 114S and the second pole 114D of the fourth active region 114 on the substrate substrate are respectively located on both sides of the orthogonal projection of the fourth gate 124 on the substrate substrate along the first direction X.

[0137] According to some exemplary embodiments, referring to FIG. 2A, in two driving circuits adjacent along the first direction X, the two fourth active regions 114 are connected as one structure, that is, the first pole 114S of one fourth active region 114 is directly connected to the first pole 114S of another fourth active region 114.

[0138] According to some exemplary embodiments, referring to FIG. 2A, in one drive circuit, the orthographic projections of the fourth transistor M4 and the first transistor M1 on the substrate are respectively located on two sides of the orthographic projection of the third transistor M3 on the substrate along the second direction Y.

[0139] According to some exemplary embodiments, the display substrate further comprises an initialization signal input structure for inputting an initialization signal to the first electrode of the fourth transistor. Referring to FIG. 2C, the initialization signal input structure 300 at least comprises a first initialization signal part 310 in the first conductive layer, the first initialization signal part 310 comprising a plurality of first initialization signal lines 311 extending along the first direction X and arranged along the second direction Y, the first initialization signal lines 311 being used for transmitting the initialization signal. Referring to FIG. 2C and FIG. 2B, in at least one drive circuit and the first initialization signal line 311 and the second gate signal line GM2 electrically connected to the drive circuit respectively, the orthographic projection of the first initialization signal line 311 on the substrate and the orthographic projection of the second gate signal line GM2 on the substrate are respectively located on two sides of the orthographic projection of the third transistor M3 on the substrate along the second direction Y.

[0140] According to some exemplary embodiments, referring to FIG. 2C, the first initialization signal part 310 further comprises at least one first signal segment 312 electrically connected to the first initialization signal line 311, the first signal segment 312 extending along the second direction Y, one end of the first signal segment 312 being electrically connected to the first initialization signal line 311 and the other end being spaced apart from the adjacent second gate signal line GM2. Referring to FIG. 2C and FIG. 2B, the orthographic projection of the first signal segment 312 on the substrate is located between the orthographic projections of the two third transistors M3 adjacent along the first direction X on the substrate. The first signal segment 312 serves as a shielding structure between the two drive circuits adjacent along the first direction X, reduces the signal crosstalk between the two drive circuits adjacent along the first direction X, and further improves the driving capability of the drive circuit.

[0141] According to some exemplary embodiments, referring to FIG. 2B and FIG. 2C, the orthographic projections of the two third transistors M3 adjacent along the first direction X on the substrate are located between the orthographic projections of the two first signal segments 312 adjacent along the first direction X on the substrate. That is, among the three third transistors M3 adjacent along the first direction X, one first signal segment 312 is arranged between the third transistor M3 in the middle and the third transistor M3 on one side; no first signal segment 312 is arranged between the third transistor M3 in the middle and the third transistor M3 on the other side, and this space is used for arranging other functional structures, which will be described later.

[0142] According to some exemplary embodiments, referring to FIGS. 2B and 2C, the first initialization signal line 311 is connected with a plurality of first signal segments 312 on one side along the second direction Y, and is also connected with a plurality of first signal segments 312 on the other side along the second direction Y, and the plurality of first signal segments 312 connected on one side and the plurality of first signal segments 312 connected on the other side are oppositely arranged along the second direction Y, respectively. Two second gate signal lines GM2 are arranged between two adjacent initialization signal lines 311, and thus two first signal segments 312 connected on two adjacent initialization signal lines 311 are arranged at intervals, respectively.

[0143] According to some exemplary embodiments, the display substrate further comprises a fourth gate signal line, the fourth gate signal line is electrically connected with the fourth gate electrode for inputting a fourth gate signal to the fourth gate electrode. For example, referring to FIG. 2E, the fourth gate signal line GM4 is located in the third conductive layer MT3, and the fourth gate signal line GM4 extends along the first direction X. Referring to FIGS. 2E and 2B, the fourth gate signal line GM4 is electrically connected with the plurality of fourth gate electrodes 124 arranged along the first direction X, respectively. Referring to FIGS. 2E and 2C, the orthogonal projection of the fourth gate signal line GM4 on the substrate is at least partially overlapped with the orthogonal projection of the first initialization signal line 311 on the substrate.

[0144] According to some exemplary embodiments, referring to FIG. 3, the driving circuit further comprises a first capacitor C1 and a second capacitor C2. The first end of the first capacitor C1 is electrically connected with the gate electrode of the third transistor M3, and the second end of the first capacitor C1 is electrically connected with the first electrode of the third transistor M3. The first end of the second capacitor C2 is electrically connected with the second end of the first capacitor C1, and the second end of the second capacitor C2 is connected with the first power signal.

[0145] According to some exemplary embodiments, the driving process of the driving circuit can include four stages, i.e., an initialization stage, a threshold voltage reading stage, a data writing stage, and a light emitting stage. The driving process will be described in detail below in combination with FIG. 3.

[0146] In the initialization stage, the data line DATA provides a reset voltage Vofs, the first gate signal line GM1 controls the first transistor M1 to be turned on, and the reset voltage Vofs is written to the gate electrode of the third transistor M3, i.e., the first node G. At the same time, the second gate signal line GM2 controls the second transistor M2 to be turned on, and the first power signal Vdd is written to the first electrode of the third transistor M3, i.e., the second node S. Since the gate-source voltage Vgs of the third transistor M3 (i.e., Vofs-Vdd) is less than the threshold voltage Vth of the third transistor M3, the third transistor M3 is in a turned-on state at this time. The fourth gate signal line GM4 controls the fourth transistor M4 to be turned on, and the initialization signal Vinit is written to the first electrode of the light emitting element EM.

[0147] In the threshold voltage reading stage, the first gate signal line GM1 controls the first transistor M1 to be off, and the first node G is maintained floating; then the second gate signal line GM2 controls the second transistor M2 to be off; and the fourth gate signal line GM4 controls the fourth transistor M4 to be on. When entering the threshold voltage reading stage, the second node S can be discharged based on the path formed by the third transistor M3 and the fourth transistor M4, so that the voltage at the second node S decreases, and the voltage at the first node G also decreases due to the bootstrap effect of the second capacitor C2, but the gate-source voltage Vgs of the third transistor M3 (the difference between the voltage at the first node G and the voltage at the second node S, which is also the voltage difference across the first capacitor C1) as a whole presents an increasing trend, and when the gate-source voltage Vgs of the driving transistor is equal to the threshold voltage Vth of the driving transistor, the driving transistor is in the off state.

[0148] In the data writing stage, the first gate signal line GM1 controls the first transistor M1 to be on, the second gate signal line GM2 controls the second transistor M2 to be off, and the fourth gate signal line GM4 controls the fourth transistor M4 to be on. The voltage at the second node S is still in a floating state, and the data voltage Vdata is written to the gate of the third transistor M3, i.e., the first node G, through the first transistor M1, and the voltage at the first node N1 becomes Vdata. At this time, due to the bootstrap effect of the first capacitor C1 and the capacitive voltage division effect of the first capacitor C1 and the second capacitor C2, the voltage at the second node S changes. The voltage at the second node S is determined by Vdata and Vth.

[0149] In the light emitting stage, the first gate signal line GM1 controls the first transistor M1 to be off, then the second gate signal line GM2 controls the second transistor M2 to be on, and the Vdd voltage is written to the second node S through the second transistor M2, and at the same time, the voltage at the first node G is also pulled up due to the bootstrap effect of the first capacitor C1. At this time, due to the effect of the first capacitor C1, the gate-source voltage Vgs of the third transistor M3 maintains the previous state. Then, the fourth gate signal line GM4 controls the fourth transistor M4 to be off, and the light emitting element EM emits light.

[0150] Of course, in addition to the above exemplary driving process, corresponding adjustments can also be made according to the actual working scene of the pixel circuit, and the present disclosure embodiments do not limit this.

[0151] According to some exemplary embodiments, the first transistor, the second transistor, the third transistor, and the fourth transistor are independently selected from a P-channel metal-oxide-semiconductor field-effect transistor (PMOS) and an N-channel metal-oxide-semiconductor field-effect transistor (NMOS). For example, the first transistor, the second transistor, and the third transistor are PMOS, and the fourth transistor is NMOS.

[0152] According to some exemplary embodiments, in the driving circuit, the first capacitor and the second capacitor are formed by the first capacitor electrode, the second capacitor electrode, the third capacitor electrode, the fourth capacitor electrode, the fifth capacitor electrode and the third gate of the third transistor. Referring to FIG. 5, the display substrate further includes a fourth insulating layer 224 located on the side of the third conductive layer MT3 away from the substrate 100, a fourth conductive layer MT4 located on the side of the fourth insulating layer 224 away from the substrate 100, a fifth insulating layer 225 located on the side of the fourth conductive layer MT4 away from the substrate 100, a fifth conductive layer MT5 located on the side of the fifth insulating layer 225 away from the substrate 100, a sixth insulating layer 226 located on the side of the fifth conductive layer MT5 away from the substrate 100, a sixth conductive layer MT6 located on the side of the sixth insulating layer 226 away from the substrate 100, a seventh insulating layer 227 located on the side of the sixth conductive layer MT6 away from the substrate 100, and a seventh conductive layer MT7 located on the side of the seventh insulating layer 227 away from the substrate 100.

[0153] According to some exemplary embodiments, referring to FIG. 5, the first capacitor electrode 131 is located on the second conductive layer MT2, the second capacitor electrode 132 is located on the third conductive layer MT3, the third capacitor electrode 133 is located on the fourth conductive layer MT4, the fourth capacitor electrode 134 is located on the fifth conductive layer MT5, and the fifth capacitor electrode 135 is located on the sixth conductive layer MT6. The first gate 123 is electrically connected to the second capacitor electrode 132, and the electrically connected first gate 123 and second capacitor electrode 132 serve as the first pole of the first capacitor; the first capacitor electrode 131 is electrically connected to the fourth capacitor electrode 134, the fourth capacitor electrode 134 is electrically connected to the third capacitor electrode 133, and the electrically connected first capacitor electrode 131, third capacitor electrode 133 and fourth capacitor electrode 134 serve as the second pole of the first capacitor and also as the first pole of the second capacitor; the fifth capacitor electrode 135 and the sixth capacitor electrode 136 serve as the second pole of the second capacitor, the fifth capacitor electrode 135 is electrically connected to the third power signal part 430, and the first power signal Vdd is input into the fifth capacitor electrode 135.

[0154] According to some exemplary embodiments, referring to FIG. 5, a via V is disposed in each of the insulating layers, and the via V is filled with a conductive material such as tungsten, for example. The first capacitor electrode 131 is electrically connected to the third active region 113 through the via V in the second insulating layer 222, the connection structure in the first conductive layer M1, and the via V in the first insulating layer 221, in sequence. The second capacitor electrode 132 is electrically connected to the third gate 123 through the via V in the third insulating layer 223, the via V in the second insulating layer 222, the connection structure in the first conductive layer M1, and the via V in the first insulating layer 221, in sequence. The fourth capacitor electrode 134 is electrically connected to the first capacitor electrode 131 through the via V in the fifth insulating layer 225 and the fourth insulating layer 224, the connection structure in the third conductive layer M3, and the via V in the third insulating layer 223. The fourth capacitor electrode 134 is electrically connected to the third capacitor electrode 133 through the via V in the fifth insulating layer 225. The third power signal part 430 is electrically connected to the fifth capacitor electrode 135 through the via V in the seventh insulating layer 227.

[0155] According to some exemplary embodiments, the shielding trace ST is used to transmit the first power signal Vdd, and the shielding trace ST is electrically connected to the first electrode of the second transistor M2, that is, the shielding trace functions as a shielding structure to reduce signal interference between the first gate signal line and the second gate signal line, and the shielding trace is also multiplexed as a signal trace for inputting the first power signal to the second transistor, which is conducive to reducing the size of the pixel and improving the resolution of the display substrate.

[0156] According to some exemplary embodiments, the display substrate includes a first power signal input structure, which is electrically connected to the first electrode of the second transistor and inputs the first power signal to the first electrode of the second transistor. Referring to FIG. 2D, the first power signal input structure 400 includes a first power signal part 410 in the second conductive layer MT2, and the first power signal part 410 includes a plurality of first power signal lines 411 extending along the first direction X and arranged along the second direction Y. In combination with FIG. 2D and FIG. 2C, the orthogonal projection of the first power signal line 411 on the substrate is at least partially overlapped with the orthogonal projection of the second gate signal line GM2 on the substrate. Here, the first power signal line 411 is multiplexed as a shielding trace ST in addition to being used to transmit the first power signal.

[0157] According to some exemplary embodiments, referring to FIG. 2D, the first power signal part 410 further comprises a plurality of second power signal lines 412 extending along the first direction X and arranged along the second direction Y, and a plurality of third power signal lines 413 extending along the second direction Y and arranged along the first direction X, the plurality of third power signal lines 413 and the plurality of first power signal lines 411 are alternately connected, and the plurality of third power signal lines 413 and the plurality of second power signal lines 412 are alternately connected, so that the first power signal part 410 has a grid shape, which is conducive to improving the uniformity of the distribution of the first power signal in the first power signal part 410.

[0158] According to some exemplary embodiments, referring to FIG. 2D and FIG. 2C, the orthogonal projection of the second power signal line 412 on the substrate is at least partially overlapped with the orthogonal projection of the first initialization signal line 311 on the substrate.

[0159] According to some exemplary embodiments, referring to FIG. 2D and FIG. 2B, the orthogonal projection of the third power signal line 413 on the substrate is located between the orthogonal projections of two adjacent third transistors M3 along the first direction X on the substrate, and a column of third transistors is arranged between the two adjacent third power signal lines 413, the column of third transistors comprising a plurality of third transistors M3 arranged along the second direction.

[0160] According to some exemplary embodiments, referring to FIG. 2E, the first power signal input structure comprises a second power signal part 420 of the third conductive layer, the second power signal part 420 comprising a plurality of fourth power signal lines 421 extending along the first direction X and arranged along the second direction Y, in combination with FIG. 2D and FIG. 2E, the orthogonal projection of the fourth power signal line 421 on the substrate is partially overlapped with the orthogonal projection of the first power signal line 411 on the substrate.

[0161] According to some exemplary embodiments, referring to FIG. 2E, the second power signal part 420 further comprises a plurality of fifth power signal segments 422 connected to the fourth power signal line 421, the fifth power signal segment 422 extending along the second direction Y, one end of the fifth power signal segment 422 being connected to the fourth power signal line 421 and extending away from the adjacent first gate signal line GM1, and the other end of the fifth power signal segment 422 being spaced apart from the fourth gate signal line GM4. In combination with FIG. 2E and FIG. 2D, the orthogonal projection of the fifth power signal segment 422 on the substrate is at least partially overlapped with the orthogonal projection of the third power signal line 413 on the substrate, and the fifth power signal segment 422 is electrically connected with the third power signal line 413, thereby realizing the electrical connection between the second power signal part and the first power signal part.

[0162] FIG. 6 schematically shows a cross-sectional view of the first conductive layer to the third conductive layer in the display substrate along BB' in FIG. 2D, according to some embodiments of the present disclosure.

[0163] Referring to FIG. 6, the first conductive layer MT1 has the second gate signal line GM2 at this position. The second conductive layer MT2 has the first power signal line 411 at this position, and the orthogonal projection of the first power signal line 411 on the substrate substrate overlaps with the orthogonal projection of the second gate signal line GM2 on the substrate substrate, and the first power signal line 411 is substantially above the second gate signal line GM2 away from the substrate substrate. The third conductive layer MT3 has the fourth power signal line 421 and the first gate signal line GM1 at this position, the orthogonal projection of the fourth power signal line 421 on the substrate substrate overlaps with the orthogonal projection of the first power signal line 411 on the substrate substrate, and the fourth power signal line 421 is substantially above the first power signal line 411 away from the substrate substrate. The orthogonal projection of the first gate signal line GM1 on the substrate substrate does not overlap with the orthogonal projection of the first power signal line 411 and the second gate signal line GM2 on the substrate substrate.

[0164] Among the different signal lines present at this position, the second gate signal line GM2 and the first gate signal line GM1 are located in different conductive layers, and in the direction perpendicular to the substrate substrate, the first power signal line 411 serving as a signal shield is further provided between the second gate signal line GM2 and the first gate signal line GM1. Therefore, the coupling capacitance generated between the second gate signal line GM2 and the first gate signal line GM1 is very small. In addition, the coupling capacitance Cpd2 will be generated between the second gate signal line GM2 and the first power signal line 411, and the coupling capacitance Cpd1 will be generated between the first gate signal line GM1 and the first power signal line 411 and the fourth power signal line 421, respectively. However, since the first power signal transmitted in the first power signal line 411 and the fourth power signal line 421 is a constant voltage signal, i.e., the first power signal line 411 and the fourth power signal line 421 are direct current signal lines, the coupling capacitance Cpd2 between the second gate signal line GM2 and the first gate signal line GM1 and the coupling capacitance Cpd1 have small capacitance values, which have no obvious influence on the driving effect of the driving circuit.

[0165] According to some exemplary embodiments, the shielding trace is used to transmit the initialization signal, and the shielding trace is electrically connected to the first electrode of the fourth transistor, i.e., the shielding trace serves as a shielding structure to reduce signal interference between the first gate signal line and the second gate signal line, and the shielding trace is also multiplexed as a signal trace for inputting the initialization signal to the fourth transistor, which is beneficial to reducing the pixel size and improving the resolution of the display substrate.

[0166] FIGS. 7A-7C schematically show plan views of some film layers in a display substrate according to some embodiments of the present disclosure, where FIG. 7A shows a combination of a first conductive layer, a second insulating layer, and a second conductive layer; FIG. 7B shows a combination of a substrate, a gate layer, a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer; and FIG. 7C shows a combination of a second conductive layer, a third insulating layer, and a third conductive layer.

[0167] According to some example embodiments, referring to FIG. 7A, the initialization signal input structure 300 further includes a second initialization signal portion 320 located in the second conductive layer, the second initialization signal portion 320 includes a plurality of second initialization signal lines 321 extending along the first direction X and arranged along the second direction Y, in combination with reference to FIG. 7A and FIG. 2C, the orthogonal projection of the second initialization signal lines 321 on the substrate overlaps at least partially with the orthogonal projection of the second gate signal lines GM2 on the substrate. Here, in addition to being used to transmit initialization signals, the second initialization signal lines 321 are also multiplexed as shielding traces ST.

[0168] According to some example embodiments, the display substrate includes a first power signal input structure electrically connected to and inputting a first power signal to the first electrode of the second transistor. Referring to FIG. 7A, the first power signal input structure 400 at least includes a first power signal portion 410 located in the second conductive layer, the first power signal portion 410 includes a plurality of third power signal lines 413 arranged along the first direction X and extending along the second direction Y. In combination with reference to FIG. 7A and FIG. 7B, the orthogonal projection of the third power signal lines 413 on the substrate is located between the orthogonal projections of two adjacent third transistors M3 on the substrate along the first direction X. The third power signal lines 413 continuously extend from one side of the substrate along the second direction to the other side of the substrate along the second direction, and the plurality of third power signal lines 413 divide the second initialization signal lines 321 into a plurality of signal segments. That is, the second initialization signal lines 321 include a plurality of second signal segments 3211 arranged at intervals along the first direction X, and the second signal segments 3211 are located between and spaced apart from the two adjacent third power signal lines 413.

[0169] According to some exemplary embodiments, with reference to FIGS. 7A and 7B, the orthographic projection of two third transistors M3 adjacent along the first direction X on the substrate is located between the orthographic projection of two adjacent third power signal lines 413 on the substrate. That is, among three third transistors M3 adjacent along the first direction X, one third transistor M3 located in the middle is provided with one third power signal line 413 between the third transistors M3 located on one side; one third transistor M3 located in the middle is not provided with a third power signal line 413 between the third transistors M3 located on the other side, and the space is used to arrange other functional structures, which will be described later.

[0170] According to some exemplary embodiments, with reference to FIG. 7A, the second initialization signal part 320 further includes a plurality of third initialization signal lines 322 extending along the second direction Y and arranged along the first direction X, and the plurality of third initialization signal lines 322 and the plurality of third power signal lines 413 are alternately arranged along the first direction X. With reference to FIGS. 7A and 2C, the orthographic projection of the third initialization signal line 322 on the substrate and the orthographic projection of the plurality of first signal segments 312 arranged along the second direction Y on the substrate at least partially overlap, respectively, and two first signal segments 312 adjacent and spaced apart along the second direction Y are electrically connected by the third initialization signal line 322. The second initialization signal part 320 and the first initialization signal part 310 are electrically connected to form a grid-shaped trace, thereby reducing the voltage drop (IR Drop) generated in the transmission process of the initialization signal, improving the distribution uniformity of the initialization signal, and further improving the display uniformity of the display substrate.

[0171] According to some exemplary embodiments, with reference to FIG. 7A, the first power signal part 410 further includes a plurality of second power signal lines 412 arranged along the second direction Y and extending along the first direction X. With reference to FIGS. 7A and 2C, the orthographic projection of the second power signal line 412 on the substrate and the orthographic projection of the first initialization signal line 311 on the substrate at least partially overlap. The second power signal line 412 continuously extends from one side of the substrate along the first direction X to the other side along the first direction, and the plurality of second power signal lines 412 divides the third initialization signal line 322 into a plurality of signal segments. That is, the third initialization signal line 322 includes a plurality of third signal segments 3221 arranged at intervals along the second direction Y, and the third signal segment 3221 is located between and spaced apart from two adjacent second power signal lines 412. With reference to FIGS. 7A and 2C, the orthographic projection of the third signal segment 3221 on the substrate and the orthographic projection of two first signal segments 312 adjacent and spaced apart along the second direction Y on the substrate partially overlap, respectively, and two first signal segments 312 adjacent and spaced apart along the second direction are electrically connected by the third signal segment 3221.

[0172] According to some exemplary embodiments, referring to FIG. 7A, one third signal segment 3221 is connected with two second signal segments 3211 spaced along the second direction Y as an integral structure, constituting a signal sub-portion 320a. The plurality of second power signal lines 412 and the plurality of third power signal lines 413 in the first power signal portion 410 are staggered to constitute a grid structure, and the first power signal portion 410 includes a plurality of hollow portions 410x, and the plurality of signal sub-portions 320a are respectively located in the plurality of hollow portions 410x of the first power signal portion 410.

[0173] According to some exemplary embodiments, referring to FIG. 7A, the plurality of signal sub-portions 320a spaced along the first direction X are alternately arranged with the plurality of third power signal lines 413 along the first direction X; and the plurality of signal sub-portions 320a spaced along the second direction Y are alternately arranged with the plurality of second power signal lines 412 along the second direction Y.

[0174] According to some exemplary embodiments, referring to FIG. 7A and FIG. 7B, the orthogonal projection of the first gate 121 of the first transistor M1 on the substrate substrate partially overlaps the orthogonal projection of the second initialization signal portion 320 on the substrate substrate, and in at least two first transistors M1, the overlapping area of the orthogonal projection of the first gate 121 of one first transistor M1 on the substrate substrate and the orthogonal projection of the second initialization signal portion 320 on the substrate substrate is substantially equal to the overlapping area of the orthogonal projection of the first gate 121 of another first transistor M1 on the substrate substrate and the orthogonal projection of the second initialization signal portion 320 on the substrate substrate. In this way, the second initialization signal portion 320 produces consistent effects on different first gates 121, thereby improving display brightness uniformity. In addition, the first transistor M1 is a P-type transistor, and the initialization signal transmitted by the second initialization signal portion 320 is a direct current low voltage signal. The overlapping arrangement of the second initialization signal portion 320 and the first gate 121 is conducive to stabilizing the first gate signal in the first gate 121.

[0175] It should be understood that, due to factors such as layout process precision, the overlapping area of the orthogonal projection of the first gate 121 of one first transistor M1 on the substrate with the orthogonal projection of the second initialization signal part 320 on the substrate and the overlapping area of the orthogonal projection of the first gate 121 of another first transistor M1 on the substrate with the orthogonal projection of the second initialization signal part 320 on the substrate are difficult to be completely equal. The overlapping area of the orthogonal projection of the first gate 121 of one first transistor M1 on the substrate with the orthogonal projection of the second initialization signal part 320 on the substrate is S1, and the overlapping area of the orthogonal projection of the first gate 121 of another first transistor M1 on the substrate with the orthogonal projection of the second initialization signal part 320 on the substrate is S2. It should be understood that 0.9*S2≤S1≤1.1*S2.

[0176] According to some exemplary embodiments, in combination with reference to FIGS. 7A and 7B, the second signal segment 3211 intersects with the third initialization signal line 322, and the intersecting second signal segment 3211 and the third initialization signal line 322 are connected as an integral structure. The orthogonal projection of the intersecting second signal segment 3211 and the third initialization signal line 322 on the substrate and the orthogonal projection of the first gates 121 of two first transistors M1 adjacent along the first direction X on the substrate respectively partially overlap. For example, the orthogonal projection of the first gate 121 of one first transistor M1 on the substrate and the orthogonal projection of the third initialization signal line 322 on the substrate partially overlap, and the orthogonal projection of the first gate 121 of the first transistor M1 on the substrate and the orthogonal projection of the second signal segment 3211 on the substrate partially overlap; the orthogonal projection of the first gate 121 of another first transistor M1 on the substrate and the orthogonal projection of the third initialization signal line 322 on the substrate are spaced apart, and the orthogonal projection of the first gate 121 of the first transistor M1 on the substrate and the orthogonal projection of the second signal segment 3211 on the substrate partially overlap. The overlapping area S3 of the orthogonal projection of the first gate 121 of one first transistor M1 on the substrate with the orthogonal projection of the intersecting second signal segment 3211 on the substrate and the overlapping area S4 of the orthogonal projection of the first gate 121 on the substrate and the orthogonal projection of the third initialization signal line 322 on the substrate (S3+S4=S2) are substantially equal to the overlapping area S1 of the orthogonal projection of the first gate 121 of another first transistor M1 on the substrate with the orthogonal projection of the second signal segment 3211 on the substrate.

[0177] According to some exemplary embodiments, with reference to FIGS. 7A and 7B, the second signal segment 3211 includes a first portion 32111 and a second portion 32112 located on two sides of the third initialization signal line 322 along the first direction X. Among the two first transistors adjacent along the first direction, the first gate 121 of one first transistor M1 has a projection on the substrate substrate partially overlapping the first portion 32111 of one second signal segment 3211 and the projection on the substrate substrate of one third initialization signal line 322, and the first gate 121 of the other first transistor M1 has a projection on the substrate substrate partially overlapping the second portion 32112 of the same second signal segment 3211. In order to achieve that the sum of the overlapping areas of the projection on the substrate substrate of the first gate 121 of one first transistor M1 and the projection on the substrate substrate of the first portion 32111 of one second signal segment 3211 and the projection on the substrate substrate of one third initialization signal line 322 is equal to the overlapping area of the projection on the substrate substrate of the first gate 121 of the other first transistor M1 and the projection on the substrate substrate of the second portion 32112 of the same second signal segment 3211, the overlapping area S3 of the projection on the substrate substrate of the first gate 121 of one first transistor M1 and the projection on the substrate substrate of the first portion 32111 is less than the overlapping area S1 of the projection on the substrate substrate of the first gate 121 of the other first transistor M1 and the projection on the substrate substrate of the second portion 32112, and thus the length of the first portion 32111 along the first direction X is less than the length of the second portion 32112 along the first direction X.

[0178] According to some exemplary embodiments, with reference to FIG. 7B, the overlapping area S3 of the projection on the substrate substrate of the first gate 121 and the projection on the substrate substrate of the first portion 32111 of the second signal segment 3211 is greater than the overlapping area S4 of the projection on the substrate substrate of the first gate 121 and the projection on the substrate substrate of the third signal segment 3221. In the embodiments of the present disclosure, the overlapping area of the first gate 121 and the third signal segment 3221 is reduced as much as possible on the basis of ensuring that the overlapping areas of the adjacent two first gates 121 and the signal sub-portion 320a are consistent.

[0179] According to some exemplary embodiments, with reference to FIG. 7B, there is a second gate 122 between the two first gates 121 adjacent along the first direction X, and the projections on the substrate substrate of the two first gates 121 and the second gate 122 respectively overlap the projection on the substrate substrate of the same second signal segment 3211.

[0180] According to some exemplary embodiments, with reference to FIG. 7B, the orthogonal projection of the third signal segment 3221 on the substrate substrate intersects with the orthogonal projection of the two first gates 121 adjacent along the second direction Y on the substrate substrate respectively.

[0181] According to some exemplary embodiments, with reference to FIG. 7A and FIG. 7B, the third initialization signal line 322 can be set as wide as possible within the range of space to reduce the impedance of the third initialization signal line 322, but in order to avoid the third initialization signal line 322 interfering with the signals in the conductive structures in other conductive layers, the third initialization signal line 322 is set as not overlapping with other signal conductive structures as much as possible.

[0182] For example, the orthogonal projection of the third initialization signal line 322 on the substrate substrate is spaced apart or tangent to the orthogonal projection of the second gate 122 of the second transistor M2 on the substrate substrate.

[0183] For example, the orthogonal projection of the third initialization signal line 322 on the substrate substrate is spaced apart or tangent to the orthogonal projection of the third gate 123 of the third transistor M3 on the substrate substrate.

[0184] For example, the orthogonal projection of the third initialization signal line 322 on the substrate substrate is spaced apart or tangent to the orthogonal projection of the fourth gate 124 of the fourth transistor M4 on the substrate substrate.

[0185] It is additionally explained that the orthogonal projection of two structures mentioned in the embodiments of the present disclosure “tangent” should be understood as: a part of the edge of the orthogonal projection of one structure substantially coincides with a part of the edge of the orthogonal projection of the other structure, and the orthogonal projection of other parts of one structure does not overlap with the orthogonal projection of other parts of the other structure.

[0186] According to some exemplary embodiments, the width of the third signal segment 3221 along the first direction X is greater than the width of the second signal segment 3211 along the second direction Y.

[0187] According to some exemplary embodiments, with reference to FIG. 7A, the second initialization signal part 320 needs to be spaced apart from other conductive structures arranged adjacent in the second conductive layer by a certain distance to avoid the problem of short circuit between the second initialization signal part 320 and the conductive structures for transmitting other signals. For example, the distance between the second initialization signal part 320 and the second power signal line 412 and the third power signal line 413 is greater than a preset value, which depends on factors such as patterning process accuracy. Exemplarily, the distance D5 between the second signal segment 3211 and the adjacent third power signal line 413 is greater than or equal to 0.15 microns, and the distance D15 between the third signal segment 3221 and the adjacent second power signal line 412 is greater than or equal to 0.15 microns.

[0188] According to some exemplary embodiments, referring to FIG. 7A, the at least one twenty-fourth connection structure L24 is located at one side of the second signal segment 3211 along the second direction Y and at one side of the third signal segment 3221 along the first direction X. A spacing distance D16 between the twenty-fourth connection structure L24 and the second signal segment 3211 is greater than or equal to 0.15 μm, and a spacing distance D17 between the twenty-fourth connection structure L24 and the third signal segment 3221 is greater than or equal to 0.15 μm.

[0189] According to some exemplary embodiments, referring to FIG. 7C, the first power signal input structure includes a second power signal part 420 located at the third conductive layer, the second power signal part 420 includes a plurality of fourth power signal lines 421 extending along the first direction X and arranged along the second direction Y, in combination with reference to FIG. 7C and FIG. 7A, a projection of the fourth power signal line 421 on the substrate is partially overlapped with a projection of the second initialization signal line 321 on the substrate.

[0190] According to some exemplary embodiments, referring to FIG. 7C, the second power signal part 420 further includes a plurality of fifth power signal segments 422 connected to the fourth power signal line 421, the fifth power signal segment 422 is arranged extending along the second direction Y, one end of the fifth power signal segment 422 is connected to the fourth power signal line 421 and extends away from the adjacent first gate signal line GM1, and the other end of the fifth power signal segment 422 is arranged spaced apart from the fourth gate signal line GM4. In combination with reference to FIG. 7C and FIG. 7A, a projection of the fifth power signal segment 422 on the substrate is at least partially overlapped with a projection of the third power signal line 413 on the substrate, and the fifth power signal segment 422 is electrically connected to the third power signal line 413, thereby realizing electrical connection between the second power signal part 420 and the first power signal part 410.

[0191] According to some exemplary embodiments, referring to FIG. 7C, the fourth power signal line 421 includes a fourth power signal line main part 421a and a fourth power signal line connecting part 421b, the fourth power signal line main part 421a is arranged extending along the first direction X, and the fourth power signal line connecting part 421b is located at one side of the fourth power signal line main part 421a along the second direction Y and close to the adjacent first gate signal line GM1, and the fourth power signal line connecting part 421b is connected to the fourth power signal line main part 421a as an integral structure.

[0192] According to some exemplary embodiments, referring to FIG. 7C, the first gate signal line GM1 is a zigzag-shaped trace extending along the first direction X, so that the first gate signal line GM1 keeps a large distance with the fourth power signal line body portion 421a and the thirty-third connection structure L33 located on both sides of the first gate signal line GM1 along the second direction Y. The first gate signal line GM1 includes a corner portion GM1a, and the orthographic projection of the thirty-first via hole V31 on the substrate substrate is located within the orthographic projection of the corner portion GM1a on the substrate substrate.

[0193] FIG. 8 schematically shows a cross-sectional view of the first conductive layer to the third conductive layer in the display substrate along the CC' in FIG. 7C according to some embodiments of the present disclosure.

[0194] According to some exemplary embodiments, referring to FIG. 7A and FIG. 8, the first conductive layer MT1 has the second gate signal line GM2 at this position. The second conductive layer MT2 has the second initialization signal line 321 at this position, and the orthographic projection of the second signal segment 3211 of the second initialization signal line 321 on the substrate substrate overlaps with the orthographic projection of the second gate signal line GM2 on the substrate substrate, and the second initialization signal line 321 is generally located above the second gate signal line GM2 away from the substrate substrate. The third conductive layer MT3 has the fourth power signal line 421 and the first gate signal line GM1 at this position, the orthographic projection of the fourth power signal line 421 on the substrate substrate overlaps with the orthographic projection of the second initialization signal line 321 on the substrate substrate, the fourth power signal line 421 is generally located above the second initialization signal line 321 away from the substrate substrate, and the orthographic projection of the first gate signal line GM1 on the substrate substrate does not overlap with the orthographic projection of the second initialization signal line 321 and the second gate signal line GM2 on the substrate substrate.

[0195] Among the different signal lines present at this position, the second gate signal line GM2 and the first gate signal line GM1 are located in different conductive layers, and in the direction perpendicular to the substrate substrate, the second gate signal line GM2 and the first gate signal line GM1 are also provided with the second initialization signal line 321 which can act as a signal shield, so that the coupling capacitance generated between the second gate signal line GM2 and the first gate signal line GM1 is very small. In addition, the coupling capacitance Cpd3 will be generated between the second gate signal line GM2 and the second initialization signal line 321, the coupling capacitance Cpd1 will be generated between the first gate signal line GM1 and the fourth power signal line 421, and the coupling capacitance Cpd2 will be generated between the second gate signal line GM2 and the fourth power signal line 421. Since the first power signal transmitted in the first power signal line 411 and the fourth power signal line 421 is a constant voltage signal, i.e., the first power signal line 411 and the fourth power signal line 421 are direct current signal lines, the generated Cpd1, Cpd2 and Cpd3 have no obvious influence on the driving effect of the driving circuit.

[0196] In addition, since only the second initialization signal line 321 is arranged in the second conductive layer at the position, the structure for transmitting the first power signal only includes the fourth power signal line 421 located in the third conductive layer, and since the second initialization signal line 321 between the fourth power signal line 421 and the second gate signal line GM2 functions as a signal shield, the coupling capacitance Cpd2 between the second gate signal line GM2 and the fourth power signal line 421 is very small. In combination with reference to FIG. 3, the Cpd2 is the capacitance Cgs formed between the gate and the source of the second transistor M2, that is, the Cgs of the second transistor M2 is reduced, and the device performance of the second transistor M2 is improved. Moreover, compared with the scheme of arranging the first power signal line as a shielding wire in the second conductive layer, the second initialization signal line 321 is used as a shielding wire here, which can reduce the RC loading of the first power signal, and uniform the load difference between the first power signal (high-level direct current signal) and the second power signal (low-level direct current signal), thereby reducing the direct current power consumption of the display substrate driving chip. Finally, the initialization signal transmitted in the second initialization signal line 321 acting as a shielding wire does not participate in the light-emitting stage in the driving process, and even if the initialization signal transmitted in the second initialization signal line 321 is disturbed by other adjacent conductive structures, the light-emitting effect of the light-emitting element will not be affected.

[0197] According to some exemplary embodiments, with reference to FIG. 7A, the width of the second signal segment 3211 along the second direction Y is greater than or equal to the width of the second gate signal line GM2 along the second direction Y.

[0198] Next, the layout and wiring of the display substrate provided by at least one embodiment of the present disclosure will be exemplarily explained by taking the pixel circuit shown in FIG. 3 as an example in combination with FIGS. 2A-2G. In the embodiments of the present disclosure, the substrate is taken as a silicon substrate as an example for illustration.

[0199] According to some exemplary embodiments, in the direction perpendicular to the substrate, the display substrate can include: a gate insulating layer, a gate layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer, a fifth conductive layer, a sixth insulating layer, a sixth conductive layer, a seventh insulating layer and a seventh conductive layer which are sequentially and laminatedly arranged on the substrate. Here, the “sequentially and laminatedly arranged” in the embodiments of the present disclosure means that the gate insulating layer, the gate layer, the first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer, the third insulating layer, the third conductive layer, the fourth insulating layer, the fourth conductive layer, the fifth insulating layer, the fifth conductive layer, the sixth insulating layer, the sixth conductive layer, the seventh insulating layer and the seventh conductive layer are arranged in the direction away from the substrate, but it does not mean that these film layers are necessarily adhered to each other.

[0200] According to some exemplary embodiments, referring to FIG. 2A and FIG. 5, the substrate 100 is a silicon-based substrate, for example, the material of the silicon-based substrate is single crystal silicon. The substrate 100 is formed with a P-type substrate region SP and an N-type substrate region SN, and the active region AA is formed on the P-type substrate region SP and the N-type substrate region SN. The active region AA includes a first active region 111, a second active region 112, a third active region 113, and a fourth active region 114. The first active region 111, the second active region 112, and the third active region 113 are located on the N-type substrate region SN, and the fourth active region 114 is located on the P-type substrate region SP.

[0201] According to some exemplary embodiments, referring to FIG. 2A, the active region can further include a first contact region 151 and a second contact region 152. The first contact region 151 is used for low-voltage biasing of the P-type substrate region SP, and the second contact region 152 is used for high-voltage biasing of the N-type substrate region SN. Thus, the parasitic PN junction between them can be reverse biased, the devices can be electrically isolated, the parasitic effects between the devices can be reduced, and the stability of the circuit can be improved. For example, the first contact region 151 is electrically connected with the initialization signal input structure, and the second contact region 152 is electrically connected with the first power signal input structure. The specific connection mode is described below.

[0202] According to some exemplary embodiments, referring to FIG. 2A, the gate layer includes a first gate 121, a second gate 122, a third gate 123, and a fourth gate 124.

[0203] According to some exemplary embodiments, referring to FIG. 2C, in addition to including the second gate signal line GM2, the first initialization signal part 310, and the first conductive connection part 141, the first conductive layer can further include a first connection structure L01, a second connection structure L02, a third connection structure L03, a fourth connection structure L04, a fifth connection structure L05, a sixth connection structure L06, and a seventh connection structure L07.

[0204] According to some exemplary embodiments, referring to FIG. 2C, the first insulating layer includes a first via V01, a second via V02, a third via V03, a fourth via V04, a fifth via V05, a sixth via V06, a seventh via V07, an eighth via V08, a ninth via V09, a tenth via V10, an eleventh via V11, and a twelfth via V12.

[0205] According to some exemplary embodiments, referring to FIG. 2C and FIG. 2B, the first connection structure L01 is electrically connected with the fourth gate 124 through the second via V02, and the first connection structure L01 is further used for electrical connection with the fourth gate signal line located in the upper layer.

[0206] According to some exemplary embodiments, referring to FIG. 2C and FIG. 2B, one end of the second connection structure L02 is electrically connected to the second pole 114D of the fourth active region 114 through a third via V03, and the other end of the second connection structure L02 is electrically connected to the second pole 113D of the third active region 113 through a fourth via V04, so that the second pole 114D of the fourth active region 114 is electrically connected to the second pole 113D of the third active region 113. The number of the third via V03 can be multiple to reduce the contact resistance.

[0207] According to some exemplary embodiments, referring to FIG. 2C and FIG. 2B, the third connection structure L03 is electrically connected to the second contact region 152 through a fifth via V05, and the number of the fifth via V05 can be multiple to reduce the contact resistance.

[0208] According to some exemplary embodiments, referring to FIG. 2C and FIG. 2B, the fourth connection structure L04 is electrically connected to the first pole 113S of the third active region 113 through a sixth via V06, and the number of the sixth via V06 can be multiple to reduce the contact resistance.

[0209] According to some exemplary embodiments, referring to FIG. 2C and FIG. 2B, one end of the fifth connection structure L05 is electrically connected to the third gate 123 through a seventh via V07, and the other end of the fifth connection structure L05 is electrically connected to the second pole 111D of the first active region 111 through an eighth via V08, so that the second pole 111D of the first active region 111 is electrically connected to the third gate 123.

[0210] According to some exemplary embodiments, referring to FIG. 2C and FIG. 2B, the sixth connection structure L06 is electrically connected to the first pole 112S of the second active region 112 through a ninth via V09.

[0211] According to some exemplary embodiments, referring to FIG. 2C and FIG. 2B, the seventh connection structure L07 is electrically connected to the first pole 111S of the first active region 111 through a tenth via V10.

[0212] According to some exemplary embodiments, referring to FIG. 2C and FIG. 2B, the first initialization signal part 310 is electrically connected to the first pole 114S of the fourth active region 114 through an eleventh via V11 to input the initialization signal to the first pole 114S of the fourth active region 114.

[0213] According to some exemplary embodiments, referring to FIG. 2C and FIG. 2B, the first initialization signal part 310 is electrically connected to the first contact region 151 through a twelfth via V12 to input the initialization signal to the first contact region 151, so as to realize low-voltage biasing of the P-type substrate region.

[0214] According to some exemplary embodiments, with reference to FIG. 2D, the second conductive layer includes, in addition to the first power signal part 410 and the second conductive connection part 142, the first capacitor electrode 131, a twenty-first connection structure L21, a twenty-second connection structure L22, a twenty-third connection structure L23, a twenty-fourth connection structure L24, and a twenty-fifth connection structure L25.

[0215] According to some exemplary embodiments, with reference to FIG. 2D, the second insulating layer includes a twenty-first via V21, a twenty-second via V22, a twenty-third via V23, a twenty-fourth via V24, a twenty-fifth via V25, a twenty-sixth via V26, a twenty-seventh via V27, and a twenty-eighth via V28.

[0216] According to some exemplary embodiments, with reference to FIG. 2D and FIG. 2C, the twenty-first connection structure L21 is electrically connected to the first connection structure L01 located in the first conductive layer through the twenty-second via V22, and since the first connection structure L01 is electrically connected to the fourth gate, the twenty-first connection structure L21 is electrically connected to the fourth gate.

[0217] According to some exemplary embodiments, with reference to FIG. 2D and FIG. 2C, the twenty-second connection structure L22 is electrically connected to the second connection structure L02 located in the first conductive layer through the twenty-third via V23, and since the second connection structure L02 is electrically connected to the second pole of the third active region, the twenty-second connection structure L22 is electrically connected to the second pole of the third active region.

[0218] According to some exemplary embodiments, with reference to FIG. 2D and FIG. 2C, the twenty-third connection structure L23 is electrically connected to the fifth connection structure L05 located in the first conductive layer through the twenty-fourth via V24, and since the fifth connection structure L05 is electrically connected to the third gate, the twenty-third connection structure L23 is electrically connected to the third gate.

[0219] According to some exemplary embodiments, with reference to FIG. 2D and FIG. 2C, the twenty-fourth connection structure L24 is electrically connected to the sixth connection structure L06 located in the first conductive layer through the twenty-fifth via V25, and since the sixth connection structure L06 is electrically connected to the first pole of the second active region, the twenty-fourth connection structure L24 is electrically connected to the first pole of the second active region.

[0220] According to some exemplary embodiments, with reference to FIG. 2D and FIG. 2C, the twenty-fifth connection structure L25 is electrically connected to the seventh connection structure L07 located in the first conductive layer through the twenty-sixth via V26, and since the seventh connection structure L07 is electrically connected to the first pole of the first active region, the twenty-fifth connection structure L25 is electrically connected to the first pole of the first active region.

[0221] According to some exemplary embodiments, referring to FIG. 2D, FIG. 2C and FIG. 2B, the orthogonal projection of the first capacitive electrode 131 on the substrate substrate at least partially overlaps with the orthogonal projection of the third gate 123 on the substrate substrate. The first capacitive electrode 131 is electrically connected with the fourth connection structure L04 located in the first conductive layer through the twenty-seventh via V27, and since the fourth connection structure L04 is electrically connected with the first pole of the third active region, the first capacitive electrode 131 is electrically connected with the first pole of the third active region.

[0222] According to some exemplary embodiments, referring to FIG. 2D and FIG. 2C, the first power signal part 410 is electrically connected with the third connection structure L03 located in the first conductive layer through the twenty-eighth via V28, and since the third connection structure L03 is electrically connected with the second contact region, the first power signal part 410 is electrically connected with the second contact region and accesses the first power signal to the second contact region, thereby realizing high-voltage biasing to the N-type substrate region.

[0223] According to some exemplary embodiments, referring to FIG. 2E, in addition to including the second power signal part 420, the first gate signal line GM1 and the fourth gate signal line GM4, the third conductive layer can also include the second capacitive electrode 132, the thirty-first connection structure L31, the thirty-second connection structure L32 and the thirty-third connection structure L33.

[0224] According to some exemplary embodiments, referring to FIG. 2E, the third insulating layer includes the thirty-first via V31, the thirty-second via V32, the thirty-third via V33, the thirty-fourth via V34, the thirty-fifth via V35, the thirty-sixth via V36, the thirty-seventh via V37 and the thirty-eighth via V38.

[0225] According to some exemplary embodiments, referring to FIG. 2E and FIG. 2D, the thirty-first connection structure L31 is electrically connected with the twenty-second connection structure L22 located in the second conductive layer through the thirty-second via V32, and since the twenty-second connection structure L22 is electrically connected with the second pole of the third active region, the thirty-first connection structure L31 is electrically connected with the second pole of the third active region.

[0226] According to some exemplary embodiments, referring to FIG. 2E and FIG. 2D, the thirty-second connection structure L32 is electrically connected with the first capacitive electrode 131 located in the second conductive layer through the thirty-third via V33.

[0227] According to some exemplary embodiments, referring to FIG. 2E and FIG. 2D, the thirty-third connection structure L33 is electrically connected with the twenty-fifth connection structure L25 located in the second conductive layer through the thirty-fourth via V34, and since the twenty-fifth connection structure L25 is electrically connected with the first pole of the first active region, the thirty-third connection structure L33 is electrically connected with the first pole of the first active region.

[0228] According to some exemplary embodiments, referring to FIG. 2E and FIG. 2D, the second capacitor electrode 132 is electrically connected with the twenty-third connection structure L23 in the second conductive layer through the thirty-fifth via hole V35, and since the twenty-third connection structure L23 is electrically connected with the third gate, the second capacitor electrode 132 is electrically connected with the third gate. The orthogonal projection of the second capacitor electrode 132 on the substrate is at least partially overlapped with the orthogonal projection of the first capacitor electrode 131 on the substrate.

[0229] According to some exemplary embodiments, referring to FIG. 2E and FIG. 2D, the fourth power signal line 421 is electrically connected with the twenty-fourth connection structure L24 in the second conductive layer through the thirty-sixth via hole V36, and since the twenty-fourth connection structure L24 is electrically connected with the first pole of the second active region, the fourth power signal line 421 is electrically connected with the first pole of the second active region and inputs the first power signal to the first pole of the second active region.

[0230] According to some exemplary embodiments, referring to FIG. 2E and FIG. 2D, the fourth gate signal line GM4 is electrically connected with the twenty-first connection structure L21 in the second conductive layer through the thirty-seventh via hole V37, and since the twenty-first connection structure L21 is electrically connected with the fourth gate, the fourth gate signal line GM4 is electrically connected with the fourth gate and inputs the fourth gate signal to the fourth gate.

[0231] According to some exemplary embodiments, referring to FIG. 2E and FIG. 2D, the second power signal part 420 is electrically connected with the first power signal part 410 in the second conductive layer through the thirty-eighth via hole V38.

[0232] According to some exemplary embodiments, referring to FIG. 2F, the fourth conductive layer includes a third capacitor electrode 133, and referring to FIG. 2E, the orthogonal projection of the third capacitor electrode 133 on the substrate is at least partially overlapped with the orthogonal projection of the second capacitor electrode 132 on the substrate, for example, the orthogonal projection of the third capacitor electrode 133 on the substrate is located within the orthogonal projection of the second capacitor electrode 132 on the substrate.

[0233] According to some exemplary embodiments, referring to FIG. 2F, the fifth conductive layer includes a fourth capacitor electrode 134, a data line DATA, a forty-first connection structure L41 and a forty-second connection structure L42.

[0234] According to some exemplary embodiments, referring to FIG. 2F, the fourth insulating layer includes a forty-first via hole V41, and the fourth insulating layer and the fifth insulating layer include a forty-second via hole V42, a forty-third via hole V43, a forty-fourth via hole V44 and a forty-fifth via hole V45, and the forty-second via hole V42, the forty-third via hole V43, the forty-fourth via hole V44 and the forty-fifth via hole V45 respectively penetrate the stacked film layers of the fourth insulating layer and the fifth insulating layer.

[0235] According to some embodiments, referring to FIG. 2F and FIG. 2E, the fourth capacitor electrode 134 is electrically connected with the third capacitor electrode 133 through the forty-first via V41. The number of the forty-first via V41 can be plural to reduce the contact resistance.

[0236] According to some embodiments, referring to FIG. 2F and FIG. 2E, the main body of the data line DATA extends along the second direction Y. The data line DATA is electrically connected with the thirty-third connection structure L33 in the third conductive layer through the forty-second via V42, and since the thirty-third connection structure L33 is electrically connected with the first electrode of the first active area, the data line DATA is electrically connected with the first electrode of the first active area.

[0237] According to some embodiments, referring to FIG. 2F and FIG. 2E, the forty-first connection structure L41 is electrically connected with the thirty-first connection structure L31 in the third conductive layer through the forty-third via V43, and since the thirty-first connection structure L31 is electrically connected with the second electrode of the third active area, the forty-first connection structure L41 is electrically connected with the second electrode of the third active area.

[0238] According to some embodiments, referring to FIG. 2F and FIG. 2E, the forty-second connection structure L42 is electrically connected with the fourth power signal line 421 through the forty-fourth via V44.

[0239] According to some embodiments, referring to FIG. 2F and FIG. 2E, the fourth capacitor electrode 134 is electrically connected with the first capacitor electrode 131 in the third conductive layer through the forty-fifth via V45, and since the thirty-second connection structure L32 is electrically connected with the first capacitor electrode 131, the fourth capacitor electrode 134 is electrically connected with the first capacitor electrode 131.

[0240] According to some embodiments, referring to FIG. 2G, the sixth conductive layer includes a fifth capacitor electrode 135, and referring to FIG. 2F, the orthogonal projection of the fifth capacitor electrode 135 on the substrate substrate at least partially overlaps with the orthogonal projection of the fourth capacitor electrode 134 on the substrate substrate.

[0241] According to some embodiments, referring to FIG. 2G, the seventh conductive layer includes a third power signal part 430 and a first electrode 160, the third power signal part 430 is in a grid shape, and the first electrode 160 is located inside the grid of the third power signal part 430.

[0242] According to some embodiments, referring to FIG. 2G, the seventh insulating layer includes a fifty-first via V51; the sixth insulating layer and the fifth insulating layer include a fifty-second via V52 and a fifty-third via V53.

[0243] According to some exemplary embodiments, referring to FIG. 2G, the fifth capacitor electrode 135 is electrically connected with the third power signal part 430 through the fifty-first via V51.

[0244] According to some exemplary embodiments, referring to FIG. 2G and FIG. 2F, the first electrode 160 is an anode of the light emitting element, and the first electrode 160 is electrically connected with the forty-first connection structure L41 through the fifty-second via V52, and since the forty-first connection structure L41 is electrically connected with the second electrode of the third active region, the first electrode 160 is electrically connected with the second electrode of the third active region.

[0245] According to some exemplary embodiments, referring to FIG. 2G and FIG. 2F, the third power signal part 430 is electrically connected with the forty-second connection structure L42 through the fifty-third via V53, and since the forty-second connection structure L42 is electrically connected with the fourth power signal line, the third power signal part 430 is electrically connected with the fourth power signal line, i.e., the third power signal part 430 is electrically connected with the second power signal part. The first power signal part, the second power signal part and the third power signal part electrically connected in sequence form a first power input structure for transmitting the first power signal.

[0246] FIG. 9A schematically shows an enlarged view of the region A1 in FIG. 2C. FIG. 9B schematically shows an enlarged view of the region A1 in FIG. 7A.

[0247] According to some exemplary embodiments, referring to FIG. 9A, the orthogonal projection of the second gate signal line GM2 on the substrate is arranged apart from the orthogonal projection of the adjacent ninth via V09 on the substrate, and the distance between the orthogonal projection of the second gate signal line GM2 on the substrate and the orthogonal projection of the adjacent ninth via V09 on the substrate along the second direction Y is the first distance D1. Referring to FIG. 9B, the orthogonal projection of the second signal segment 3211 on the substrate is arranged apart from the orthogonal projection of the adjacent twenty-fifth via V25 on the substrate, and the distance between the orthogonal projection of the second signal segment 3211 on the substrate and the orthogonal projection of the adjacent twenty-fifth via V25 on the substrate along the second direction Y is the second distance D2. Exemplarily, D1 and D2 are not equal.

[0248] For example, the width of the second gate signal line GM2 along the second direction Y is greater than the width of the second signal segment 3211 along the second direction Y, and D1 can be greater than D2.

[0249] According to some exemplary embodiments, referring to FIG. 7A, the first capacitance electrode 131 is located between the adjacent third power signal line 413 and the third signal segment 3221, the minimum distance between the first capacitance electrode 131 and the adjacent third power signal line 413 along the first direction X is a third distance D3, and the distance between the first capacitance electrode 131 and the adjacent third signal segment 3221 is a fourth distance D4. The distance between the second signal segment 3211 and the adjacent third power signal line 413 is a fifth distance D5. Exemplarily, D5 is not equal to D3, and / or D5 is not equal to D4.

[0250] In embodiments of the present disclosure, any one of D3, D4, and D5 is greater than 0. The fifth distance D5 between the second signal segment 3211 and the adjacent third power signal line 413 is greater than 0, meaning that the second signal segment 3211 is spaced apart from the adjacent third power signal line 413, which can avoid short circuit between the second signal segment 3211 and the adjacent third power signal line 413.

[0251] For example, in order to reduce the parasitic capacitance between the first capacitance electrode 131 and the adjacent third power signal line 413 and third signal segment 3221, and stabilize the potential of the second node S (referring to FIG. 3) in the driving circuit, D3 and D4 can be set to be larger, i.e., D3 is greater than D5, and D4 is greater than D5.

[0252] According to some exemplary embodiments, referring to FIG. 9B, the at least one twenty-sixth via hole V26 is adjacent to and spaced apart from the third signal segment 3221 along the first direction X, and the distance between the orthogonal projection of the twenty-sixth via hole V26 on the substrate and the orthogonal projection of the adjacent third signal segment 3221 on the substrate along the first direction X is a sixth distance D6. The at least one twenty-fifth via hole V25 is adjacent to and spaced apart from the third signal segment 3221 along the first direction X, and the distance between the orthogonal projection of the twenty-fifth via hole V25 on the substrate and the orthogonal projection of the adjacent third signal segment 3221 on the substrate along the first direction X is a ninth distance D9. The twenty-first via hole V21 is spaced apart from the twenty-sixth via hole V26 along the first direction X, and the distance between the orthogonal projection of the twenty-first via hole V21 on the substrate and the orthogonal projection of the twenty-sixth via hole V26 on the substrate along the first direction X is a seventh distance D7. The twenty-first via hole V21 is spaced apart from the twenty-fifth via hole V25 along the first direction X, and the distance between the orthogonal projection of the twenty-first via hole V21 on the substrate and the orthogonal projection of the twenty-fifth via hole V25 on the substrate along the first direction X is an eighth distance D8. For example, at least two of D6, D7, D8, and D9 are not equal to each other.

[0253] According to some exemplary embodiments, referring to FIG. 9B, the signal transmitted by the connection structure in the twenty-sixth via V26 is a data signal, the signal transmitted by the connection structure in the twenty-first via V21 is a first gate signal, and the signal transmitted by the connection structure in the twenty-fifth via V25 is a first power signal. Interference between the data signal and the first gate signal should be avoided in priority, and therefore, the pitch D7 of the twenty-first via V21 and the twenty-sixth via V26 in the first direction X can be set to be slightly larger, for example, D7 is greater than or equal to D6, and D7 is greater than or equal to D8.

[0254] For another example, referring to FIG. 9B, the sixth pitch D6 can effectively reduce the signal interference between the initialization signal transmitted in the third signal segment 3221 and the data signal transmitted by the connection structure in the twenty-sixth via V26, and the eighth pitch D8 can effectively reduce the signal interference between the first gate signal transmitted by the connection structure in the twenty-first via V21 and the first power signal transmitted by the connection structure in the twenty-fifth via V25. In comparison, the signal interference between the first gate signal and the first power signal can be avoided in priority, and therefore, D8 can be set to be greater than or equal to D6.

[0255] According to some exemplary embodiments, referring to FIG. 7C and FIG. 9B, since the first gate signal line GM1 is a polyline extending in the first direction X, the corner portion GM1a of the first gate signal line GM1 is electrically connected to the twenty-fourth connection structure L24 through the thirty-first via V31. In order to leave space for the corner portion GM1a, D9 can be set to be slightly larger, for example, D6 is less than or equal to D9, or D7 is less than or equal to D9, or D8 is less than or equal to D9.

[0256] FIG. 9C schematically shows an enlarged view of the region A3 in FIG. 7C.

[0257] According to some exemplary embodiments, referring to FIG. 7C and FIG. 9C, the second capacitor electrode 132 is located between two adjacent fifth power signal segments 422 and is spaced apart from the adjacent fourth power signal line 421. The pitch of the second capacitor electrode 132 and the adjacent fourth power signal line 421 in the second direction Y is the eleventh pitch D11, and the pitch of the second capacitor electrode 132 and the adjacent fifth power signal segment 422 in the second direction X is the twelfth pitch D12. Herein, D11 and D12 are not equal.

[0258] According to some exemplary embodiments, the size of the second capacitive electrode 132 along the second direction Y is greater than the size along the first direction X, and the parasitic capacitance generated between the second capacitive electrode 132 and the fifth power signal segment 422 is greater, so the distance D12 between the second capacitive electrode 132 and the fifth power signal segment 422 can be set to be greater, which is beneficial to stabilize the potential of the first node G (referring to FIG. 3) in the driving circuit. For example, D12 is greater than D11.

[0259] According to some exemplary embodiments, in combination with reference to FIGS. 7C, 9B and 9C, in order to reduce the parasitic capacitance between the second capacitive electrode 132 and the fourth power signal line 421, D11 can be set to be slightly greater, which is beneficial to stabilize the potential of the first node G (referring to FIG. 3) in the driving circuit. In addition, the distance D2 between the second signal segment 3211 and the adjacent twenty-fifth via hole V25 is only to avoid short circuit between the second signal segment 3211 and the twenty-fourth connection structure L24, and D2 can be set to be slightly smaller under the condition of ensuring no short circuit. For example, D11 is set to be greater than D2.

[0260] According to some exemplary embodiments, in combination with reference to FIGS. 9B and 9C, the orthogonal projection of the second capacitive electrode 132 on the substrate is spaced apart from the orthogonal projection of the second signal segment 3211 on the substrate, and the spacing distance between the orthogonal projection of the second capacitive electrode 132 on the substrate and the orthogonal projection of the adjacent second signal segment 3211 on the substrate along the second direction Y is the tenth distance D10. Exemplarily, D2 and D10 are not equal. The second capacitive electrode 132 and the second signal segment 3211 are located in different conductive layers, and the second capacitive electrode 132 and the second signal segment 3211 do not overlap, so D10 can be set to be slightly smaller, so that the area of the orthogonal projection of the second capacitive electrode 132 on the substrate can be increased, so that the capacitance of the storage capacitor can be increased. In addition, the second signal segment 3211 and the adjacent twenty-fourth connection structure L24 are located in the same conductive layer, and in order to avoid short circuit between the second signal segment 3211 and the adjacent twenty-fourth connection structure L24, the distance D2 between the second signal segment 3211 and the adjacent twenty-fifth via hole V25 can be set to be slightly larger. For example, D10 is less than D2.

[0261] According to some exemplary embodiments, in combination with reference to FIGS. 9B and 9C, the geometric center of the orthogonal projection of the twenty-fifth via hole V25 on the substrate and the orthogonal projection of the adjacent second signal segment 3211 on the substrate along the second direction Y is the thirteenth distance D13, and the geometric center of the orthogonal projection of the thirty-sixth via hole V36 on the substrate and the orthogonal projection of the adjacent fourth power signal line main body part 421a on the substrate along the second direction Y is the fourteenth distance D14. Exemplarily, D13 and D14 are not equal.

[0262] For example, in order to reduce the parasitic capacitance between the fourth power signal line body part 421a and the second capacitor electrode 132, the fourth power signal line body part 421a is arranged as far away from the second capacitor electrode 132 as possible. Meanwhile, the fourth power signal line body part 421a transmits the same signal as the connection structure in the thirty-sixth via hole V36, so the fourth power signal line body part 421a can be arranged closer to the thirty-sixth via hole V36, that is, the fourteenth distance D14 between the center of the fourth power signal line body part 421a and the thirty-sixth via hole V36 is smaller. In addition, the second signal segment 3211 transmits a different signal from the twenty-fourth connection structure L24 in the twenty-fifth via hole V25, so in order to avoid short circuiting between the second signal segment 3211 and the twenty-fifth via hole V25, the thirteenth distance D13 can be arranged to be slightly larger. Exemplarily, D14 can be arranged to be smaller than D13.

[0263] According to some exemplary embodiments, the orthographic projection of the fourth power signal line body part 421a on the substrate and the orthographic projection of the thirty-sixth via hole V36 on the substrate can partially overlap, so that the distance between the fourth power signal line body part 421a and the adjacent second capacitor electrode 132 is larger, for example, the geometric center of the orthographic projection of the thirty-sixth via hole V36 on the substrate can be located within the orthographic projection of the adjacent fourth power signal line body part 421a on the substrate.

[0264] According to some exemplary embodiments, referring to FIG. 7C, in order to further reduce the parasitic capacitance between the fourth power signal line body part 421a and the second capacitor electrode 132, the fourth power signal line body part 421a is arranged as far away from the second capacitor electrode 132 as possible. The fourth power signal line body part 421a can be arranged farther away from the second capacitor electrode 132 than the second signal segment 3211. The orthographic projection on the substrate of the part of the fourth power signal line body part 421a that is farther away from the second capacitor electrode 132 can be located on the side of the orthographic projection on the substrate of the second signal segment 3211 that is farther away from the second capacitor electrode 132, that is, the orthographic projection on the substrate of at least part of the fourth power signal line body part 421a is spaced apart from the orthographic projection on the substrate of the second signal segment 3211.

[0265] According to some exemplary embodiments, the display substrate further comprises a pixel definition layer on the side of the seventh conductive layer away from the substrate, a light-emitting layer on the side of the pixel definition layer away from the substrate, and a second electrode layer on the side of the light-emitting layer away from the substrate. The pixel definition layer has a pixel opening, and the pixel opening exposes at least part of the first electrode; the light-emitting layer comprises a light-emitting part, and the light-emitting part is in contact with the first electrode through the pixel opening. The first electrode, the light-emitting part, and the second electrode layer constitute a light-emitting element.

[0266] According to some exemplary embodiments, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer, and the seventh conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material made of a combination of the above metals, such as an aluminum-neodymium alloy (AlNd) or a molybdenum-niobium alloy (MoNb), etc. The conductive layers can be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. Here, the exemplary embodiments of the present disclosure do not limit the conductive layers.

[0267] According to some exemplary embodiments, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, the sixth insulating layer, and the seventh insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multi-layer, or a composite layer. Here, the exemplary embodiments of the present disclosure do not limit the insulating layers.

[0268] According to some exemplary embodiments, the planar shape of the via can be rectangular (e.g., square) or circular, etc. For example, the size of the plurality of vias in each insulating layer can be the same. Here, the exemplary embodiments of the present disclosure do not limit the vias.

[0269] At least some embodiments of the present disclosure also provide a display device including the display substrate as described above. The display device can include any device or product having a display function. For example, the display device can be a smartphone, a mobile phone, an e-book reader, a desktop PC, a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (e.g., a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, electronic accessories, an electronic tattoo, or a smart watch), a television, etc.

[0270] It should be understood that the display device according to the embodiments of the present disclosure has all the features and advantages of the display substrate described above, and specific details can be found in the above description, which will not be repeated here. Although some embodiments of the general inventive concept of the present disclosure have been shown and described, it will be understood by those having ordinary skill in the art that changes can be made to these embodiments without departing from the principles and spirit of the general inventive concept, and the scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein, The display substrate comprises: a substrate substrate; a driving circuit layer on the substrate substrate, the driving circuit layer comprising a driving circuit and an initialization signal input structure for inputting an initialization signal to the driving circuit; wherein the driving circuit layer comprises at least two conductive layers, the at least two conductive layers comprising a first conductive layer and a second conductive layer on a side of the first conductive layer away from the substrate substrate, and the initialization signal input structure comprises a second initialization signal part on the second conductive layer, the second initialization signal part comprising a plurality of signal subparts arranged in an array along a first direction and a second direction intersecting the first direction; the driving circuit comprises a first transistor comprising a first gate, and the driving circuit layer comprises a gate layer on a side of the first conductive layer close to the substrate substrate, and the first gate is on the gate layer; and a normal projection of the signal subpart on the substrate substrate and a normal projection of the first gate on the substrate substrate partially overlap, the signal subpart comprises a second signal segment extending along the first direction and a third signal segment extending along the second direction, and the second signal segment comprises a first part and a second part on two sides of the third signal segment along the first direction, and a length of the first part along the first direction is less than a length of the second part along the first direction. 2.The display substrate of claim 1, wherein, Normal projections of two first gates adjacent along the first direction on the substrate substrate and a normal projection of the same signal subpart on the substrate substrate overlap respectively, and an overlapping area of a normal projection of one first gate on the substrate substrate and a normal projection of the signal subpart on the substrate substrate is substantially equal to an overlapping area of a normal projection of another first gate on the substrate substrate and a normal projection of the signal subpart on the substrate substrate. 3.The display substrate of claim 2, wherein, A normal projection of one first gate on the substrate substrate and a normal projection of the second part of the second signal segment on the substrate substrate overlap and are spaced apart from a normal projection of the third signal segment on the substrate substrate, and a normal projection of another first gate on the substrate substrate and a normal projection of the first part of the second signal segment on the substrate substrate and a normal projection of the third signal segment on the substrate substrate overlap respectively; and an overlapping area of a normal projection of one first gate on the substrate substrate and a normal projection of the second part of the second signal segment on the substrate substrate is substantially equal to a sum of overlapping areas of a normal projection of another first gate on the substrate substrate and a normal projection of the first part of the second signal segment and a normal projection of the third signal segment on the substrate substrate. 4.The display substrate of claim 3, wherein, An overlapping area of a normal projection of the first gate on the substrate substrate and a normal projection of the first part of the second signal segment on the substrate substrate is greater than an overlapping area of a normal projection of the first gate on the substrate substrate and a normal projection of the third signal segment on the substrate substrate. 5.The display substrate according to claim 3 or 4, wherein, The driving circuit comprises a second transistor, the second transistor comprises a second gate, there is one second gate between two first gates adjacent in the first direction, and the orthographic projection of the two first gates and one second gate on the substrate substrate respectively intersects with the orthographic projection of the same second signal segment on the substrate substrate. 6.The display substrate of any one of claims 2-4, wherein, The orthographic projection of the third signal segment on the substrate substrate respectively intersects with the orthographic projection of two first gates adjacent in the second direction on the substrate substrate. 7.The display substrate according to any one of claims 1-6, wherein, The driving circuit layer further comprises a plurality of second gate signal lines for accessing a second gate signal to the driving circuit, the second gate signal lines are located in the first conductive layer, the plurality of second gate signal lines extend in the first direction and are arranged in the second direction, and the orthographic projection of the second signal segment on the substrate substrate partially overlaps with the orthographic projection of the second gate signal line on the substrate substrate. 8.The display substrate of claim 7, wherein, The width of the second signal segment in the second direction is greater than or equal to the width of the second gate signal line in the second direction. 9.The display substrate according to claim 7 or 8, wherein, The first conductive layer comprises a sixth connection structure, the sixth connection structure is located on one side of the second gate signal line in the second direction, the driving circuit comprises a second transistor, the second transistor comprises a second active region, the driving circuit layer further comprises a first insulating layer located between the second active region and the first conductive layer, the first insulating layer has a ninth via hole, and the sixth connection structure is electrically connected with the first electrode of the second active region through the ninth via hole; And The second conductive layer comprises a twenty-fourth connection structure, at least one of the twenty-fourth connection structures is located on one side of the second signal segment in the second direction, the driving circuit layer further comprises a second insulating layer located between the first conductive layer and the second conductive layer, the second insulating layer has a twenty-fifth via hole, and the twenty-fourth connection structure is electrically connected with the sixth connection structure through the twenty-fifth via hole. The orthographic projection of the second gate signal line on the substrate substrate and the orthographic projection of the adjacent ninth via hole on the substrate substrate in the second direction has a first interval, the orthographic projection of the second signal segment on the substrate substrate and the orthographic projection of the adjacent twenty-fifth via hole on the substrate substrate in the second direction has a second interval, and the first interval is greater than the second interval. 10.The display substrate according to any one of claims 7-9, wherein, The driving circuit layer further comprises a first power signal input structure for accessing a first power signal to the driving circuit, the first power signal input structure comprises a first power signal part located in the second conductive layer, the first power signal part comprises a plurality of third power signal lines, the plurality of third power signal lines extend in the second direction and are arranged in the first direction, and the signal subpart is located between two adjacent third power signal lines. 11.The display substrate of claim 10, wherein, The second conductive layer comprises a first capacitor electrode, the first capacitor electrode is located between adjacent third power supply signal lines and the third signal segment, the minimum distance of the first capacitor electrode and the adjacent third power supply signal line along the first direction is a third distance, and the distance of the first capacitor electrode and the adjacent third signal segment along the first direction is a fourth distance; and The distance of the second signal segment and the adjacent third power supply signal line along the first direction is a fifth distance, the third distance is greater than the fifth distance, and / or the fourth distance is greater than the fifth distance. 12.The display substrate of claim 10, wherein, The first conductive layer comprises a first conductive connection part, a sixth connection structure and a seventh connection structure, the driving circuit comprises a first transistor and a second transistor, the first transistor comprises a first gate and a first active region, the second transistor comprises a second active region, the first conductive connection part is electrically connected with the first gate, the sixth connection structure is electrically connected with a first pole of the second active region, and the seventh connection structure is electrically connected with a first pole of the first active region; The second conductive layer comprises a second conductive connection part, a twenty-fourth connection structure and a twenty-fifth connection structure, the second conductive connection part, the twenty-fourth connection structure and the twenty-fifth connection structure are located between adjacent third signal segments and third power supply signal lines; The driving circuit layer further comprises a second insulating layer located between the first conductive layer and the second conductive layer, the second insulating layer comprises a twenty-first via hole, a twenty-fifth via hole and a twenty-sixth via hole, the twenty-first via hole is located between the twenty-fifth via hole and the twenty-sixth via hole, the second conductive connection part is electrically connected with the first conductive connection part through the twenty-first via hole, the twenty-fourth connection structure is electrically connected with the sixth connection structure through the twenty-fifth via hole, and the twenty-fifth connection structure is electrically connected with the seventh connection structure through the twenty-sixth via hole; At least one twenty-sixth via hole is arranged adjacent to the third signal segment along the first direction, and the distance of the orthogonal projection of the twenty-sixth via hole on the substrate and the orthogonal projection of the adjacent third signal segment on the substrate along the first direction is a sixth distance; At least one twenty-fifth via hole is arranged adjacent to the third signal segment along the first direction, and the distance of the orthogonal projection of the twenty-fifth via hole on the substrate and the orthogonal projection of the adjacent third signal segment on the substrate along the first direction is a ninth distance; and The distance of the orthogonal projection of the twenty-first via hole on the substrate and the orthogonal projection of the twenty-sixth via hole on the substrate along the first direction is a seventh distance, and the distance of the orthogonal projection of the twenty-first via hole on the substrate and the orthogonal projection of the twenty-fifth via hole on the substrate along the first direction is an eighth distance; Among them, at least two of the sixth distance, the seventh distance, the eighth distance and the ninth distance are not equal to each other. 13.The display substrate of claim 12, wherein, The sixth interval is less than or equal to the seventh interval, and / or the sixth interval is less than or equal to the eighth interval, and / or the eighth interval is less than or equal to the seventh interval, and / or the sixth interval is less than or equal to the ninth interval, and / or the seventh interval is less than or equal to the ninth interval, and / or the eighth interval is less than or equal to the ninth interval. 14.The display substrate of claim 12, wherein, At least one of the twenty-fourth connection structures is located on one side of the second signal segment along the second direction and on one side of the third signal segment along the first direction. The interval between the twenty-fourth connection structure and the second signal segment is greater than or equal to 0.15 μm; and / or The interval between the twenty-fourth connection structure and the third signal segment is greater than or equal to 0.15 μm. 15.The display substrate according to any one of claims 1-14, wherein, The at least two conductive layers further include a third conductive layer located on a side of the second conductive layer away from the substrate, the third conductive layer including a second power signal part and a second capacitor electrode, the second power signal part transmitting a first power signal; The second power signal part includes a fourth power signal line and a plurality of fifth power signal segments connected to the fourth power signal line, the fourth power signal line extending along the first direction, and the plurality of fifth power signal segments extending along the second direction and arranged along the first direction; and The second capacitor electrode is located between two adjacent fifth power signal segments and is spaced apart from the adjacent fourth power signal line. 16.The display substrate of claim 15, wherein, The interval between the second capacitor electrode and the adjacent fourth power signal line along the second direction is an eleventh interval, and the interval between the second capacitor electrode and the adjacent fifth power signal segment along the first direction is a twelfth interval, wherein the twelfth interval is greater than the eleventh interval.

17. The display substrate of claim 15 or 16, wherein, The second conductive layer includes a twenty-fourth connection structure, at least one of the twenty-fourth connection structures being located on one side of the second signal segment along the second direction, the drive circuit layer further including a second insulating layer between the first conductive layer and the second conductive layer, the second insulating layer having a twenty-fifth via, the twenty-fourth connection structure being electrically connected to the sixth connection structure through the twenty-fifth via, the drive circuit including a second transistor, the second transistor including a second active region, the sixth connection structure being electrically connected to a first electrode of the second active region; and The second capacitor electrode is spaced apart from the second signal segment on the substrate; The interval between the second signal segment on the substrate and the twenty-fifth via on the substrate along the second direction is a second interval, and the interval between the second capacitor electrode on the substrate and the adjacent second signal segment on the substrate along the second direction is a tenth interval, the tenth interval being less than the second interval. The interval between the second capacitor electrode and the adjacent fourth power signal line along the second direction is an eleventh interval, the eleventh interval being greater than the second interval. 18.The display substrate of claim 17, wherein, ​ 19.The display substrate of claim 17, wherein, The fourth power signal line includes a fourth power signal line main body portion and a fourth power signal line connecting portion. The fourth power signal line main body portion extends along the first direction. The fourth power signal line connecting portion is located on one side of the fourth power signal line main body portion along the second direction and is connected with the fourth power signal line main body portion. And The driving circuit layer further includes a third insulating layer between the third conductive layer and the second conductive layer. The third insulating layer has a thirty-sixth via hole. The fourth power signal line main body portion is electrically connected with the twenty-fourth connecting structure through the thirty-sixth via hole. The geometric center of the orthogonal projection of the twenty-fifth via hole on the substrate substrate and the geometric center of the orthogonal projection of the adjacent second signal segment on the substrate substrate along the second direction are spaced apart by a thirteenth distance. The geometric center of the orthogonal projection of the thirty-sixth via hole on the substrate substrate and the geometric center of the orthogonal projection of the adjacent fourth power signal line main body portion on the substrate substrate along the second direction are spaced apart by a fourteenth distance. The fourteenth distance is less than the thirteenth distance. Or The geometric center of the orthogonal projection of the twenty-fifth via hole on the substrate substrate and the geometric center of the orthogonal projection of the adjacent second signal segment on the substrate substrate along the second direction are spaced apart by a thirteenth distance. The geometric center of the orthogonal projection of the thirty-sixth via hole on the substrate substrate is located within the orthogonal projection of the adjacent fourth power signal line main body portion on the substrate substrate. 20.The display substrate of claim 19, wherein, At least a portion of the orthogonal projection of the fourth power signal line main body portion on the substrate substrate is spaced apart from the orthogonal projection of the second signal segment on the substrate substrate. 21.The display substrate of claim 10, wherein, The first power signal portion further includes a plurality of second power signal lines. The plurality of second power signal lines extend along the first direction and are arranged along the second direction. The plurality of second power signal lines and the plurality of third power signal lines are interleaved to form a grid structure. The first power signal portion includes a plurality of hollow portions. The plurality of signal sub-portions are respectively located in the plurality of hollow portions of the first power signal portion.

22. The display substrate of claim 21, wherein, The plurality of signal sub-portions arranged along the first direction and the plurality of third power signal lines are alternately arranged along the first direction; and / or The plurality of signal sub-portions arranged along the second direction and the plurality of second power signal lines are alternately arranged along the second direction.

23. The display substrate of claim 21 or 22, wherein, The distance between the second part of the second signal segment and the adjacent third power signal line is greater than or equal to 0.15 μm; And / or The distance between the third signal segment and the adjacent second power signal line is greater than or equal to 0.15 μm.

24. The display substrate of any one of claims 21-23, wherein, The initialization signal input structure further includes a first initialization signal portion. The first initialization signal portion is located on the first conductive layer. The first initialization signal portion includes a plurality of first initialization signal lines. The plurality of first initialization signal lines extend along the first direction and are arranged along the second direction. Adjacent two first initialization signal lines are electrically connected through at least one signal sub-portion. 25.The display substrate of claim 24, wherein, The first initialization signal part further comprises at least one first signal segment electrically connected with the first initialization signal line, the first signal segment extends along the second direction, one end of the first signal segment is electrically connected with the first initialization signal line and the other end is arranged spaced apart from the adjacent second gate signal line; And The third signal segment is partially overlapped with the orthographic projections of two first signal segments adjacent and spaced apart along the second direction on the substrate substrate respectively, and the two first signal segments adjacent and spaced apart along the second direction are electrically connected through the third signal segment.

26. The display substrate of claim 24, wherein, The driving circuit comprises a third transistor, and the orthographic projection of the first signal segment on the substrate substrate is located between the orthographic projections of two third transistors adjacent along the first direction on the substrate substrate.

27. The display substrate of claim 26, wherein, The orthographic projections of two third transistors adjacent along the first direction on the substrate substrate are located between the orthographic projections of two first signal segments adjacent along the first direction on the substrate substrate. 28.The display substrate according to any one of claims 7-14, 21-27, wherein, The driving circuit layer further comprises a plurality of first gate signal lines, the plurality of first gate signal lines extend along a first direction and are arranged along a second direction, the first gate signal lines are used for transmitting first gate signals, and the driving circuit comprises a third transistor; In one of the driving circuits, the first gate signal line and the second gate signal line electrically connected with the driving circuit, the orthographic projection of the first gate signal line on the substrate substrate is located on the same side of the orthographic projection of the third transistor on the substrate substrate as the orthographic projection of the second gate signal line on the substrate substrate, and the first gate signal line and the second gate signal line are respectively located in different conductive layers. 29.The display substrate of claim 28, wherein, The at least two conductive layers further comprise a third conductive layer located on the side of the second conductive layer away from the substrate substrate, and the first gate signal line is located in the third conductive layer. 30.The display substrate of claim 28, wherein, The orthographic projection of the second gate signal line on the substrate substrate is spaced apart from the orthographic projection of the first gate signal line on the substrate substrate; The second conductive layer comprises a shielding trace, and the orthographic projection of the shielding trace on the substrate substrate is at least partially overlapped with the orthographic projection of the second gate signal line on the substrate substrate; And The orthographic projection of the shielding trace on the substrate substrate is spaced apart from the orthographic projection of the first gate signal line on the substrate substrate. 31.The display substrate of any one of claims 28-30, wherein, The second conductive layer comprises a second conductive connection part, the driving circuit layer further comprises a third insulating layer located between the second conductive layer and the third conductive layer, the third insulating layer comprises a thirty-first via hole, and the first gate signal line is electrically connected with the second conductive connection part through the thirty-first via hole; and The first gate signal line is a polyline shape trace extending along the first direction, the first gate signal line comprises a corner part, and the orthographic projection of the thirty-first via hole on the substrate substrate is located in the orthographic projection of the corner part on the substrate substrate. The driving circuit comprises a first transistor, a second transistor, a third transistor and a fourth transistor, and the display substrate further comprises a light emitting element electrically connected with the driving circuit; 32.The display substrate according to any one of claims 1-31, wherein ​ The first electrode of the first transistor is configured to access a data signal, the second electrode of the first transistor is electrically connected with the third gate electrode of the third transistor, and the first gate electrode of the first transistor is configured to access a first gate signal. The first electrode of the second transistor is configured to access a first power supply signal, the second electrode of the second transistor is electrically connected with the first electrode of the third transistor, and the second gate electrode of the second transistor is configured to access a second gate signal. The second electrode of the third transistor is electrically connected with the first electrode of the light emitting element. The first electrode of the fourth transistor is configured to access the initialization signal, the second electrode of the fourth transistor is electrically connected with the first electrode of the light emitting element, and the fourth gate electrode of the fourth transistor is configured to access a fourth gate signal; and The second electrode of the light emitting element is configured to access a second power supply signal. 33.The display substrate of claim 32, wherein, The third signal segment is spaced apart from or tangent to the second gate electrode on the substrate substrate; and / or The third signal segment is spaced apart from or tangent to the third gate electrode on the substrate substrate; and / or The third signal segment is spaced apart from or tangent to the fourth gate electrode on the substrate substrate. 34.The display substrate of claim 33, wherein, The width of the third signal segment along the first direction is greater than the width of the second signal segment along the second direction.

35. A display substrate, wherein, The display substrate comprises: A substrate substrate is a silicon-based substrate, the substrate substrate comprises a first active area, a second active area and a third active area, the first electrode of the first active area is configured to access a data signal, the first electrode of the second active area is configured to access a first power supply signal, and the second electrode of the second active area is electrically connected with the first The gate layer is located on the substrate substrate and comprises a first gate, a second gate and a third gate, the first gate is partially overlapped with the first active area on the substrate substrate, the second gate is partially overlapped with the second active area on the substrate substrate, and the third gate is partially overlapped with the third active area on the substrate substrate, and the third gate is electrically connected with the second electrode of the first active area; The first conductive layer is located on the side of the gate layer away from the substrate substrate, and the first conductive layer comprises a first conductive connection part, and the first conductive connection part is electrically connected with the first gate; The second conductive layer is located on the side of the first conductive layer away from the substrate substrate, and the second conductive layer comprises a second conductive connection part, and the second conductive connection part is electrically connected with the first conductive connection part; and The third conductive layer is located on the side of the second conductive layer away from the substrate substrate, and the third conductive layer comprises a first gate signal line, the first gate signal line is electrically connected with the second conductive connection part, and the first gate signal line accesses the first gate signal to the first gate through the second conductive connection part and the first conductive connection part. ​ 36. A display device comprising: The display substrate according to any one of claims 1-35.

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