Semiconductor device and manufacturing method therefor, and electronic device

Abstract

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: a plurality of memory cells, which are distributed in different layers and are stacked in a direction perpendicular to a substrate (1); word lines (40), which pass through the memory cells in different layers and extend in the direction perpendicular to the substrate; and a plurality of bit lines (30), which are distributed in different layers, wherein the word lines (40) and the bit lines (30) are distributed in a first direction parallel to the substrate (1), and the bit lines (30) extend in a second direction parallel to the substrate (1); the memory cells comprise transistors, semiconductor layers (23) of the transistors surround the word lines (40), the semiconductor layers (23) are connected to the bit lines (30), and the bit lines (30) are adapted to the contours of the side walls on the sides of the semiconductor layers (23) facing the bit lines (30); a plurality of semiconductor layers (23) of a plurality of transistors at the same position in different layers are distributed at intervals on side walls of the word lines (40); and in the direction perpendicular to the substrate (1), an insulating layer is provided between every two adjacent bit lines (30), and between each bit line (30) and the insulating layer, a first barrier layer (81) covering the side of the bit line (30) facing the insulating layer is provided.

Description

A semiconductor device and its manufacturing method, and an electronic device.

[0001] This application claims priority to Chinese Patent Application No. 202411017944X, filed on July 26, 2024, entitled "A Semiconductor Device and a Method for Manufacturing the Same Thereof, and an Electronic Device", the contents of which shall be construed as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and electronic equipment. Background Technology

[0003] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0004] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands.

[0005] Summary of the Invention

[0006] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0007] This application provides a semiconductor device, including:

[0008] Multiple memory cells are stacked along the vertical substrate direction, distributed across different layers;

[0009] Word lines, which penetrate the memory cells of different layers, extend along a direction perpendicular to the substrate;

[0010] Multiple bit lines are distributed in different layers. The word lines and the bit lines are distributed along a first direction parallel to the substrate, and the bit lines extend along a second direction parallel to the substrate. The first direction and the second direction intersect.

[0011] The memory cell includes a transistor, the transistor includes a semiconductor layer surrounding the word line, the semiconductor layer connecting the bit line, the bit line conforming to the contour of a sidewall of the semiconductor layer facing the bit line; multiple semiconductor layers of multiple transistors at the same position on different layers are spaced apart on the sidewall of the word line;

[0012] An insulating layer is disposed between adjacent bit lines along a direction perpendicular to the substrate, and a first barrier layer is disposed between the bit lines and the insulating layer, covering the side of the bit lines facing the insulating layer.

[0013] In some embodiments, the transistor further includes a first electrode connected to the semiconductor layer, the first electrode being disposed on the word line on the side opposite to the bit line;

[0014] The first electrode forms an annular groove, the annular groove including a bottom wall perpendicular to the substrate and two side walls parallel to the substrate, the bottom wall including an inner bottom wall located within the annular groove and an outer bottom wall located outside the annular groove, and a portion of the semiconductor layer is connected to the outer bottom wall.

[0015] In some embodiments, the memory cell further includes a capacitor, wherein the capacitor and the transistor in the same memory cell are distributed along the first direction;

[0016] The capacitor includes a first capacitor electrode and a second capacitor electrode; the first electrode is reused as the first capacitor electrode of the capacitor; the second capacitor electrode includes a first sub-electrode, and the first capacitor electrode surrounds the first sub-electrode; the first sub-electrode is distributed on the inner wall of the annular groove formed by the first electrode; the first sub-electrodes of the storage cells at the same position in different layers are connected to form an integral structure extending in a direction perpendicular to the substrate.

[0017] In some embodiments, the sidewall of the annular groove includes an inner sidewall located within the annular groove and an outer sidewall located outside the annular groove, and the first sub-electrode is also distributed on the outer sidewall of the annular groove.

[0018] In some embodiments, the outer bottom wall of the annular groove includes a first region and a second region spaced apart along the circumferential direction of the annular groove, and two intermediate regions spaced apart from the first region, respectively disposed on both sides of the first region. The first region is located on the side of the annular groove facing the bit line, and the semiconductor layer is distributed on the first region and connected to the first region. The second capacitor electrode further includes a second sub-electrode, which is distributed on the second region of the outer bottom wall of the annular groove.

[0019] In some embodiments, a second dielectric layer is disposed between the first capacitor electrode and the second sub-electrode, and the second dielectric layers of capacitors at the same position in different layers are spaced apart along a direction perpendicular to the substrate.

[0020] In some embodiments, memory cells in the same layer are arrayed along the first direction and the second direction, and the second sub-electrodes of multiple memory cells in the same layer and column distributed along the second direction are connected to form an integrated structure.

[0021] In some embodiments, every two columns of memory cells distributed along a first direction are connected to the same bit line.

[0022] In some embodiments, the second sub-electrode of the memory cell at the same location in different layers, the first electrode adjacent to it along the second direction, the semiconductor layer adjacent to it along the second direction, and the region defined by the bit line connected to the semiconductor layer are filled with an isolation layer extending in a direction perpendicular to the substrate. A second barrier layer is disposed between the isolation layer and the first electrode, the semiconductor layer, and the bit line. The isolation layer is connected to the second dielectric layer.

[0023] In some embodiments, the semiconductor device further includes:

[0024] An insulating layer and a conductive layer are alternately distributed along a direction perpendicular to the substrate;

[0025] A first hole penetrating the insulating layer and the conductive layer; the first hole includes a first sub-hole located in the insulating layer and a second sub-hole located in the conductive layer, the second sub-hole having a first groove extending in a direction parallel to the substrate relative to the first sub-hole;

[0026] The first electrode is distributed on the inner wall of the first groove, and the first electrode, the first dielectric layer, and the first sub-electrode are distributed sequentially from the outside to the inside in the first hole.

[0027] In some embodiments, the semiconductor device further includes:

[0028] A second hole penetrating the insulating layer and the conductive layer; the second hole includes a third sub-hole located in the insulating layer and a fourth sub-hole located in the conductive layer, the third sub-hole having a second groove extending in a direction parallel to the substrate relative to the fourth sub-hole;

[0029] The semiconductor layer is distributed on the sidewall of the fourth sub-hole, and the semiconductor layer, the gate insulating layer, and the word line are distributed sequentially from the outside to the inside in the second hole.

[0030] In some embodiments, the gate insulating layers of memory cells at the same location on different layers are connected to form an integral structure extending in a direction perpendicular to the substrate, and the isolation layer is connected to the region of the gate insulating layer located on the insulating layer.

[0031] This disclosure provides a method for manufacturing a semiconductor device, including:

[0032] A stacked structure comprising alternating first insulating layers and first sacrificial layers is formed on a substrate;

[0033] A plurality of second holes are formed that penetrate the stacked structure along a second direction perpendicular to the substrate direction and are spaced apart.

[0034] A plurality of first holes are formed that penetrate the stacked structure along a second direction perpendicular to the substrate, and the first holes and second holes are spaced apart along a first direction. The first sacrificial layer is etched along a direction parallel to the substrate based on the second holes to form a first lateral groove. The first holes and the second holes are connected in the first lateral groove. A first electrode is formed on the inner wall of the first lateral groove.

[0035] A first trench is formed on the side of the first hole away from the second hole, penetrating the stacked structure and extending along the second direction, and the first sacrificial layer is removed by etching based on the first trench;

[0036] A first barrier layer film and a first conductive film are deposited sequentially. The first conductive film fills the region between adjacent first insulating layers. The first barrier layer film is distributed on the side of the first insulating layer facing the substrate and the side facing away from the substrate. The first conductive film is etched to form bit lines located between adjacent first insulating layers and extending along a second direction. The bit lines are distributed on the sidewall of the second hole facing away from the first hole.

[0037] Multiple semiconductor layers are formed in the second hole and word lines are filled in the second hole. The multiple semiconductor layers surround the word lines and are spaced apart on the sidewalls of the word lines. The multiple semiconductor layers are respectively connected to the bit lines and the first electrode of different layers.

[0038] In some embodiments, forming a plurality of semiconductor layers in the second hole and filling the word lines in the second hole includes:

[0039] A second sacrificial layer is formed, filling the spaces between adjacent first insulating layers and located between adjacent first holes along the second direction, and located on the side of the first holes facing the second holes, and a second barrier layer is disposed between the second sacrificial layer and the bit line; the first insulating layer is replaced with a second insulating layer and a third sacrificial layer, the third sacrificial layer being located between adjacent second sacrificial layers along the direction perpendicular to the substrate and between adjacent second holes along the second direction, and connected to the second sacrificial layer;

[0040] The inner wall of the second hole is exposed, and the sidewall of the second hole is exposed to the bit line. The third sacrificial layer is etched in a direction parallel to the substrate based on the second hole. The second insulating layer and the first insulating layer are etched in a direction parallel to the substrate based on the second hole, such that the sub-hole of the second hole located in the third sacrificial layer has a second lateral groove extending in a horizontal direction relative to the sub-hole located in the second sacrificial layer.

[0041] A dummy layer is formed on the inner wall of the second transverse groove; a semiconductor thin film, a gate insulating film and a second conductive film filling the second hole are sequentially deposited in the second hole to form multiple semiconductor layers, multiple gate insulating layers and word lines;

[0042] The second and third sacrificial layers are etched away, and the dummy layer is etched away; the semiconductor thin film covered by the dummy layer is etched away, thereby disconnecting the plurality of semiconductor layers.

[0043] In some embodiments, the method further includes:

[0044] The method further includes: exposing the first hole and the first transverse groove, and forming a first sub-electrode within the first hole and the first transverse groove.

[0045] In some embodiments, before forming the first sub-electrode in the first hole and the first lateral groove, the method further includes: exposing the side of the first electrode away from the substrate and the side facing the substrate to form a third lateral groove;

[0046] Forming a first sub-electrode within the first hole and the first transverse groove includes: forming a first sub-electrode within the first hole, the first transverse groove, and the third transverse groove.

[0047] In some embodiments, after forming the second sacrificial layer and before replacing the first insulating layer with the second insulating layer and the third sacrificial layer, the method further includes:

[0048] A second sub-electrode is formed on the side of the first electrode opposite to the bit line;

[0049] After replacing the first insulating layer with the second insulating layer and the third sacrificial layer, the method further includes:

[0050] A connecting electrode is formed that fills the first trench and is connected to the second sub-electrode.

[0051] This disclosure provides an electronic device, including any of the semiconductor devices described above, or a semiconductor device formed according to the manufacturing method of any of the semiconductor devices described above.

[0052] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.

[0053] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0054] Overview of the attached figures

[0055] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0056] Figure 1A is a cross-sectional view of a semiconductor device provided in some embodiments along the AA' direction parallel to the substrate; Figure 1B is a cross-sectional view of a semiconductor device provided in some embodiments along the BB' direction parallel to the substrate; Figure 1C is a cross-sectional view along the CC' direction in Figure 1A; Figure 1D is a cross-sectional view along the DD' direction in Figure 1A; Figure 1E is a cross-sectional view along the EE' direction in Figure 1A; Figure 1F is a cross-sectional view along the FF' direction in Figure 1A; Figure 1G is a schematic diagram of a first capacitor electrode provided in some embodiments.

[0057] Figure 2A is a cross-sectional view along the AA' direction after the second hole is formed according to some embodiments; Figure 2B is a cross-sectional view along the CC' direction after the second hole is formed according to some embodiments; Figure 2C is a cross-sectional view along the EE' direction after the second hole is formed according to some embodiments.

[0058] Figure 3A is a cross-sectional view along the AA' direction after the formation of the first capacitor electrode according to some embodiments; Figure 3B is a cross-sectional view along the CC' direction after the formation of the first capacitor electrode according to some embodiments; Figure 3C is a cross-sectional view along the EE' direction after the formation of the first capacitor electrode according to some embodiments.

[0059] Figure 4A is a cross-sectional view along the AA' direction after the first trench is formed according to some embodiments; Figure 4B is a cross-sectional view along the CC' direction after the first trench is formed according to some embodiments; Figure 4C is a cross-sectional view along the EE' direction after the first trench is formed according to some embodiments.

[0060] Figure 5A is a cross-sectional view along the AA' direction after bit line formation according to some embodiments; Figure 5B is a cross-sectional view along the CC' direction after bit line formation according to some embodiments; Figure 5C is a cross-sectional view along the EE' direction after bit line formation according to some embodiments.

[0061] Figure 6A is a cross-sectional view along the AA' direction after the formation of the second sacrificial layer according to some embodiments; Figure 6B is a cross-sectional view along the CC' direction after the formation of the second sacrificial layer according to some embodiments; Figure 6C is a cross-sectional view along the EE' direction after the formation of the second sacrificial layer according to some embodiments.

[0062] Figure 7A is a cross-sectional view along the AA' direction after forming the second dielectric layer and the second sub-electrode according to some embodiments; Figure 7B is a cross-sectional view along the CC' direction after forming the second dielectric layer and the second sub-electrode according to some embodiments; Figure 7C is a cross-sectional view along the EE' direction after forming the second dielectric layer and the second sub-electrode according to some embodiments.

[0063] Figure 8A is a cross-sectional view along the AA' direction after exposing the upper and lower surfaces of the second sacrificial layer according to some embodiments; Figure 8B is a cross-sectional view along the CC' direction after exposing the upper and lower surfaces of the second sacrificial layer according to some embodiments; Figure 8C is a cross-sectional view along the EE' direction after exposing the upper and lower surfaces of the second sacrificial layer according to some embodiments.

[0064] Figure 9A is a cross-sectional view along the AA' direction after the connection electrode is formed according to some embodiments; Figure 9B is a cross-sectional view along the CC' direction after the connection electrode is formed according to some embodiments; Figure 9C is a cross-sectional view along the EE' direction after the connection electrode is formed according to some embodiments.

[0065] Figure 10A is a cross-sectional view along the AA' direction after the second transverse groove is formed according to some embodiments; Figure 10B is a cross-sectional view along the CC' direction after the second transverse groove is formed according to some embodiments; Figure 10C is a cross-sectional view along the EE' direction after the second transverse groove is formed according to some embodiments.

[0066] Figure 11A is a cross-sectional view along the AA' direction after the formation of the semiconductor layer, gate insulating layer and word line according to some embodiments; Figure 11B is a cross-sectional view along the CC' direction after the formation of the semiconductor layer, gate insulating layer and word line according to some embodiments; Figure 11C is a cross-sectional view along the EE' direction after the formation of the semiconductor layer, gate insulating layer and word line according to some embodiments.

[0067] Figure 12A is a cross-sectional view along the AA' direction after disconnecting different semiconductor layers according to some embodiments; Figure 12B is a cross-sectional view along the CC' direction after disconnecting different semiconductor layers according to some embodiments; Figure 12C is a cross-sectional view along the EE' direction after disconnecting different semiconductor layers according to some embodiments.

[0068] Figure 13A is a cross-sectional view along the AA' direction after the formation of the first dielectric layer and the first sub-electrode according to some embodiments; Figure 13B is a cross-sectional view along the CC' direction after the formation of the first dielectric layer and the first sub-electrode according to some embodiments; and Figure 13C is a cross-sectional view along the EE' direction after the formation of the first dielectric layer and the first sub-electrode according to some embodiments.

[0069] Detailed Explanation

[0070] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0071] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0072] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0073] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0074] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0075] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0076] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0077] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0078] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0079] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0080] In this embodiment of the disclosure, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with interconnected relationships.

[0081] In this embodiment of the disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0082] Figure 1A is a cross-sectional view of a semiconductor device provided in some embodiments along the AA' direction parallel to the substrate; Figure 1B is a cross-sectional view of a semiconductor device provided in some embodiments along the BB' direction parallel to the substrate; Figure 1C is a cross-sectional view along the CC' direction perpendicular to the substrate in Figure 1A; Figure 1D is a cross-sectional view along the DD' direction perpendicular to the substrate in Figure 1A; Figure 1E is a cross-sectional view along the EE' direction perpendicular to the substrate in Figure 1A; and Figure 1F is a cross-sectional view along the FF' direction perpendicular to the substrate in Figure 1A. As shown in Figures 1A to 1F, embodiments of this disclosure provide a semiconductor device including a multilayer memory cell array vertically stacked on a substrate 1.

[0083] The memory cell array may include multiple memory cells, multiple bit lines 30, and multiple word lines 40. Each layer of the memory cell array may include multiple memory cells distributed along a first direction X parallel to the substrate 1 and a second direction Y parallel to the substrate 1. The first direction X and the second direction Y may intersect. In some embodiments, the first direction X and the second direction Y may be perpendicular.

[0084] The word line 40 can extend in a direction perpendicular to the substrate 1, and multiple memory cells stacked at the same position in different layers in a direction perpendicular to the substrate 1 can be connected to the same word line 40.

[0085] The bit lines 30 can extend along a second direction Y parallel to the substrate 1. Multiple bit lines 30 of the same memory cell array can be spaced apart from each other, and the multiple bit lines 30 of the same memory cell array can be distributed at intervals along a first direction X. Bit lines 30 of different layers of memory cell arrays can be stacked in a direction perpendicular to the substrate 1.

[0086] In some embodiments, two adjacent columns of memory cells along the first direction X are connected to the same bit line 30. Each pair of memory cells can be grouped together, and memory cells within the same group are connected to the same bit line 30.

[0087] The storage unit can be a 1T1C storage unit.

[0088] The memory cell may include a transistor and a capacitor connected to the transistor. The transistor and capacitor within the same memory cell may be distributed along a first direction X. The capacitor, the word line 40, and the bit line 30 are distributed along the first direction X. The transistor may include a gate electrode 26, a first electrode 51, and a second electrode 52. The gate electrode 26 may be part of the word line 40, and the gate electrodes 26 of transistors at the same location on different layers may be connected to form a single word line 40 structure.

[0089] The second electrode 52 may be connected to the bit line 30, or the second electrode 52 may be part of the bit line 30. The second electrodes 52 of transistors in the same layer and column of memory cells may be connected to the same bit line 30. The second electrodes 52 of the transistors in the same layer and column are connected to form a single-piece structure of the bit line 30 extending along the second direction Y.

[0090] The following explanation uses a semiconductor device comprising multiple vertically stacked transistors at the same location as an example.

[0091] As shown in Figures 1A to 1F, embodiments of this disclosure provide a semiconductor device, which may include:

[0092] Multiple memory cells are stacked along the direction perpendicular to substrate 1, distributed across different layers;

[0093] Word line 40 extends through the memory cells in different layers along a direction perpendicular to the substrate 1;

[0094] Multiple bit lines 30 are distributed in different layers. The word lines 40 and the bit lines 30 are distributed along a first direction X parallel to the substrate 1, and the bit lines 30 extend along a second direction Y parallel to the substrate 1. The first direction X and the second direction Y intersect.

[0095] The memory cell may include a transistor, the transistor including a semiconductor layer 23 surrounding the word line 40, the semiconductor layer 23 being connected to the bit line 30, and the bit line 30 conforming to the contour of the sidewall of the semiconductor layer 23 facing the bit line 30; multiple semiconductor layers 23 of multiple transistors at the same position on different layers are spaced apart on the sidewall of the word line 40. The bit line 30 conforms to the contour of the sidewall of the semiconductor layer 23 facing the bit line 30, that is, the bit line 30 is distributed on the sidewall of the semiconductor layer 23 facing the bit line 30 and is attached to the semiconductor layer 23.

[0096] In some embodiments, an insulating layer is provided between bit lines 30 at the same position on different layers, and a first barrier layer 81 is provided between the insulating layer and the bit line 30.

[0097] In some embodiments, recesses exist on the two side walls of the bit line 30 that are opposite each other along the first direction X, in the region between adjacent word lines 30 along the second direction Y. As shown in FIG1A, multiple recesses exist on both side walls of the bit line 30 that are opposite each other along the first direction X. The recesses of the bit line 30 are formed by etching from both sides during the manufacturing of the bit line 30. That is, the bit line 30 can be formed by etching from both sides without the need for a photomask.

[0098] In some embodiments, the transistor may further include: a gate insulating layer 24 disposed between the word line 40 and the semiconductor layer 23, the gate insulating layer 24 surrounding the word line 40, and multiple gate insulating layers 24 of multiple transistors at the same position on different layers may be connected to form an integral structure.

[0099] In some embodiments, the first electrode 51 of the transistor is disposed on the side of the word line 40 away from the bit line 30 and is connected to the semiconductor layer 23.

[0100] In some embodiments, the first electrode 51 may form an annular groove, which may include an annular bottom wall perpendicular to the substrate 1 and two side walls parallel to the substrate 1. The annular bottom wall includes an inner bottom wall located within the annular groove and an outer bottom wall located outside the annular groove. A portion of the semiconductor layer 23 is connected to the outer bottom wall of the annular bottom wall. The orthographic projection of the annular groove onto the substrate 1 may be a closed ring.

[0101] In some embodiments, the capacitor may include a first capacitor electrode 41 and a second capacitor electrode 42, and the first electrode 51 may be reused as the first capacitor electrode 41.

[0102] In some embodiments, the second capacitor electrode 42 may include a first sub-electrode 421, with the first capacitor electrode 41 surrounding the first sub-electrode 421, and a first dielectric layer 431 disposed between the first capacitor electrode 41 and the first sub-electrode 421; the first sub-electrode 421 extends along a direction perpendicular to the substrate 1 and fills the annular groove formed by the first electrode 51; the first sub-electrodes 421 of memory cells at the same position in different layers may be connected to form an integral structure extending along a direction perpendicular to the substrate 1. That is, the first sub-electrode 421 is disposed in the area surrounded by the first electrode 51. The solution provided in this embodiment can form multiple first sub-electrodes 421 of capacitors in a single manufacturing process, simplifying the process and reducing costs.

[0103] In some embodiments, the first dielectric layer 431 of capacitors at the same location on different layers can be connected to form a single structure. The solution provided in this embodiment allows multiple capacitors' first dielectric layers 431 to be formed in a single manufacturing process, simplifying the process and reducing costs.

[0104] In some embodiments, the sidewall of the annular groove may include an inner sidewall located within the annular groove and an outer sidewall located outside the annular groove, and the first sub-electrode 421 may also be distributed on the outer sidewall of the annular groove. That is, the first sub-electrode 421 may be distributed on the inner wall (including the inner bottom wall and the inner sidewall) of the annular groove, and may also be distributed on the outer sidewall of the annular groove, thereby maximizing the facing area between the first sub-electrode 421 and the first capacitor electrode 41, and increasing the capacitance of the capacitor.

[0105] In some embodiments, the second capacitor electrode 42 may further include a second sub-electrode 422, which is distributed on the outer bottom wall of the annular bottom wall of the annular groove, and a second dielectric layer 432 is disposed between the first capacitor electrode 41 and the second sub-electrode 422. The solution provided in this embodiment, by disposing an electrode outside the first capacitor electrode 41, can further increase the capacitance of the capacitor.

[0106] In some embodiments, the second sub-electrodes 422 of multiple memory cells distributed in the same layer and column along the second direction Y can be connected to form an integral structure. The solution provided in this embodiment allows multiple capacitor second sub-electrodes 422 to be formed in a single manufacturing process, simplifying the process and reducing costs.

[0107] In some embodiments, the second sub-electrode 422 fills the region between adjacent first capacitor electrodes 41 along the second direction Y.

[0108] In some embodiments, second sub-electrodes 422 of multiple memory cells at the same location in different layers are connected. The multiple second sub-electrodes 422 can be connected by a connecting electrode 424 extending in a direction perpendicular to the substrate 1. The connecting electrode 424 can be disposed in a trench extending in a second direction Y and perpendicular to the substrate 1. The connecting electrode 424 can be a planar film layer extending in a direction perpendicular to the substrate 1 and in the second direction Y, connecting the second sub-electrodes 422 of multiple memory cells in the same layer and column, and connecting the second sub-electrodes 422 of multiple memory cells at the same location in different layers.

[0109] In some embodiments, the second dielectric layers 432 of capacitors distributed in the same layer and column along the second direction Y can be connected to form an integral structure. The solution provided in this embodiment can form the second dielectric layers 432 of multiple capacitors in the same layer through a single manufacturing process, simplifying the process and reducing costs.

[0110] In some embodiments, the second dielectric layers 432 of capacitors at the same location on different layers can be disconnected, for example, physically disconnected.

[0111] Figure 1G is a schematic diagram of a first capacitor electrode 41 or a first electrode 51 provided in some embodiments. In some embodiments, as shown in Figure 1G, the outer bottom wall of the annular groove includes a first region 511 and a second region 512 spaced apart along the circumferential direction of the annular groove, and two intermediate regions, respectively referred to as the first intermediate region 513 and the second intermediate region 512, disposed on both sides of the first region 511. The first region 511 is located on the side of the annular groove facing the bit line 30, and the semiconductor layer 23 is connected to the first region 511.

[0112] In some embodiments, the second sub-electrode 422 may be distributed on the second region 512 of the outer bottom wall of the annular groove.

[0113] In some embodiments, an isolation layer 6 is provided between adjacent semiconductor layers 23 spaced apart along the second direction Y, penetrating the memory cells of different layers and extending along a direction perpendicular to the substrate 1. That is, adjacent semiconductor layers 23 along the second direction Y are spaced apart by the isolation layer 6.

[0114] The isolation layer 6 is disposed between the integral structure formed by connecting the second sub-electrodes 422, the bit line 30, the first capacitor electrodes 41 of two adjacent capacitors along the second direction Y, and the region defined by two adjacent semiconductor layers 23 along the second direction Y, and fills the integral structure formed by connecting the second sub-electrodes 422, the bit line 30, the first capacitor electrodes 41 of two adjacent capacitors along the second direction Y, and the region defined by two adjacent semiconductor layers 23 along the second direction Y.

[0115] A barrier layer (the second barrier layer 82 described below) is provided between the isolation layer 6 and the bit line 30, a barrier layer (the second barrier layer 82 described below) is provided between the isolation layer 6 and the semiconductor layer 23, and a barrier layer (the first barrier layer 81 and the second barrier layer 82) is provided between the isolation layer 6 and the first capacitor electrode 41. The isolation layer 6 is connected to the second dielectric layer 432.

[0116] In some embodiments, the semiconductor device may further include:

[0117] An insulating layer and a conductive layer are alternately distributed along a direction perpendicular to the substrate 1; the conductive layer may include a first electrode 51;

[0118] A first hole penetrating the insulating layer and the conductive layer; the first hole includes a first sub-hole located in the insulating layer and a second sub-hole located in the conductive layer, the second sub-hole having a first groove (i.e., a subsequent first lateral groove V1) extending in a horizontal direction (i.e., parallel to the direction of substrate 1) relative to the first sub-hole; that is, the orthographic projection of the first sub-hole onto substrate 1 falls within the orthographic projection of the second sub-hole onto substrate 1;

[0119] The first electrode 51 is distributed on the inner wall of the first groove, and the first electrode 51, the first dielectric layer 431, and the first sub-electrode 421 are distributed sequentially from the outside to the inside in the first hole. The solution provided in this embodiment can form the first capacitor electrode 41 (i.e., the first electrode 51) of multiple capacitors at one time, as well as the first dielectric layer 431 of multiple capacitors at one time, and the first sub-electrode 421 of multiple capacitors at one time, simplifying the process.

[0120] In some embodiments, the semiconductor device may further include:

[0121] A second hole penetrating the insulating layer and the conductive layer; the second hole includes a third sub-hole located in the insulating layer and a fourth sub-hole located in the conductive layer, the third sub-hole having a second groove extending in the horizontal direction relative to the fourth sub-hole (i.e., a subsequent second lateral groove V2); that is, the orthographic projection of the fourth sub-hole onto the substrate 1 falls within the orthographic projection of the third sub-hole onto the substrate 1;

[0122] The semiconductor layer 23 is distributed on the sidewall of the fourth sub-hole, and the semiconductor layer 23, the gate insulating layer 24, and the word line 40 are distributed sequentially from the outside to the inside in the second hole. The solution provided in this embodiment can form the semiconductor layer and gate insulating layer of multiple transistors at once, simplifying the process. Furthermore, by making the diameter of the third sub-hole larger, different semiconductor layers 23 can be disconnected by an external drilling method.

[0123] In some embodiments, the isolation layer 6 is connected to the gate insulating layer 24 in the region of the insulating layer. The solution provided in this embodiment allows for external excavation by exposing the region where the isolation layer 6 is located, eliminating the need for an additional photomask and reducing costs. In addition, due to the limitations of photomask size, if a photomask is required for external excavation, the device needs to reserve a larger size. Therefore, external excavation without an additional photomask is beneficial for reducing device size.

[0124] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor device in this embodiment. The "patterning process" mentioned in this embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes film coating, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."

[0125] In one exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0126] 1) Formation of the second hole K2;

[0127] A substrate 1 is provided, and a first insulating film and a first sacrificial layer film are alternately deposited on the substrate 1 to form a stacked structure comprising a plurality of alternately arranged first insulating layers 11 and first sacrificial layers 10;

[0128] The stacked structure is etched from the top layer to the bottom layer along a direction perpendicular to the substrate 1 (etching stops on the substrate 1) to pattern a plurality of second holes K2 spaced apart along the second direction Y; subsequently, a semiconductor layer 23 and word lines 40 can be formed in the second holes K2; multiple rows of second holes K2 spaced apart along the first direction X can be formed;

[0129] After depositing the first dummy layer film, it is smoothed to form the first dummy layer 91 that fills the second hole K2; as shown in Figures 2A, 2B, and 2C. Figure 2A is a cross-sectional view along the AA' direction after the formation of the second hole K2 according to some embodiments; Figure 2B is a cross-sectional view along the CC' direction after the formation of the second hole K2 according to some embodiments; and Figure 2C is a cross-sectional view along the EE' direction after the formation of the second hole K2 according to some embodiments.

[0130] In some embodiments, substrate 1 may be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

[0131] In some embodiments, the first insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO2), etc. The subsequent second to sixth insulating films are similar and will not be described in detail.

[0132] In some embodiments, the first sacrificial layer film may be a film layer that has an etching selectivity ratio with the first insulating film, such as silicon nitride (SiN).

[0133] In some embodiments, the second hole K2 along a cross section parallel to the substrate 1 can be circular, square, or the like.

[0134] In some embodiments, the first dummy layer film may be a film layer with an etching selectivity ratio to the first insulating film and the first sacrificial layer film, such as polysilicon. The materials of the subsequent second to fourth dummy layer films are similar to those of the first dummy layer film and will not be described further.

[0135] 2) Form the first capacitor electrode 41;

[0136] A second insulating film is deposited to form a second insulating layer 12, which covers the bit line 30 and the topmost first sacrificial layer 10.

[0137] The stacked structure is etched from the top layer to the bottom layer along a direction perpendicular to the substrate 1 (etching stops on the substrate 1) to form a plurality of first initial holes K1 spaced apart along the second direction Y; the first initial holes K1 and the second holes K2 are spaced apart along the first direction X;

[0138] Based on the first initial hole K1, the first sacrificial layer 10 is etched laterally (i.e., etched along a direction parallel to the substrate 1) to form a first lateral groove V1. The first initial hole K1 and the first lateral groove V1 constitute a first hole. The first hole is located in the orthographic projection of the sub-hole of the first insulating layer 11 onto the substrate 1. The first hole is located in the orthographic projection of the sub-hole of the first sacrificial layer 10 onto the substrate 1. The bottom wall of the first lateral groove V1 exposes the first dummy layer 91.

[0139] A first conductive film and a second dummy layer film are deposited sequentially to form a first capacitor electrode 41 and a second dummy layer 92. The first conductive film covers the inner wall of the first initial hole K1 and the inner wall of the first transverse groove V1, and the second dummy layer film fills the first initial hole K1 and the first transverse groove V1. The first capacitor electrode 41 is connected to the first dummy layer 91, so that when the semiconductor layer 23 is subsequently formed in the second hole K2, the semiconductor layer 23 is connected to the first capacitor electrode 41.

[0140] The first capacitor electrode 41 and the second dummy layer 92 in the first initial hole K1 are removed by etching, while the first capacitor electrode 41 and the second dummy layer 92 in the first transverse groove V1 are retained, as shown in Figures 3A, 3B, and 3C. Figure 3A is a cross-sectional view along the AA' direction after the formation of the first capacitor electrode 41 according to some embodiments; Figure 3B is a cross-sectional view along the CC' direction after the formation of the first capacitor electrode 41 according to some embodiments; and Figure 3C is a cross-sectional view along the EE' direction after the formation of the first capacitor electrode 41 according to some embodiments.

[0141] In some embodiments, the first initial hole K1 along a cross section parallel to the substrate 1 can be circular, square, or the like.

[0142] In some embodiments, the first conductive film may be one or more of the following different types of materials:

[0143] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can also be a metal alloy containing these metals.

[0144] Alternatively, it can be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as highly conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and aluminum-doped zinc oxide (AZO); or metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0145] Alternatively, it could be polycrystalline silicon, conductive doped semiconductor materials, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; or other materials that exhibit conductivity.

[0146] The materials of the second to sixth conductive films are similar to those of the first conductive film, and will not be described in detail here.

[0147] 3) Form the first trench T1;

[0148] A third dummy layer film is deposited to form a third dummy layer 93 that fills the first initial hole K1;

[0149] The third dummy layer 93 is wet-etched to remove a portion of the third dummy layer film on top of the first initial hole K1, deposit a third insulating film, and form a third insulating layer 13, which covers the stacked structure; the third insulating layer 13 forms the top cover of the first initial hole K1, covering the third dummy layer 93.

[0150] A first hard mask layer thin film is deposited to form a first hard mask layer 7 covering the second insulating layer 12 and the third insulating layer 13; the first hard mask layer 7 serves as the hard mask layer for subsequent etching.

[0151] The stacked structure is etched along a direction perpendicular to the substrate 1 to form a plurality of first trenches T1 penetrating the stacked structure; the first trenches T1 extend along a second direction Y and penetrate the stacked structure along the second direction Y, and adjacent first trenches T1 define a group of memory cells, each group of memory cells including two columns of memory cells.

[0152] The first sacrificial layer 10 is removed by lateral etching based on the first trench T1, as shown in Figures 4A, 4B, and 4C. Figure 4A is a cross-sectional view along the AA' direction after the formation of the first trench T1 according to some embodiments; Figure 4B is a cross-sectional view along the CC' direction after the formation of the first trench T1 according to some embodiments; and Figure 4C is a cross-sectional view along the EE' direction after the formation of the first trench T1 according to some embodiments.

[0153] In some embodiments, the first hard mask layer thin film may be polycrystalline silicon or the like.

[0154] 4) Form bit line 30;

[0155] A first barrier layer film is deposited to form a first barrier layer 81. The first barrier layer 81 surrounds the first capacitor electrode 41, the first dummy layer 91, and covers the surface of the first insulating layer 11 facing the substrate and the surface facing away from the substrate 1, as well as the sidewall of the first insulating layer 11 facing the first trench T1.

[0156] A second conductive film is deposited to fill the area between adjacent first insulating layers 11. The second conductive film is then wet-etched laterally. Between adjacent first insulating layers 11, a strip-shaped second conductive film extending along the second direction Y is retained on the side of the second hole K2 opposite to the first initial hole K1, forming a bit line 30. A second conductive film extending along the second direction Y can be retained between two adjacent columns of memory cells, that is, two adjacent columns of memory cells share a bit line 30, as shown in Figures 5A, 5B, and 5C. Among them, Figure 5A is a cross-sectional view along the AA' direction after the bit line 30 is formed according to some embodiments, Figure 5B is a cross-sectional view along the CC' direction after the bit line 30 is formed according to some embodiments, and Figure 5C is a cross-sectional view along the EE' direction after the bit line 30 is formed according to some embodiments.

[0157] In some embodiments, the first barrier layer film may be an insulating film layer with an etching selectivity ratio to the first insulating film, such as SiN. The material of the subsequent second barrier layer film is similar to that of the first barrier layer film and will not be described further.

[0158] 5) Formation of a second sacrificial layer 61;

[0159] A second barrier layer film is deposited to form a second barrier layer 82, which covers the area of ​​the bit line 30 facing the first initial hole K1 and not in contact with the first barrier layer 81, and also covers the first barrier layer 81.

[0160] A second sacrificial layer film is deposited, which fills the area between adjacent first insulating layers 11. The second sacrificial layer film is then wet-etched laterally to the junction of the second hole K2 and the first lateral groove V1 to form the second sacrificial layer 61.

[0161] Wet etching is performed on the second barrier layer 82 not covered by the second sacrificial layer 61, and the first barrier layer 81 located beneath the second barrier layer 82 not covered by the second sacrificial layer 61, thereby exposing the sidewall of the first capacitor electrode 41 facing away from the bit line 30, and the sidewall of the first capacitor electrode 41 adjacent along the second direction Y, as shown in Figures 6A, 6B, and 6C. Figure 6A is a cross-sectional view along the AA' direction after the formation of the second sacrificial layer 61 according to some embodiments; Figure 6B is a cross-sectional view along the CC' direction after the formation of the second sacrificial layer 61 according to some embodiments; and Figure 6C is a cross-sectional view along the EE' direction after the formation of the second sacrificial layer 61 according to some embodiments.

[0162] In some embodiments, the second sacrificial layer film may be a film layer with an etching selectivity ratio to the first sacrificial layer film and the first insulating film, such as aluminum oxide. The material of the subsequent third sacrificial layer film is similar to that of the second sacrificial layer film and will not be described in detail.

[0163] 6) Form the second dielectric layer 432 and the second sub-electrode 422;

[0164] A second dielectric film and a third conductive film are sequentially deposited, and the second dielectric film and the third conductive film in the first trench T1 are etched away to form a second dielectric layer 432 and a second sub-electrode 422, as shown in Figures 7A, 7B, and 7C. Figure 7A is a cross-sectional view along the AA' direction after the formation of the second dielectric layer 432 and the second sub-electrode 422 according to some embodiments; Figure 7B is a cross-sectional view along the CC' direction after the formation of the second dielectric layer 432 and the second sub-electrode 422 according to some embodiments; and Figure 7C is a cross-sectional view along the EE' direction after the formation of the second dielectric layer 432 and the second sub-electrode 422 according to some embodiments.

[0165] In some embodiments, the second dielectric film may be a high-K dielectric material. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary examples include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials. The subsequent description of the first dielectric film is similar to that of the second dielectric film and will not be repeated.

[0166] 7) Expose the upper and lower surfaces of the second sacrificial layer 61;

[0167] Based on the first trench T1, the first insulating layer 11, the second insulating layer 12, and the third insulating layer 13 are wet laterally etched, and the first insulating layer 11 located between adjacent bit lines 30 along the direction perpendicular to the substrate 1 and the second insulating layer 12 between the bit line 30 and the first hard mask layer 7 are retained.

[0168] Wet etching is used to cover the second barrier layer 82 and the first barrier layer 81 on the side of the second sacrificial layer 61 facing away from the substrate 1 and the side facing the substrate 1, respectively, exposing the side of the second sacrificial layer 61 facing away from the substrate 1 and the side facing the substrate 1, as shown in Figures 8A, 8B, and 8C. Figure 8A is a cross-sectional view along the AA' direction after exposing the upper and lower surfaces of the second sacrificial layer 62 according to some embodiments; Figure 8B is a cross-sectional view along the CC' direction after exposing the upper and lower surfaces of the second sacrificial layer 61 according to some embodiments; and Figure 8C is a cross-sectional view along the EE' direction after exposing the upper and lower surfaces of the second sacrificial layer 61 according to some embodiments.

[0169] 8) Form connecting electrode 424;

[0170] A third sacrificial layer film is deposited, and the third sacrificial film is wet-etched to retain the third sacrificial layer film located between adjacent second sacrificial layers 61 along the direction perpendicular to substrate 1 and between adjacent second holes K2 along the second direction Y. The third sacrificial layer film covering the topmost second sacrificial layer 61 and the second hole K2 is retained to form a third sacrificial layer 62. The third sacrificial layer 62 and the second sacrificial layer 61 are connected to form a structure that fills the space between adjacent second holes K2 along the second direction Y and extends along the direction perpendicular to substrate 1.

[0171] A fourth insulating film is deposited to fill the area between adjacent first capacitor electrodes 41 along a direction perpendicular to the substrate 1. The fourth insulating film in the first trench T1 is etched away to expose the second sub-electrode 422 facing the first trench T1, forming a fourth insulating layer 14. The fourth insulating layer 14 also covers the side of the first hole K1 away from the substrate 1.

[0172] A fourth conductive film is deposited and smoothed to form a connecting electrode 424. The connecting electrode 424 fills the first trench T1 and is connected to the second sub-electrode 422, which is also connected to the second sub-electrode 422 of a capacitor at the same position in a different layer. When smoothing the fourth conductive film, the first hard mask layer 7 is removed; as shown in Figures 9A, 9B, and 9C. Figure 9A is a cross-sectional view along the AA' direction after forming the connecting electrode 424 according to some embodiments; Figure 9B is a cross-sectional view along the CC' direction after forming the connecting electrode 424 according to some embodiments; and Figure 9C is a cross-sectional view along the EE' direction after forming the connecting electrode 424 according to some embodiments.

[0173] 9) Form the second transverse groove V2;

[0174] A fifth insulating film is deposited to form a fifth insulating layer 15, which covers the structure formed in the preceding steps;

[0175] The first dummy layer 91 in the second hole K2 is removed by etching; the first dummy layer 91 can be removed by dry etching.

[0176] Based on the second hole K2, the second barrier layer 82 is wet-etched so that the bit line 30 is exposed in the second hole K2;

[0177] Based on the second hole K2, the third sacrificial layer 62 is wet-etched laterally, so that the fourth insulating layer 14 is exposed in the second hole K2; and along the EE' direction, the aperture of the sub-hole of the second hole K2 in the conductive layer is smaller than the aperture of the sub-hole in the insulating layer, so that when the semiconductor thin film is subsequently deposited, the semiconductor thin film located in the insulating layer is more outward than the semiconductor thin film located in the conductive layer, which facilitates the subsequent removal of the interlayer semiconductor thin film by the external removal method.

[0178] Based on the second hole K2, the fourth insulating layer 14 and the first insulating layer 11 are wet-etched laterally to form a second lateral groove V2, as shown in Figures 10A, 10B, and 10C. Figure 10A is a cross-sectional view along the AA' direction after the formation of the second lateral groove V2 according to some embodiments; Figure 10B is a cross-sectional view along the CC' direction after the formation of the second lateral groove V2 according to some embodiments; and Figure 10C is a cross-sectional view along the EE' direction after the formation of the second lateral groove V2 according to some embodiments.

[0179] 10) Forming a semiconductor layer 23, a gate insulating layer 24, and a word line 40;

[0180] A fourth dummy layer film is deposited, and the fourth dummy layer film in the second hole K2 is etched away, while the fourth dummy layer film in the second transverse groove V2 is retained to form the fourth dummy layer 94.

[0181] A semiconductor thin film, a gate insulating film, and a fifth conductive film are deposited sequentially. The fifth conductive film fills the second hole K2 and the second lateral groove V2 to form a semiconductor layer 23, a gate insulating layer 24, and a word line 40. The layer is then polished until the first capacitor electrode 41 of the top layer is exposed on the side facing away from the substrate 1, as shown in Figures 11A, 11B, and 11C. Figure 11A is a cross-sectional view along the AA' direction after the formation of the semiconductor layer 23, gate insulating layer 24, and word line 40 in some embodiments; Figure 11B is a cross-sectional view along the CC' direction after the formation of the semiconductor layer 23, gate insulating layer 24, and word line 40 in some embodiments; and Figure 11C is a cross-sectional view along the EE' direction after the formation of the semiconductor layer 23, gate insulating layer 24, and word line 40 in some embodiments. At this point, the semiconductor layers 23 of transistors at the same location in different layers are interconnected.

[0182] In some embodiments, the material of the semiconductor thin film may be silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or it may be a wide band gap material, such as a metal oxide material with a band gap of greater than 1.65 eV.

[0183] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.

[0184] In some embodiments, the material of the metal oxide semiconductor layer or channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), and indium tungsten oxide (InWO4). Materials such as IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) can be used. As long as the leakage current of the transistor meets the requirements, it is acceptable. The specific requirements can be adjusted according to the actual situation.

[0185] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.

[0186] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0187] In some embodiments, the material of the gate insulating layer 24 may comprise one or more high-K dielectric materials. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary examples include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0188] In some embodiments, the word line 40 may include a first sub-layer 31 and a second sub-layer 32. The first sub-layer 31 may be a conductive film layer with good adhesion, such as TiN, and the second sub-layer 32 may be a conductive material with low resistivity, such as tungsten. The first sub-layer 31 covers the bottom and sidewalls of the second hole K2 and the second transverse groove V2, and the second sub-layer 32 fills the second hole K2 and the second transverse groove V2.

[0189] 11) Disconnect the semiconductor layer 23 of multiple transistors at the same location on different layers;

[0190] The second sacrificial layer 61 and the third sacrificial layer 62 are etched away to expose the fourth dummy layer 94.

[0191] The fourth dummy layer 94 surrounding the semiconductor layer 23 is etched away, exposing the semiconductor layer film between adjacent transistors along the direction perpendicular to the substrate 1; the semiconductor layer 23 of the transistor is covered by the first barrier layer 81; when the semiconductor film between adjacent layers is subsequently etched, the semiconductor layer 23 of the transistor will not be etched due to the protection of the first barrier layer 81.

[0192] The exposed semiconductor layer film is removed by etching; at this time, the semiconductor layers 23 of transistors at the same position in different layers are disconnected; as shown in Figures 12A, 12B, and 12C. Among them, Figure 12A is a cross-sectional view along the AA' direction after the semiconductor layers 23 of different layers are disconnected according to some embodiments, Figure 12B is a cross-sectional view along the CC' direction after the semiconductor layers 23 of different layers are disconnected according to some embodiments, and Figure 12C is a cross-sectional view along the EE' direction after the semiconductor layers 23 of different layers are disconnected according to some embodiments.

[0193] The solution provided in this embodiment disconnects the semiconductor layers 23 between different layers by external removal. When removing the semiconductor thin film between layers using this method, the second sacrificial layer 61 and the third sacrificial layer 62 can be removed by etching. No additional photomask is required to form holes or trenches. The process is simple and low-cost. Furthermore, there is no need to reserve space for holes or trenches during external removal, which is beneficial for reducing the size of the memory cell and increasing the device density.

[0194] 12) Form the first dielectric layer 431 and the first sub-electrode 421;

[0195] A sixth insulating film is deposited to form an isolation layer 6, which fills the region between adjacent second holes K2 along the second direction Y.

[0196] Etching removes the second dummy layer 92 and the third dummy layer 93 in the first initial hole K1 and the first transverse groove V1; exposing the inner wall of the first capacitor electrode 41;

[0197] The fourth insulating layer 14 and the isolation layer 6 are etched to form a third lateral groove, exposing the outer wall of the first capacitor electrode 41 facing the substrate 1 and the outer wall facing away from the substrate 1, forming a third lateral groove between adjacent first capacitor electrodes 41 along a direction perpendicular to the substrate 1. In this step, the first capacitor electrode 41 is exposed except for the area in contact with the semiconductor layer 23, thereby increasing the facing area between the first capacitor electrode 41 and the subsequently formed first sub-electrode 421, and increasing the capacitance of the capacitor. However, the embodiments of this disclosure are not limited to this. For example, the outer wall of the first capacitor electrode 41 facing the substrate 1 and the outer wall facing away from the substrate 1 may not be exposed, that is, the first sub-electrode 421 may only be distributed on the inner wall of the first capacitor electrode 41.

[0198] A first dielectric film and a sixth conductive film are deposited sequentially to form a first dielectric layer 431 and a first sub-electrode 421; the first dielectric layer 431 covers the inner wall of the first capacitor electrode 41 and the inner wall of the third lateral groove (including the outer wall of the first capacitor electrode 41 facing the substrate 1 and the outer wall of the first capacitor electrode 41 away from the substrate 1); the first sub-electrode 421 fills the first initial hole K1, the first lateral groove V1 and the third lateral groove.

[0199] In some embodiments, the first sub-electrode 421 may include a third sub-layer 33 and a fourth sub-layer 34. The third sub-layer 33 may be a film layer with good adhesion, such as TiN, and the fourth sub-layer 34 may be a conductive material with low resistivity, such as tungsten. The third sub-layer 33 is distributed on the bottom wall and inner sidewall of the first capacitor electrode 41, as well as on the outer sidewall facing the substrate 1 and the outer sidewall facing away from the substrate 1. The fourth sub-layer 34 fills the first initial hole K1 and the first lateral groove V1, as shown in Figures 13A, 13B, and 13C. Figure 13A is a cross-sectional view along the AA' direction after the formation of the first dielectric layer 431 and the first sub-electrode 421 in some embodiments; Figure 13B is a cross-sectional view along the CC' direction after the formation of the first dielectric layer 431 and the first sub-electrode 421 in some embodiments; and Figure 13C is a cross-sectional view along the EE' direction after the formation of the first dielectric layer 431 and the first sub-electrode 421 in some embodiments. In Figures 13A, 13B, and 13C, the first transverse groove V1 and the third transverse groove have been filled by the first dielectric layer 431, so the first sub-electrode 421 is not distributed in the first transverse groove V1 and the third transverse groove. However, it is not limited to this. When the thickness of the first dielectric layer 431 is small and it does not fill the first transverse groove V1 and the third transverse groove, the first sub-electrode 421 fills the first transverse groove V1 and the third transverse groove. That is, the first sub-electrode 421 fills the area formed by the first initial hole K1, the first transverse groove V1, and the third transverse groove of the first dielectric layer 431.

[0200] The solution provided in this embodiment only requires three photomasks (the photomasks used to form the first hole, the second hole, and the first trench). No photomasks are needed when manufacturing bit lines, which simplifies the process, reduces costs, and eliminates the need to reserve space for etching grooves for bit line manufacturing, thereby reducing device size and increasing device density.

[0201] This disclosure also provides an electronic device, including the semiconductor device described in any of the foregoing embodiments, or a semiconductor device formed by the manufacturing method of the semiconductor device described in any of the foregoing embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0202] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, comprising: a plurality of memory cells stacked along a vertical substrate direction at different levels; word lines extending along a vertical direction of the substrate through the memory cells at different levels; a plurality of bit lines distributed at different levels, the word lines and the bit lines being distributed along a first direction parallel to the substrate, the bit lines extending along a second direction parallel to the substrate, the first and second directions intersecting; the memory cells including transistors, the transistors including semiconductor layers surrounding the word lines, the semiconductor layers connecting the bit lines, the bit lines conforming to a profile of sidewalls of the semiconductor layers on a side of the semiconductor layers facing the bit lines; a plurality of the semiconductor layers of a plurality of transistors at the same position at different levels being spaced apart on sidewalls of the word lines; an insulating layer being provided between adjacent bit lines along a direction perpendicular to the substrate, a first blocking layer being provided between the bit lines and the insulating layer, the first blocking layer covering a side of the bit lines facing the insulating layer; the transistors further including first electrodes connected to the semiconductor layers, the first electrodes being provided on a side of the word lines facing away from the bit lines; the first electrodes forming a ring-shaped recess, the ring-shaped recess including a bottom wall perpendicular to the substrate and two sidewalls parallel to the substrate, the bottom wall including an inner bottom wall inside the ring-shaped recess and an outer bottom wall outside the ring-shaped recess, the semiconductor layers being connected to a portion of the outer bottom wall; the memory cells further including capacitors, the capacitors and the transistors of the same memory cell being distributed along the first direction; the capacitors including first capacitor electrodes and second capacitor electrodes, the first electrodes being multiplexed as the first capacitor electrodes of the capacitors, the second capacitor electrodes including first sub-electrodes, the first capacitor electrodes surrounding the first sub-electrodes, the first sub-electrodes being distributed on inner walls of the ring-shaped recess formed by the first electrodes, the first sub-electrodes of memory cells at the same position at different levels being connected to form an integrated structure extending along a direction perpendicular to the substrate; sidewalls of the ring-shaped recess including inner sidewalls inside the ring-shaped recess and outer sidewalls outside the ring-shaped recess, the first sub-electrodes being further distributed on the outer sidewalls of the ring-shaped recess; the outer bottom wall of the ring-shaped recess including a first region, a second region spaced apart from the first region along a surrounding direction of the ring-shaped recess, and two intermediate regions respectively provided on two sides of the first region and spaced apart from the first region and the second region, the first region being on a side of the ring-shaped recess facing the bit lines, the semiconductor layers being distributed on the first region and connected to the first region, the second capacitor electrodes further including second sub-electrodes, the second sub-electrodes being distributed on the second region of the outer bottom wall of the ring-shaped recess; a second dielectric layer being provided between the first capacitor electrodes and the second sub-electrodes, the second dielectric layers of the capacitors at the same position at different levels being spaced apart along a direction perpendicular to the substrate; the memory cells at the same level being arrayed along the first direction and the second direction, the second sub-electrodes of a plurality of memory cells at the same column and the same level along the second direction being connected to form an integrated structure. ​ ​ ​ ​ ​ ​ 2. The semiconductor device of claim 1, wherein, ​ ​ 3. The semiconductor device of claim 2, wherein, ​ ​ 4. The semiconductor device of claim 3, wherein, ​ 5. The semiconductor device of claim 3, wherein, ​ 6. The semiconductor device of claim 5, wherein, ​ 7. The semiconductor device of claim 6, wherein, ​ 8. The semiconductor device of claim 7, wherein, Each two columns of memory cells distributed along the first direction are connected to the same bit line.

9. The semiconductor device of claim 8, wherein, The second sub-electrode of the memory cell at the same position of different layers, the first electrode adjacent along the second direction, the semiconductor layer adjacent along the second direction, and the region defined by the bit line to which the semiconductor layer is connected are filled with an isolation layer extending along a direction perpendicular to the substrate direction, and a second barrier layer is arranged between the isolation layer and the first electrode, the semiconductor layer, and the bit line, and the isolation layer is connected to the second dielectric layer.

10. The semiconductor device of claim 9, wherein, The semiconductor device further comprises: insulating layers and conductive layers distributed along a direction perpendicular to the substrate direction alternately; a first hole penetrating through the insulating layers and the conductive layers; the first hole comprises a first sub-hole located in the insulating layer and a second sub-hole located in the conductive layer, and the second sub-hole has a first groove extending along a direction parallel to the substrate direction relative to the first sub-hole; the first electrode is distributed on the inner wall of the first groove, and the first electrode, a first dielectric layer, and the first sub-electrode are sequentially distributed from outside to inside in the first hole.

11. The semiconductor device of claim 10, wherein, The semiconductor device further comprises: a second hole penetrating through the insulating layers and the conductive layers; the second hole comprises a third sub-hole located in the insulating layer and a fourth sub-hole located in the conductive layer, and the third sub-hole has a second groove extending along a direction parallel to the substrate direction relative to the fourth sub-hole; the semiconductor layer is distributed on the side wall of the fourth sub-hole, and the semiconductor layer, a gate insulating layer, and the word line are sequentially distributed from outside to inside in the second hole.

12. The semiconductor device of claim 11, wherein, The gate insulating layers of the memory cells at the same position of different layers are connected to form an integrated structure extending along a direction perpendicular to the substrate direction, and the isolation layer and the gate insulating layer are connected in the region of the insulating layer.

13. A manufacturing method of a semiconductor device, comprising: forming a stack structure comprising alternately arranged first insulating layers and first sacrificial layers on a substrate; forming a plurality of second holes spaced along a second direction penetrating through the stack structure along a direction perpendicular to the substrate direction; forming a plurality of first holes spaced along the second direction penetrating through the stack structure along a direction perpendicular to the substrate direction, and the first holes are spaced along a first direction from the second holes, based on etching the first sacrificial layers along a direction parallel to the substrate direction, a first lateral groove is formed, and the first holes and the second holes are communicated in the first lateral groove; a first electrode is formed on the inner wall of the first lateral groove; forming a first trench penetrating through the stack structure and extending along the second direction on the side of the first hole away from the second hole, and based on etching the first trench, the first sacrificial layers are removed; sequentially depositing a first barrier layer film and a first conductive film, the first conductive film fills the region between adjacent first insulating layers, the first barrier layer film is distributed on the side of the first insulating layer facing the substrate and the side away from the substrate, and the first conductive film is etched to form a bit line located between adjacent first insulating layers and extending along the second direction, and the bit line is distributed on the side wall of the second hole away from the first hole. forming a plurality of semiconductor layers and a word line filling the second hole in the second hole, the plurality of semiconductor layers surrounding the word line and being spaced apart on the sidewall of the word line, the plurality of semiconductor layers being connected with different layers of the bit line and the first electrode respectively.

14. The method of manufacturing a semiconductor device according to Claim 13, wherein forming a plurality of semiconductor layers and a word line filling the second hole in the second hole includes: forming a second sacrificial layer filling between adjacent first insulating layers and being located between adjacent first holes in the second direction and being located on the side of the first hole toward the second hole, and a second space being provided between the second sacrificial layer and the bit line; there is a second barrier layer; the first insulating layer is replaced by a second insulating layer and a third sacrificial layer, the third sacrificial layer being located between adjacent second sacrificial layers in a direction perpendicular to the substrate and being located between adjacent second holes in the second direction, and being connected with the second sacrificial layer; exposing the inner wall of the second hole and making the sidewall of the second hole expose the bit line, based on the second hole etching the third sacrificial layer in the direction parallel to the substrate, and based on the second hole etching the second insulating layer and the first insulating layer in the direction parallel to the substrate, so that the second hole is located in the sub-hole of the third sacrificial layer relative to the sub-hole of the second sacrificial layer with a second lateral groove extending in the horizontal direction; forming a dummy layer on the inner wall of the second lateral groove; sequentially depositing a semiconductor thin film, a gate insulating thin film and a second conductive thin film filling the second hole in the second hole, to form a plurality of semiconductor layers, a plurality of gate insulating layers and a word line; etching to remove the second sacrificial layer and the third sacrificial layer, etching to remove the dummy layer; etching to remove the semiconductor thin film covered by the dummy layer, so that the plurality of semiconductor layers are disconnected.

15. The semiconductor device manufacturing method of claim 14, further comprising: The method further comprises: exposing the first hole and the first lateral groove, and forming a first sub-electrode in the first hole and the first lateral groove.

16. The semiconductor device manufacturing method of claim 15, wherein, Before forming the first sub-electrode in the first hole and the first lateral groove, further comprising: exposing the first electrode on the side away from the substrate and on the side toward the substrate, and forming a third lateral groove; forming a first sub-electrode in the first hole, the first lateral groove and the third lateral groove.

17. The method of manufacturing a semiconductor device according to Claim 16, wherein After forming the second sacrificial layer, before replacing the first insulating layer with the second insulating layer and the third sacrificial layer, further comprising: forming a second sub-electrode distributed on the side of the first electrode away from the bit line; After replacing the first insulating layer with the second insulating layer and the third sacrificial layer, further comprising: forming a connection electrode filling the first groove and connected with the second sub-electrode.

18. An electronic device comprising the semiconductor device of any one of claims 1 to 12, or a semiconductor device formed according to the semiconductor device manufacturing method of any one of claims 13 to 17.

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