Semiconductor device and manufacturing method therefor, and electronic device

Abstract

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: a plurality of layers of memory cell arrays stacked in a direction perpendicular to a substrate (1), each memory cell array comprising at least one column of memory cells distributed in a second direction parallel to the substrate (1); a plurality of bit lines (30), the bit lines (30) extending vertically through memory cells in different layers, the memory cells in the same layer and in the same column being respectively connected to bit lines (30) distributed at intervals in the second direction, and the bit lines (30) to which every two adjacent columns of memory cells are respectively connected being located in the same trench extending in the second direction; and a plurality of word lines (40), extending in the second direction and distributed in different layers, the word lines (40) and the bit lines (30) being distributed in a first direction. The memory cells comprise transistors. Semiconductor layers (23) of the transistors surround the word lines (40), and semiconductor layers (23) of transistors at the same positions in different layers are connected to the same bit line (30).

Description

A semiconductor device and its manufacturing method, and an electronic device.

[0001] This application claims priority to Chinese Patent Application No. 2024110170924, filed on July 26, 2024, entitled "A Semiconductor Device and a Method for Manufacturing the Same Thereof, and an Electronic Device", the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and electronic equipment. Background Technology

[0003] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0004] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands.

[0005] Summary of the Invention

[0006] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0007] This application provides a semiconductor device, including:

[0008] A multilayer array of memory cells stacked perpendicular to the substrate, the array comprising a plurality of memory cells distributed along a first direction and a second direction; the first direction and the second direction intersect.

[0009] Multiple bit lines extend through the memory cells in different layers along a direction perpendicular to the substrate; memory cells in the same layer and column are respectively connected to multiple bit lines spaced apart along a second direction, and adjacent memory cells along a first direction are connected to different bit lines, and the multiple bit lines connected to each pair of adjacent columns of memory cells are located in the same trench extending along the second direction.

[0010] Multiple word lines are distributed in different layers, the word lines and the bit lines are distributed along the first direction, and the word lines extend along the second direction;

[0011] The memory cell includes a transistor, the transistor including a semiconductor layer surrounding the word line, the semiconductor layer having a sidewall facing the bit line and perpendicular to the substrate connected to the bit line, and multiple semiconductor layers of multiple transistors at the same position on different layers being connected to the same bit line.

[0012] In some embodiments, two bit lines connected to memory cells adjacent to each other along the first direction in the same trench are spaced apart along the first direction.

[0013] In some embodiments, a first air gap extending perpendicular to the substrate direction is provided between two adjacent bit lines in the same trench along a first direction.

[0014] In some embodiments, a second air gap is provided between adjacent first air gaps in the same trench along a second direction and is spaced apart from the first air gap and extends in a direction perpendicular to the substrate.

[0015] In some embodiments, the transistor further includes a first electrode disposed on the word line on the side opposite to the bit line;

[0016] The first electrode forms an annular groove, the annular groove including a bottom wall perpendicular to the substrate and two side walls parallel to the substrate. The bottom wall includes an inner bottom wall located within the annular groove and an outer bottom wall located outside the annular groove. The outer bottom wall of the annular groove includes a first region and a second region sequentially distributed along the circumferential direction of the annular groove. The first region is located on the side of the annular groove facing the bit line. The word line is distributed on the first region. The semiconductor layer is connected to a portion of the first region.

[0017] In some embodiments, the memory cell further includes a capacitor, wherein the capacitor and the transistor in the same memory cell are distributed along the first direction;

[0018] The capacitor includes a first capacitor electrode and a second capacitor electrode; the first electrode is reused as the first capacitor electrode of the capacitor; the second capacitor electrode includes a first sub-electrode, the first capacitor electrode surrounds the first sub-electrode, and a first dielectric layer is disposed between the first capacitor electrode and the first sub-electrode; the first sub-electrode is distributed on the inner wall of the annular groove formed by the first electrode; the first sub-electrodes of the storage cells at the same position in different layers are connected to form an integral structure.

[0019] In some embodiments, the sidewall of the annular groove includes an inner sidewall located within the annular groove and an outer sidewall located outside the annular groove, and the first sub-electrode is also distributed on the outer sidewall of the annular groove.

[0020] In some embodiments, the second capacitor electrode further includes a second sub-electrode, which is distributed on the second region of the outer bottom wall of the annular groove.

[0021] In some embodiments, the second sub-electrodes of a plurality of memory cells distributed in the same layer and column along the second direction are connected to form an integral structure.

[0022] In some embodiments, the word lines are also distributed on the sidewall of an integral structure formed by connecting the second sub-electrodes of a plurality of memory cells in the same layer and column distributed along the second direction, facing the bit lines.

[0023] In some embodiments, a second dielectric layer is disposed between the first capacitor electrode and the second sub-electrode, and the second dielectric layers of capacitors at the same position in different layers are connected to form an integral structure.

[0024] In some embodiments, the semiconductor device further includes:

[0025] An insulating layer and a conductive layer are alternately distributed along a direction perpendicular to the substrate;

[0026] A first hole penetrating the insulating layer and the conductive layer; the first hole includes a first sub-hole located in the insulating layer and a second sub-hole located in the conductive layer, the second sub-hole having a groove extending in a direction parallel to the substrate relative to the first sub-hole;

[0027] The first electrode is distributed on the inner wall of the groove, and the first electrode, the first dielectric layer, and the first sub-electrode are distributed sequentially from the outside to the inside in the first hole.

[0028] In some embodiments, the semiconductor layers of a plurality of memory cells in the same column distributed along a second direction are spaced apart along the second direction and surround the same word line.

[0029] In some embodiments, the transistor further includes a gate insulating layer disposed between the semiconductor layer and the word line; the gate insulating layers of a plurality of transistors in the same layer and column on the side of the semiconductor layer facing the bit line are disconnected; and the gate insulating layers of a plurality of transistors in the same layer and column on the side of the semiconductor layer away from the bit line are connected to form an integral structure.

[0030] In some embodiments, a third air gap is provided between adjacent semiconductor layers in the same layer along a second direction, at least partially surrounding the word line.

[0031] In some embodiments, the third air gap includes a first sub-air gap and a second sub-air gap, wherein:

[0032] The first sub-air gap is distributed on the word line facing the bit line side and extends from the word line facing the bit line side to the word line facing the substrate side and away from the substrate side, respectively. On the word line facing the bit line side, the first sub-air gap extends between adjacent semiconductor layers and breaks at adjacent gate insulating layer breaks; on the side facing the substrate and the side away from the substrate side, the first sub-air gap extends continuously in a second direction between adjacent semiconductor layers.

[0033] The second sub-air gap is distributed on the word line away from the bit line and extends from the word line away from the bit line to the word line facing the substrate and away from the substrate, respectively; on the word line away from the bit line, the second sub-air gap includes two parts distributed in the first region of adjacent first electrodes and disconnected from each other; on the side facing the substrate and the side away from the substrate, the second sub-air gap extends continuously in a second direction between adjacent semiconductor layers.

[0034] This disclosure provides a method for manufacturing a semiconductor device, including:

[0035] A stacked structure comprising alternating first insulating layers and sacrificial layers is formed on a substrate;

[0036] A plurality of first holes are formed that are spaced apart along a second direction through the stacked structure perpendicular to the substrate direction; the sacrificial layer is etched along a direction parallel to the substrate based on the first holes to form a first lateral groove; and first electrodes are formed distributed on the inner wall of the first lateral groove.

[0037] A first trench is formed that penetrates the stacked structure and extends along the second direction; the first trench and the first hole are spaced apart along the first direction; two rows of bit lines are formed in the first trench that are spaced apart along the first direction, each row of bit lines is spaced apart along the second direction, the bit lines extend along the direction perpendicular to the substrate and penetrate the stacked structure; the first direction and the second direction intersect.

[0038] Based on the first trench, the sacrificial layer is etched along a direction parallel to the substrate to expose the side of the first electrode facing the bit line, forming a first lateral trench;

[0039] A word line extending in a second direction is formed in the first lateral trench, and a plurality of semiconductor layers are spaced apart in the second direction around the word line, the semiconductor layers being connected to the first electrode and the bit line respectively.

[0040] In some embodiments, forming two spaced-apart lines in the first trench along a first direction includes:

[0041] A first dummy layer is formed to fill the first trench;

[0042] A plurality of second holes are formed in the first trench, which penetrate the stacked structure along a second direction perpendicular to the substrate, and the sidewalls of the second holes expose the first insulating layer and the sacrificial layer.

[0043] A bit line layer is formed covering the sidewalls and bottom wall of the plurality of second holes; the bit line layer covering the bottom wall of the plurality of second holes is etched away; a second insulating layer is formed to fill the second holes, wherein the second insulating layer is a solid structure or the second insulating layer includes a first air gap extending in a direction perpendicular to the substrate.

[0044] Etching removes the first dummy layer in the first trench;

[0045] The bit line layer is etched such that the bit line layer within each second hole is divided into two bit lines spaced apart along a first direction, the bit lines being distributed on the first insulating layer and the sacrificial layer exposed on the sidewalls of the second hole.

[0046] In some embodiments, etching the sacrificial layer along a direction parallel to the substrate to expose the first electrode facing the bit line, thereby forming a first lateral trench, includes:

[0047] An insulating film is deposited to fill the first trench;

[0048] A second groove is formed on the side of the first hole opposite to the first groove, penetrating the stacked structure and extending along the second direction;

[0049] Based on the second trench, the sacrificial layer is etched along a direction parallel to the substrate, and the sacrificial layer located between the first hole and the bit line is retained to form a second lateral trench, wherein the retained sacrificial layer is connected to the first electrode;

[0050] A third hole is formed between adjacent second holes in the first trench, penetrating the stacked structure;

[0051] Based on the third hole, the sacrificial layer is etched along a direction parallel to the substrate to expose the side of the first electrode facing the bit line, forming the first lateral trench;

[0052] The formation of word lines extending in a second direction in the first lateral trench, and the plurality of semiconductor layers spaced apart in the second direction around the word lines, include:

[0053] A semiconductor thin film, a gate insulating film, and a conductive thin film are sequentially deposited to cover the inner wall of the third hole and the inner wall of the first lateral trench, and the conductive thin film fills the first lateral trench, forming multiple semiconductor layers, multiple gate insulating layers, and word lines that are connected to form an integral structure; the multiple semiconductor layers that are connected to form an integral structure are composed of a first part and a second part distributed along a first direction, and the first part is disposed on the side of the second part facing the bit lines;

[0054] The semiconductor thin film, the gate insulating film, and the conductive film are etched to remove the semiconductor thin film, the gate insulating film, and the conductive film from the third hole, and to divide the first portion into multiple segments distributed along the second direction, each segment being connected to a bit line;

[0055] The second portion is etched based on the second trench and the second lateral trench, such that the multiple semiconductor layers of the integral structure are formed into multiple semiconductor layers spaced apart along the second direction.

[0056] In some embodiments, after etching the semiconductor thin film, the gate insulating thin film, and the conductive thin film, and before etching the second portion based on the second trench and the second lateral trench, the method further includes:

[0057] A third insulating layer is formed to fill the etched areas of the third hole and the semiconductor thin film, gate insulating film, and conductive thin film. The third insulating layer is a solid structure. Alternatively, the third insulating layer includes a plurality of second air gaps and a plurality of first sub-air gaps. The second air gaps are disposed within the third hole and extend in a direction perpendicular to the substrate. The first sub-air gaps partially surround the word line, are distributed on the side of the word line facing the bit line, and extend from the side of the word line facing the bit line to the side of the word line facing the substrate and the side away from the substrate, respectively. On the side of the word line facing the bit line, the first sub-air gaps extend between adjacent semiconductor layers and are interrupted at the connection between the second hole and the first lateral trench. On the side facing the substrate and the side away from the substrate, the first sub-air gaps extend continuously in a second direction between adjacent semiconductor layers.

[0058] In some embodiments, after forming the first electrode distributed on the inner wall of the first transverse groove and before forming the first trench extending through the stacked structure and along the second direction, the method further includes:

[0059] The first hole and the first lateral groove on which the first electrode is formed are exposed, and the side of the first electrode facing away from the substrate and the side facing the substrate are exposed, forming a second lateral groove;

[0060] A first sub-electrode is formed within the first hole, the first transverse groove, and the second transverse groove, filling the first hole, the first transverse groove, and the second transverse groove.

[0061] In some embodiments, after etching the second portion based on the second trench and the second lateral trench, the method further includes:

[0062] A dielectric film and a conductive film are sequentially deposited in the second trench, the second lateral trench, and the region formed after the second portion is etched to form a second dielectric layer and a second sub-electrode. The second dielectric layer is a solid structure covering the inner walls of the second trench, the second lateral trench, and the region formed after the second portion is etched; alternatively, the second dielectric layer forms a plurality of second sub-air gaps. The second sub-air gaps are distributed on the word line away from the bit line and extend from the word line away from the bit line to the word line facing the substrate and away from the substrate, respectively. On the word line away from the bit line, the second sub-air gaps are distributed in the region where the adjacent first electrode along the second direction is exposed to the first lateral trench and does not contact the semiconductor layer. On the side facing the substrate and the side away from the substrate, the second sub-air gaps extend continuously along the second direction between adjacent semiconductor layers.

[0063] The second sub-electrode fills the second trench, the second lateral trench, and the area formed after the second portion is etched.

[0064] This disclosure provides an electronic device, including any of the semiconductor devices described above, or a semiconductor device formed according to the manufacturing method of any of the semiconductor devices described above.

[0065] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.

[0066] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0067] Overview of the attached figures

[0068] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0069] Figures 1A, 1B, 1C, and 1D are cross-sectional views of semiconductor devices provided in some embodiments along the directions AA', CC', EE', and FF'.

[0070] Figures 2A, 2B, and 2C are cross-sectional views along the directions AA', CC', and FF' after the formation of the first hole, as provided in some embodiments.

[0071] Figures 3A, 3B, and 3C are cross-sectional views along the AA', CC', and FF' directions after the formation of the first capacitor electrode, as provided in some embodiments.

[0072] Figures 4A, 4B, and 4C are cross-sectional views along the AA', CC', and FF' directions after the formation of the first dielectric layer and the first sub-electrode, respectively, according to some embodiments.

[0073] Figures 5A, 5B, and 5C are cross-sectional views along the directions AA', CC', and FF' after the formation of the first trench, as provided in some embodiments.

[0074] Figures 6A, 6B, and 6C are cross-sectional views along the AA', CC', and DD' directions after the bit line layer is formed, according to some embodiments.

[0075] Figures 7A, 7B, and 7C are cross-sectional views along the AA', CC', and DD' directions after the formation of the fourth insulating layer, as provided in some embodiments.

[0076] Figures 8A, 8B, and 8C are cross-sectional views along the AA', CC', and DD' directions after bit lines are formed, as provided in some embodiments.

[0077] Figures 9A, 9B, and 9C are cross-sectional views along the directions AA', CC', and FF' after the second trench is formed, according to some embodiments.

[0078] Figures 10A, 10B, 10C, and 10D are cross-sectional views along the directions AA', CC', EE', and FF' after the formation of the first transverse trench, as provided in some embodiments.

[0079] Figures 11A, 11B, 11C, and 11D are cross-sectional views along the AA', CC', EE', and FF' directions after the formation of the semiconductor layer, gate insulating layer, and word line, respectively, according to some embodiments.

[0080] Figures 12A, 12B, 12C, and 12D are cross-sectional views along the directions AA', CC', EE', and FF' after disconnecting multiple semiconductor layers in the same column near the bit line side, according to some embodiments.

[0081] Figures 13A, 13B, 13C, and 13D are cross-sectional views along the directions AA', CC', EE', and FF' after disconnecting multiple semiconductor layers in the same column from one side of the bit line, according to some embodiments.

[0082] Figures 14A, 14B, 14C, 14D, and 14E are cross-sectional views along the AA', CC', DD', EE', and FF' directions of a semiconductor device with an air gap formed according to some embodiments.

[0083] Figures 15A, 15B, and 15C are cross-sectional views along the directions AA', CC', and DD' after the formation of the first air gap, as provided in some embodiments.

[0084] Figures 16A, 16B, and 16C are cross-sectional views along the AA', CC', and DD' directions after bit lines are formed, according to some embodiments.

[0085] Figures 17A, 17B, and 17C are cross-sectional views along the AA', CC', and FF' directions after the second trench is formed, according to some embodiments.

[0086] Figures 18A, 18B, 18C and 18D are cross-sectional views along the directions AA', CC', EE' and FF' after the formation of the first transverse groove according to some embodiments;

[0087] Figures 19A, 19B, 19C and 19D are cross-sectional views along the directions AA', CC', EE' and FF' after disconnecting multiple semiconductor layers in the same column near the bit line side according to some embodiments;

[0088] Figures 20A, 20B, 20C, and 20D are cross-sectional views along the directions AA', CC', EE', and FF' after disconnecting the semiconductor layers of different transistors in the same column according to some embodiments.

[0089] Detailed Explanation

[0090] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0091] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0092] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0093] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0094] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0095] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0096] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0097] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0098] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0099] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0100] In this embodiment of the disclosure, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with interconnected relationships.

[0101] In this embodiment of the disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0102] Figures 1A, 1B, 1C, and 1D are cross-sectional views of a semiconductor device provided in some embodiments along directions parallel to substrate 1 (AA'), and perpendicular to substrate 1 (CC', EE', and FF'). As shown in Figures 1A to 1D, an embodiment of this application provides a semiconductor device, including:

[0103] A multilayer array of memory cells stacked along a direction perpendicular to substrate 1, the array comprising a plurality of memory cells distributed along a first direction X and a second direction Y; the first direction X and the second direction Y intersect.

[0104] Multiple bit lines 30 extend through the memory cells in different layers along a direction perpendicular to the substrate 1; memory cells in the same layer and column are respectively connected to multiple bit lines 30 spaced apart along the second direction Y; adjacent memory cells along the first direction X are connected to different bit lines 30; the multiple bit lines 30 connected to each pair of adjacent columns of memory cells are located in the same trench extending along the second direction Y.

[0105] Multiple word lines 40 are distributed in different layers. The word lines 40 and the bit lines 30 are distributed at intervals along the first direction X, and the word lines 40 extend along the second direction Y.

[0106] The memory cell includes a transistor, the transistor includes a semiconductor layer 23, the semiconductor layer 23 surrounds the word line 40, the semiconductor layer 23 is connected to the bit line 30 on the side facing the bit line 30 and perpendicular to the sidewall of the substrate 1, and multiple semiconductor layers 23 of multiple transistors at the same position on different layers are connected to the same bit line 30.

[0107] The solution provided in this embodiment connects adjacent memory cells to different bit lines, reducing the load on the bit lines and allowing the common bit line to be connected to more bit lines, thus increasing memory density. Furthermore, the structure of horizontal word lines and vertical bit lines reduces the coupling capacitance between word lines and bit lines.

[0108] The transistor may include a gate electrode 26, a first electrode 51 and a second electrode 52. The gate electrode 26 may be part of a word line 40. The gate electrodes 26 of transistors distributed in the same column along the second direction Y in the same layer may be connected to form a word line 40 with an integrated structure.

[0109] The second electrode 52 can be connected to the bit line 30, or the second electrode 52 can be part of the bit line 30. The second electrodes 52 of the transistors of the memory cells at the same position in different layers can be connected to the same bit line 30, or the second electrodes 52 of the transistors at the same position in different layers can be connected to the bit line 30 forming an integral structure extending perpendicular to the substrate 1.

[0110] In some embodiments, the first direction X and the second direction Y can be perpendicular.

[0111] In some embodiments, two bit lines 30 connected to memory cells adjacent to each other along the first direction X in the same trench are distributed at intervals along the first direction X.

[0112] Figures 14A, 14B, 14C, 14D, and 14E are cross-sectional views along the directions AA', CC', DD', EE', and FF' of a semiconductor device with air gaps provided in some embodiments. The DD' direction is perpendicular to the substrate 1. In this embodiment, a first air gap 81 extending perpendicular to the substrate 1 is provided between two adjacent bit lines 30 along the first direction X in the same trench. The solution provided in this embodiment reduces the coupling capacitance between adjacent bit lines 30 along the first direction X by providing air gaps, allowing the common bit line to connect more bit lines and increasing storage density.

[0113] In some embodiments, a second air gap 82 is provided between adjacent first air gaps 81 along the second direction Y in the same trench, spaced apart from the first air gaps 81 and extending in a direction perpendicular to the substrate 1. The solution provided in this embodiment can reduce the coupling capacitance between adjacent bit lines 30 along the second direction Y, allowing the common bit line to connect more bit lines and increasing the storage density.

[0114] In some embodiments, the transistor may further include a first electrode 51 disposed on the word line 40 on the side opposite to the bit line 30;

[0115] The first electrode 51 can form an annular groove, the annular groove including a bottom wall perpendicular to the substrate 1 and two side walls parallel to the substrate 1. The bottom wall includes an inner bottom wall located within the annular groove and an outer bottom wall located outside the annular groove. The outer bottom wall of the annular groove includes a first region and a second region sequentially distributed along the circumferential direction of the annular groove. The first region is located on the side of the annular groove facing the bit line 30. The word line 40 is distributed on the first region. The semiconductor layer 23 is connected to a portion of the first region.

[0116] In some embodiments, the transistor may further include a gate insulating layer 24 disposed between the semiconductor layer 23 and the word line 40; on the side of the semiconductor layer 23 facing the bit line 30, the gate insulating layers 24 of multiple transistors in the same layer and column may be disconnected; on the side of the semiconductor layer 23 away from the bit line 30, the gate insulating layers 24 of multiple transistors in the same layer and column may be connected to form an integral structure. Referring to FIG1A, the integral structure formed by the gate insulating layer 24 surrounding the word line 40 and the gate insulating layers 24 of multiple transistors in the same column has an opening on the side facing the bit line 30. This opening is formed during the manufacturing process of the semiconductor device when multiple semiconductor layers 23 are disconnected on the side facing the bit line 30. In some embodiments, this opening may extend to both the side of the word line 40 facing the substrate 1 and the side away from the substrate 1.

[0117] In some embodiments, the storage unit may be a 1T1C storage unit, or it may be a storage unit with other structures.

[0118] In some embodiments, when the memory cell is a 1T1C memory cell, the memory cell may further include a capacitor, and the capacitor and the transistor in the same memory cell are distributed along the first direction X; the capacitor, the word line 40, and the bit line 30 may be distributed along the first direction X.

[0119] The capacitor may include a first capacitor electrode 41 and a second capacitor electrode; the first electrode 51 may be reused as the first capacitor electrode 41 of the capacitor; the second capacitor electrode may include a first sub-electrode 421, the first capacitor electrode 41 surrounds the first sub-electrode 421, and a first dielectric layer 431 is disposed between the first capacitor electrode 41 and the first sub-electrode 421; the first sub-electrodes 421 are distributed on the inner wall (including the inner bottom wall and the inner side wall) of the annular groove formed by the first electrode 41; the first sub-electrodes 421 of the memory cells at the same position in different layers may be connected to form an integral structure. The solution provided in this embodiment can form the first sub-electrodes 421 of multiple capacitors in a single manufacturing process, simplifying the process and reducing costs.

[0120] In some embodiments, the sidewall of the annular groove includes an inner sidewall located within the annular groove and an outer sidewall located outside the annular groove. The first sub-electrode 421 may also be distributed on the outer sidewall of the annular groove. That is, the first sub-electrode 421 may be distributed on the inner wall (including the inner bottom wall and the inner sidewall) of the annular groove, and may also be distributed on the outer sidewall of the annular groove, thereby maximizing the facing area between the first sub-electrode 421 and the first capacitor electrode 41, and increasing the capacitance of the capacitor. However, the embodiments of this disclosure are not limited to this, and the first sub-electrode 421 may not be distributed on the outer sidewall surrounding the groove.

[0121] In some embodiments, the second capacitor electrode may further include a second sub-electrode 422, which is distributed on the second region of the outer bottom wall of the annular groove. A second dielectric layer 432 is disposed between the first capacitor electrode 41 and the second sub-electrode 422 to isolate the first capacitor electrode 41 and the second sub-electrode 422.

[0122] In some embodiments, the second sub-electrodes 422 of multiple memory cells distributed in the same layer and column along the second direction Y can be connected to form an integral structure. The solution provided in this embodiment can form the second sub-electrodes 422 of multiple capacitors in a single manufacturing process, simplifying the process and reducing costs.

[0123] In some embodiments, the word lines 40 may also be distributed on the sidewall of an integral structure formed by connecting the second sub-electrodes 422 of multiple memory cells distributed in the same layer and column along the second direction Y, facing the bit lines 30. The word lines 40 and the second sub-electrodes 422 are spaced apart by a second dielectric layer 432 and a gate insulating layer 24. That is, no additional insulating film layer is required between the word lines 40 and the second sub-electrodes 422, facilitating the formation of a straight structure for the word lines 40. Compared to a curved structure, this helps reduce the resistance of the word lines 40. Furthermore, with this structure, the word lines can be implemented without a photomask, thereby reducing the need for photomasks and lowering costs. Additionally, the device can be more compact, increasing device density.

[0124] In some embodiments, a second dielectric layer 432 is disposed between the first capacitor electrode 41 and the second sub-electrode 422. The second dielectric layers 432 of capacitors at the same position in different layers can be connected to form an integral structure. The solution provided in this embodiment can form the second dielectric layers 432 of multiple capacitors in a single manufacturing process, simplifying the process and reducing costs.

[0125] In some embodiments, the semiconductor device may further include:

[0126] An insulating layer and a conductive layer are alternately distributed along a direction perpendicular to the substrate; the conductive layer may include a first electrode 51;

[0127] A first hole penetrating the insulating layer and the conductive layer; the first hole includes a first sub-hole located in the insulating layer and a second sub-hole located in the conductive layer, the second sub-hole having a groove (i.e., a subsequent first lateral groove V1) extending in a direction parallel to the substrate 1 relative to the first sub-hole; that is, the orthographic projection of the first sub-hole onto the substrate 1 falls within the orthographic projection of the second sub-hole onto the substrate 1;

[0128] The first electrode 51 is distributed on the inner wall of the groove, and the first electrode 51, the first dielectric layer 431, and the first sub-electrode 421 are sequentially distributed from the outside to the inside in the first hole. Multiple first electrodes 51 are spaced apart on the sidewall of the first hole along a direction perpendicular to the substrate 1. The solution provided in this embodiment can form multiple first capacitor electrodes 41 (multiplexed with the first electrode 51), multiple first dielectric layers 431, and multiple first sub-electrodes 421 of capacitors in one step, simplifying the process.

[0129] In some embodiments, a plurality of semiconductor layers 23 of a plurality of memory cells distributed in the same column along the second direction Y are spaced apart along the second direction Y and surround the same word line 40.

[0130] In some embodiments, a third air gap is provided between adjacent semiconductor layers 23 in the same layer along the second direction Y, at least partially surrounding the word line 40.

[0131] In some embodiments, the third air gap may include a first sub-air gap 831 and a second sub-air gap 832, wherein:

[0132] The first sub-air gap 831 is distributed on the word line 40 facing the bit line 30 and extends from the word line 40 facing the bit line 30 to the word line 40 facing the substrate 1 and away from the substrate 1, respectively. On the word line 40 facing the bit line 30, the first sub-air gap 831 extends between adjacent semiconductor layers 23 and breaks at the break of adjacent gate insulating layer 24. On the word line 40 facing the substrate 1 and away from the substrate 1, the first sub-air gap 831 extends continuously along the second direction Y between adjacent semiconductor layers 23.

[0133] The second sub-air gap 832 is distributed on the side of the word line 40 away from the bit line 30 and extends from the side of the word line 40 away from the bit line 30 to the side of the word line 40 facing the substrate 1 and away from the substrate 1, respectively. On the side of the word line 40 away from the bit line 30, the second sub-air gap 832 includes two parts distributed in the first region of adjacent first electrodes 51 and disconnected from each other. On the side of the word line 40 facing the substrate 1 and the side away from the substrate 1, the second sub-air gap 832 extends continuously in the second direction Y between adjacent semiconductor layers 23. The solution provided in this embodiment, by setting the first sub-air gap 831 and the second sub-air gap 832, can reduce the coupling capacitance between word lines and between word lines and bit lines, so that more memory cells can be connected to the word lines, thereby increasing the memory density.

[0134] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor device in this embodiment. The "patterning process" mentioned in this embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes film coating, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."

[0135] In one exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0136] 101) Form the first hole;

[0137] A substrate 1 is provided, and a first insulating film and a sacrificial layer film are alternately deposited on the substrate 1 to form a stacked structure comprising a plurality of alternately arranged first insulating layers 11 and sacrificial layers 10;

[0138] The stacked structure is etched from the top layer to the bottom layer along a direction perpendicular to the substrate 1 (etching stops on the substrate 1) to form a plurality of first initial holes K1 spaced apart along the second direction Y; when manufacturing the memory array, the plurality of first initial holes K1 spaced apart along the second direction Y are referred to as a column of first initial holes K1, and multiple columns of first initial holes K1 can be formed; the multiple columns of first initial holes K1 are spaced apart along the first direction X.

[0139] Based on the first initial hole K1, the sacrificial layer 10 is etched laterally (parallel to the direction of substrate 1) to form a first lateral groove V1. The first initial hole K1 and the first lateral groove V1 constitute a first hole. The first sub-hole of the first hole located on the first insulating layer 11 is projected onto the substrate 1 in the orthogonal projection of the first hole located on the sacrificial layer 10 onto the substrate 1. This facilitates the subsequent formation of the first electrode 51 or the first capacitor electrode 41 in the second sub-hole, as shown in Figures 2A, 2B, and 2C. Figures 2A, 2B, and 2C are cross-sectional views along the AA', CC', and FF' directions after the formation of the first hole provided in some embodiments.

[0140] In some embodiments, substrate 1 may be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

[0141] In some embodiments, the first insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO2), etc. The materials of the subsequent second to seventh insulating films are similar and will not be described in detail.

[0142] In some embodiments, the sacrificial layer film may be a film layer that has an etching selectivity ratio with the first insulating film, such as silicon nitride (SiN).

[0143] In some embodiments, the first initial hole K1 along a cross section parallel to the substrate 1 can be circular, square, elliptical, etc.

[0144] 102) Form the first capacitor electrode 41;

[0145] A first conductive film and a first dummy layer film are deposited sequentially to form a first capacitor electrode 41 and a first dummy layer 91. The first conductive film covers the inner wall of the first initial hole K1 and the inner wall of the first transverse groove V1, and the first dummy layer film fills the first initial hole K1 and the first transverse groove V1.

[0146] The first dummy layer 91 in the first initial hole K1 is removed by etching, while the first dummy layer 91 in the first transverse groove V1 is retained;

[0147] The first conductive film in the first initial hole K1 is removed by etching, so that the multiple first capacitor electrodes 41 of multiple memory cells at the same position in different layers are disconnected; as shown in FIG3A, FIG3B and FIG3C, FIG3A, FIG3B and FIG3C are cross-sectional views along the AA', CC' and FF' directions after the formation of the first capacitor electrode 41 provided in some embodiments.

[0148] In some embodiments, the first dummy layer film may be a material with an etching selectivity ratio to the first insulating film and the sacrificial layer film, such as polysilicon. The materials of the subsequent second to third dummy layer films are similar to those of the first dummy layer film and will not be described again.

[0149] In some embodiments, the first conductive film may be one or more of the following different types of materials:

[0150] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can also be a metal alloy containing these metals.

[0151] Alternatively, it can be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as highly conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and aluminum-doped zinc oxide (AZO); or metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0152] Alternatively, it could be polycrystalline silicon, conductive doped semiconductor materials, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; or other materials that exhibit conductivity.

[0153] The materials of the subsequent second to fifth conductive films are similar to those of the first conductive film, and will not be described in detail again.

[0154] 103) Form the first dielectric layer 431 and the first sub-electrode 421;

[0155] The first dummy layer 91 is etched away to expose the inner wall of the first capacitor electrode 41, that is, the inner wall of the groove formed by the first capacitor electrode 41, including the inner bottom wall and the inner side wall.

[0156] Based on the first initial hole K1, the first insulating layer 11 is laterally etched to expose the outer wall of the first capacitor electrode 41 facing the substrate 1 and the outer wall of the first capacitor electrode 41 away from the substrate 1, forming a second lateral groove between adjacent first capacitor electrodes 41 along the direction perpendicular to the substrate 1.

[0157] A first dielectric film and a second conductive film are deposited sequentially to form a first dielectric layer 431 and a first sub-electrode 421; the first dielectric layer 431 covers the inner wall of the first capacitor electrode 41 and the inner wall of the second lateral groove (including the outer wall of the first capacitor electrode 41 facing the substrate 1 and the outer wall of the first capacitor electrode 41 away from the substrate 1); the first sub-electrode 421 fills the first initial hole K1, the first lateral groove V1 and the second lateral groove.

[0158] In some embodiments, the first sub-electrode 421 may include a first sub-layer 31 and a second sub-layer 32. The first sub-layer 31 may be a conductive thin film with good adhesion, such as TiN, and the second sub-layer 32 may be a conductive material with low resistivity, such as tungsten. The first sub-layer 31 is distributed on the inner bottom wall and inner sidewall of the first capacitor electrode 41, as well as on the outer sidewall facing the substrate 1 and the outer sidewall facing away from the substrate 1. The second sub-layer 32 fills the first initial hole K1, the first lateral groove V1, and the second lateral groove. As shown in Figures 4A, 4B, and 4C, Figures 4A, 4B, and 4C are cross-sectional views along the AA', CC', and FF' directions after the formation of the first dielectric layer 431 and the first sub-electrode 421 in some embodiments.

[0159] In Figures 4B and 4C, the second transverse groove is filled with the first dielectric layer 431, so the first sub-electrode 421 is not distributed in the second transverse groove. However, it is not limited to this. When the thickness of the first dielectric layer 431 is small and does not fill the second transverse groove, the first sub-electrode 421 fills the second transverse groove. That is, the first sub-electrode 421 fills the area formed by the first initial hole K1 of the first dielectric layer 431, the first transverse groove V1, and the second transverse groove.

[0160] In some embodiments, the first dielectric film may be a high-K dielectric material. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary examples include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials. The subsequent second dielectric film is similar to the first dielectric film and will not be described further.

[0161] 104) Formation of the first trench T1;

[0162] A second insulating film is deposited to form a second insulating layer 12 covering the first initial hole K1 and the topmost first insulating layer 11;

[0163] The stacked structure is etched along a direction perpendicular to the substrate 1 to form a first trench T1 that penetrates the stacked structure; the first trench T1 extends along the second direction Y and penetrates the stacked structure along the second direction Y, and a bit line 30 can be formed in the first trench T1 subsequently;

[0164] A second dummy layer film is deposited and smoothed to form a second dummy layer 92 that fills the first trench T1. The second dummy layer 92 is flush with the second insulating layer 12, as shown in Figures 5A, 5B, and 5C. Figures 5A, 5B, and 5C are cross-sectional views along the AA', CC', and FF' directions after the formation of the first trench T1 provided in some embodiments.

[0165] 105) Forming a bitline layer 30';

[0166] A third insulating film is deposited to form a third insulating layer 13 covering the structure formed in step 104;

[0167] The second dummy layer 92 is etched to form a plurality of second holes K2 spaced apart along the second direction Y. The second holes K2 expose the bottom wall of the first trench T1. The second dummy layer 92 is also etched through along the first direction X, exposing the sidewalls of the second holes K2 to the first insulating layer 11 and the sacrificial layer 10. In some embodiments, the second holes K2 can be formed first by dry etching in the second dummy layer 92, in which case the first insulating layer 11 and the sacrificial layer 10 are not exposed. Then, the second dummy layer 92 is wet-etched to expose the first insulating layer 11 and the sacrificial layer 10. Dry etching in the second dummy layer 92 is less technically demanding. Therefore, compared to directly dry etching to expose the first insulating layer 11 and the sacrificial layer 10 to form the second holes K2, performing wet etching after dry etching in the second dummy layer 92 results in a more controllable structure for the second holes K2.

[0168] After depositing the third conductive film, the surface is smoothed to form a bit line layer 30' covering the bottom and sidewalls of the second hole K2. The bit line layer 30' does not completely fill the second hole K2, that is, there are gaps in the second hole K2, as shown in Figures 6A, 6B, and 6C. Figures 6A, 6B, and 6C are cross-sectional views along the AA', CC', and DD' directions after the bit line layer 30' is formed, respectively, according to some embodiments.

[0169] In some embodiments, the second hole K2 along a cross section parallel to the substrate 1 can be circular, square, or the like.

[0170] 106) Forming the fourth insulating layer 14;

[0171] The bit line layer 30' on the bottom wall of the second hole K2 is etched away; at this time, the bit line layer 30' forms an annular structure covering the sidewall of the second hole K2;

[0172] A fourth insulating film is deposited and smoothed to form a fourth insulating layer 14 that fills the second hole K2. The fourth insulating layer 14 is flush with the second dummy layer 92. At this time, the third insulating layer 13 is removed. As shown in Figures 7A, 7B, and 7C, Figures 7A, 7B, and 7C are cross-sectional views along the AA', CC', and DD' directions after the formation of the fourth insulating layer 14 provided in some embodiments.

[0173] 107) Formation of bit line 30;

[0174] The second dummy layer 92 is removed by etching; the second dummy layer 92 can be removed by wet etching; the sidewall of the bit line layer 30' is exposed; the second dummy layer 92 can be removed by wet etching.

[0175] The bit line layer 30' is etched to divide it into two bit lines 30 spaced apart along a first direction X. The two bit lines 30 are respectively distributed on the sidewalls of the first insulating layer 11 and the sacrificial layer 10 exposed in the second hole K2 and disposed opposite to each other. The bit lines 30 are elongated strips extending perpendicular to the substrate 1. That is, the two bit lines 30 are obtained by cutting the annular structure formed by the bit line layer 30' into two parts along a direction perpendicular to the substrate 1. The bit line layer 30' can be etched using a wet etching process.

[0176] A fifth insulating film is deposited to form a fifth insulating layer 15 that fills the first trench T1. The fifth insulating layer 15 also covers the bit line 30, as shown in Figures 8A, 8B, and 8C. Figures 8A, 8B, and 8C are cross-sectional views along the AA', CC', and DD' directions after the bit line 30 is formed, as provided in some embodiments.

[0177] 108) Formation of the second trench T2;

[0178] The stacked structure is etched along a direction perpendicular to the substrate 1 on the side of the first initial hole K1 away from the first trench T1 to form a plurality of second trenches T2 that are spaced apart along the first direction X through the stacked structure; the second trenches T2 extend along the second direction Y and penetrate the stacked structure along the second direction Y, and adjacent second trenches T2 define a group of memory cells, each group of memory cells including two columns of memory cells.

[0179] Based on the second trench T2, the sacrificial layer 10 is laterally etched to form a second lateral trench T4, retaining the strip-shaped sacrificial layer 10 extending along the second direction Y between the first hole K1 and the first trench T1, and the retained sacrificial layer 10 is connected to the first capacitor electrode 41; subsequently, a word line 40 is formed at the location of the retained sacrificial layer 10; at this time, the sidewall of the first capacitor electrode 41 perpendicular to the substrate 1 is exposed except for the area connected to the sacrificial layer 10 on the side facing the bit line 30, as shown in Figures 9A, 9B, and 9C, where Figures 9A, 9B, and 9C are cross-sectional views along the AA', CC', and FF' directions after the formation of the second trench T2 provided in some embodiments.

[0180] 109) Form the first transverse groove T3;

[0181] A third dummy layer film is deposited to form a third dummy layer 93 that fills the second trench T2 and the second transverse trench T4;

[0182] A sixth insulating film is deposited to form a sixth insulating layer 16, which covers the third dummy layer 93 and the fifth insulating layer 15.

[0183] A third hole K3 is formed between adjacent second holes K2 along the second direction Y in the first trench T1, and the sidewall of the third hole K3 does not expose the bit line 30; a third hole K3 can be formed between every two adjacent second holes K2 along the second direction Y; the diameter of the third hole K3 is greater than the height of the subsequently formed first transverse trench T3 along the direction perpendicular to the substrate 1, that is, the distance between adjacent first insulating layers 11, so that when the word line 40 is formed laterally, the first transverse trench T3 can be completely filled and the third hole K3 can not be completely filled.

[0184] Based on the third hole K3, the sacrificial layer 10 is removed by lateral etching to form a first lateral trench T3 disposed between adjacent first insulating layers 11, as shown in Figures 10A, 10B, 10C, and 10D. Figures 10A, 10B, 10C, and 10D are cross-sectional views along the directions AA', CC', EE', and FF' after the formation of the first lateral trench T3 provided in some embodiments.

[0185] The first transverse trench T3 extends along the second direction Y. The first transverse trench T3 along the second direction Y can be approximately straight, so that the subsequently formed word line 40 is approximately straight, thereby minimizing the resistance of the word line 40.

[0186] 110) Forming a semiconductor layer 23, a gate insulating layer 24, and a word line 40;

[0187] A semiconductor thin film, a gate insulating thin film, and a fourth conductive thin film are sequentially deposited to form multiple semiconductor layers 23, multiple gate insulating layers 24, and word lines 40 connected in an integral structure, as shown in Figures 11A, 11B, 11C, and 11D. Figures 11A, 11B, 11C, and 11D are cross-sectional views along the AA', CC', EE', and FF' directions after the formation of the semiconductor layers 23, gate insulating layers 24, and word lines 40, respectively, according to some embodiments.

[0188] At this time, the semiconductor thin film covers the inner wall of the third hole K3 and the inner wall of the first transverse trench T3, the gate insulating film covers the surface of the semiconductor thin film, and the fourth conductive film fills the first transverse trench T3 but does not completely fill the third hole K3, that is, there are gaps in the third hole K3.

[0189] In some embodiments, the material of the semiconductor thin film may be silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or it may be a wide band gap material, such as a metal oxide material with a band gap of greater than 1.65 eV.

[0190] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.

[0191] In some embodiments, the material of the metal oxide semiconductor layer or channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), and indium tungsten oxide (InWO4). Materials such as IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) can be used. As long as the leakage current of the transistor meets the requirements, it is acceptable. The specific requirements can be adjusted according to the actual situation.

[0192] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.

[0193] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0194] In some embodiments, the material of the gate insulating layer 24 may comprise one or more high-K dielectric materials. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary examples include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0195] 111) Disconnect multiple semiconductor layers 23 in the same column from the side near bit line 30;

[0196] Based on the third hole K3, the semiconductor layer 23, gate insulating layer 24, and word line 40 are wet-etched. The semiconductor layer 23, gate insulating layer 24, and word line 40 in the third hole K3 are removed by etching, and the semiconductor thin film in the first lateral trench T3 is also etched, causing the semiconductor thin film near the bit line 30 to be broken into multiple parts, as shown in Figures 12A, 12B, 12C, and 12D. Figures 12A, 12B, 12C, and 12D are cross-sectional views along the directions AA', CC', EE', and FF' after the multiple semiconductor layers 23 in the same column are broken near the bit line 30, respectively, according to some embodiments. The multiple semiconductor layers 23 connected into a single structure consist of a first part and a second part distributed along the first direction X. The first part is disposed on the side of the second part facing the bit line 30. That is, the semiconductor thin film can be divided into two parts, and these two parts are subsequently etched into multiple segments from opposite sides along the first direction X, thereby breaking the multiple semiconductor layers 23 in the same layer and column.

[0197] At this time, the first part includes a semiconductor thin film distributed on the word line 40 facing the bit line 30, and also includes a semiconductor thin film distributed on the first insulating layer 11 facing the substrate 1 and on the first insulating layer 11 away from the substrate 1, close to the bit line 30. The second part is disposed on the side of the first part away from the bit line 30. The second part includes a semiconductor thin film distributed on the word line 40 away from the bit line 30, and also includes a semiconductor thin film distributed on the first insulating layer 11 facing the substrate 1 and on the first insulating layer 11 away from the substrate 1, away from the bit line 30.

[0198] Based on the third hole K3, the first part can be etched, so that the first part is broken into multiple segments in the current step, each segment connecting to a bit line 30. And the gate insulating film facing the bit line 30 is also etched into multiple segments, that is, multiple gate insulating layers 24 in the same layer and column are broken on the side facing the bit line 30.

[0199] 112) Disconnect the semiconductor layers 23 of different transistors in the same column;

[0200] A seventh insulating film is deposited to fill the area where the third hole K3 and the semiconductor film etched away in step 110) are located, forming a seventh insulating layer 17;

[0201] The sixth insulating layer 16 is ground flat to remove it, exposing the side of the third dummy layer 93 facing away from the substrate 1.

[0202] The third dummy layer 93 is removed by etching, exposing the second trench T2 and the second transverse trench T4; the third dummy layer 93 can be removed by wet etching.

[0203] Based on the second trench T2 and the second lateral trench T4, the second portion of the semiconductor thin film is wet-etched, causing the semiconductor layers 23 of multiple transistors in the same layer and column to be disconnected, as shown in Figures 13A, 13B, 13C, and 13D. Figures 13A, 13B, 13C, and 13D are cross-sectional views along the directions AA', CC', EE', and FF' after the multiple semiconductor layers 23 in the same column are disconnected from the bit line 30 side, according to some embodiments. At this time, the second portion of the semiconductor thin film in the first lateral trench T3 is etched into multiple segments, thereby disconnecting the semiconductor layers 23 of the multiple transistors in the same column.

[0204] 113) Forming a second dielectric layer 432 and a second sub-electrode 422;

[0205] A second dielectric film and a fifth conductive film are deposited sequentially. The second dielectric film covers the inner walls of the second trench T2 and the second lateral trench T4, and the fifth conductive film fills the second trench T2 and the second lateral trench T4 to form a second dielectric layer 432 and a second sub-electrode 422.

[0206] The second insulating layer 12 is ground flat to remove it, exposing the first sub-electrode 421, the second sub-electrode 422, and the bit line 30 on the side opposite to the substrate 1; as shown in Figures 1A, 1B, 1C, and 1D.

[0207] In some embodiments, the second sub-electrode 422 may include a third sub-layer 33 and a fourth sub-layer 34. The third sub-layer 33 may be a conductive film with good adhesion, such as TiN, and the fourth sub-layer 34 may be a conductive material with low resistivity, such as tungsten. The third sub-layer 33 is distributed on the inner walls of the second trench T2 and the second transverse trench T4, and the fourth sub-layer 34 fills the second trench T2 and the second transverse trench T4.

[0208] In another embodiment, the manufacturing process of a semiconductor device having an air gap may include:

[0209] 201)~205), same as 101)~105); forming the structure shown in Figures 6A, 6B, and 6C;

[0210] 206) Forming the first air gap 81;

[0211] The bit line layer 30' on the bottom wall of the second hole K2 is etched away; at this time, the bit line layer 30' forms an annular structure covering the sidewall of the second hole K2;

[0212] A fourth insulating film is deposited and smoothed to form a fourth insulating layer 14 having a first air gap 81 and closing the top of the second hole K2. The fourth insulating layer 14 is flush with the second dummy layer 92, at which point the third insulating layer 13 is removed. As shown in Figures 15A, 15B, and 15C, where Figures 15A, 15B, and 15C are cross-sectional views along the AA', CC', and DD' directions after the formation of the first air gap 81 according to some embodiments. The first air gap 81 extends in a direction perpendicular to the substrate 1 and can extend to the region where each sacrificial layer 10 is located. The height of the first air gap 81 in the direction perpendicular to the substrate 1 can be as high as possible to isolate the bit lines 30 adjacent along the first direction X.

[0213] 207) Same as step 107), forming the structure shown in Figures 16A, 16B, and 16C, wherein Figures 16A, 16B, and 16C are cross-sectional views along the AA', CC', and DD' directions after forming bit line 30 according to some embodiments.

[0214] 208) Same as step 108), forming the structure shown in Figures 17A, 17B, and 17C, wherein Figures 17A, 17B, and 17C are cross-sectional views along the AA', CC', and FF' directions after the formation of the second trench T2 provided in some embodiments.

[0215] 209) Same as step 109), forming the structure shown in Figures 18A, 18B, 18C and 18D, wherein Figures 18A, 18B, 18C and 18D are cross-sectional views along the directions AA', CC', EE' and FF' after forming the first transverse groove T3 according to some embodiments.

[0216] Steps 210) to 211) are the same as steps 110) to 111), forming the structure shown in Figures 19A, 19B, 19C and 19D. Figures 19A, 19B, 19C and 19D are cross-sectional views along the directions AA', CC', EE' and FF' after disconnecting multiple semiconductor layers 23 in the same column near the bit line 30 in some embodiments.

[0217] 212) Disconnect the semiconductor layers 23 of different transistors in the same column;

[0218] A seventh insulating film is deposited to form a seventh insulating layer 17 having a plurality of second air gaps 82 and a plurality of first sub-air gaps 831 and being closed on top of the third hole K3. The second air gaps 82 are located in the third hole K3 and extend in a direction perpendicular to the substrate 1, extending to the region where each sacrificial layer 10 is located. The height of the second air gaps 82 in the direction perpendicular to the substrate 1 can be as high as possible to isolate the bit lines 30 adjacent along the second direction Y. The first sub-air gaps 831 are located in the region where the semiconductor film is etched in the first portion. The first sub-air gaps 831 can partially surround the word line 40, distributed on the side of the word line 40 facing the bit line 30, and extending to the side of the word line 40 facing the substrate 1 and the side away from the substrate 1, respectively. On the side of the word line 40 facing the bit line 30, the first sub-air gap 831 extends between adjacent semiconductor layers 23 along the second direction Y and is interrupted at the junction of the second hole K2 and the first lateral trench T3. The first sub-air gap 831 is distributed in the region of the seventh insulating layer 17 near the gate insulating layer 24. On both the side of the word line 40 facing the substrate 1 and the side away from the substrate 1, the first sub-air gap 831 extends continuously along the second direction Y between adjacent semiconductor layers 23 along the second direction Y.

[0219] The sixth insulating layer 16 is ground flat to remove it, exposing the side of the third dummy layer 93 facing away from the substrate 1.

[0220] Based on the second trench T2 and the second lateral trench T4, the second portion of the semiconductor thin film is wet-etched, thereby disconnecting the semiconductor layers 23 of multiple transistors in the same layer and column, as shown in Figures 20A, 20B, 20C, and 20D. Figures 20A, 20B, 20C, and 20D are cross-sectional views along the AA', CC', EE', and FF' directions after disconnecting the semiconductor layers 23 of different transistors in the same column according to some embodiments. At this time, the second portion of the semiconductor thin film in the first lateral trench T3 is etched into multiple segments, thereby disconnecting the semiconductor layers 23 of multiple transistors in the same column.

[0221] 213) Forming a second dielectric layer 432 and a second sub-electrode 422;

[0222] A second dielectric film and a fifth conductive film are deposited sequentially to form a second dielectric layer 432 and a second sub-electrode 422. The second dielectric layer 432 is distributed on the inner wall of the second trench T2, the second lateral trench T4, and the area formed after the second portion is etched, and the second dielectric layer 432 forms a plurality of second sub-air gaps 832. The fifth conductive film fills the second trench T2, the second lateral trench T4, and the area formed after the second portion is etched.

[0223] The second sub-air gap 832 is distributed between adjacent semiconductor layers 23 along the second direction Y, with the gate insulating layer 24 facing away from the word line 40. The second sub-air gap 832 may partially surround the word line 40, distributed on the side of the word line 40 facing away from the bit line 30 and extending to both the side of the word line 40 facing the substrate 1 and the side facing away from the substrate 1. On the side of the word line 40 facing away from the bit line 30, the second sub-air gap 832 is distributed in the region where the first capacitor electrode 41 is exposed to the first lateral trench T3 and does not contact the semiconductor layer 23, with the second sub-air gap 832 distributed between the first capacitor electrode 41 and the gate insulating layer 24; on both the side of the word line 40 facing the substrate 1 and the side facing away from the substrate 1, the second sub-air gap 832 extends continuously along the second direction Y between adjacent semiconductor layers 23 along the second direction Y.

[0224] The third air gap includes a first sub-air gap 831 and a second sub-air gap 832. The first sub-air gap 831 and the second sub-air gap 832 may be connected or not connected. The first sub-air gap 831 partially surrounds the word line 40 (the word line 40 may be divided into two halves along the second direction Y, and the first sub-air gap 831 may surround the half of the word line 40 near the bit line 30). The second sub-air gap 832 partially surrounds the word line 40 (it may be the other half of the word line 40 near the capacitor). The first sub-air gap 831 and the second sub-air gap 832 together nearly completely surround the word line 40.

[0225] The second insulating layer 12 is ground flat to remove it, exposing the first sub-electrode 421, the second sub-electrode 422, and the bit line 30 on the side opposite to the substrate 1; as shown in Figures 14A, 14B, 14C, 14D, and 14E.

[0226] This disclosure also provides an electronic device, including the semiconductor device described in any of the foregoing embodiments, or a semiconductor device formed by the manufacturing method of the semiconductor device described in any of the foregoing embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0227] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, comprising: a plurality of memory cell arrays stacked along a direction perpendicular to a substrate, the memory cell arrays comprising a plurality of memory cells arranged along a first direction and a second direction; the first direction and the second direction intersecting; a plurality of bit lines extending along the direction perpendicular to the substrate through the memory cells of different layers; memory cells in the same column of different layers are connected to a plurality of bit lines spaced along the second direction, and memory cells adjacent along the first direction are connected to different bit lines, and the plurality of bit lines to which each two adjacent columns of memory cells are connected are located in a same trench extending along the second direction; a plurality of word lines distributed in different layers, the word lines and the bit lines being distributed along the first direction, and the word lines extending along the second direction; the memory cells comprising transistors, the transistors comprising a semiconductor layer, the semiconductor layer surrounding the word line, and the semiconductor layer being connected to the bit line at a side thereof facing the bit line and a side wall thereof perpendicular to the substrate, and a plurality of semiconductor layers of a plurality of transistors in the same position of different layers being connected to a same bit line.

2. The semiconductor device of claim 1, wherein, The two bit lines connected to the memory cells adjacent along the first direction in the same trench are spaced along the first direction.

3. The semiconductor device of claim 1, wherein, A first air gap extending along the direction perpendicular to the substrate and spaced from the bit lines is arranged between the two bit lines adjacent along the first direction in the same trench.

4. The semiconductor device of claim 1, wherein, A second air gap extending along the direction perpendicular to the substrate and spaced from the first air gap is arranged between the first air gaps adjacent along the second direction in the same trench.

5. The semiconductor device of claim 1, wherein, The transistor further comprises a first electrode arranged at a side of the word line away from the bit line. The first electrode forms an annular recess comprising a bottom wall perpendicular to the substrate and two side walls parallel to the substrate, the bottom wall comprising an inner bottom wall located inside the annular recess and an outer bottom wall located outside the annular recess, the outer bottom wall of the annular recess comprising a first region and a second region distributed along a surrounding direction of the annular recess in sequence, the first region being located at a side of the annular recess facing the bit line, the word line being distributed on the first region, and the semiconductor layer being connected to a part of the first region.

6. The semiconductor device of claim 5, wherein, The memory cell further comprises a capacitor, the capacitor and the transistor of the same memory cell being distributed along the first direction. The capacitor comprises a first capacitor electrode and a second capacitor electrode, the first electrode being multiplexed as the first capacitor electrode of the capacitor, the second capacitor electrode comprising a first sub-electrode, the first capacitor electrode surrounding the first sub-electrode, and a first dielectric layer being arranged between the first capacitor electrode and the first sub-electrode, the first sub-electrode being distributed on an inner wall of the annular recess formed by the first electrode, and the first sub-electrodes of the memory cells in the same position of different layers being connected to form an integrated structure.

7. The semiconductor device of claim 6, wherein, The side wall of the annular recess comprises an inner side wall located inside the annular recess and an outer side wall located outside the annular recess, and the first sub-electrode is further distributed on the outer side wall of the annular recess.

8. The semiconductor device of claim 6, wherein, The second capacitor electrode further comprises a second sub-electrode, which is distributed on the second region of the outer bottom wall of the annular groove.

9. The semiconductor device of claim 8, wherein, The second sub-electrodes of the plurality of memory cells in the same column and in the same layer distributed along the second direction are connected to form an integrated structure.

10. The semiconductor device of claim 9, wherein, The word line is further distributed on the side wall of the integrated structure formed by the second sub-electrodes of the plurality of memory cells in the same column and in the same layer distributed along the second direction, towards the side of the bit line.

11. The semiconductor device of claim 8, wherein, A second dielectric layer is arranged between the first capacitor electrode and the second sub-electrode, and the second dielectric layers of the capacitors in the same position and in different layers are connected to form an integrated structure.

12. The semiconductor device according to any one of claims 6 to 11, wherein The semiconductor device further comprises: insulating layers and conductive layers which are alternately distributed along the direction perpendicular to the substrate; a first hole penetrating through the insulating layers and the conductive layers; the first hole comprises a first sub-hole in the insulating layer and a second sub-hole in the conductive layer, and the second sub-hole has a groove extending along a direction parallel to the substrate direction relative to the first sub-hole; the first electrode is distributed on the inner wall of the groove, and the first electrode, the first dielectric layer and the first sub-electrode are sequentially distributed from outside to inside in the first hole.

13. The semiconductor device according to any one of claims 6 to 11, wherein The plurality of semiconductor layers of the plurality of memory cells in the same column and along the second direction in the same layer are spaced apart along the second direction and surround the same word line.

14. The semiconductor device of claim 13, wherein, The transistor further comprises a gate insulating layer arranged between the semiconductor layer and the word line; on the side of the semiconductor layer towards the bit line, the gate insulating layers of the plurality of transistors in the same column and in the same layer are disconnected; on the side of the semiconductor layer away from the bit line, the gate insulating layers of the plurality of transistors in the same column and in the same layer are connected to form an integrated structure.

15. The semiconductor device of claim 14, wherein, At least a third air gap which at least partially surrounds the word line is arranged between the semiconductor layers in the same layer and along the second direction.

16. The semiconductor device of claim 15, wherein, The third air gap comprises a first sub-air gap and a second sub-air gap, wherein: The first sub-air gap is distributed on the side of the word line towards the bit line and extends from the side of the word line towards the bit line to the side of the word line towards the substrate and the side of the word line away from the substrate respectively, on the side of the word line towards the bit line, the first sub-air gap extends between the semiconductor layers along the second direction and is disconnected at the disconnected place of the gate insulating layers along the second direction; on the side of the word line towards the substrate and the side of the word line away from the substrate, the first sub-air gap continuously extends along the second direction between the semiconductor layers along the second direction; The second sub-air gap is distributed on the side of the word line away from the bit line and extends from the side of the word line away from the bit line to the side of the word line towards the substrate and the side of the word line away from the substrate respectively; on the side of the word line away from the bit line, the second sub-air gap comprises two parts which are distributed on the first region of the first electrode along the second direction and disconnected from each other respectively; on the side of the word line towards the substrate and the side of the word line away from the substrate, the second sub-air gap continuously extends along the second direction between the semiconductor layers along the second direction.

17. A manufacturing method of a semiconductor device, comprising: Forming a stack structure including first insulating layers and sacrificial layers alternately arranged on a substrate; Forming a plurality of first holes spaced along a second direction through the stack structure along a direction perpendicular to the substrate direction, etching the sacrificial layers along a direction parallel to the substrate direction based on the first holes to form first lateral recesses; Forming first electrodes distributed on inner walls of the first lateral recesses; Forming a first trench extending along the second direction through the stack structure; the first trench and the first holes are spaced along a first direction; forming two columns of bit lines spaced along the first direction in the first trench, each column of bit lines is spaced along a second direction, the bit lines extend along a direction perpendicular to the substrate direction and through the stack structure; the first direction and the second direction intersect; Etching the sacrificial layers along a direction parallel to the substrate direction based on the first trench to expose a side of the first electrodes facing the bit lines to form first lateral trenches; Forming word lines extending along the second direction in the first lateral trenches, and a plurality of semiconductor layers spaced along the second direction around the word lines, the semiconductor layers are connected to the first electrodes and the bit lines respectively. The forming two columns of bit lines spaced along the first direction in the first trench includes:

18. The method of manufacturing a semiconductor device according to Claim 17, wherein Forming a first dummy layer filling the first trench; Forming a plurality of second holes spaced along the second direction through the stack structure along a direction perpendicular to the substrate direction in the first trench, and the sidewalls of the second holes expose the first insulating layers and the sacrificial layers; Forming a bit line layer covering the sidewalls and bottom walls of a plurality of the second holes, etching to remove the bit line layer covering the bottom walls of a plurality of the second holes; forming a second insulating layer filling the second holes, the second insulating layer is a solid structure or the second insulating layer includes a first air gap extending along a direction perpendicular to the substrate direction inside the second insulating layer; Etching to remove the first dummy layer in the first trench; Etching the bit line layer so that the bit line layer in each second hole is divided into two bit lines spaced along the first direction, the bit lines are distributed on the first insulating layers and the sacrificial layers exposed on the sidewalls of the second holes. The forming first lateral trenches based on etching the sacrificial layers along a direction parallel to the substrate direction based on the first trench to expose a side of the first electrodes facing the bit lines includes:

19. The method of manufacturing a semiconductor device according to Claim 18, wherein Depositing an insulating thin film to fill the first trench; Forming a second trench extending along the second direction through the stack structure on a side of the first hole away from the first trench; Etching the sacrificial layers along a direction parallel to the substrate direction based on the second trench to form second lateral trenches by retaining the sacrificial layers between the first holes and the bit lines, wherein the retained sacrificial layers are connected to the first electrodes; Forming a third hole through the stack structure between adjacent second holes in the first trench; Forming the first lateral trenches based on etching the sacrificial layers along a direction parallel to the substrate direction based on the third hole to expose a side of the first electrodes facing the bit lines; The forming word lines extending along the second direction in the first lateral trenches, and a plurality of semiconductor layers spaced along the second direction around the word lines includes: ​ sequentially depositing a semiconductor thin film, a gate insulating thin film and a conductive thin film to cover inner walls of the third holes and inner walls of the first lateral trenches, and the conductive thin film filling the first lateral trenches, forming a plurality of semiconductor layers connected to form an integrated structure, a plurality of gate insulating layers, and word lines; the plurality of semiconductor layers connected to form an integrated structure is composed of a first part and a second part distributed along a first direction, and the first part is arranged on a side of the second part facing the bit lines; etching the semiconductor thin film, the gate insulating thin film and the conductive thin film to remove the semiconductor thin film, the gate insulating thin film and the conductive thin film in the third holes, and so that the first part is divided into a plurality of segments distributed along a second direction, each segment connecting a bit line; etching the second part based on the second trenches and the second lateral trenches, so that the plurality of semiconductor layers of the integrated structure form a plurality of semiconductor layers spaced along the second direction.

20. The method of manufacturing a semiconductor device according to Claim 19, wherein After etching the semiconductor thin film, the gate insulating thin film and the conductive thin film, before etching the second part based on the second trenches and the second lateral trenches, further comprising: forming a third insulating layer filling the third holes and the etched regions of the semiconductor thin film, the gate insulating thin film and the conductive thin film, the third insulating layer being a solid structure, or the third insulating layer including a plurality of second air gaps and a plurality of first sub-air gaps inside, the second air gaps being arranged in the third holes and extending in a direction perpendicular to the substrate; the first sub-air gaps partially surround the word lines, are distributed on a side of the word lines facing the bit lines, and respectively extend from the side of the word lines facing the bit lines to the side of the word lines facing the substrate and the side away from the substrate, and on the side of the word lines facing the bit lines, the first sub-air gaps extend between semiconductor layers adjacent in the second direction and are disconnected at the communication between the second holes and the first lateral trenches; on the side of the word lines facing the substrate and the side away from the substrate, the first sub-air gaps continuously extend in the second direction between semiconductor layers adjacent in the second direction.

21. The method of manufacturing a semiconductor device according to Claim 17, wherein After forming the first electrode distributed on the inner walls of the first lateral recesses, before forming the first trenches extending through the stack structure and along the second direction, further comprising: exposing the first holes and the first lateral recesses formed with the first electrodes, exposing the first electrodes away from the substrate side and the substrate side, and forming second lateral recesses; forming first sub-electrodes filling the first holes, the first lateral recesses and the second lateral recesses in the first holes, the first lateral recesses and the second lateral recesses.

22. The method of manufacturing a semiconductor device according to Claim 19, wherein After etching the second part based on the second trenches and the second lateral trenches, further comprising: Depositing dielectric thin films and conductive thin films in the region formed after etching the second trench, the second lateral trench and the second part in sequence to form a second dielectric layer and a second sub-electrode, wherein the second dielectric layer is a solid structure covering the inner wall of the region formed after etching the second trench, the second lateral trench and the second part, or the second dielectric layer is formed with a plurality of second sub-air gaps; the second sub-air gaps are distributed on the side of the word line away from the bit line and respectively extend from the side of the word line away from the bit line to the side of the word line facing the substrate and the side of the word line away from the substrate; on the side of the word line away from the bit line, the second sub-air gaps are distributed on the region where the first electrode exposed to the first lateral trench and not in contact with the semiconductor layer along the second direction adjacent to each other; on the side of the word line facing the substrate and the side of the word line away from the substrate, the second sub-air gaps continuously extend along the second direction between the semiconductor layers along the second direction adjacent to each other; The second sub-electrode fills the second trench, the second lateral trench and the region formed after etching the second part.

23. An electronic device comprising the semiconductor device according to any one of claims 1 to 16, or a semiconductor device formed by the manufacturing method according to any one of claims 17 to 22.

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