Semiconductor device and manufacturing method therefor, and electronic device

Abstract

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: a plurality of layers of memory cell arrays stacked in a direction perpendicular to a substrate, each memory cell array comprising at least one column of memory cells distributed in a second direction parallel to the substrate (1); a plurality of bit lines (30), the bit lines (30) extending vertically through the memory cells in different layers, memory cells in the same layer and in the same column being respectively connected to bit lines (30) distributed at intervals in the second direction, and the bit lines (30) to which the memory cells in the same column are respectively connected being located in the same trench extending in the second direction; and a plurality of word lines (40), extending in the second direction and distributed in different layers, the word lines (40) and the bit lines (30) being distributed in a first direction. The memory cells comprise transistors. Semiconductor layers (23) of the transistors surround the word lines (40), and the semiconductor layers (23) of the transistors at the same positions in different layers are connected to the same bit line (30).

Description

A semiconductor device, a manufacturing method thereof, and an electronic device

[0001] The present application claims priority to the Chinese patent application No. 2024110171043, filed on July 26, 2024, and entitled "A semiconductor device, a manufacturing method thereof, and an electronic device", the content of which should be understood as incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing thereof in the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. BACKGROUND

[0003] With the development of integrated circuit technology, the critical dimension of devices is increasingly shrinking, and the types and number of devices contained in a single chip are increasing, so that any slight difference in process production can affect the performance of the device.

[0004] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs.

[0005] SUMMARY

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] The present application provides a semiconductor device, comprising:

[0008] A plurality of memory cell arrays stacked along a direction perpendicular to a substrate, the memory cell arrays comprising at least one column of a plurality of memory cells distributed along a second direction parallel to the substrate;

[0009] A plurality of bit lines extending along a direction perpendicular to the substrate through the memory cells of different layers; the memory cells of the same column in the same layer are respectively connected to a plurality of bit lines distributed at intervals along the second direction, and the plurality of bit lines respectively connected to the memory cells of the same column are located in the same trench extending along the second direction;

[0010] A plurality of word lines distributed in different layers, the word lines and the bit lines being distributed along a first direction parallel to the substrate, the word lines extending along the second direction, and the first direction and the second direction intersecting;

[0011] The storage unit comprises a transistor, the transistor comprises a semiconductor layer, the semiconductor layer surrounds the word line, and a side of the semiconductor layer facing the bit line and being perpendicular to the sidewall of the substrate is connected with the bit line. Multiple semiconductor layers of multiple transistors at the same position of different layers are connected with the same bit line.

[0012] In some embodiments, a dimension of a cross section of the bit line along a direction parallel to the substrate in the second direction is smaller than a dimension of the cross section along the first direction.

[0013] In some embodiments, the transistor further comprises a gate insulating layer arranged between the semiconductor layer and the word line; on the side of the semiconductor layer facing the bit line, multiple gate insulating layers of multiple transistors at the same position of the same layer are disconnected; on the side of the semiconductor layer facing away from the bit line, multiple gate insulating layers of multiple transistors at the same position of the same layer are connected to form an integrated structure.

[0014] In some embodiments, the transistor further comprises a first electrode arranged on the side of the word line facing away from the bit line.

[0015] The first electrode forms an annular groove, the annular groove comprises a bottom wall perpendicular to the substrate and two sidewalls parallel to the substrate, the bottom wall comprises an inner bottom wall located inside the annular groove and an outer bottom wall located outside the annular groove, the outer bottom wall of the annular groove comprises a first region and a second region distributed in sequence along a surrounding direction of the annular groove, the first region is located on the side of the annular groove facing the bit line; the word line is distributed on the first region; and the semiconductor layer is connected with part of the first region.

[0016] In some embodiments, the storage unit further comprises a capacitor, the capacitor and the transistor of the same storage unit are distributed along the first direction.

[0017] The capacitor comprises a first capacitor electrode and a second capacitor electrode; the first electrode is multiplexed as the first capacitor electrode of the capacitor; the second capacitor electrode comprises a first sub-electrode, the first capacitor electrode surrounds the first sub-electrode, and a first dielectric layer is arranged between the first capacitor electrode and the first sub-electrode; the first sub-electrode is distributed on the inner wall of the annular groove formed by the first electrode; and the first sub-electrodes of the storage units at the same position of different layers are connected to form an integrated structure.

[0018] In some embodiments, the sidewall of the annular groove comprises an inner sidewall located inside the annular groove and an outer sidewall located outside the annular groove, and the first sub-electrode is further distributed on the outer sidewall of the annular groove.

[0019] In some embodiments, the second capacitor electrode further comprises a second sub-electrode, the second sub-electrode is distributed on the second region of the outer bottom wall of the annular groove.

[0020] In some embodiments, the second sub-electrodes of the plurality of memory cells in the same column and in the second direction are connected to form an integrated structure.

[0021] In some embodiments, the word line is further distributed on the side wall of the side of the integrated structure formed by the second sub-electrodes towards the bit line.

[0022] In some embodiments, a second dielectric layer is arranged between the first capacitor electrode and the second sub-electrode, the second dielectric layers of the capacitors in the same position of different layers are connected to form an integrated structure.

[0023] In some embodiments, the semiconductor device further comprises:

[0024] insulating layers and conductive layers alternately distributed along the direction perpendicular to the substrate;

[0025] a first hole penetrating through the insulating layers and the conductive layers; the first hole comprises a first sub-hole located in the insulating layer and a second sub-hole located in the conductive layer, the second sub-hole has a groove extending along the direction parallel to the substrate direction relative to the first sub-hole;

[0026] the first electrode is distributed on the inner wall of the groove, and the first electrode, the first dielectric layer and the first sub-electrode are sequentially distributed from outside to inside in the first hole.

[0027] In some embodiments, the plurality of semiconductor layers of the plurality of memory cells in the same column and in the second direction in the same layer are arranged in the second direction and surround the same word line.

[0028] In some embodiments, two memory cells adjacent in the first direction in each two columns are connected to the same bit line.

[0029] Embodiments of the present disclosure provide a manufacturing method of a semiconductor device, comprising:

[0030] forming a stack structure comprising alternately arranged first insulating layers and first sacrificial layers on a substrate;

[0031] forming a plurality of first holes spaced in a second direction penetrating through the stack structure perpendicular to the direction of the substrate, based on the first hole, etching the first sacrificial layer along the direction parallel to the substrate direction to form a first lateral groove; forming a first electrode distributed on the inner wall of the first lateral groove;

[0032] forming a first trench extending through the stack structure and along the second direction; the first trench and the first hole are spaced along a first direction; forming a plurality of bit lines extending along a vertical substrate direction and through the stack structure along the second direction in the first trench; the first direction and the second direction are intersected;

[0033] forming a first lateral trench based on etching the first sacrificial layer along a direction parallel to the substrate direction to expose a side of the first electrode facing the bit line;

[0034] forming a word line extending along the second direction in the first lateral trench, and a plurality of semiconductor layers spaced along the second direction around the word line, the semiconductor layers are connected to the first electrode and the bit line respectively.

[0035] In some embodiments, the forming a plurality of bit lines extending along a vertical substrate direction and through the stack structure along the second direction in the first trench comprises:

[0036] forming a first dummy layer filling the first trench;

[0037] forming a plurality of second holes spaced along the second direction through the stack structure along a direction perpendicular to the substrate direction in the first trench, and a sidewall of the second hole exposes the first insulating layer and the first sacrificial layer;

[0038] forming a plurality of initial bit lines filling the plurality of second holes;

[0039] etching to remove the first dummy layer in the first trench, forming a protection structure covering an included angle between the initial bit line and the stack structure at the included angle;

[0040] etching the initial bit line to thin a dimension of the initial bit line along the second direction to form the bit line.

[0041] In some embodiments, the forming a first lateral trench based on etching the first sacrificial layer along a direction parallel to the substrate direction to expose a side of the first electrode facing the bit line comprises:

[0042] depositing an insulating film to fill the first trench;

[0043] forming a second trench extending through the stack structure and along the second direction on a side of the first hole facing away from the first trench;

[0044] forming a second lateral trench based on etching the first sacrificial layer along a direction parallel to the substrate direction based on the second trench, retaining a first sacrificial layer between the first hole and the bit line, wherein the retained first sacrificial layer is connected to the first electrode;

[0045] forming a third hole through the stack structure between adjacent bit lines in the first trench;

[0046] forming the first lateral trench by etching the first sacrificial layer along a direction parallel to the substrate based on the third hole to expose a side of the first electrode facing the bit line;

[0047] the word line formed along the second direction in the first lateral trench and the plurality of semiconductor layers spaced along the second direction surrounding the word line comprise:

[0048] sequentially depositing a semiconductor film, a gate insulating film, and a conductive film to cover inner walls of the third hole and the first lateral trench, and the conductive film filling the first lateral trench to form the plurality of semiconductor layers connected to form an integrated structure, the plurality of gate insulating layers, and the word line; the plurality of semiconductor layers connected to form the integrated structure consisting of a first portion and a second portion distributed along the first direction, the first portion being disposed on a side of the second portion facing the bit line;

[0049] etching the semiconductor film, the gate insulating film, and the conductive film to remove the semiconductor film, the gate insulating film, and the conductive film in the third hole, and to divide the first portion into multiple segments, each segment connecting one bit line;

[0050] etching the second portion based on the second trench and the second lateral trench to form the plurality of semiconductor layers connected to form the integrated structure to be spaced along the second direction.

[0051] In some embodiments, after forming the first electrode distributed on inner walls of the first lateral recess, before forming the first trench through the stack structure and extending along the second direction, further comprising:

[0052] exposing the first hole and the first lateral recess with the first electrode to expose a side of the first electrode facing away from the substrate and a side of the first electrode facing the substrate to form a second lateral recess;

[0053] forming a first sub-electrode filling the first hole, the first lateral recess, and the second lateral recess in the first hole, the first lateral recess, and the second lateral recess.

[0054] In some embodiments, after etching the second portion based on the second trench and the second lateral trench, further comprising:

[0055] forming a second dielectric layer covering inner walls of the second trench and the second lateral trench, and a second sub-electrode filling the second trench and the second lateral trench.

[0056] The embodiment of the present disclosure provides a semiconductor device manufacturing method, comprising:

[0057] forming a stack structure comprising first insulating layers and first sacrificial layers arranged alternately on a substrate;

[0058] forming a first trench extending through the stack structure and along a second direction;

[0059] forming a plurality of first holes extending through the stack structure and spaced along the second direction, and simultaneously forming a plurality of second holes extending through the stack structure and spaced along the second direction in the first trench; and the sidewall of the second hole exposes the first insulating layer and the first sacrificial layer; the first direction and the second direction intersect;

[0060] etching the first sacrificial layer along a direction parallel to the substrate based on the first hole to form a first lateral recess; and forming a first electrode distributed on the inner wall of the first lateral recess;

[0061] etching the first sacrificial layer along a direction parallel to the substrate based on the first trench to expose the side of the first electrode away from the first hole to form a first lateral trench;

[0062] forming a bit line extending along a direction perpendicular to the substrate and extending through the stack structure in the second hole;

[0063] forming a word line extending along the second direction in the first lateral trench, and a plurality of semiconductor layers spaced along the second direction around the word line, the semiconductor layers being connected to the first electrode and the bit line respectively.

[0064] In some embodiments, the second trench extending through the stack structure and along the second direction is formed at the same time as the first trench, the first trench and the second trench are spaced along the first direction, and the first hole is arranged between the first trench and the second trench;

[0065] Before forming the first lateral trench by etching the first sacrificial layer along a direction parallel to the substrate based on the first trench to expose the side of the first electrode facing the bit line, the method further comprises: exposing the region in the first trench except the second hole to form a first sub-trench;

[0066] The forming a word line extending along the second direction in the first lateral trench, and a plurality of semiconductor layers spaced along the second direction around the word line comprises:

[0067] sequentially depositing a semiconductor thin film, a gate insulating thin film and a conductive thin film to cover inner walls of the first sub-trenches and inner walls of the first lateral trenches, and the conductive thin film fills the first lateral trenches, forming a plurality of semiconductor layers forming an integrated structure, a plurality of gate insulating layers, and word lines; the plurality of semiconductor layers of the integrated structure is composed of a first part and a second part distributed along a first direction, and the first part is arranged on a side of the second part facing the bit lines;

[0068] etching the semiconductor thin film, the gate insulating thin film and the conductive thin film, so that the first part is divided into multiple segments, and each segment connects a bit line;

[0069] exposing the second trench, etching the first sacrificial layer based on the second trench along a direction parallel to the substrate to expose the semiconductor thin film, forming a second lateral trench; etching the second part based on the second trench and the second lateral trench, so that the plurality of semiconductor layers of the integrated structure form a plurality of semiconductor layers spaced along a second direction.

[0070] In some embodiments, the forming a plurality of bit lines extending along a direction perpendicular to the substrate and penetrating through the stack structure in the second holes comprises:

[0071] forming a plurality of initial bit lines filling a plurality of the second holes before exposing the area in the first trench except the second holes;

[0072] forming a protection structure covering a side of the word line facing the first trench, and covering an angle between the initial bit line and the first insulating layer, and an angle between the initial bit line and the semiconductor thin film and the gate insulating thin film; etching the initial bit line to thin the size of the initial bit line along the second direction to form the bit line.

[0073] In some embodiments, after forming the first electrode distributed on the inner wall of the first lateral recess, and before forming a plurality of initial bit lines filling a plurality of the second holes, further comprising:

[0074] exposing the first hole and the first lateral recess with the first electrode formed therein, exposing a side of the first electrode facing away from the substrate and a side of the first electrode facing the substrate, and forming a second lateral recess;

[0075] forming a first sub-electrode filling the first hole, the first lateral recess and the second lateral recess in the first hole, the first lateral recess and the second lateral recess.

[0076] In some embodiments, after etching the second part based on the second trench and the second lateral trench, further comprising:

[0077] forming a second dielectric layer covering inner walls of the second trench and the second lateral trench, and filling the second trench, the second lateral trench with a second sub-electrode.

[0078] The electronic device includes the semiconductor device of any of the above embodiments, or is formed by the manufacturing method of the semiconductor device of any of the above embodiments.

[0079] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art upon examination of the following or can be learned by practice of the present application. Other advantages of the present application can be realized and attained by means of the instrumentalities and combinations particularly pointed out in the description and appended claims.

[0080] Other aspects can become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description.

[0081] BRIEF DESCRIPTION OF DRAWINGS

[0082] The accompanying drawings are included to provide a further understanding of the present application and are incorporated in and constitute a part of this specification, illustrate embodiments of the present application and together with the description serve to explain the principles of the present application. The drawings are intended for illustrative purposes, and therefore are not drawn to scale.

[0083] FIG. 1A is a cross-sectional view of a semiconductor device along AA' direction parallel to the substrate, FIG. 1B is a cross-sectional view of a semiconductor device along BB' direction parallel to the substrate, FIG. 1C is a cross-sectional view along CC' direction perpendicular to the substrate in FIG. 1A, FIG. 1D is a cross-sectional view along DD' direction perpendicular to the substrate in FIG. 1A, FIG. 1E is a cross-sectional view along EE' direction perpendicular to the substrate in FIG. 1A, and FIG. 1F is a cross-sectional view along FF' direction perpendicular to the substrate in FIG. 1A;

[0084] FIG. 2A is a cross-sectional view along AA' direction after forming a first capacitor electrode, FIG. 2B is a cross-sectional view along BB' direction after forming a first capacitor electrode, FIG. 2C is a cross-sectional view along CC' direction after forming a first capacitor electrode, and FIG. 2D is a cross-sectional view along FF' direction after forming a first capacitor electrode;

[0085] FIG. 3A is a cross-sectional view along AA' direction after forming a first dielectric layer and a first sub-electrode, FIG. 3B is a cross-sectional view along BB' direction, FIG. 3C is a cross-sectional view along CC' direction, and FIG. 3D is a cross-sectional view along FF' direction;

[0086] FIG. 4A is a cross-sectional view along AA' direction after forming a first trench, FIG. 4B is a cross-sectional view along BB' direction, FIG. 4C is a cross-sectional view along CC' direction, and FIG. 4D is a cross-sectional view along FF' direction;

[0087] FIG. 5A is a cross-sectional view along the direction of AA' of forming an initial bit line according to some embodiments, FIG. 5B is a cross-sectional view along the direction of BB', and FIG. 5C is a cross-sectional view along the direction of CC';

[0088] FIG. 6A is a cross-sectional view along the direction of AA' of forming a bit line according to some embodiments, FIG. 6B is a cross-sectional view along the direction of BB', FIG. 6C is a cross-sectional view along the direction of CC', and FIG. 6D is a cross-sectional view along the direction of DD';

[0089] FIG. 7A is a cross-sectional view along the direction of AA' of forming a second trench according to some embodiments, FIG. 7B is a cross-sectional view along the direction of BB', FIG. 7C is a cross-sectional view along the direction of CC', and FIG. 7D is a cross-sectional view along the direction of EE';

[0090] FIG. 8A is a cross-sectional view along the direction of AA' of forming a first lateral trench according to some embodiments, FIG. 8B is a cross-sectional view along the direction of BB', FIG. 8C is a cross-sectional view along the direction of CC', and FIG. 8D is a cross-sectional view along the direction of EE';

[0091] FIG. 9A is a cross-sectional view along the direction of AA' of forming a semiconductor layer, a gate insulating layer, and a word line according to some embodiments, FIG. 9B is a cross-sectional view along the direction of CC', FIG. 9C is a cross-sectional view along the direction of DD', and FIG. 9D is a cross-sectional view along the direction of EE';

[0092] FIG. 10A is a cross-sectional view along the direction of AA' of disconnecting a partial region of a plurality of semiconductor layers according to some embodiments, FIG. 10B is a cross-sectional view along the direction of CC', FIG. 10C is a cross-sectional view along the direction of DD', and FIG. 10D is a cross-sectional view along the direction of EE';

[0093] FIG. 11A is a cross-sectional view along the direction of AA' of disconnecting semiconductor layers of different transistors in the same column according to some embodiments, FIG. 11B is a cross-sectional view along the direction of CC', FIG. 11C is a cross-sectional view along the direction of DD', and FIG. 11D is a cross-sectional view along the direction of EE';

[0094] FIG. 12A is a cross-sectional view along the direction of AA' of forming a second dielectric layer and a second sub-electrode according to some embodiments, FIG. 12B is a cross-sectional view along the direction of CC', and FIG. 12C is a cross-sectional view along the direction of DD';

[0095] FIGS. 13A, 13B, 13C, and 13D are cross-sectional views along the directions of AA', BB', CC', and DD', respectively, of forming a first trench and a second trench according to some embodiments;

[0096] FIGS. 14A, 14B, 14C and 14D are cross-sectional views along the AA', BB', CC' and DD' directions, respectively, of forming a first initial hole and a second hole according to some embodiments;

[0097] FIGS. 15A, 15B, 15C and 15D are cross-sectional views along the AA', BB', CC' and DD' directions, respectively, of forming a first capacitor electrode according to some embodiments;

[0098] FIGS. 16A, 16B, 16C and 16D are cross-sectional views along the AA', BB', CC' and DD' directions, respectively, of forming a first dielectric layer and a first sub-electrode according to some embodiments;

[0099] FIGS. 17A, 17B, 17C and 17D are cross-sectional views along the AA', BB', CC' and DD' directions, respectively, of exposing a region where a second hole is located according to some embodiments;

[0100] FIGS. 18A, 18B, 18C and 18D are cross-sectional views along the AA', BB', CC' and DD' directions, respectively, of forming an initial bit line according to some embodiments;

[0101] FIGS. 19A, 19B, 19C and 19D are cross-sectional views along the AA', BB', CC' and DD' directions, respectively, of exposing a first trench according to some embodiments;

[0102] FIGS. 20A, 20B, 20C and 20D are cross-sectional views along the AA', BB', CC' and DD' directions, respectively, of forming a first horizontal trench according to some embodiments;

[0103] FIGS. 21A, 21B, 21C and 21D are cross-sectional views along the AA', BB', CC' and DD' directions, respectively, of forming a semiconductor layer, a gate insulating layer and a word line according to some embodiments;

[0104] FIGS. 22A, 22B, 22C and 22D are cross-sectional views along the AA', BB', CC' and DD' directions, respectively, of disconnecting a partial region of a plurality of semiconductor layers 23 in the same layer and the same column according to some embodiments;

[0105] FIGS. 23A, 23B, 23C and 23D are cross-sectional views along the AA', BB', CC' and DD' directions, respectively, of forming a bit line according to some embodiments;

[0106] FIG. 24A, FIG. 24B, FIG. 24C and FIG. 24D are cross-sectional views of some embodiments along the direction of AA', the direction of BB', the direction of CC', and the direction of FF' respectively after forming the second transverse trench;

[0107] FIG. 25A, FIG. 25B, FIG. 25C, FIG. 25D, FIG. 25E, FIG. 25F are cross-sectional views of some embodiments along the direction of AA', the direction of BB', the direction of CC', the direction of EE', the direction of FF', and the direction of GG' respectively after forming the second dielectric layer and the second sub-electrode.

[0108] DETAILED DESCRIPTION

[0109] The embodiments of the present disclosure will be described in detail below with reference to the drawings. The features of the embodiments of the present disclosure and the embodiments can be combined with each other as long as there is no conflict.

[0110] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood as the common meaning understood by a person with ordinary skill in the art to which the present disclosure belongs.

[0111] The embodiments of the present disclosure are not necessarily limited to the sizes shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the actual proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values shown in the drawings.

[0112] The ordinal numbers "first", "second", "third", etc. in the present disclosure are set to avoid confusion of the components, and do not represent any order, number, or importance.

[0113] In the present disclosure, for the convenience of description, the words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of the components with reference to the drawings, and are only for the convenience of describing the present specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the disclosure, and can be appropriately replaced according to the situation.

[0114] In the present disclosure, unless otherwise explicitly specified and limited, the terms "mount", "connect", "connection" should be understood broadly. For example, it can be a physical connection or a signal connection, it can be a contact connection or an integral connection; it can be directly connected, or indirectly connected through an intermediate, or the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0115] In this disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to a region through which current mainly flows.

[0116] In this disclosure, it can be that the first electrode is the drain electrode and the second electrode is the source electrode, or it can be that the first electrode is the source electrode and the second electrode is the drain electrode. In the case of using a transistor having opposite polarity, or in the case of changing the direction of current in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes exchanged with each other. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be exchanged with each other.

[0117] In this disclosure, "connection" includes a case where constituent elements are connected together through an element having a certain electrical action. The element having a certain electrical action is not particularly limited as long as it can perform transmission and reception of an electrical signal between the connected constituent elements. Examples of the element having a certain electrical action include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0118] In this disclosure, "parallel" means approximately parallel or almost parallel, such as a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state where the angle is -5° or more and 5° or less. In addition, "perpendicular" means approximately perpendicular, such as a state where the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state where the angle is 85° or more and 95° or less.

[0119] In this disclosure, "A and B are in an integral structure" can mean that there is no clear boundary interface such as a clear fault or gap in the microstructure. Generally, a film layer formed by patterning on one film layer is in an integral structure. For example, A and B are formed as one film layer using the same material and are formed in a connected relationship at the same time by the same patterning process.

[0120] In this disclosure, "the orthogonal projection of B is within the range of the orthogonal projection of A" means that the boundary of the orthogonal projection of B falls within the boundary range of the orthogonal projection of A, or the boundary of the orthogonal projection of A and the boundary of the orthogonal projection of B overlap.

[0121] FIG. 1A is a cross-sectional view of a semiconductor device along AA' direction parallel to the substrate 1, FIG. 1B is a cross-sectional view of a semiconductor device along BB' direction parallel to the substrate 1, FIG. 1C is a cross-sectional view along CC' direction perpendicular to the substrate 1 in FIG. 1A, FIG. 1D is a cross-sectional view along DD' direction perpendicular to the substrate 1 in FIG. 1A, FIG. 1E is a cross-sectional view along EE' direction perpendicular to the substrate 1 in FIG. 1A, and FIG. 1F is a cross-sectional view along FF' direction perpendicular to the substrate 1 in FIG. 1A. As shown in FIGS. 1A-1F, embodiments of the present disclosure provide a semiconductor device including a plurality of vertically stacked memory cell arrays on a substrate 1.

[0122] The memory cell array can include a plurality of memory cells, a plurality of bit lines 30, and a plurality of word lines 40. Each of the memory cell arrays can include a plurality of memory cells arrayed along a first direction X parallel to the substrate 1 and a second direction Y parallel to the substrate 1. The first direction X and the second direction Y can be perpendicular.

[0123] The bit lines 30 can extend along a direction perpendicular to the substrate 1, and the plurality of memory cells at the same position of different layers stacked along the direction perpendicular to the substrate 1 are connected to the same bit line 30.

[0124] In some embodiments, two columns of memory cells adjacent along the first direction X are connected to the same bit line 30. Each two vertical columns of memory cells can form a group, and the memory cells in the same group are connected to the same bit line 30. A vertical column of memory cells includes a plurality of memory cells at the same position of different layers.

[0125] The word lines 40 can extend along the second direction Y parallel to the substrate 1, and the plurality of word lines 40 of the same memory cell array can be spaced apart from each other, and the plurality of word lines 40 of the same memory cell array can be spaced apart along the first direction X. The word lines 40 of different memory cell arrays can be stacked along a direction perpendicular to the substrate 1.

[0126] The memory cell can be a 1T1C memory cell, or can be a memory cell of other structures.

[0127] Taking the 1T1C memory cell as an example, the memory cell can include a transistor and a capacitor connected to the transistor. The transistor and the capacitor of the same memory cell can be distributed along the first direction X. The capacitor, the word line 40, and the bit line 30 are distributed along the first direction X. The transistor can include a gate electrode 26, a first electrode 51, and a second electrode 52. The gate electrode 26 can be part of the word line 40, and the gate electrodes 26 of the same column of transistors in the same layer can be connected to form an integrated word line 40.

[0128] The second electrode 52 can be connected to a bit line 30, or the second electrode 52 can be part of a bit line 30. The second electrodes 52 of the transistors of the memory cells in the same position of different layers can be connected to the same bit line 30. The second electrodes 52 of the transistors in the same position of different layers can be connected to form a bit line 30 extending in a direction perpendicular to the substrate 1.

[0129] The semiconductor device is described by taking an example of a semiconductor device including at least one column of memory cells per layer of memory cell arrays.

[0130] The semiconductor device provided by the embodiments of the present disclosure can include:

[0131] A plurality of memory cell arrays stacked in a direction perpendicular to the substrate 1, the memory cell arrays including at least one column of memory cells distributed in a second direction Y parallel to the substrate 1;

[0132] A plurality of bit lines 30 extending in a direction perpendicular to the substrate 1 through the memory cells of different layers; the memory cells in the same column of the same layer are respectively connected to a plurality of bit lines 30 spaced apart in the second direction Y, and the plurality of bit lines 30 respectively connected to the memory cells in the same column are located in the same trench extending in the second direction Y;

[0133] A plurality of word lines 40 distributed in different layers, the word lines 40 and the bit lines 30 being distributed in a first direction X parallel to the substrate 1, the word lines 40 extending in the second direction Y, and the first direction X and the second direction Y intersecting;

[0134] The memory cells include transistors, the transistors including a semiconductor layer 23 surrounding the word lines 40, a side of the semiconductor layer 23 facing the bit lines 30 and perpendicular to the substrate 1 being connected to the bit lines 30, and a plurality of semiconductor layers 23 of a plurality of transistors in the same position of different layers being connected to the same bit line 30.

[0135] Compared with the scheme in which the bit lines extend horizontally and the word lines extend vertically, in the scheme provided by the embodiments, the bit lines extend vertically and the word lines extend horizontally, and the thickness of the bit lines is greater than the thickness of the word lines when the word lines extend horizontally (the area where the bit lines are located is occupied by the word lines, the semiconductor layer, and the gate insulating layer between the word lines and the semiconductor layer, and in the case of the same thickness of the transistors, the thickness of the word lines when the word lines extend horizontally is smaller than the thickness of the bit lines when the bit lines extend horizontally), so that the parasitic capacitance between the word lines and the bit lines is smaller.

[0136] In some embodiments, a cross section of the bit line 30 parallel to the direction of the substrate 1 has a dimension along the second direction Y smaller than a dimension along the first direction X. The smaller dimension of the bit line 30 along the second direction Y can increase the distance between adjacent bit lines 30 along the second direction Y and reduce the parasitic capacitance between the bit lines 30.

[0137] In some embodiments, a cross section of the bit line 30 parallel to the direction of the substrate 1 can be rectangular or substantially rectangular.

[0138] In some embodiments, the transistor can further include a gate insulating layer 24 disposed between the semiconductor layer 23 and the word line 40; on the side of the semiconductor layer 23 facing the bit line 30, the gate insulating layers 24 of the plurality of transistors in the same layer and column can be disconnected; on the side of the semiconductor layer 23 away from the bit line 30, the gate insulating layers 24 of the plurality of transistors in the same layer and column can be connected to form an integrated structure. Referring to FIG. 1A, the gate insulating layer 24 surrounds the word line 40, and the integrated structure formed by the gate insulating layers 24 of the plurality of transistors in the same column has an opening on the side facing the bit line 30. The opening is formed when the plurality of semiconductor layers 23 on the side facing the bit line 30 are disconnected during the manufacturing process of the semiconductor device.

[0139] In some embodiments, the transistor can further include a first electrode 51 disposed on the side of the word line 40 away from the bit line 30;

[0140] The first electrode 51 forms an annular recess, and the annular recess includes a bottom wall perpendicular to the substrate 1 and two side walls parallel to the substrate 1. The bottom wall includes an inner bottom wall located inside the annular recess and an outer bottom wall located outside the annular recess. The outer bottom wall of the annular recess includes a first region and a second region distributed in sequence along the circumferential direction of the annular recess. The first region is located on the side of the annular recess facing the bit line 30. The word line 40 is distributed on the first region. The semiconductor layer 23 is connected to part of the first region. The semiconductor layer 23 can be connected to the middle region of the first region.

[0141] In some embodiments, the storage unit can further include a capacitor, the capacitor can include a first capacitor electrode 41 and a second capacitor electrode; the first electrode 51 is multiplexed as the first capacitor electrode 41 of the capacitor; the second capacitor electrode includes a first sub-electrode 421, the first capacitor electrode 41 surrounds the first sub-electrode 421, and a first dielectric layer 421 is arranged between the first capacitor electrode 41 and the first sub-electrode 421; the first sub-electrode 421 is distributed on the inner wall of the annular groove formed by the first electrode 51; and the first sub-electrodes 421 of the storage units at the same position of different layers can be connected to form an integrated structure. The scheme provided in this embodiment can form the first sub-electrodes 421 of multiple capacitors through one manufacturing process, simplifies the process, and reduces the cost.

[0142] In some embodiments, the side wall of the annular groove includes an inner side wall located inside the annular groove and an outer side wall located outside the annular groove, and the first sub-electrode 421 can also be distributed on the outer side wall of the annular groove. That is, the first sub-electrode 421 can be distributed on the inner wall (including the inner bottom wall and the inner side wall) of the annular groove and also on the outer side wall of the annular groove, so that the facing area of the first sub-electrode 421 and the first capacitor electrode 41 can be increased as much as possible, and the capacitance of the capacitor can be increased. However, the embodiments of the present disclosure are not limited thereto, and the first sub-electrode 421 can not be distributed on the outer side wall of the annular groove.

[0143] In some embodiments, the second capacitor electrode can further include a second sub-electrode 422, and the second sub-electrode 422 can be distributed on the second region of the outer bottom wall of the annular groove. A second dielectric layer 422 is arranged between the first capacitor electrode 41 and the second sub-electrode 422.

[0144] In some embodiments, the second sub-electrodes 422 of the multiple storage units of the same layer and the same column distributed along the second direction Y can be connected to form an integrated structure. The scheme provided in this embodiment can form the second sub-electrodes 422 of multiple capacitors through one manufacturing process, simplifies the process, and reduces the cost.

[0145] In some embodiments, the word line 40 can also be distributed on the side wall of the integrated structure formed by the second sub-electrode 422 towards the side of the bit line 30. The word line 40 and the second sub-electrode 422 are spaced apart by the second dielectric layer 432 and the gate insulating layer 24. That is, the word line 40 and the second sub-electrode 422 do not need to be provided with an additional insulating film layer, which facilitates the word line 40 to form a straight line type structure and reduces the resistance of the word line 40. In addition, under this structure, the word line can be realized without a photomask, so that the number of photomasks can be reduced, the cost is reduced, and in addition, the device can be more compact, and the device density is improved.

[0146] In some embodiments, the second dielectric layers 432 of the capacitors in different layers and same positions can be connected to form an integrated structure. The solution provided in this embodiment can form the second dielectric layers 432 of multiple capacitors through one manufacturing process, simplify the process, and reduce the cost.

[0147] In some embodiments, the semiconductor device can further include:

[0148] insulating layers and conductive layers distributed alternately along the direction of the vertical substrate; the conductive layers can include the first electrodes 51;

[0149] first holes penetrating through the insulating layers and the conductive layers; the first holes include first sub-holes located in the insulating layers and second sub-holes located in the conductive layers, the second sub-holes have recesses (i.e., subsequent first lateral recesses V1) extending along the direction parallel to the substrate 1 relative to the first sub-holes; that is, the orthographic projection of the first sub-holes on the substrate 1 falls within the orthographic projection of the second sub-holes on the substrate 1;

[0150] The first electrodes 51 are distributed on the inner walls of the recesses, and the first electrodes 51, the first dielectric layers 431, and the first sub-electrodes 421 are sequentially distributed from the outside to the inside in the first holes. The solution provided in this embodiment can form the first capacitor electrodes 41 (multiplexed with the first electrodes 51) of multiple capacitors at one time, form the first dielectric layers 431 of multiple capacitors at one time, and form the first sub-electrodes 421 of multiple capacitors at one time, thereby simplifying the process.

[0151] In some embodiments, multiple semiconductor layers 23 of multiple memory cells in the same column distributed along the second direction Y in the same layer are arranged along the second direction Y and surround the same word line 40.

[0152] The technical scheme of the embodiment is further illustrated by a manufacturing process of the semiconductor device in the embodiment. The "patterning process" in the embodiment includes deposition of a film, coating of photoresist, mask exposure, development, etching, stripping of photoresist, and the like, which are mature manufacturing processes in the related art. The "lithography process" in the embodiment includes coating of a film, mask exposure, and development, which are mature manufacturing processes in the related art. Deposition can be performed by known processes such as sputtering, evaporation, chemical vapor deposition, and the like, coating can be performed by known coating processes, and etching can be performed by known methods, and no specific limitation is made herein. In the description of the embodiment, it is to be understood that "film" refers to a film of a certain material formed on a substrate by deposition or coating. If the "film" does not need to be subjected to a patterning process or a lithography process during the entire manufacturing process, the "film" can also be referred to as a "layer". If the "film" needs to be subjected to a patterning process or a lithography process during the entire manufacturing process, the "film" is referred to as a "film" before the patterning process and as a "layer" after the patterning process. The "layer" after the patterning process or the lithography process includes at least one "pattern".

[0153] In an exemplary embodiment, the manufacturing process of the semiconductor device can include:

[0154] 101) forming a first capacitor electrode 41;

[0155] A substrate 1 is provided, and first insulating films and first sacrificial layer films are alternately deposited on the substrate 1 to form a stack structure including a plurality of first insulating layers 11 and first sacrificial layers 10 alternately arranged;

[0156] The stack structure is etched from the top layer to the bottom layer in a direction perpendicular to the substrate 1 (the etching is stopped on the substrate 1) to form a plurality of first initial holes K1 spaced apart in a second direction Y; when a memory array is manufactured, the plurality of first initial holes K1 spaced apart in the second direction Y is referred to as a column of first initial holes K1, and a plurality of columns of first initial holes K1 spaced apart in a first direction X can be formed;

[0157] The first sacrificial layers 10 are laterally etched (parallel to the direction of the substrate 1) based on the first initial holes K1 to form first lateral recesses V1, the first initial holes K1 and the first lateral recesses V1 constitute first holes, and the sub-holes of the first holes in the first insulating layers 11 fall within the sub-holes of the first holes in the first sacrificial layers 10 in the orthographic projection on the substrate 1;

[0158] First conductive films and first dummy layer films are sequentially deposited to form first capacitor electrodes 41 and first dummy layers 91, the first conductive films cover the inner walls of the first initial holes K1 and the inner walls of the first lateral recesses V1, and the first dummy layer films fill the first initial holes K1 and the first lateral recesses V1.

[0159] The first dummy layer 91 in the first initial hole K1 is etched and removed, and the first dummy layer 91 in the first lateral groove V1 is reserved, as shown in FIGS. 2A, 2B, 2C and 2D. FIG. 2A is a cross-sectional view of the back along the AA' direction after forming the first capacitor electrode 41 according to some embodiments, FIG. 2B is a cross-sectional view of the back along the BB' direction after forming the first capacitor electrode 41 according to some embodiments, FIG. 2C is a cross-sectional view of the back along the CC' direction after forming the first capacitor electrode 41 according to some embodiments, and FIG. 2D is a cross-sectional view of the back along the FF' direction after forming the first capacitor electrode 41 according to some embodiments.

[0160] In some embodiments, the substrate 1 can be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

[0161] In some embodiments, the first insulating film can be a low-K dielectric layer, including but not limited to silicon oxide such as silicon dioxide (SiO2) and the like, and the materials of the second to fifth insulating films are similar to the first insulating film, which will not be repeated here.

[0162] In some embodiments, the first sacrificial layer film can be a film layer having etching selectivity with the first insulating film, such as silicon nitride (SiN) and the like.

[0163] In some embodiments, the first dummy layer film can be a material such as polysilicon and the like having etching selectivity with the first insulating film and the first sacrificial layer film. The materials of the second to fifth dummy layer films are similar to the first dummy layer film, which will not be repeated here.

[0164] In some embodiments, the first conductive film can be one or more of the following different types of materials:

[0165] For example, containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt and the like metals; can be a metal alloy containing the aforementioned metals;

[0166] Or, can be a metal oxide, a metal nitride, a metal silicide, a metal carbide and the like, such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), aluminum doped zinc oxide (AZO) and the like high-conductivity metal oxide materials; such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and the like metal nitride materials;

[0167] Or, it can be a polysilicon material, a conductive doped semiconductor material, etc., such as conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that exhibit electrical conductivity, etc.

[0168] The materials of the subsequent second to fifth conductive films are similar to the first conductive film, and will not be described again.

[0169] In some embodiments, the first initial hole K1 can be circular, square, oval, etc. along a cross section parallel to the substrate 1.

[0170] 102) Forming a first dielectric layer 431 and a first sub-electrode 421;

[0171] Etching the first conductive film on the sidewall of the first initial hole K1, so as to disconnect the plurality of first capacitor electrodes 41 of the plurality of memory cells at the same position of different layers;

[0172] Etching the first dummy layer 91 to expose the inner wall of the first capacitor electrode 41;

[0173] Based on the lateral etching of the first insulating layer 11 on the first initial hole K1, the outer sidewall of the first capacitor electrode 41 facing the substrate 1 and the outer sidewall of the first capacitor electrode 41 away from the substrate 1 are exposed, and a second lateral groove between the adjacent first capacitor electrodes 41 along the direction perpendicular to the substrate 1 is formed;

[0174] Sequentially depositing a first dielectric film and a second conductive film to form a first dielectric layer 431 and a first sub-electrode 421; the first dielectric layer 431 covers the inner wall of the first capacitor electrode 41, and the inner wall of the second lateral groove (including the outer sidewall of the first capacitor electrode 41 facing the substrate 1, and the outer sidewall of the first capacitor electrode 41 away from the substrate 1); the first sub-electrode 421 fills the first initial hole K1, the first lateral groove V1 and the second lateral groove;

[0175] In some embodiments, the first sub-electrode 421 can include a first sub-layer 31, such as TiN, and a second sub-layer 32, such as tungsten, etc. The first sub-layer 31 is distributed on the bottom wall and the inner side wall of the first capacitor electrode 41, and the outer side wall facing the substrate 1 side and the outer side wall facing away from the substrate 1 side, and the second sub-layer 32 fills the first initial hole K1, the first lateral recess V1, and the second lateral recess; as shown in FIGS. 3A, 3B, 3C, and 3D. FIG. 3A is a cross-sectional view of the substrate 1 along the AA' direction after forming the first dielectric layer 431 and the first sub-electrode 421 in some embodiments, FIG. 3B is a cross-sectional view of the substrate 1 along the BB' direction after forming the first dielectric layer 431 and the first sub-electrode 421 in some embodiments, FIG. 3C is a cross-sectional view of the substrate 1 along the CC' direction after forming the first dielectric layer 431 and the first sub-electrode 421 in some embodiments, and FIG. 3D is a cross-sectional view of the substrate 1 along the FF' direction after forming the first dielectric layer 431 and the first sub-electrode 421 in some embodiments. In FIGS. 3A to 3D, the second lateral recess has been filled with the first dielectric layer 431, so that the first sub-electrode 421 is not distributed in the second lateral recess, but is not limited thereto. When the first dielectric layer 431 is relatively thin and does not fill the second lateral recess, the first sub-electrode 421 fills the second lateral recess, that is, the first sub-electrode 421 fills the area formed by the first initial hole K1, the first lateral recess V1, and the second lateral recess with the first dielectric layer 431.

[0176] In some embodiments, the first dielectric film can be a High-K dielectric material. In some embodiments, it can include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. For example, it can include, but is not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials. The subsequent second dielectric film is similar to the first dielectric film and will not be described again.

[0177] 103) forming a first trench T1;

[0178] depositing a second insulating film to form a second insulating layer 12 covering the first initial hole K1 and the first insulating layer 11 of the topmost layer;

[0179] etching the stack structure in a direction perpendicular to the substrate 1 to form a first trench T1 penetrating through the stack structure; the first trench T1 extends along the second direction Y and penetrates through the stack structure along the second direction Y, and a subsequent bit line 30 can be formed in the first trench T1;

[0180] depositing a second dummy layer film, planarizing, to form a second dummy layer 92 filling the first trench T1; the second dummy layer 92 is flush with the second insulating layer 12, as shown in FIG. 4A, FIG. 4B, FIG. 4C and FIG. 4D. Among them, FIG. 4A is a cross-sectional view along the AA' direction after forming the first trench T1 provided by some embodiments, FIG. 4B is a cross-sectional view along the BB' direction after forming the first trench T1 provided by some embodiments, FIG. 4C is a cross-sectional view along the CC' direction after forming the first trench T1 provided by some embodiments, and FIG. 4D is a cross-sectional view along the FF' direction after forming the first trench T1 provided by some embodiments.

[0181] 104) forming an initial bit line 30';

[0182] etching the second dummy layer 92 to form a plurality of second holes K2 spaced along the second direction Y, the second holes K2 exposing the bottom wall of the first trench T1; and etching through the second dummy layer 92 along the first direction X, so that the sidewall of the second hole K2 exposes the first insulating layer 11 and the first sacrificial layer 10;

[0183] depositing a third conductive film and then planarizing to form an initial bit line 30' filling the second hole K2, the initial bit line 30' being flush with the second dummy layer 92, as shown in FIG. 5A, FIG. 5B, FIG. 5C. Among them, FIG. 5A is a cross-sectional view along the AA' direction after forming the initial bit line 30' provided by some embodiments, FIG. 5B is a cross-sectional view along the BB' direction after forming the initial bit line 30' provided by some embodiments, and FIG. 5C is a cross-sectional view along the CC' direction after forming the initial bit line 30' provided by some embodiments.

[0184] In some embodiments, the initial bit line 30' can include a third sub-layer 33, which can be TiN for example, and a fourth sub-layer 34, which can be tungsten or the like. The third sub-layer 33 covers the bottom wall and sidewall of the second hole K2, and the fourth sub-layer 34 fills the second hole K2.

[0185] In some embodiments, the second hole K2 can be circular, square, or the like along a cross section parallel to the substrate 1.

[0186] 105) forming a bit line 30;

[0187] etching to remove the second dummy layer 92;

[0188] depositing a third insulating film to form a third insulating layer 13, wet etching the third insulating layer 13 to retain the third insulating layer 13 at the included angle of the stack structure formed by the initial bit line 30' and the first insulating layer 11 and the first sacrificial layer 10 as a protective structure for subsequent etching of the initial bit line 30';

[0189] The initial bit line 30' is etched by a wet etching method. Under the protection of the third insulating layer 13, the initial bit line 30' forms a structure with a rectangular cross section along a direction parallel to the substrate 1, i.e., a bit line 30; as shown in FIGS. 6A, 6B, 6C and 6D. FIG. 6A is a cross-sectional view along the AA' direction of some embodiments after forming the bit line 30, FIG. 6B is a cross-sectional view along the BB' direction of some embodiments after forming the bit line 30, FIG. 6C is a cross-sectional view along the CC' direction of some embodiments after forming the bit line 30, and FIG. 6D is a cross-sectional view along the DD' direction of some embodiments after forming the bit line 30. In this embodiment, by etching the initial bit line 30', the distance between the bit lines 30 formed finally along the second direction Y can be increased, and the parasitic capacitance between the bit lines 30 can be reduced. By providing the protection structure to protect the corner of the initial bit line 30', the etching amount of the initial bit line 30' at the non-corner position can be greater than that at the corner position, the etching amount of the bit line at the corner position can be reduced, the contact surface between the bit line 30 and the semiconductor layer 23 can be increased, and the contact resistance can be reduced.

[0190] When the initial bit line 30' includes the third sub-layer 33 and the fourth sub-layer 34, the fourth sub-layer 34 connected with the second dummy layer 92 is etched away.

[0191] 106) forming a second trench T2;

[0192] After depositing the fourth insulating film, the fourth insulating layer 14 filling the first trench T1 is formed by polishing, and the fourth insulating layer 14 is flush with the second insulating layer 12;

[0193] The stack structure is etched along a direction perpendicular to the substrate 1 on the side of the first initial hole K1 away from the second hole K2, and a plurality of second trenches T2 spaced along the first direction X are formed through the stack structure; the second trenches T2 extend along the second direction Y and penetrate through the stack structure along the second direction Y, and adjacent second trenches T2 define a group of memory cells, and each group of memory cells includes two rows of memory cells;

[0194] etching the first sacrificial layer 10 based on the second trench T2 to form a second lateral trench T4, and a strip-shaped first sacrificial layer 10 between the first hole K1 and the first trench T1 is reserved, and the reserved first sacrificial layer 10 is connected with the first capacitor electrode 41; subsequently, a word line 40 is formed at the position where the reserved first sacrificial layer 10 is located; at this time, the side wall of the first capacitor electrode 41 perpendicular to the substrate 1 is exposed, except for the area on the side of the bit line 30, as shown in FIGS. 7A, 7B, 7C and 7D. FIG. 7A is a cross-sectional view along the AA' direction after the second trench T2 is formed according to some embodiments, FIG. 7B is a cross-sectional view along the BB' direction after the second trench T2 is formed according to some embodiments, FIG. 7C is a cross-sectional view along the CC' direction after the second trench T2 is formed according to some embodiments, and FIG. 7D is a cross-sectional view along the EE' direction after the second trench T2 is formed according to some embodiments.

[0195] 107) forming a first lateral trench T3;

[0196] depositing a third dummy layer film to form a third dummy layer 93 filling the second trench T2 and the second lateral trench T4;

[0197] depositing a fifth insulating film to form a fifth insulating layer 15 covering the third dummy layer 93, the second insulating layer 12 and the fourth insulating layer 14;

[0198] forming a third hole K3 between the bit lines 30 adjacent in the second direction Y in the first trench T1, and the side wall of the third hole K3 does not expose the bit line 30; one third hole K3 can be formed between every two bit lines 30 adjacent in the second direction Y; the aperture of the third hole K3 is larger than the height of the first lateral trench T3 formed subsequently, that is, the distance between the adjacent first insulating layers 11, so that when the word line is formed subsequently, the first lateral trench T3 can be completely filled and the third hole K3 is not completely filled.

[0199] The first sacrificial layer 10 is removed by lateral etching based on the third hole K3, to form a first lateral trench T3 arranged between adjacent first insulating layers 11, as shown in FIGS. 8A, 8B, 8C and 8D. FIG. 8A is a cross-sectional view along the AA' direction after forming the first lateral trench T3 according to some embodiments, FIG. 8B is a cross-sectional view along the BB' direction after forming the first lateral trench T3 according to some embodiments, FIG. 8C is a cross-sectional view along the CC' direction after forming the first lateral trench T3 according to some embodiments, and FIG. 8D is a cross-sectional view along the EE' direction after forming the first lateral trench T3 according to some embodiments. The first lateral trench T3 extends along the second direction Y. The first lateral trench T3 can be approximately linear along the second direction Y, so that the subsequently formed word line 40 is approximately linear, thereby reducing the resistance of the word line 40 as much as possible.

[0200] 108) forming the semiconductor layer 23, the gate insulating layer 24 and the word line 40;

[0201] The semiconductor thin film, the gate insulating thin film and the fourth conductive thin film are sequentially deposited to form the plurality of semiconductor layers 23 connected into an integrated structure, the plurality of gate insulating layers 24 connected into an integrated structure and the word line 40, as shown in FIGS. 9A, 9B, 9C and 9D. FIG. 9A is a cross-sectional view along the AA' direction after forming the semiconductor layer 23, the gate insulating layer 24 and the word line 40 according to some embodiments, FIG. 9B is a cross-sectional view along the CC' direction after forming the semiconductor layer 23, the gate insulating layer 24 and the word line 40 according to some embodiments, FIG. 9C is a cross-sectional view along the DD' direction after forming the semiconductor layer 23, the gate insulating layer 24 and the word line 40 according to some embodiments, and FIG. 9D is a cross-sectional view along the EE' direction after forming the semiconductor layer 23, the gate insulating layer 24 and the word line 40 according to some embodiments. At this time, the semiconductor thin film covers the inner wall of the third hole K3 and the inner wall of the first lateral trench T3, the gate insulating thin film covers the surface of the semiconductor thin film, and the fourth conductive thin film fills the first lateral trench T3 and does not completely fill the third hole K3, i.e., there is a gap in the third hole K3.

[0202] In some embodiments, the material of the semiconductor thin film can be silicon or polycrystalline silicon or the like material with a band gap less than 1.65 eV, or can be a wide band gap material, such as a metal oxide material with a band gap greater than 1.65 eV.

[0203] For example, the material of the metal oxide semiconductor layer or channel can include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide can also include compounds containing other elements, such as N, Si, etc.; and can also include other small amounts of doped elements.

[0204] In some embodiments, the material of the metal-oxide semiconductor layer or channel can include one or more of indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and the like, as long as the leakage current of the transistor can meet the requirements, which can be adjusted according to the actual situation.

[0205] The band gap of these materials is wide, and the leakage current is low, for example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the working performance of the dynamic memory.

[0206] The material of the metal-oxide semiconductor layer or channel described above only emphasizes the element type of the material, and does not emphasize the atomic percentage in the material and the film quality of the material.

[0207] In some embodiments, the material of the gate insulating layer 24 can include one or more layers of High-K dielectric material. In some embodiments, one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. can be included. For example, at least one of the following high-K materials can be included, such as but not limited to: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and the like.

[0208] 109) disconnecting the partial region of the plurality of semiconductor layers 23 in the same column;

[0209] Based on the third hole K3, the semiconductor layer 23, the gate insulating layer 24 and the word line 40 are etched by wet etching, the semiconductor layer 23, the gate insulating layer 24 and the word line 40 in the third hole K3 are etched and removed, and the semiconductor thin film in the first transverse groove T3 is etched, so that the semiconductor thin film near the side of the bit line 30 is disconnected into multiple parts, as shown in FIGS. 10A, 10B, 10C and 10D. Among them, FIG. 10A is a sectional view of the rear along the AA' direction of the disconnected part area of the multiple semiconductor layers 23 provided by some embodiments, FIG. 10B is a sectional view of the rear along the CC' direction of the disconnected part area of the multiple semiconductor layers 23 provided by some embodiments, FIG. 10C is a sectional view of the rear along the DD' direction of the disconnected part area of the multiple semiconductor layers 23 provided by some embodiments, and FIG. 10D is a sectional view of the rear along the EE' direction of the disconnected part area of the multiple semiconductor layers 23 provided by some embodiments. The multiple semiconductor layers 23 connected into an integrated structure are composed of a first part and a second part distributed along the first direction X, and the first part is arranged on the side of the second part facing the bit line 30. That is, the semiconductor thin film can be divided into two parts, and the two parts are subsequently etched on both sides into multiple segments, so that the multiple semiconductor layers 23 in the same layer and column are disconnected.

[0210] At this time, the semiconductor thin film near the side of the bit line 30 includes the semiconductor thin film distributed on the side of the word line 40 facing the bit line 30, and also includes part of the semiconductor thin film distributed on the side of the first insulating layer 11 facing the substrate 1 and the side of the first insulating layer 11 away from the substrate 1. Based on the third hole K3, the first part can be etched so that the first part is disconnected into multiple segments in the current step. And the gate insulating thin film on the side facing the bit line 30 is also etched into multiple segments, that is, the multiple gate insulating layers 24 in the same layer and column are disconnected on the side facing the bit line 30.

[0211] 110) disconnecting the semiconductor layers 23 of different transistors in the same column;

[0212] Depositing a sixth insulating thin film to fill the third hole K3 and the area where the semiconductor thin film etched away in step 109) is located, forming a sixth insulating layer 16;

[0213] Polishing to remove the fifth insulating layer 15, exposing the third dummy layer 93;

[0214] Etching to remove the third dummy layer 93, exposing the second groove T2 and the second transverse groove T4; the third dummy layer 93 can be removed by wet etching;

[0215] The semiconductor thin film is etched based on the second trench T2 and the second lateral trench T4, so that the semiconductor layers 23 of the same layer and the same column of multiple transistors are disconnected, as shown in FIG. 11A, FIG. 11B, FIG. 11C and FIG. 11D. Among them, FIG. 11A is a cross-sectional view of the rear along the AA' direction after the semiconductor layers 23 of different transistors in the same column are disconnected, FIG. 11B is a cross-sectional view of the rear along the CC' direction after the semiconductor layers 23 of different transistors in the same column are disconnected, FIG. 11C is a cross-sectional view of the rear along the DD' direction after the semiconductor layers 23 of different transistors in the same column are disconnected, and FIG. 11D is a cross-sectional view of the rear along the EE' direction after the semiconductor layers 23 of different transistors in the same column are disconnected. At this time, the second part of the semiconductor thin film in the first lateral trench T3 is etched into multiple segments, so that the semiconductor layers 23 of multiple transistors in the same column are disconnected.

[0216] 111) forming a second dielectric layer 432 and a second sub-electrode 422;

[0217] The second dielectric thin film covers the inner walls of the second trench T2 and the second lateral trench T4, and the fifth conductive thin film fills the second trench T2 and the second lateral trench T4, thereby forming the second dielectric layer 432 and the second sub-electrode 422.

[0218] The second insulating layer 12 and the fourth insulating layer 14 are ground and removed, exposing the first sub-electrode 421, the second sub-electrode 422, and the back of the bit line 30 away from the substrate 1, as shown in FIG. 12A, FIG. 12B, and FIG. 12C. Among them, FIG. 12A is a cross-sectional view of the rear along the AA' direction after the second dielectric layer 432 and the second sub-electrode 422 are formed, FIG. 12B is a cross-sectional view of the rear along the CC' direction after the second dielectric layer 432 and the second sub-electrode 422 are formed, and FIG. 12C is a cross-sectional view of the rear along the DD' direction after the second dielectric layer 432 and the second sub-electrode 422 are formed.

[0219] In some embodiments, the second sub-electrode 422 can include a fifth sub-layer 35 and a sixth sub-layer 36. The fifth sub-layer 35 can be a conductive thin film with good adhesion, such as TiN, and the sixth sub-layer 36 can be a conductive material with low resistivity, such as tungsten. The fifth sub-layer 35 is distributed on the inner walls of the second trench T2 and the second lateral trench T4, and the sixth sub-layer 36 fills the second trench T2 and the second lateral trench T4.

[0220] In another embodiment, the manufacturing process of the semiconductor device can include:

[0221] 201) forming a first trench T1 and a second trench T2;

[0222] A substrate 1 is provided, on which a stack structure comprising a plurality of first insulating layers 11 and first sacrificial layers 10 arranged alternately is formed by alternately depositing a first insulating thin film and a first sacrificial layer thin film;

[0223] The stack structure is etched in a direction perpendicular to the substrate 1 to form a first trench T1 and a second trench T2 penetrating through the stack structure, the first trench T1 extending along the second direction Y and penetrating through the stack structure along the second direction Y, the second trench T2 extending along the second direction Y and penetrating through the stack structure along the second direction Y, the first trench T1 and the second trench T2 are spaced apart along the first direction X, one first trench T1 is arranged between adjacent second trenches T2, and adjacent second trenches T2 define a group of memory cells (two columns of memory cells).

[0224] After sequentially depositing a seventh insulating thin film and a fourth dummy layer thin film and then polishing, a seventh insulating layer 17 covering the inner walls of the first trench T1 and the second trench T2 is formed, and a fourth dummy layer 94 filling the first trench T1 and the second trench T2 is formed; as shown in FIGS. 13A, 13B, 13C and 13D. FIGS. 13A to 13D are cross-sectional views along the AA', BB', CC' and DD' directions, respectively, after forming the first trench T1 and the second trench T2, provided by some embodiments. Subsequently, a bit line 30 can be formed in the first trench T1, and an electrode of a capacitor can be formed in the second trench T2.

[0225] 202) forming a first initial hole K1 and a second hole K2;

[0226] An eighth insulating thin film is deposited to form an eighth insulating layer 18 covering the structure formed in step 201), i.e., covering the fourth dummy layer 94, the seventh insulating layer 17, and the topmost first insulating layer 11;

[0227] The stack structure is etched in a direction perpendicular to the substrate 1 from the top layer to the bottom layer (the etching stops on the substrate 1) to form a plurality of first initial holes K1 spaced apart along the second direction Y between the first trench T1 and the second trench T2, and a plurality of second holes K2 spaced apart along the second direction Y in the first trench T1; the second hole K2 exposes the bottom wall of the first trench T1, and the sidewall of the second hole K2 exposes the first insulating layer 11 and the first sacrificial layer 10;

[0228] After depositing the ninth insulating thin film and the fifth dummy layer thin film in sequence and then polishing, the ninth insulating layer 19 covering the inner walls of the first initial hole K1 and the second hole K2 is formed, and the fifth dummy layer 95 filling the first initial hole K1 and the second hole K2 is formed; the ninth insulating layer 19, the fifth dummy layer 95 and the eighth insulating layer 18 are flush. As shown in FIGS. 14A, 14B, 14C and 14D. Among them, FIGS. 14A to 14D are cross-sectional views along the AA' direction, the BB' direction, the CC' direction and the DD' direction respectively after forming the first initial hole K1 and the second hole K2 according to some embodiments.

[0229] 203) forming the first capacitor electrode 41;

[0230] Depositing a tenth insulating thin film to form a tenth insulating layer 70 covering the structure formed in the foregoing step 202), i.e., covering the ninth insulating layer 19, the fifth dummy layer 95 and the eighth insulating layer 18;

[0231] Photoetching to open the first initial hole K1 and etching to remove the fifth dummy layer 95 in the first initial hole K1;

[0232] Etching to remove the ninth insulating layer 19 in the first initial hole K1 to expose the first sacrificial layer 10;

[0233] Based on the lateral etching of the first sacrificial layer 10 in the first initial hole K1, a first lateral groove V1 is formed;

[0234] Depositing a first conductive thin film and a first dummy layer thin film in sequence to form the first capacitor electrode 41 and the first dummy layer 91, the first conductive thin film covering the inner walls of the first initial hole K1 and the first lateral groove V1, and the first dummy layer thin film filling the first initial hole K1 and the first lateral groove V1;

[0235] Etching to remove the first dummy layer 91 in the first initial hole K1, leaving the first dummy layer 91 in the first lateral groove V1, and exposing the first capacitor electrode 41 covering the side wall of the first insulating layer 11; as shown in FIGS. 15A, 15B, 15C and 15D. Among them, FIGS. 15A to 15D are cross-sectional views along the AA' direction, the BB' direction, the CC' direction and the DD' direction respectively after forming the first capacitor electrode 41 according to some embodiments.

[0236] 204) forming the first dielectric layer 431 and the first sub-electrode 421;

[0237] Etching to remove the first conductive thin film on the side wall of the first initial hole K1, so as to disconnect the plurality of first capacitor electrodes 41 at the same position of different layers;

[0238] The first dummy layer 91 is etched to expose the inner wall of the first capacitor electrode 41; the first dummy layer 91 can be removed by wet etching;

[0239] The first insulating layer 11 is etched based on the first initial hole K1 to expose the outer side wall of the first capacitor electrode 41 towards the substrate 1 side and the outer side wall of the first capacitor electrode 41 away from the substrate 1 side, forming a second lateral groove between the first capacitor electrodes 41 adjacent in the direction perpendicular to the substrate 1;

[0240] The first dielectric layer 431 and the first sub-electrode 421 are sequentially deposited by depositing a first dielectric film and a second conductive film to form; the first dielectric layer 431 covers the inner wall of the first capacitor electrode 41, and the inner wall of the second lateral groove (including the outer side wall of the first capacitor electrode 41 towards the substrate 1 side, and the outer side wall of the first capacitor electrode 41 away from the substrate 1 side); the first sub-electrode 421 fills the first initial hole K1, the first lateral groove V1 and the second lateral groove; as shown in FIGS. 16A, 16B, 16C and 16D. FIGS. 16A-16D are cross-sectional views along the AA', BB', CC' and DD' directions, respectively, after the first dielectric layer 431 and the first sub-electrode 421 are formed according to some embodiments.

[0241] 205) Expose the area where the second hole K2 is located;

[0242] The first dielectric layer 431 and the first sub-electrode 421 are etched by wet etching to form a recessed space at the top of the capacitor;

[0243] After depositing the eleventh insulating film, the eleventh insulating layer 71 is formed to fill the recessed space, and the fifth dummy layer 95 in the second hole K2 away from the substrate 1 side is exposed; as shown in FIGS. 17A, 17B, 17C and 17D. FIGS. 17A-17D are cross-sectional views along the AA', BB', CC' and DD' directions, respectively, after the area where the second hole K2 is exposed according to some embodiments. The eleventh insulating layer 71 can protect the first sub-electrode 421 in the capacitor.

[0244] 206) Form an initial bit line 30';

[0245] The fifth dummy layer 95 in the second hole K2 is etched to be removed; the fifth dummy layer 95 can be removed by wet etching;

[0246] The ninth insulating layer 19 on the side wall of the second hole K2 is etched to be removed;

[0247] After depositing the third conductive thin film, polish it to form an initial bit line 30' filling the second hole K2, which is flush with the fourth dummy layer 94, as shown in FIGS. 18A, 18B, 18C and 18D. FIGS. 18A-18D are cross-sectional views along the AA', BB', CC' and DD' directions, respectively, after forming the initial bit line 30' according to some embodiments.

[0248] 207) exposing the first trench T1;

[0249] depositing a twelfth insulating thin film to form a twelfth insulating layer 72;

[0250] etching the twelfth insulating layer 72 to form an opening exposing the initial bit line 30', and the opening overlaps the first trench T1 in the orthographic projection of the substrate 1;

[0251] etching to remove the fifth dummy layer 95 in the first trench T1 to expose the inner wall of the first trench T1 formed with the seventh insulating layer 17 and the initial bit line 30', as shown in FIGS. 19A, 19B, 19C and 19D. FIGS. 19A-19D are cross-sectional views along the AA', BB', CC' and DD' directions, respectively, after exposing the first trench T1 according to some embodiments.

[0252] 208) forming a first lateral trench T3;

[0253] etching to remove the seventh insulating layer 17; at this time, the first trench T1 is exposed except for the area where the second hole K2 is located, and the area of the first trench T1 except for the second hole K2 is referred to as a first sub-trench T1';

[0254] lateral etching the first sacrificial layer 10 based on the first trench T1 to expose the first capacitor electrode 41 toward the initial bit line 30' to form a first lateral trench T3, as shown in FIGS. 20A, 20B, 20C and 20D. FIGS. 20A-20D are cross-sectional views along the AA', BB', CC' and DD' directions, respectively, after forming the first lateral trench T3 according to some embodiments.

[0255] 209) forming a semiconductor layer 23, a gate insulating layer 24 and a word line 40;

[0256] Depositing a semiconductor thin film, a gate insulating thin film and a fourth conductive thin film in sequence to form a plurality of semiconductor layers 23 connected as an integral structure, a plurality of gate insulating layers 24 connected as an integral structure and a word line 40; as shown in FIGS. 21A, 21B, 21C and 21D. Among them, FIGS. 21A to 21D are cross-sectional views along AA', BB', CC' and DD' directions respectively after forming the semiconductor layer 23, the gate insulating layer 24 and the word line 40 provided by some embodiments.

[0257] At this time, the semiconductor thin film covers the inner wall of the first sub-trench T1' and the inner wall of the first horizontal trench T3, the semiconductor thin film surrounds the bit line 30, the gate insulating thin film covers the surface of the semiconductor thin film, and the fourth conductive thin film fills the first horizontal trench T3 and does not completely fill the first sub-trench T1', i.e. there is a gap in the first sub-trench T1'. The plurality of semiconductor layers 23 connected as an integral structure is composed of a first part and a second part distributed along the first direction X, and the first part is arranged on the side of the second part towards the initial bit line 30'. That is, the semiconductor thin film can be divided into two parts, and the two parts are subsequently etched into multiple segments on both sides, so that the plurality of semiconductor layers 23 in the same layer and the same column are disconnected.

[0258] 210) disconnecting part of the semiconductor layer 23 of the plurality of memory cells in the same layer and the same column;

[0259] Based on the gap in the first sub-trench T1', the semiconductor layer 23, the gate insulating layer 24 and the word line 40 are etched by wet etching, and the semiconductor layer 23, the gate insulating layer 24 and the word line 40 in the first trench T1 are removed by etching, so that the first part of the plurality of semiconductor layers 23 connected as an integral structure is disconnected into multiple segments, and the semiconductor thin film in contact with the initial bit line 30' is reserved. At this time, the semiconductor layers 23 of the plurality of transistors in the same layer and the same column are connected at the bottom wall of the first horizontal trench T3 and the side wall close to the bottom wall, while the plurality of semiconductor layers 23 distributed at the opening of the first horizontal trench T3 and the side wall away from the bottom wall of the first horizontal trench T3 are disconnected. As shown in FIGS. 22A, 22B, 22C and 22D. Among them, FIGS. 22A to 22D are cross-sectional views along AA', BB', CC' and DD' directions respectively after disconnecting part of the plurality of semiconductor layers 23 in the same layer and the same column provided by some embodiments.

[0260] 211) forming a bit line 30;

[0261] Depositing a third insulating thin film to form a third insulating layer 13, wet etching the third insulating layer 13, and retaining the third insulating layer 13 at the corner of the initial bit line 30' and the stack structure formed by the first insulating layer 11 and the first sacrificial layer 10 as a protection structure for subsequent etching of the initial bit line 30'; and the third insulating layer 13 also covers the side of the word line 40 facing the first trench T1 (the region exposed in the first trench T1 in step 210); so that the word line 40 can be protected during subsequent etching of the initial bit line 30';

[0262] Wet etching the initial bit line 30', under the protection of the third insulating layer 13, the bit line 30 forms a structure with a rectangular cross-section in the direction parallel to the substrate 1, that is, a bit line 30 is formed. As shown in FIGS. 23A, 23B, 23C and 23D. Among them, FIGS. 23A to 23D are cross-sectional views along the AA' direction, BB' direction, CC' direction, and DD' direction, respectively, after the formation of the bit line 30 according to some embodiments. In this embodiment, by etching the initial bit line 30', the spacing between the finally formed bit lines 30 can be increased, and the parasitic capacitance between the bit lines 30 can be reduced. By setting the protection structure to protect the corner of the initial bit line 30', the etching amount of the initial bit line 30' at the non-corner can be greater than that at the corner, the etching amount of the bit line at the corner can be reduced, and the contact area between the bit line 30 and the semiconductor layer 23 can be increased.

[0263] 212) forming a second lateral trench T4;

[0264] After depositing the thirteenth insulating thin film, polishing to form a thirteenth insulating layer 73 filling the first trench T1, and the thirteenth insulating layer 73 is flush with the fourth dummy layer 94 filled in the second trench T2;

[0265] Etching to remove the fourth dummy layer 94; the fourth dummy layer 94 can be removed by wet etching.

[0266] Etching to remove the seventh insulating layer 17 in the second trench T2, for example, by wet etching, at this time, the second trench T2 is exposed;

[0267] Based on the second lateral trench T4, etching to remove the first sacrificial layer 10 to form a second lateral trench T4; as shown in FIGS. 24A, 24B, 24C and 24D. Among them, FIGS. 24A to 24D are cross-sectional views along the AA' direction, BB' direction, CC' direction, and FF' direction, respectively, after the formation of the second lateral trench T4 according to some embodiments.

[0268] 213) forming a second dielectric layer 432 and a second sub-electrode 422;

[0269] Based on the second trench T2 and the second lateral trench T4, the semiconductor thin film is etched by wet etching, so that the same layer and the same column of the plurality of semiconductor layers 23 are disconnected, at this time, the semiconductor thin film distributed on the bottom wall and the side wall close to the bottom wall of the first lateral trench T3 is etched into an independent plurality of segments, and the plurality of semiconductor layers 23 in the same layer and the same column are disconnected through the etching in step 210) and the etching this time;

[0270] After sequentially depositing and polishing the second dielectric thin film and the fifth conductive thin film, the second dielectric thin film covers the inner walls of the second trench T2 and the second lateral trench T4, and the fifth conductive thin film fills the second trench T2 and the second lateral trench T4, forming a second dielectric layer 432 and a second sub-electrode 422; when polishing, the insulating film layer covering the first sub-electrode 421 is removed, and the first sub-electrode 421 is exposed on the side away from the substrate 1; as shown in FIGS. 25A, 25B, 25C, 25D, 25E, 25F. FIGS. 25A-25F are cross-sectional views along the AA', BB', CC', EE', FF', and GG' directions, respectively, after forming the second dielectric layer 432 and the second sub-electrode 422 according to some embodiments.

[0271] The electronic device can be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, or the like. The storage device can include a memory in a computer, and the like, which is not limited herein.

[0272] Although the embodiments of the present application are disclosed as above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the present application, and is not intended to limit the present application. Any person skilled in the art of the present application can make any modification and change in the form and details without departing from the spirit and scope of the present application, but the patent protection scope of the present application shall be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, comprising: a plurality of memory cell arrays stacked in a direction perpendicular to a substrate, the memory cell arrays comprising at least one column of a plurality of memory cells distributed in a second direction parallel to the substrate; a plurality of bit lines extending in the direction perpendicular to the substrate through the memory cells of different layers; the memory cells of the same column in the same layer are connected to a plurality of bit lines distributed in the second direction respectively, and the plurality of bit lines connected to the memory cells of the same column are located in a same trench extending in the second direction; a plurality of word lines distributed in different layers, the word lines and the bit lines being distributed in a first direction parallel to the substrate, the word lines extending in the second direction, the first direction and the second direction intersecting; the memory cells comprising transistors, the transistors comprising a semiconductor layer, the semiconductor layer surrounding the word lines, a side of the semiconductor layer facing the bit lines and perpendicular to the substrate being connected to the bit lines, a plurality of the semiconductor layers of a plurality of transistors in the same position of different layers being connected to the same bit line.

2. The semiconductor device of claim 1, wherein, a cross section of the bit line in a direction parallel to the substrate has a dimension in the second direction smaller than a dimension in the first direction.

3. The semiconductor device of claim 1, wherein, the transistors further comprising a gate insulating layer arranged between the semiconductor layer and the word line; on the side of the semiconductor layer facing the bit lines, a plurality of the gate insulating layers of a plurality of transistors in the same column in the same layer are disconnected; on the side of the semiconductor layer facing away from the bit lines, a plurality of the gate insulating layers of a plurality of transistors in the same column in the same layer are connected to form an integrated structure.

4. The semiconductor device of claim 1, wherein, the transistors further comprising a first electrode arranged on the side of the word line facing away from the bit line; the first electrode forms an annular recess, the annular recess comprising a bottom wall perpendicular to the substrate and two side walls parallel to the substrate, the bottom wall comprising an inner bottom wall located inside the annular recess and an outer bottom wall located outside the annular recess, the outer bottom wall of the annular recess comprising a first region and a second region distributed in a surrounding direction of the annular recess in sequence, the first region being located on the side of the annular recess facing the bit line; the word line is distributed on the first region; and the semiconductor layer is connected to a part of the first region.

5. The semiconductor device of claim 4, wherein, the memory cells further comprising a capacitor, the capacitor and the transistor of the same memory cell being distributed in the first direction; the capacitor comprising a first capacitor electrode and a second capacitor electrode; the first electrode is multiplexed as the first capacitor electrode of the capacitor; the second capacitor electrode comprises a first sub-electrode, the first capacitor electrode surrounds the first sub-electrode, and a first dielectric layer is arranged between the first capacitor electrode and the first sub-electrode; the first sub-electrode is distributed on the inner wall of the annular recess formed by the first electrode; and the first sub-electrodes of the memory cells in the same position of different layers are connected to form an integrated structure.

6. The semiconductor device of claim 5, wherein, the side wall of the annular recess comprises an inner side wall located inside the annular recess and an outer side wall located outside the annular recess, and the first sub-electrode is further distributed on the outer side wall of the annular recess.

7. The semiconductor device of claim 5, wherein, The second capacitor electrode further comprises a second sub-electrode, which is distributed on the second region of the outer bottom wall of the annular groove.

8. The semiconductor device of claim 7, wherein, The second sub-electrodes of the plurality of memory cells in the same column and distributed along the second direction are connected to form an integrated structure.

9. The semiconductor device of claim 8, wherein, The word line is further distributed on the side wall of the integrated structure formed by the second sub-electrode towards the side of the bit line.

10. The semiconductor device of claim 7, wherein, A second dielectric layer is arranged between the first capacitor electrode and the second sub-electrode, and the second dielectric layers of the capacitors in different layers and same positions are connected to form an integrated structure.

11. The semiconductor device of claim 6, wherein, The semiconductor device further comprises: insulating layers and conductive layers which are alternately distributed along the direction perpendicular to the substrate; a first hole penetrating through the insulating layers and the conductive layers; the first hole comprises a first sub-hole located in the insulating layer and a second sub-hole located in the conductive layer, and the second sub-hole has a groove extending along the direction parallel to the substrate direction relative to the first sub-hole; the first electrode is distributed on the inner wall of the groove, and the first electrode, the first dielectric layer and the first sub-electrode are sequentially distributed from outside to inside in the first hole.

12. The semiconductor device of claim 1, wherein, The plurality of semiconductor layers of the plurality of memory cells in the same column and distributed along the second direction in the same layer are arranged along the second direction and surround the same word line.

13. The semiconductor device of claim 1, wherein, Two memory cells adjacent along the first direction in every two columns are connected to the same bit line.

14. A manufacturing method of a semiconductor device, comprising: forming a stack structure comprising alternately arranged first insulating layers and first sacrificial layers on a substrate; forming a plurality of first holes spaced along a second direction and penetrating through the stack structure along a direction perpendicular to the substrate direction, and based on the first hole, etching the first sacrificial layer along a direction parallel to the substrate direction to form a first lateral groove; forming a first electrode distributed on the inner wall of the first lateral groove; forming a first trench penetrating through the stack structure and extending along the second direction; the first trench and the first hole are spaced along a first direction; a plurality of bit lines extending along a direction perpendicular to the substrate direction and penetrating through the stack structure are formed in the first trench; the first direction and the second direction intersect; based on the first trench, etching the first sacrificial layer along a direction parallel to the substrate direction to expose the side of the first electrode towards the bit line, to form a first lateral trench; forming a word line extending along the second direction in the first lateral trench, and a plurality of semiconductor layers spaced along the second direction and surrounding the word line, the semiconductor layers are connected to the first electrode and the bit line respectively.

15. The method of manufacturing a semiconductor device according to Claim 14, wherein The forming a plurality of bit lines extending along a direction perpendicular to the substrate direction and penetrating through the stack structure along the second direction in the first trench comprises: forming a first dummy layer filling the first trench; forming a plurality of second holes spaced along the second direction and penetrating through the stack structure along a direction perpendicular to the substrate direction in the first trench, and the side wall of the second hole exposes the first insulating layer and the first sacrificial layer; forming a plurality of initial bit lines filling the plurality of second holes; etching to remove the first dummy layer in the first trench, and forming a protection structure covering the included angle between the initial bit line and the stack structure at the included angle; etching the initial bit line to thin the initial bit line along the second direction to form the bit line.

16. The method of manufacturing a semiconductor device according to claim 15, wherein forming the first lateral trench based on etching the first sacrificial layer along a direction parallel to the substrate to expose a side of the first electrode facing the bit line includes: depositing an insulating thin film to fill the first trench; forming a second trench extending through the stack structure along the second direction on a side of the first hole facing away from the first trench; etching the first sacrificial layer based on the second trench along a direction parallel to the substrate to retain the first sacrificial layer between the first hole and the bit line to form a second lateral trench, wherein the retained first sacrificial layer is connected to the first electrode; forming a third hole extending through the stack structure between adjacent bit lines in the first trench; forming the first lateral trench based on etching the first sacrificial layer along a direction parallel to the substrate to expose a side of the first electrode facing the bit line; forming the word line extending along the second direction in the first lateral trench, and a plurality of semiconductor layers spaced along the second direction around the word line includes: sequentially depositing a semiconductor thin film, a gate insulating thin film, and a conductive thin film to cover inner walls of the third hole and the first lateral trench, and the conductive thin film fills the first lateral trench to form a plurality of semiconductor layers connected to form an integrated structure, a plurality of gate insulating layers, and a word line; the plurality of semiconductor layers connected to form the integrated structure is composed of a first portion and a second portion distributed along the first direction, and the first portion is disposed on a side of the second portion facing the bit line; etching the semiconductor thin film, the gate insulating thin film, and the conductive thin film to remove the semiconductor thin film, the gate insulating thin film, and the conductive thin film in the third hole, and to divide the first portion into multiple segments, each segment being connected to one bit line; etching the second portion based on the second trench and the second lateral trench to form a plurality of semiconductor layers spaced along the second direction from the integrated structure of the plurality of semiconductor layers.

17. The method of manufacturing a semiconductor device according to Claim 16, wherein after forming the first electrode distributed on the inner wall of the first lateral recess, and before forming the first trench extending through the stack structure along the second direction, further comprising: exposing the first hole and the first lateral recess with the first electrode to expose a side of the first electrode facing away from the substrate and a side of the first electrode facing the substrate to form a second lateral recess; forming a first sub-electrode filling the first hole, the first lateral recess, and the second lateral recess in the first hole, the first lateral recess, and the second lateral recess.

18. The method of manufacturing a semiconductor device according to Claim 16, wherein after etching the second portion based on the second trench and the second lateral trench, further comprising: forming a second dielectric layer covering inner walls of the second trench and the second lateral trench, and a second sub-electrode filling the second trench and the second lateral trench.

19. A method for manufacturing a semiconductor device, comprising: forming a stack structure including alternately arranged first insulating layers and first sacrificial layers on a substrate; forming a first trench extending through the stack structure along a second direction; forming a plurality of first holes penetrating the stack structure and spaced apart along a second direction, and simultaneously forming a plurality of second holes penetrating the stack structure and spaced apart along the second direction in the first trench; and a sidewall of the second hole exposes the first insulating layer and the first sacrificial layer; forming a first lateral recess based on etching the first sacrificial layer along a direction parallel to the substrate based on the first hole; forming a first electrode distributed on an inner wall of the first lateral recess; forming a first lateral trench based on etching the first sacrificial layer along a direction parallel to the substrate based on the first trench to expose a side of the first electrode facing away from the first hole; forming a bit line extending along a direction perpendicular to the substrate and penetrating the stack structure in the second hole; forming a word line extending along the second direction in the first lateral trench, and a plurality of semiconductor layers spaced apart along the second direction surrounding the word line, the semiconductor layers being connected to the first electrode and the bit line respectively.

20. The semiconductor device manufacturing method of claim 19, wherein, forming a second trench penetrating the stack structure and extending along the second direction simultaneously with forming the first trench, the first trench and the second trench being spaced apart along a first direction, and the first hole being disposed between the first trench and the second trench; the first direction and the second direction intersect; before forming the first lateral trench based on etching the first sacrificial layer along a direction parallel to the substrate based on the first trench to expose a side of the first electrode facing the bit line, further comprising exposing a region in the first trench other than the second hole to form a first sub-trench; the forming a word line extending along the second direction in the first lateral trench, and a plurality of semiconductor layers spaced apart along the second direction surrounding the word line comprises: sequentially depositing a semiconductor thin film, a gate insulating thin film, and a conductive thin film to cover inner walls of the first sub-trench and the first lateral trench, and the conductive thin film filling the first lateral trench to form a plurality of semiconductor layers, a plurality of gate insulating layers, and a word line forming an integrated structure; the plurality of semiconductor layers of the integrated structure being composed of a first portion and a second portion distributed along the first direction, the first portion being disposed on a side of the second portion facing the bit line; etching the semiconductor thin film, the gate insulating thin film, and the conductive thin film to divide the first portion into multiple segments, each segment being connected to one bit line; exposing the second trench, forming a second lateral trench based on etching the first sacrificial layer along a direction parallel to the substrate based on the second trench to expose the semiconductor thin film, and etching the second portion based on the second trench and the second lateral trench to form a plurality of semiconductor layers spaced apart along the second direction from the plurality of semiconductor layers of the integrated structure.

21. The semiconductor device manufacturing method of claim 20, wherein, the forming a bit line extending along a direction perpendicular to the substrate and penetrating the stack structure in the second hole comprises: forming a plurality of initial bit lines filling a plurality of the second holes before exposing a region in the first trench other than the second hole. forming a protection structure covering the word line toward a first trench side, and covering the initial bit line and the first insulating layer at an angle, and the initial bit line and the semiconductor thin film, gate insulating thin film at an angle; etching the initial bit line to thin the initial bit line along the second direction to form the bit line.

22. The method of manufacturing a semiconductor device according to Claim 21, wherein After forming the first electrode distributed on the inner wall of the first lateral recess, before forming the plurality of initial bit lines filling the plurality of second holes, further comprising: exposing the first hole and the first lateral recess with the first electrode, exposing the first electrode away from the substrate side and toward the substrate side, forming a second lateral recess; forming a first sub-electrode filling the first hole, the first lateral recess, and the second lateral recess in the first hole, the first lateral recess, and the second lateral recess.

23. The method of manufacturing a semiconductor device according to Claim 21, wherein After etching the second part based on the second trench and the second lateral trench, further comprising: forming a second dielectric layer covering the inner wall of the second trench and the second lateral trench, and a second sub-electrode filling the second trench and the second lateral trench.

24. An electronic device comprising the semiconductor device according to any one of claims 1 to 14, or the semiconductor device formed according to the manufacturing method of the semiconductor device according to any one of claims 15 to 18, or the semiconductor device formed according to the manufacturing method of the semiconductor device according to any one of claims 19 to 23. ​

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