Driving current regulation method and regulation circuit, and driving apparatus and electronic device

Abstract

The present invention relates to the technical field of electric current regulation. Provided are a driving current regulation method and regulation circuit, and a driving apparatus and an electronic device. By means of applying a target back-bias voltage to a substrate electrode of a short-channel FDSOI transistor, the resistance value of a series resistor of the short-channel FDSOI transistor is regulated, so as to finally achieve the aim of regulating a driving current when a driving voltage is applied to the short-channel FDSOI transistor. Therefore, in the technical solution provided by the present invention, the resistance value of a series resistor of an FDSOI transistor can be regulated without the need for changing the structure, material and preparation process of the FDSOI transistor, thereby finally achieving the aim of driving current regulation.

Description

Methods and circuits for adjusting drive current, drive devices and electronic equipment

[0001] This application claims priority to Chinese Patent Application No. 202410992955.3, filed on July 23, 2024, entitled "Method and Circuit for Adjusting Drive Current, Drive Device and Electronic Equipment", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of current regulation technology, and more specifically, to a method for regulating drive current, a regulating circuit, a driving device, and an electronic device. Background Technology

[0003] FDSOI (Fully Depleted Silicon On Insulator) transistors, as an alternative to planar silicon MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), offer the advantage of fabrication processes compatible with planar silicon MOSFETs, and their fabrication process is simpler. Furthermore, the ultra-thin active layer in FDSOI transistors enhances the gate's control over the channel, suppressing the short-channel effect (SCE). As the channel size of FDSOI transistors shrinks, the channel resistance continuously decreases, while the proportion of series resistance in the total resistance continuously increases, making series resistance one of the main factors affecting the performance of short-channel transistors. Simultaneously, series resistance is also one of the main factors affecting the magnitude of the drive current generated when a drive voltage is applied to an FDSOI transistor. Summary of the Invention

[0004] This invention provides a method, circuit, driving device, and electronic device for adjusting the driving current, which effectively solves the technical problems existing in the prior art. It can adjust the resistance value of the series resistance of the FDSOI transistor without changing the structure, material, and fabrication process, and ultimately achieve the purpose of adjusting the driving current.

[0005] To achieve the above objectives, the technical solution provided by the present invention is as follows:

[0006] A method for regulating drive current, applied to a driving device, the driving device including a short-channel FDSOI transistor and a driving power supply electrically connected to the source and drain of the short-channel FDSOI transistor, wherein the method for regulating drive current includes:

[0007] Generate adjustment signals;

[0008] The target back bias voltage is generated according to the adjustment signal;

[0009] The target back bias voltage is applied to the substrate electrode of the short-channel FDSOI transistor, and the series resistance of the short-channel FDSOI transistor is adjusted to the target resistance value so that the drive current is adjusted when the drive voltage output by the drive power supply is applied to the short-channel FDSOI transistor.

[0010] Optionally, the generation of the adjustment signal includes:

[0011] The adjustment signal is generated by looking up the data table.

[0012] Optionally, the data table includes one-to-one correspondence data between multiple back bias voltages and multiple series resistors.

[0013] Optionally, the data table includes conversion data between back bias voltage and series resistance values.

[0014] Based on the same inventive concept, the present invention also provides a driving current regulation circuit applied to a driving device, the driving device including a short-channel FDSOI transistor and a driving power supply electrically connected to the source and drain of the short-channel FDSOI transistor, wherein the driving current regulation circuit includes:

[0015] Processor, the processor being used to generate adjustment signals;

[0016] A voltage generation circuit is provided, which generates a target back bias voltage according to the adjustment signal and applies the target back bias voltage to the substrate electrode of the short-channel FDSOI transistor. The series resistance of the short-channel FDSOI transistor is adjusted to a target resistance value so that the drive current is adjusted when the drive voltage output by the drive power supply is applied to the short-channel FDSOI transistor.

[0017] Optionally, the processor is used to generate an adjustment signal by looking up a data table.

[0018] Optionally, the data table includes one-to-one correspondence data between multiple back bias voltages and multiple series resistors.

[0019] Optionally, the data table includes conversion data between back bias voltage and series resistance values.

[0020] Based on the same inventive concept, the present invention also provides a driving device, the driving device comprising:

[0021] Short-channel FDSOI transistor;

[0022] The driving power supply is electrically connected to the source and drain of the short-channel FDSOI transistor.

[0023] And, an adjustment circuit electrically connected to the substrate electrode of the short-channel FDSOI transistor, wherein the adjustment circuit is the aforementioned drive current adjustment circuit.

[0024] Based on the same inventive concept, the present invention also provides an electronic device, which includes the above-described driving device.

[0025] Compared with the prior art, the technical solution provided by the present invention has at least the following advantages:

[0026] This invention provides a method and circuit for regulating drive current, a driving device, and an electronic device. The driving device includes a short-channel FDSOI transistor and a driving power supply electrically connected to the source and drain of the short-channel FDSOI transistor. The method for regulating drive current includes: generating a regulation signal; generating a target back bias voltage based on the regulation signal; applying the target back bias voltage to the substrate electrode of the short-channel FDSOI transistor; and adjusting the series resistance of the short-channel FDSOI transistor to a target resistance value so that the driving current is regulated when the driving voltage output by the driving power supply is applied to the short-channel FDSOI transistor.

[0027] As described above, by applying a target back-bias voltage to the substrate electrode of the short-channel FDSOI transistor, the resistance value of the series resistance of the short-channel FDSOI transistor is adjusted, ultimately achieving the purpose of regulating the drive current when the drive voltage is applied to the short-channel FDSOI transistor. Therefore, the technical solution provided by this invention can achieve the adjustment of its series resistance value and ultimately the purpose of driving current regulation without changing the structure, materials, and fabrication process of the FDSOI transistor. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 is a flowchart of a method for adjusting the driving current according to an embodiment of the present invention;

[0030] Figure 2 is a schematic diagram of a driving device provided in an embodiment of the present invention;

[0031] Figure 3 is an IV characteristic curve of a short-channel FDSOI transistor provided in an embodiment of the present invention;

[0032] Figure 4 is a graph of the series resistance extracted using a TLM model according to an embodiment of the present invention;

[0033] Figure 5 is a curve showing the change of drive current when the series resistance of a short-channel FDSOI transistor is changed by a simulator according to an embodiment of the present invention.

[0034] Figure 6 is a graph showing the variation of series resistance and total resistance with driving voltage in a short-channel FDSOI transistor according to an embodiment of the present invention.

[0035] Figure 7 is a flowchart of another method for adjusting the driving current provided by an embodiment of the present invention;

[0036] Figure 8 is a schematic diagram of a drive current adjustment circuit provided in an embodiment of the present invention;

[0037] Figure 9 is a schematic diagram of a driving device provided in an embodiment of the present invention. Detailed Implementation

[0038] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] As described in the background section, FDSOI transistors, as an alternative to planar silicon MOSFETs, offer the advantage of fabrication processes compatible with planar silicon MOSFETs, and their fabrication process is simpler. Furthermore, the ultra-thin active layer in FDSOI transistors enhances the gate's control over the channel, achieving suppression of short-channel emission (SCE). With the miniaturization of FDSOI transistor channel dimensions, channel resistance continues to decrease, while the proportion of series resistance in the total resistance continues to increase. Series resistance (i.e., the parasitic resistance RSD of the source-drain region of the FDSOI transistor) has become one of the main factors affecting the performance of short-channel transistors. Simultaneously, series resistance is also one of the main factors affecting the magnitude of the drive current generated when a drive voltage is applied to the FDSOI transistor.

[0040] In existing technologies, adjusting the series resistance of an FDSOI transistor typically involves regulating the source-drain annealing temperature during the FDSOI transistor fabrication process. This adjusts the depth of diffusion from the source-drain region into the spacer and channel regions, thereby controlling the series resistance. The principle is to change the transport length of charge carriers in regions other than the channel to regulate the series resistance. However, this method of adjusting the series resistance of an FDSOI transistor by changing the source-drain annealing temperature alters the effective channel length. This is particularly true in short-channel FDSOI transistors, where diffusion in the source-drain region changes the effective channel length. In short-channel FDSOI transistors, performance is highly sensitive to changes in the effective channel length. Therefore, all techniques involving changing the annealing temperature degrade the stability of the FDSOI transistor, ultimately leading to a decrease in circuit performance.

[0041] In addition, existing methods also involve adjusting the series resistance of FDSOI transistors by regulating the thickness of the spacer region (the region of the gate sidewall) or by adjusting the dielectric constant. The principle is that adjusting the spacer thickness changes the length of the silicon layer beneath the spacer, thereby adjusting the transport length of the FDSOI transistor outside the channel, and thus adjusting the series resistance. Alternatively, adjusting the dielectric constant of the spacer can change the gate edge field strength, thereby controlling the conductivity of the silicon layer beneath the spacer, and thus changing the series resistance. However, in the design process of different FDSOI transistor fabrication processes, the gate pitch of a single FDSOI transistor is fixed. Changing the spacer width means compressing the width of the source and drain regions, which increases the difficulty of carrier injection from the metal electrode into the semiconductor layer, resulting in increased contact resistance and reduced mobility and drive current. Changes in spacer width and dielectric constant also alter the parasitic capacitance of the FDSOI transistor, affecting its response frequency.

[0042] Based on this, embodiments of the present invention provide a method for adjusting the driving current, an adjusting circuit, a driving device, and an electronic device, which effectively solves the technical problems existing in the prior art. It can achieve the adjustment of the series resistance value of the short-channel FDSOI transistor without changing the structure, materials, and fabrication process, and ultimately achieve the purpose of adjusting the driving current.

[0043] To achieve the above objectives, the technical solutions provided by the embodiments of the present invention are as follows, and will be described in detail with reference to Figures 1 to 9. It should be noted that the driving current is the current generated when a driving voltage is applied to the short-channel FDSOI transistor, and the back bias voltage is the voltage applied to the substrate electrode of the short-channel FDSOI transistor.

[0044] Referring to Figures 1 and 2, Figure 1 is a flowchart of a driving current adjustment method provided by an embodiment of the present invention, and Figure 2 is a structural schematic diagram of a driving device provided by an embodiment of the present invention. The driving current adjustment method provided by this embodiment is applied to a driving device, which includes a short-channel FDSOI transistor 100 and a driving power supply 200 electrically connected to the source and drain of the short-channel FDSOI transistor 100. The gate of the short-channel FDSOI transistor 100 is connected to a control structure (not shown). The driving current adjustment method includes:

[0045] S1, Generate adjustment signal.

[0046] S2. Generate the target back bias voltage according to the adjustment signal.

[0047] S3. Apply the target back bias voltage to the substrate electrode of the short-channel FDSOI transistor, and adjust the series resistance of the short-channel FDSOI transistor to the target resistance value so that the driving current is adjusted when the driving voltage output by the driving power supply is applied to the short-channel FDSOI transistor.

[0048] Referring to Figure 2, the short-channel FDSOI transistor 100 provided in this embodiment of the invention has a length L of less than 70 nm. The specific channel length L can be less than 60 nm, 50 nm, 40 nm, 30 nm, 26 nm, 20 mm, etc., and this invention does not impose specific limitations on this. The short-channel FDSOI transistor 100 includes a substrate electrode (the substrate electrode is the semiconductor bottom layer), an intermediate dielectric buried layer (the intermediate dielectric buried layer can be called a buried oxide layer) located on the substrate electrode, a semiconductor top layer located on the intermediate dielectric buried layer (the semiconductor top layer includes a channel region, a source, and a drain), and a gate structure disposed on the channel region and a gate sidewall surrounding the gate structure (the gate structure includes a gate dielectric layer and a gate). This is the same as the structure in the prior art, so this invention will not elaborate further. Furthermore, the short-channel FDSOI transistor provided in this embodiment of the invention is not limited to the structure shown in Figure 2. In other embodiments of the invention, other types of short-channel FDSOI transistor structures can also be used.

[0049] Understandably, by applying a target back-bias voltage to the substrate electrode of the short-channel FDSOI transistor, the resistance value of the series resistance of the short-channel FDSOI transistor can be adjusted, ultimately achieving the purpose of regulating the drive current when the drive voltage is applied to the short-channel FDSOI transistor. Therefore, the technical solution provided by the embodiments of the present invention can achieve the adjustment of the series resistance value of the FDSOI transistor without changing its structure, materials, and fabrication process, thereby achieving the purpose of driving current regulation.

[0050] Specifically, the short-channel FDSOI transistor is a four-terminal device (refer to the structure of the short-channel FDSOI transistor 100 in Figure 2, where the four terminals are the substrate electrode, source, drain, and gate). The inventors discovered that the electrical performance of the FDSOI can be adjusted by applying a back bias voltage to the substrate electrode. Referring specifically to Figures 3 and 4, Figure 3 shows the IV characteristic curve of a short-channel FDSOI transistor according to an embodiment of the present invention, and Figure 4 shows the series resistance curve extracted using a TLM model according to an embodiment of the present invention. Taking a short-channel FDSOI transistor with a channel length of 26nm as an example, the structure of the short-channel FDSOI transistor was built using Sentaurus simulation software. Using an electrical simulator, different back bias voltages were applied to the substrate electrode of the short-channel FDSOI transistor (as shown by the arrows in Figure 3; the four IV curves from bottom to top represent the IV curves corresponding to back bias voltages VBG of -2V, -1V, 0V, and 1V), obtaining the IV characteristics of the short-channel FDSOI transistor under different back bias voltages. The series resistance of the short-channel FDSOI transistor was extracted using the TLM (Transmission Line Method) model, and the effect of back bias voltage on the series resistance of the short-channel FDSOI transistor was compared.

[0051] Continuing with Figure 3, by simulating the IV-specific curves of the short-channel FDSOI transistor under different back bias voltages, it was found that when a back bias voltage VBG in the range of -2V to 1V is applied, the back bias voltage will regulate the driving current generated by the short-channel FDSOI transistor (the driving current is shown in the drain current diagram in Figure 3) by approximately 10%. And as shown in Figure 4, after extracting the series resistance of the short-channel FDSOI transistor using the TLM model, it was found that in a short-channel FDSOI transistor structure with a BOX (BOX being the thickness of the buried intermediate dielectric layer) of 20nm, when a back bias voltage VBG in the range of -2V to 1V is applied to the substrate electrode, the series resistance RSD decreases from 145Ω·μm to 135Ω·μm, representing a decrease of approximately 6%.

[0052] Referring to Figures 5 and 6, Figure 5 shows a curve illustrating the change in drive current when the series resistance of a short-channel FDSOI transistor is changed using a simulator, according to an embodiment of the present invention. Figure 6 shows a curve illustrating the change in series resistance and total resistance of a short-channel FDSOI transistor as a function of drive voltage, according to an embodiment of the present invention. The figures illustrate curves using a short-channel FDSOI transistor with a channel length L of 26 nm as an example. In Figure 5, the curves, from bottom to top, represent series resistances of 145 Ω·μm, 141 Ω·μm, 138 Ω·μm, and 135 Ω·μm, respectively. In Figure 6, the curves, from bottom to top, represent the series resistance and total resistance of the short-channel FDSOI transistor. The series resistance of the short-channel FDSOI transistor was set to 145 Ω·μm, 141 Ω·μm, 138 Ω·μm, and 135 Ω·μm using a simulator. These correspond to the back bias voltages VBG = -2V, VBG = -1V, VBG = 0V, and VBG = 1V, respectively. At these values, a change of approximately 6% in the series resistance directly leads to a change of approximately 5% in the drive current generated by the short-channel FDSOI transistor. In other words, in a short-channel FDSOI transistor with a channel length L of 26nm, 50% of the increase in drive current due to back bias voltage is caused by the change in series resistance. Simulations revealed that in a short-channel FDSOI transistor with a channel length L of 26nm, when the drive voltage VGT is greater than 0.65V, the series resistance accounts for approximately 65% ​​of the total resistance. This further verifies that in short-channel FDSOI transistors, the series resistance gradually becomes dominant. Therefore, adjusting the series resistance by applying a back bias voltage to regulate the drive current is effective in short-channel FDSOI transistors. Thus, in circuit applications, the back bias voltage can be used to reduce the series resistance of short-channel FDSOI transistors to improve their performance. In applications such as differential circuits, increasing the series resistance can also reduce the drive current, thereby meeting the performance matching requirements of short-channel FDSOI transistors.

[0053] Based on the above influence of back bias voltage applied to the substrate electrode on the short-channel FDSOI transistor, it can be seen that the principle of adjusting the series resistance of the short-channel FDSOI transistor by back bias voltage is as follows: First, it needs to be clarified that the total resistance of the short-channel FDSOI transistor can be simply divided into the sum of the series resistance and the channel resistance (that is, the total resistance Rtotal = series resistance RSD + channel resistance Rchannel). The back bias voltage mainly affects the silicon layer in the source and drain regions. The change in resistance in this region with the back bias voltage dominates the change in the series resistance of the entire short-channel FDSOI transistor with the back bias voltage. A positive back bias voltage (VBG > 0V for N-type transistors) leads to the accumulation of charge carriers in the silicon layer of the source and drain regions, causing the charge carrier centroid to shift downwards, resulting in a larger transistor channel cross-sectional area and consequently a decrease in series resistance. Conversely, when a reverse back bias voltage is applied (VBG < 0V for N-type transistors), the charge carriers in the silicon layer of the source and drain regions are depleted, causing the charge carrier centroid to shift upwards, resulting in a smaller transistor conduction cross-sectional area and consequently an increase in the transistor series resistance. Therefore, by applying a positive or reverse back bias voltage to the substrate electrode of the short-channel FDSOI transistor according to actual needs, the series resistance of the short-channel FDSOI transistor can be adjusted to the target resistance value.

[0054] Referring to Figure 7, which is a flowchart of another method for adjusting the drive current provided by an embodiment of the present invention, the generation of the adjustment signal provided by the embodiment of the present invention includes: S1, generating the adjustment signal by looking up a data table. The table lookup method facilitates the acquisition of relevant adjustment signals according to requirements, thereby improving the adjustment efficiency of the drive current.

[0055] In one embodiment of the invention, the data table provided by this embodiment includes one-to-one correspondence data between multiple back bias voltages and multiple series resistor values. This allows for direct lookup of the back bias voltage based on the required resistance value, thereby generating a corresponding adjustment signal and improving response and adjustment speed. Alternatively, the data table provided by this embodiment includes conversion relationship data between back bias voltage and series resistor values. Based on the required resistance value, the back bias voltage is calculated and analyzed to generate a corresponding adjustment signal, reducing data storage space requirements.

[0056] Furthermore, after applying the target back bias voltage to the substrate electrode, the drive current can be monitored. When there is a difference between the drive current and the target drive current, a compensation voltage is applied to the substrate electrode of the short-channel FDSOI transistor to adjust the drive current to the target drive current. This avoids the problem of inaccurate drive current generated by the short-channel FDSOI transistor due to environmental factors, and improves the regulation effect of the drive current.

[0057] Based on the same inventive concept, this embodiment of the invention also provides a driving current adjustment circuit. Referring to FIG8, a schematic diagram of a driving current adjustment circuit provided in this embodiment of the invention is shown. The driving current adjustment circuit is applied to a driving device, which includes a short-channel FDSOI transistor 100 and a driving power supply 200 electrically connected to the source and drain of the short-channel FDSOI transistor 100. The driving current adjustment circuit includes:

[0058] Processor 310 is configured to generate an adjustment signal. A voltage generation circuit 320 is configured to generate a target back bias voltage based on the adjustment signal, apply the target back bias voltage to the substrate electrode of the short-channel FDSOI transistor, and adjust the series resistance of the short-channel FDSOI transistor to a target resistance value so that the drive current is adjusted when the drive voltage output from the drive power supply is applied to the short-channel FDSOI transistor.

[0059] Understandably, by applying a target back-bias voltage to the substrate electrode of the short-channel FDSOI transistor, the resistance value of the series resistance of the short-channel FDSOI transistor can be adjusted, ultimately achieving the purpose of regulating the drive current when the drive voltage is applied to the short-channel FDSOI transistor. Therefore, the technical solution provided by the embodiments of the present invention can achieve the adjustment of the series resistance value of the FDSOI transistor without changing its structure, materials, and fabrication process, thereby achieving the purpose of driving current regulation.

[0060] In one embodiment of the present invention, the processor provided in this embodiment is used to generate an adjustment signal by looking up a data table. The table lookup method facilitates the acquisition of relevant adjustment signals according to requirements, improving the adjustment efficiency of the drive current. Optionally, the data table provided in this embodiment includes one-to-one correspondence data between multiple back bias voltages and multiple series resistor values. This allows the back bias voltage to be directly looked up based on the required resistance value to generate the corresponding adjustment signal, improving response and adjustment speed. Alternatively, the data table provided in this embodiment includes conversion relationship data between back bias voltage and series resistor values. This allows the back bias voltage to be calculated and analyzed based on the required resistance value before generating the corresponding adjustment signal, reducing data storage space.

[0061] Furthermore, the drive current adjustment circuit provided in this application embodiment may further include an auxiliary processor and a compensation circuit. The auxiliary processor monitors the drive current generated by the short-channel FDSOI transistor. When there is a difference between the drive current and the target drive current, it controls the compensation circuit to generate a compensation voltage. The compensation circuit applies the compensation voltage to the substrate electrode of the short-channel FDSOI transistor to adjust the drive current to the target drive current. This avoids the problem of inaccurate drive current generated by the short-channel FDSOI transistor due to environmental factors, thus improving the adjustment effect of the drive current. Optionally, the auxiliary processor may be the same device as the processor, and this invention does not impose specific limitations on this.

[0062] Based on the same inventive concept, embodiments of the present invention also provide a driving device. Referring to FIG9, a schematic diagram of a driving device provided in an embodiment of the present invention is shown, wherein the driving device provided in the embodiment of the present invention includes:

[0063] Short-channel FDSOI transistor 100.

[0064] A drive power supply 200 is electrically connected to the source and drain of the short-channel FDSOI transistor 100.

[0065] And, an adjustment circuit 300 electrically connected to the substrate electrode of the short-channel FDSOI transistor 100, wherein the adjustment circuit 300 is a drive current adjustment circuit provided in any of the above embodiments.

[0066] Based on the same inventive concept, embodiments of the present invention also provide an electronic device, which includes the driving device provided in any of the above embodiments.

[0067] This invention provides a method and circuit for adjusting drive current, a driving device, and an electronic device. The driving device includes a short-channel FDSOI transistor and a driving power supply electrically connected to the source and drain of the short-channel FDSOI transistor. The method for adjusting drive current includes: generating an adjustment signal; generating a target back bias voltage based on the adjustment signal; applying the target back bias voltage to the substrate electrode of the short-channel FDSOI transistor; and adjusting the series resistance of the short-channel FDSOI transistor to a target resistance value so that the driving current is adjusted when the driving voltage output by the driving power supply is applied to the short-channel FDSOI transistor.

[0068] As described above, by applying a target back-bias voltage to the substrate electrode of the short-channel FDSOI transistor, the resistance value of the series resistance of the short-channel FDSOI transistor is adjusted, ultimately achieving the purpose of regulating the drive current when the drive voltage is applied to the short-channel FDSOI transistor. Therefore, the technical solution provided by the embodiments of the present invention can achieve the adjustment of the series resistance value of the FDSOI transistor without changing its structure, materials, and fabrication process, thereby achieving the purpose of driving current regulation.

[0069] In the description of this invention, it should be understood that terms such as "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0070] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0071] In this invention, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between components; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0072] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0073] In this invention, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

Claims

1. A method of regulating a drive current applied to a drive device, characterized by, The driving device comprises a short channel FDSOI transistor, and a driving power source electrically connected to the source and the drain of the short channel FDSOI transistor, wherein the adjusting method of the driving current comprises: generating an adjusting signal; generating a target back bias voltage according to the adjusting signal; applying the target back bias voltage to the substrate electrode of the short channel FDSOI transistor, and adjusting the series resistance of the short channel FDSOI transistor to a target resistance value, so as to adjust the driving current when the driving voltage output by the driving power source is applied to the short channel FDSOI transistor.

2. The method of adjusting the drive current according to claim 1, wherein, The generating of the adjusting signal comprises: generating the adjusting signal by looking up a data table.

3. The method of regulating the driving current according to claim 2, characterized in that, The data table comprises one-to-one corresponding relationship data of a plurality of back bias voltages and a plurality of resistance values of series resistances.

4. The method of claim 2, wherein the driving current is adjusted by, The data table comprises conversion relationship data of back bias voltages and resistance values of series resistances.

5. A driving current regulating circuit, applied to a driving device, characterized in that, The driving device comprises a short channel FDSOI transistor, and a driving power source electrically connected to the source and the drain of the short channel FDSOI transistor, wherein the adjusting circuit of the driving current comprises: a processor for generating an adjusting signal; a voltage generating circuit for generating a target back bias voltage according to the adjusting signal, and applying the target back bias voltage to the substrate electrode of the short channel FDSOI transistor, and adjusting the series resistance of the short channel FDSOI transistor to a target resistance value, so as to adjust the driving current when the driving voltage output by the driving power source is applied to the short channel FDSOI transistor.

6. The drive current regulating circuit of claim 5, wherein, The processor is configured to generate the adjusting signal by looking up a data table.

7. The drive current regulating circuit of claim 6, wherein, The data table comprises one-to-one corresponding relationship data of a plurality of back bias voltages and a plurality of resistance values of series resistances.

8. The drive current regulating circuit of claim 6, wherein, The data table comprises conversion relationship data of back bias voltages and resistance values of series resistances.

9. A drive device characterized by comprising: The driving device comprises: a short channel FDSOI transistor; a driving power source electrically connected to the source and the drain of the short channel FDSOI transistor; and an adjusting circuit electrically connected to the substrate electrode of the short channel FDSOI transistor, wherein the adjusting circuit is the adjusting circuit of the driving current according to any one of claims 5-8.

10. An electronic device, comprising: The electronic device comprises the driving device according to claim 9.

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