Interface lead-out method for flip-chip stacked transistor, transistor, component, and device

Abstract

The present disclosure provides an interface lead-out method for a flip-chip stacked transistor, a transistor, a component, and a device. The method comprises: on the basis of a flip-chip stacked transistor, forming a first metal interconnection layer and a second metal interconnection layer, the flip-chip stacked transistor comprising a first transistor and a second transistor which are self-aligned, and the second metal interconnection layer, the second transistor, the first transistor and the first metal interconnection layer being stacked in sequence along a first direction; forming an RDL layer, and forming a first carrier layer on the RDL layer, the first metal interconnection layer being connected to the first carrier layer by means of the RDL layer; and forming a second carrier layer on the second metal interconnection layer, the second carrier layer being connected to the second metal interconnection layer.

Description

Flip-chip stacked transistor interface extraction method, transistor, device and apparatus

[0001] Cross-reference to Related Applications

[0002] This application is based on and claims priority to Chinese Patent Application No. 202410980601.7, filed on July 22, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the field of integrated circuits, and in particular to a flip-chip stacked transistor interface extraction method, transistor, device and apparatus. BACKGROUND

[0004] In the context of Moore's Law deepening, continuing to promote transistor size miniaturization is a hot issue in current industry research and development. Stacked transistors, by integrating two or more layers of transistors in vertical space, achieve further improvement of transistor integration density, and become one of the important technologies to continue the size miniaturization of integrated circuits.

[0005] Currently, many types of transistors are made from bottom to top, and the back-end interconnection of the transistor is also completed on the top of the finished transistor, so the input and output interface of the transistor is extracted from one direction. For flip-chip stacked transistors in stacked transistors, the flip-chip stacked transistor includes a first transistor and a second transistor, and the back-end interconnection of the first transistor and the second transistor is also completed respectively, so there is an urgent need for a method that can extract the input and output interface from two directions. SUMMARY

[0006] The present disclosure provides a flip-chip stacked transistor interface extraction method, transistor, device and apparatus.

[0007] The first aspect of the present disclosure provides a flip-chip stacked transistor interface extraction method. The method comprises: based on a flip-chip stacked transistor, forming a first metal interconnection layer and a second metal interconnection layer, the flip-chip stacked transistor including self-aligned first and second transistors, the second metal interconnection layer, the second transistor, the first transistor and the first metal interconnection layer being stacked in the first direction in turn; forming a redistribution layer (RDL) and a first carrier layer formed on the RDL layer, the first metal interconnection layer being connected to the first carrier layer through the RDL layer; forming a second carrier layer on the second metal interconnection layer, the second carrier layer being connected to the second metal interconnection layer.

[0008] The second aspect of the present disclosure provides a flip-chip stacked transistor. The flip-chip stacked transistor is manufactured by the method provided in the first aspect, and includes: a first transistor, a second transistor, a first metal interconnection layer, and a second metal interconnection layer, the first transistor and the second transistor are self-aligned, the second metal interconnection layer, the second transistor, the first transistor, and the first metal interconnection layer are sequentially stacked along a first direction; an RDL layer and a first carrier layer on the RDL layer, the first metal interconnection layer is connected to the first carrier layer through the RDL layer; and a second carrier layer, the second carrier layer is on the second metal interconnection layer, and the second carrier layer is connected to the second metal interconnection layer.

[0009] The third aspect of the present disclosure provides a semiconductor device, which includes the flip-chip stacked transistor provided in the second aspect.

[0010] The fourth aspect of the present disclosure provides an electronic device, which includes a circuit board and the semiconductor device provided in the third aspect, and the semiconductor device is arranged on the circuit board.

[0011] In the present disclosure, based on the flip-chip stacked transistor including the first transistor and the second transistor which are self-aligned, the first metal interconnection layer and the second metal interconnection layer are formed, the RDL layer and the first carrier layer formed on the RDL layer are formed to connect the first metal interconnection layer and the first carrier layer through the RDL layer, and the second carrier layer is formed on the second metal interconnection layer, and the second carrier layer is connected to the second metal interconnection layer, so that the input and output interfaces of the flip-chip stacked transistor on two sides can be led out from two directions.

[0012] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, rather than limiting the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0013] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of embodiments of the present disclosure.

[0014] FIG. 1 is an implementation flow diagram of an interface leading-out method of a flip-chip stacked transistor in an embodiment of the present disclosure;

[0015] FIGS. 2 to 6 are structural schematic diagrams of a flip-chip stacked transistor in a first interface leading-out process in an embodiment of the present disclosure;

[0016] FIG. 7 is a first structural schematic diagram of a flip-chip stacked transistor in an embodiment of the present disclosure;

[0017] FIGS. 8 to 12 are structural schematic diagrams of a flip-chip stacked transistor in a second interface leading-out process in an embodiment of the present disclosure;

[0018] FIG. 13 is a schematic diagram of a second structure of the flip-chip stacked transistor in the embodiments of the present disclosure.

[0019] Legend: first transistor 11; first active structure 111; first source-drain structure 112; first interlayer dielectric layer 113; first source-drain metal 114; first metal interconnection layer 115; second transistor 12; second active structure 121; second source-drain structure 122; second interlayer dielectric layer 123; second source-drain metal 124; second metal interconnection layer 125; substrate 21; shallow trench isolation structure 22; first metal line 23; RDL layer 24; third metal line 241; first carrier wafer layer 25; first lead-out point 251; second metal line 26; second carrier wafer layer 27; second lead-out point 271; solder joint 28; metal connection structure 29; base plate 30; recess 31; carrier wafer 32; third carrier wafer layer 33; chip 34. DETAILED DESCRIPTION

[0020] The exemplary embodiments will be described in detail herein below with reference to the drawings. In the following description, unless otherwise indicated, like numbers in the different drawings represent the same or similar elements. The following exemplary embodiments described in the exemplary embodiments are not meant to represent all embodiments consistent with the embodiments of the present disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of the present disclosure.

[0021] The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0022] Currently, most transistors are fabricated from bottom to top, and the back-end interconnection of the transistor is also completed on the top of the transistor, so the input and output interfaces of the transistor are led out from one direction. For flip-chip stacked transistors, both the front and back surfaces of the flip-chip stacked transistors have transistors, and the back surface transistors and the back-end interconnection of the back surface transistors both have input and output interfaces to be led out. Therefore, there is an urgent need for a method capable of leading out the input and output interfaces from both the front and back surfaces.

[0023] To solve the above problems, the embodiments of the present disclosure provide a method for leading out the interfaces of a flip-chip stacked transistor, which can realize the leading out of the input and output interfaces of the flip-chip stacked transistor from both surfaces.

[0024] In the embodiments of the present disclosure, the flip-chip stacked transistor described above can be applied to device architectures such as memories, logic devices, etc. that need to be led out from both surfaces.

[0025] In some embodiments, the flip-chip stacked transistor can include at least two transistors, for example, a first transistor and a second transistor, the first transistor and the second transistor are stacked, the first transistor is formed based on a first active structure, the second transistor is formed based on a second active structure, and the first active structure and the second active structure are actually formed by the same process, so it can be understood that the first transistor is self-aligned with the second transistor.

[0026] In the embodiments of the present disclosure, the first transistor and the second transistor in the flip-chip stacked transistor can be the same type of transistor, and the type of the transistor can include but is not limited to a fin field effect transistor (FinFET), a gate-all-around field effect transistor (GAAFET), and a planar transistor, etc.

[0027] FIG. 1 is an implementation flow diagram of an interface leading-out method of a flip-chip stacked transistor in the embodiments of the present disclosure, as shown in FIG. 1, the interface leading-out method of the flip-chip stacked transistor can include steps S110 to S130.

[0028] Step S110: based on a flip-chip stacked transistor, a first metal interconnection layer and a second metal interconnection layer are formed.

[0029] In some embodiments, the flip-chip stacked transistor includes self-aligned first and second transistors, the second metal interconnection layer, the second transistor, the first transistor, and the first metal interconnection layer are stacked in a first direction.

[0030] In some embodiments, the first transistor and the second transistor are arranged opposite to each other.

[0031] In some embodiments, the implementation process of forming the flip-chip stacked transistor can be divided into the following three steps: Step one: forming an active structure on a substrate, the active structure includes a first active structure and a second active structure, the first active structure is away from the substrate relative to the second active structure; Step two: based on the first active structure, a first transistor is formed, the first transistor includes a first source-drain structure, a first interlayer dielectric layer, a first gate structure, and a first source-drain metal; Step three: based on the second active structure, a second transistor is formed, the second transistor includes a second source-drain structure, a second interlayer dielectric layer, a second gate structure, and a second source-drain metal. Wherein, the first direction is the stacking direction of the flip-chip stacked transistor, which is perpendicular to the extension direction of the substrate.

[0032] In step one, the active structures can be formed by etching the substrate, so that the flip stacked transistors can be subsequently prepared based on the active structures.

[0033] In some embodiments, the implementation process of step one can be: providing a substrate; etching a first part of the substrate to form active structures; and depositing an oxide material on a second part of the substrate to form a shallow trench isolation (STI) structure, the height of the STI structure being lower than the height of the active structures.

[0034] For example, the substrate can be any one of a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, a silicon-on-insulator (SOI) substrate, etc.

[0035] In some embodiments, the SOI substrate includes a three-layer structure: a thin top silicon layer, a buried oxide (BOX) layer, and a base silicon layer serving as a support. That is, the BOX layer is arranged between the top silicon layer and the base silicon substrate, so that the SOI substrate can realize the medium isolation of components in integrated circuits and eliminate the parasitic latch effect in bulk CMOS circuits. The integrated circuit prepared by using the SOI substrate also has the advantages of small parasitic capacitance, high integration density, high speed, simple process, small short channel effect, and being particularly suitable for low-voltage and low-power circuits.

[0036] It can be understood that after the substrate is provided, a plurality of active structures can be formed on the substrate, that is, the first part of the substrate is etched to form the active structures.

[0037] In some embodiments, the implementation process of etching the first part of the substrate to form the active structures can be: forming an epitaxial layer on the surface of the substrate by an epitaxial growth process; etching the epitaxial layer to a certain depth in the epitaxial layer or to the surface of the substrate or to a certain depth in the substrate, thereby forming a plurality of active structures. Each active structure includes a first active structure and a second active structure, and the first active structure is farther away from the substrate than the second active structure.

[0038] In the case where the transistor is a fin field effect transistor, the active structure is a fin structure. In the case where the transistor is a fully wrapped gate transistor, the active structure is a nanosheet. In the case where the transistor is a planar transistor, the active structure is a block planar structure.

[0039] For example, the etching process can be at least one of dry etching, wet etching, and reactive ion etching.

[0040] After the active structure is formed, an insulating material can be deposited on the second portion of the substrate and the surface of the active structure to form a shallow trench isolation structure wrapping the second active structure.

[0041] It can be understood that the insulating material can be deposited on the surface of the substrate and the active structure, and a planarization process can be used to remove the upper surface of the oxide material until the upper surface of the active structure is exposed, so as to form a shallow trench isolation structure with the upper surface of the active structure. Then, the shallow trench isolation structure is etched back to a certain depth, so that the shallow trench isolation structure wraps the second active structure and exposes the first active structure. In this way, the subsequent step two is performed based on the exposed first active structure to form the operation of the first transistor. The planarization process can be, for example, a chemical-mechanical planarization (CMP) process. The insulating material forming the shallow trench isolation structure can be, for example, any one of silicon nitride (SiN, Si3N4), silicon dioxide (SiO2), or silicon carbon oxide (SiCO), etc.

[0042] In some embodiments, the implementation process of step two can be: epitaxially growing a first source / drain structure on the first active structure; depositing an insulating material on the first source / drain structure and the first active structure to form a first interlayer dielectric layer; forming a first gate structure based on the first active structure; etching a first portion of the first interlayer dielectric layer to expose the first source / drain structure and form a first source / drain metal on the first source / drain structure.

[0043] In some embodiments, after the shallow trench isolation structure is formed, a material such as polysilicon or amorphous silicon can also be deposited in the gate region of the first transistor in the flip-chip stacked transistor to form a first dummy gate structure; a first spacer is formed on both sides of the first dummy gate structure; and a first source / drain structure is formed on the first active structure on both sides of the first dummy gate structure and the first spacer. The first spacer is used to isolate the first source / drain structure from the first gate structure. The structure of the first spacer can be set according to actual needs, and the embodiments of the present disclosure do not make specific limitations thereon. For example, the first spacer can have a single-layer structure and be made of the same material, such as porous silicon carbon oxide hydride (SiCOH).

[0044] In some embodiments, the implementation process of forming the first source / drain structure on the first active structure on both sides of the first dummy gate structure and the first spacer can be: etching the first active structure in the source / drain region of the first transistor to form a first source / drain recess, and performing source / drain epitaxial growth at the first source / drain recess to form the first source / drain structure.

[0045] In some embodiments, a strained material such as silicon germanium or silicon carbide can be formed by selective epitaxy to fill the source / drain recess of the first transistor, and then a heavy doping process can be performed to form the first source / drain structure on the strained material.

[0046] It can be appreciated that after the first source / drain structure is formed, an interlayer dielectric can be deposited on the first source / drain structure, and the interlayer dielectric can be thinned to the upper surface of the first source / drain structure to form a first interlayer dielectric layer. For example, an insulating material such as SiO2 can be deposited on the first source / drain structure and the first active structure, and a planarization process can be performed to form the first interlayer dielectric layer, which can cover the first source / drain structure and the first active structure.

[0047] After the first interlayer dielectric layer is formed, a gate structure of the first transistor, i.e., a first gate structure, can be formed.

[0048] In some embodiments, the first dummy gate structure formed above can be removed by an etching process to form a first gate recess, an insulating material can be deposited in the first gate recess to form a first gate dielectric layer, and a metal material can be deposited on the first gate dielectric layer to form a first gate electrode layer. The first gate dielectric layer and the first gate electrode layer together constitute the first gate structure.

[0049] For example, the first gate dielectric layer can be composed of a silicon oxide layer and a high-K hafnium oxide layer, and the thickness of the silicon oxide layer and the hafnium oxide layer can be determined according to the polarity and performance of the transistor. For example, the first gate electrode layer can be composed of multiple layers of electrode materials, each layer of electrode material including but not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0050] After the first gate structure is formed, a first portion of the first interlayer dielectric layer formed above can be etched to expose the first source / drain structure, and then a metal material can be deposited on the first source / drain structure to form a first source / drain metal.

[0051] In some embodiments, after the first transistor is formed, a back-end-of-line process such as interconnection line interlayer dielectric deposition, metal line formation, and lead-out pad formation can be performed on the first transistor to form a first metal interconnection layer.

[0052] In some embodiments, the first metal interconnection layer includes a first metal line, which can include a signal metal line and / or a power supply metal line, and these metal lines need to be led out to the outside of the flip-chip stacked transistor as an input / output interface.

[0053] It can be understood that after the first metal interconnection layer is formed, the first transistor and the first metal interconnection layer can be developed and the substrate can be removed to expose the second active structure, so that the second transistor can be formed based on the second active structure.

[0054] In some embodiments, after the substrate is developed and removed, the shallow trench structure can be thinned to a preset height to expose the second active structure, and the thinned shallow trench isolation structure is used to isolate the first transistor and the second transistor. The preset height can be set according to actual needs, and the embodiments of the present disclosure are not limited thereto.

[0055] In some embodiments, based on the second active structure, the implementation process of forming the second transistor can be: epitaxially growing a second source / drain structure on the second active structure; depositing a semiconductor material on the second source / drain structure and the second active structure to form a second interlayer dielectric layer; forming a second gate structure based on the second active structure; etching a part of the second interlayer dielectric layer to expose the second source / drain structure, and forming a second source / drain metal on the second source / drain structure.

[0056] After the second transistor is formed, a back-end process can be performed on the second transistor to form a second metal interconnection layer.

[0057] In some embodiments, the preparation methods of the second source / drain structure, the second interlayer dielectric layer, the second gate structure, the second source / drain metal, and the second metal interconnection layer of the second transistor are the same as those of the first source / drain structure, the first interlayer dielectric layer, the first gate structure, the first source / drain metal, and the first metal interconnection layer of the first transistor, and will not be described here.

[0058] In some embodiments, the second metal interconnection layer includes a second metal line, which can exemplarily include a signal metal line and / or a power metal line, and these metal lines need to be led out to the outside of the flip-chip stacked transistor as input / output interfaces.

[0059] The flip-chip stacked transistor formed by the above scheme is prepared by first preparing the first transistor and the first metal interconnection layer, then developing the first transistor and the first carrier layer located on the first metal interconnection layer to make the first transistor located at the bottom, and then preparing the second transistor and the second metal interconnection layer on the first transistor. Therefore, in the first scheme, from bottom to top, it is the first metal interconnection layer, the first transistor, the second transistor, and the second metal interconnection layer in sequence, and this preparation method is the first scheme. In this scheme, the first transistor is a front transistor, and the second transistor is a back transistor.

[0060] In some embodiments, the second transistor and the second metal interconnection layer are prepared first, and then the second transistor is flipped, and the first transistor and the first metal interconnection layer are prepared on the second transistor. Thus, in the second scheme, from bottom to top, the second metal interconnection layer, the second transistor, the first transistor and the first metal interconnection layer are sequentially prepared, and this preparation method is the second scheme. In this scheme, the first transistor is a backside transistor, and the second transistor is a frontside transistor.

[0061] In some embodiments, in the second scheme, when the second transistor is flipped, the second metal interconnection layer can be bonded to a carrier wafer before being flipped.

[0062] Step S120: forming an RDL layer and a first carrier layer formed on the RDL layer.

[0063] In some embodiments, the first metal interconnection layer is connected to the first carrier layer through the RDL layer.

[0064] In some embodiments, the RDL layer includes a third metal line, the first carrier layer includes a plurality of first lead-out points, one end of the third metal line is connected to the first metal line, and the other end is connected to the first lead-out points. In this way, the input and output interfaces of the first transistor can be led out to the first lead-out points through the RDL layer.

[0065] It can be understood that RDL is a rewiring technology that can flexibly optimize the packaging layout of electronic devices. The principle of RDL technology is to deposit metal layers and dielectric layers on the wafer surface to form an RDL layer, the RDL layer carries the corresponding metal wiring pattern, and rearranges the input and output interfaces of the chip on the loose area outside the chip. The metal wiring formed by the RDL layer has a small line width and pitch, thereby providing higher interconnection density, and at the same time, the signal quality can be improved by shortening the circuit length, and the chip integration capability can be improved by reducing the chip area.

[0066] Based on the first scheme for preparing a flip-chip stacked transistor, in some embodiments, the implementation process of step S120 can be: after forming the first metal interconnection layer and before forming the second metal interconnection layer, forming an RDL layer and a first carrier layer on the RDL layer; and bonding the RDL layer and the first carrier layer to the first metal interconnection layer, so that the RDL layer is attached to the first metal interconnection layer.

[0067] It can be understood that in the first scheme, after the first metal interconnection layer is formed, the RDL layer and the first carrier layer on the RDL layer can be formed before the second transistor is formed, the RDL layer has the rewired third metal wires, the first carrier layer includes a plurality of first lead-out points and insulating medium between the lead-out points, and one end of the third metal wires is connected to the first lead-out points in the first carrier layer. Then the RDL layer and the first carrier layer are bonded with the first metal interconnection layer, so that the RDL layer is attached to the first metal interconnection layer, and the other end of the third metal wires in the RDL layer is connected to the first metal wires, so that the first metal interconnection layer and the first carrier layer can be connected through the RDL layer. For example, the first lead-out points can be made of metal materials. This is only an illustrative description, and the actual RDL layer can be flexibly routed according to requirements, and a higher routing density can be achieved.

[0068] It can be understood that in the first scheme, the first metal interconnection layer herein is the front metal interconnection layer on the front transistor. In addition, in the first scheme, the front transistor and the carrier with the RDL layer are connected through hybrid bonding, so that the carrier with the RDL layer formed in this way can support the process of completing the back transistor and realize the lead-out of the input and output interface of the front transistor.

[0069] For the second scheme, the implementation process of step S120 can be: forming a substrate including an RDL layer and a medium layer stacked along a first direction, and a first carrier layer formed on the RDL layer; opening a first groove on the medium layer; and embedding the flip-chip stacked transistor after flipping.

[0070] It can be understood that the second scheme can prepare the substrate including the RDL layer and the medium layer in advance, then etch a first region of the medium layer to form the first groove, the first region is a region for bearing the flip-chip stacked transistor, and finally embed the flip-chip stacked transistor after flipping in the first groove.

[0071] In some embodiments, when the first groove is etched, the thickness is controlled so that the bottom of the first groove stops at the RDL layer. Moreover, after the flip-chip stacked transistor is flipped, the first metal interconnection layer is located at the lowermost part of the device, so that the first metal interconnection layer at the bottom of the first groove can be connected to the first carrier layer through the RDL layer. In the second scheme, the first metal interconnection layer herein is the back metal interconnection layer on the back transistor.

[0072] It can be understood that the substrate is a common carrier for carrying chips in packaging, which can play a role of temporary buffering, switching, facilitating wiring and connection, and arranging chips in the packaging space. The substrate can also be called an interposer, a switching board, etc. The thickness of the substrate is generally greater than the thickness of the device. The dielectric layer in the substrate can be formed by a low-k dielectric (Low-K) material, and the RDL layer can be made by lamination and buried in the dielectric layer. The first carrier layer here can be prepared in advance with the substrate, or the first carrier layer can be formed on the RDL layer after the substrate is prepared, and the embodiments of the present disclosure do not limit this.

[0073] Step S130: forming a second carrier layer on the second metal interconnection layer.

[0074] In some embodiments, the second carrier layer is connected with the second metal interconnection layer.

[0075] In some embodiments, the second carrier layer includes a plurality of second lead-out points and an insulating medium between the lead-out points, and the second metal lines in the second metal interconnection layer are connected with the second lead-out points, so that the input and output interfaces of the second transistor can be led out to the second lead-out points. The second lead-out point can be made of a metal material, for example.

[0076] In the second scheme, after the flip-chip stacked transistors are flipped and buried in the first groove, the carrier wafer on the second metal interconnection layer is exposed on the surface of the first groove, so that the carrier wafer can be removed, and the second carrier layer is formed on the second metal interconnection layer.

[0077] In some embodiments, the carrier wafer can be removed by selective etching, or by thinning, but the thinning method will also remove part of the substrate, so a certain amount of allowance can be left when preparing the substrate.

[0078] In some embodiments, during the process of forming the flip-chip stacked transistors, the second carrier layer can be formed on the second metal interconnection layer of the front-side transistor before wafer bonding, and then the second carrier layer is bonded with a carrier wafer, and then the flipping is performed and the back-side transistor is prepared. In this way, after the carrier wafer is removed, the second carrier layer is exposed.

[0079] In some embodiments, after the second carrier layer is formed, a solder bump can be formed on the first carrier layer and the second carrier layer respectively, and the solder bump is connected with the circuit board. In the case that the interfaces on both sides of the flip-chip stacked transistors are led out, the flip-chip stacked transistors are packaged.

[0080] In the second scheme, in some embodiments, a metal connection structure can also be formed on the area on the substrate on the side of the RDL layer, which is used to connect with the chip mounted on the upper surface of the substrate, the upper surface being the surface of the substrate away from the RDL layer, and the height of the metal connection structure is the same as the height of the substrate.

[0081] In some embodiments, the dielectric layer can be etched on the area on the substrate on the side of the RDL layer to form a metal connection structure. In this way, the packaging space can be fully utilized to mount a chip above the substrate, and the chip can be connected to the metal connection structure through a solder point to realize the lead-out of the electrical signal of the chip. The type of chip is not limited in the embodiments of the present disclosure.

[0082] In some embodiments, the metal connection structure can be prepared in advance with the substrate, or can be formed by etching the area on the substrate on the side of the RDL layer when the chip is mounted. The embodiments of the present disclosure are not limited in this regard.

[0083] In some embodiments, the metal connection structure can be a through silicon via (TSV) structure, for example.

[0084] In the embodiments of the present disclosure, based on the flip stacked transistor including the first transistor and the second transistor in self-alignment, a first metal interconnection layer and a second metal interconnection layer are formed; an RDL layer and a first carrier layer formed on the RDL layer are formed to connect the first metal interconnection layer and the first carrier layer through the RDL layer; a second carrier layer is formed on the second metal interconnection layer, and the second carrier layer is connected with the second metal interconnection layer, so that the input and output interfaces of the flip stacked transistor on two sides can be led out from two directions.

[0085] In some embodiments, the embodiments of the present disclosure can realize the lead-out of the front and back transistor input and output interfaces through the carrier with the RDL layer and the substrate. Meanwhile, the scheme of forming the substrate can also fully utilize the packaging space to mount other chips, save the volume, and be beneficial to the further miniaturization of integrated circuits.

[0086] The interface lead-out method of the flip stacked transistor provided by the embodiments of the present disclosure will be described below taking the fin-shaped structure as an example. The first scheme will be introduced below, and FIG. 2 to FIG. 6 are structure schematic diagrams of the flip stacked transistor in the first interface lead-out process in the embodiments of the present disclosure, and FIG. 7 is a first structure schematic diagram of the flip stacked transistor in the embodiments of the present disclosure.

[0087] In an example, the interface lead-out method of the flip stacked transistor can include the following steps:

[0088] First step: prepare the first transistor 11 and complete the back-end interconnection to form the first metal interconnection layer 115, to obtain the structure as shown in FIG. 2.

[0089] It can be understood that the fin is first formed on the substrate 21 by a standard method to form a fin structure, and then the oxide material is deposited on the substrate 21 to form the shallow trench isolation structure 22. Based on the part of the fin structure away from the substrate, i.e., the first fin structure 111 (first active structure), the first source-drain structure 112, the first interlayer dielectric layer 113, the first gate structure (not shown in the figure), the first source-drain metal 114, and the first metal interconnection layer 115 of the first transistor 11 are formed. As shown in FIG. 2, the first metal interconnection layer 115 includes the first metal line 23.

[0090] Second step: form the RDL layer 24 and the first carrier layer 25 on the RDL layer 24, and bond the RDL layer 24 and the first carrier layer 25 with the first metal interconnection layer 115, to obtain the structure as shown in FIG. 3.

[0091] It can be understood that the RDL layer 24 includes the third metal line 241, one end of the third metal line 241 is connected with the first metal line 23, and the first metal line 23 (input / output interface) of the first transistor is led out through the RDL layer 241. Then the other end of the third metal line 241 of the RDL layer is led out through the first lead-out point 251 in the first carrier layer 25, to prepare for the subsequent chip packaging. The first carrier layer 25 includes a plurality of first lead-out points 251 and an insulating medium between the first lead-out points, and the insulating medium is used to isolate each first lead-out point. Here, the first transistor 11 and the first metal interconnection layer 115 are bonded with the carrier with the RDL layer. That is, the carrier here includes the RDL layer 24 and the first carrier layer 25.

[0092] It should be noted that in the previous preparation process of the flip stacked transistor, the first transistor is bonded with the ordinary carrier wafer as a whole. The carrier wafer only serves to support the transistor. However, in the embodiment of the present disclosure, this step is to connect the first transistor with the carrier with the RDL layer through hybrid bonding, so that the first transistor can be supported to complete the process of the second transistor, and the input / output interface of the first transistor can be led out.

[0093] Third step: flip the first transistor and remove the substrate 21 to expose the shallow trench isolation structure 22, to obtain the structure as shown in FIG. 4.

[0094] It can be understood that the structure shown in FIG. 3 is flipped and CMPed to the shallow trench isolation structure 22.

[0095] Fourth step: prepare the second transistor 12, and perform the subsequent process to form the second metal interconnection layer 125, to obtain the structure as shown in FIG. 5.

[0096] It can be understood that, above the shallow trench isolation structure 22, based on the upper half of the fin structure, that is, the second fin structure 121 (the second active structure), the second source-drain structure 122, the second interlayer dielectric layer 123, the second gate structure (not shown in the figure), the second source-drain metal 124, and the second metal interconnection layer 125 of the second transistor 12 are formed. As shown in FIG. 5, the second metal interconnection layer 125 includes the second metal line 26.

[0097] Fifth step: form the second carrier layer 27 on the second metal interconnection layer 125, to obtain the structure as shown in FIG. 6.

[0098] It can be understood that the second carrier layer 27 includes a plurality of second lead-out points 271 of the carrier layer and an insulating medium located between each second lead-out point, which is used to isolate each second lead-out point. The second lead-out point in the second carrier layer 27 is connected with the second metal line 26, so as to lead out the input and output interface of the second transistor.

[0099] Sixth step: form the solder joint 28 on each first lead-out point 251 of the first carrier layer 25 and each second lead-out point 271 of the second carrier layer 27, respectively, to obtain the structure as shown in FIG. 7.

[0100] It can be understood that the input and output interface of the first transistor is led out through the RDL layer and the first carrier layer, and the input and output interface of the second transistor is led out through the second carrier layer, so that the double-sided interface of the flip-chip stacked transistor can be led out.

[0101] The first scheme uses a wafer bonding process to replace the previous carrier wafer with a carrier with an RDL layer, so that the carrier can support the first transistor in the subsequent process and lead out the input and output interface of the first transistor, and is also compatible with the process of preparing the flip-chip stacked transistor.

[0102] The second scheme will be introduced below. FIGS. 8-12 are structure schematic diagrams of the flip-chip stacked transistor in the second interface leading-out process in the embodiment of the present disclosure, and FIG. 13 is a second structure schematic diagram of the flip-chip stacked transistor in the embodiment of the present disclosure.

[0103] In an example, the interface leading-out method of the flip-chip stacked transistor can include the following steps:

[0104] First step: prepare the substrate 30 including the RDL layer 24 and the metal connection structure 29 in advance, to obtain the structure as shown in FIG. 8.

[0105] It can be understood that the substrate 30 including the RDL layer can be prepared in advance. The substrate 30 can be prepared by lamination, and the RDL layer 24 is pressed in the substrate 30, and the metal connection structure 29 is formed in the substrate 30. The RDL layer 24 includes the first metal line 241, and the height of the metal connection structure 29 is equal to the height of the substrate 30. The metal connection structure can be a TSV structure as an example.

[0106] The second step is to prepare the recess 31 for embedding the flip-chip stacked transistor device by photolithography and etching, and obtain the structure as shown in FIG. 9.

[0107] In some embodiments, by controlling the etching thickness, the bottom of the formed recess 31 can be just at the RDL layer 24.

[0108] The third step is to fill the flip-chip stacked transistor in the recess 31, and obtain the structure as shown in FIG. 10.

[0109] It can be understood that the flip-chip stacked transistor including the first transistor 11, the second metal interconnection layer 115, the second transistor 12, and the second metal interconnection layer 125 can be prepared according to a standard process. The first transistor 11 includes the first fin structure 111, the first source-drain structure 112, the first interlayer dielectric layer 113, the first gate structure (not shown in the figure), the first source-drain metal 114, and the first metal interconnection layer 115 includes the first metal line 23. The second transistor 12 includes the second fin structure 121, the second source-drain structure 122, the second interlayer dielectric layer 123, the second gate structure (not shown in the figure), the second source-drain metal 124, and the second metal interconnection layer 125 includes the second metal line 26. In the preparation of the flip-chip stacked transistor, the second transistor and the second metal interconnection layer are prepared first, then the second transistor is flipped, and the first transistor and the first metal interconnection layer are prepared on the second transistor. After the flip-chip stacked transistor is flipped, the first transistor is located below.

[0110] In the process of preparing the flip-chip stacked transistor, after the second metal interconnection layer 125 is formed, the second carrier layer 27 can be formed on the second metal interconnection layer 125, and the second carrier layer 27 includes the second lead-out points 271 and the isolation medium between the second lead-out points. Then, the second carrier layer 27 is wafer bonded with the carrier wafer 32. Then, the flip-chip is performed to prepare the first transistor 11 and the first metal interconnection layer 115, and then the third carrier layer 33 can be formed on the first metal interconnection layer 115 to connect one end of the third metal line of the RDL layer through the third lead-out points in the third carrier layer 33.

[0111] The fourth step is to remove the carrier wafer 32, and obtain the structure as shown in FIG. 11.

[0112] It can be understood that after the removal of the carrier wafer 32, the second carrier layer 27 is exposed, so as to subsequently lead out the pins of the front-side transistors based on the second lead-out points 271 in the second carrier layer 27.

[0113] In some embodiments, the carrier wafer can be removed by selective etching, or by thinning. However, the thinning method also removes a part of the substrate, so a margin can be left at the beginning of the fabrication.

[0114] Step 5: Form the first carrier layer 25 on the RDL layer 24, and form the solder points 28 on the first lead-out points 251 of the first carrier layer 25 and the second lead-out points 271 of the second carrier layer 27 respectively, to obtain the structure as shown in FIG. 12.

[0115] It can be understood that the input and output interfaces of the first transistors are led out through the RDL layer and the first carrier layer, and the input and output interfaces of the second transistors are led out through the second carrier layer, so that the double-side interfaces of the flip-chip stacked transistors can be led out.

[0116] Step 6: Mount the chip 34 on the substrate 30, and connect the chip 34 with the metal connection structure 29 through the solder points 28, to obtain the structure as shown in FIG. 13.

[0117] It can be understood that the chip can include a memory and the like, and the input and output interfaces of the chip are led out through the metal connection structure, so that the electrical signals of the chip can be led out.

[0118] In the second scheme, the RDL layer and the metal connection structure are prepared in advance on the substrate, the depth and size of the substrate are strictly designed according to the flip-chip stacked transistors, then a groove is formed in the substrate by thinning or etching, the flip-chip stacked transistors are buried in the groove after being flipped, and the input and output interfaces are led out. Meanwhile, the substrate can also carry other chips, and the mounting of the other chips is realized by using the metal connection structure and the like, so as to fully utilize the packaging space.

[0119] In some embodiments, the flip-chip stacked transistor provided by the embodiments of the present disclosure can be detected by a detection analysis instrument, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), and the like. Taking the TEM as an example, the embodiments of the present disclosure can detect the packaging structure of the flip-chip stacked transistor as a whole in the TEM sectioning manner. In a first scheme, a slide with an RDL layer can be seen. In a second scheme, a substrate carrying an RDL layer and a buried flip-chip stacked transistor can be seen.

[0120] The embodiments of the present disclosure provide a semiconductor device, comprising the flip-chip stacked transistor of the above embodiments. The specific limitations of the flip-chip stacked transistor can be referred to the flip-chip stacked transistor described above, which will not be repeated here.

[0121] The embodiments of the present disclosure provide an electronic device, comprising a circuit board and the semiconductor device of the above embodiments, wherein the semiconductor device is arranged on the circuit board. The semiconductor device comprises the flip-chip stacked transistor described above, which will not be repeated here.

[0122] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0123] The above is only an exemplary embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. An interface lead-out method of flip-chip stacked transistors, comprising: forming a first metal interconnection layer and a second metal interconnection layer based on a flip-chip stacked transistor, the flip-chip stacked transistor comprising a first transistor and a second transistor in self-alignment, the second metal interconnection layer, the second transistor, the first transistor and the first metal interconnection layer being stacked in a first direction in sequence; forming a redistribution layer (RDL) and a first carrier layer formed on the RDL, the first metal interconnection layer being connected to the first carrier layer through the RDL; forming a second carrier layer on the second metal interconnection layer, the second carrier layer being connected to the second metal interconnection layer.

2. The method of claim 1, wherein, The first metal interconnection layer comprises a first metal line, the second metal interconnection layer comprises a second metal line, the RDL comprises a third metal line, the first carrier layer comprises a first lead-out point, and the second carrier layer comprises a second lead-out point; one end of the third metal line is connected to the first metal line, the other end of the third metal line is connected to the first lead-out point, and the second lead-out point is connected to the second metal line.

3. The method of claim 1, wherein, The forming of the RDL and the first carrier layer formed on the RDL comprises: forming the RDL and the first carrier layer on the RDL after forming the first metal interconnection layer and before forming the second metal interconnection layer; bonding the RDL and the first carrier layer to the first metal interconnection layer so that the RDL is attached to the first metal interconnection layer.

4. The method of claim 1, wherein, The forming of the RDL and the first carrier layer formed on the RDL comprises: forming a substrate, the substrate comprising the RDL and a dielectric layer stacked in the first direction, the first carrier layer being formed on the RDL; opening a first slot on the dielectric layer; de-flipping the flip-chip stacked transistor and embedding it into the first slot.

5. The method of claim 4, wherein, The method further comprises: forming a metal connection structure on an area of the substrate on a side of the RDL, the metal connection structure being used to connect to a chip mounted on an upper surface of the substrate, the upper surface being a surface of the substrate away from the RDL, the height of the metal connection structure being the same as the height of the substrate.

6. The method according to any one of claims 1 to 5, wherein, The method further comprises: forming a solder joint on the first carrier layer and the second carrier layer respectively, and connecting to a circuit board through the solder joint.

7. The method of claim 1, wherein, The method further comprises: forming an active structure on a substrate, the active structure comprising a first active structure and a second active structure, the first active structure being away from the substrate relative to the second active structure; forming the first transistor based on the first active structure, the first transistor comprising a first source-drain structure, a first interlayer dielectric layer, a first gate structure and a first source-drain metal; forming the second transistor based on the second active structure, the second transistor comprising a second source-drain structure, a second interlayer dielectric layer, a second gate structure and a second source-drain metal.

8. A flip-chip stacked transistor, prepared by the method of any one of claims 1 to 7, comprising: a first transistor, a second transistor, a first metal interconnection layer, and a second metal interconnection layer, the first transistor is self-aligned with the second transistor, the second metal interconnection layer, the second transistor, the first transistor, and the first metal interconnection layer are stacked in a first direction; a redistribution layer (RDL) layer and a first carrier layer on the RDL layer, the first metal interconnection layer is connected to the first carrier layer through the RDL layer; a second carrier layer on the second metal interconnection layer, the second carrier layer is connected to the second metal interconnection layer. The flip-chip stacked transistor is embedded in a substrate, the substrate comprises the RDL layer and a dielectric layer stacked in the first direction, the first carrier layer is formed on the RDL layer.

9. The inverted stack transistor of claim 8, wherein, The flip-chip stacked transistor of claim 8 or 9.

10. A semiconductor device comprising: A circuit board and the semiconductor device of claim 10, the semiconductor device is disposed on the circuit board.

11. An electronic device comprising: ​

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