Data processing method, apparatus and system

Abstract

Disclosed in the embodiments of the present application are a data processing method and a data processing apparatus, which are applicable to metropolitan-area telecommunications transmission and DCI scenarios with data rates greater than 800 Gbps (including 1.2 Tbps, 1.6 Tbps, etc.). The method specifically comprises: acquiring first data, which comprises din bits, wherein din is an integer greater than or equal to 1; performing CRC on or inserting padding bits into the first data, so as to obtain second data, which comprises dscr bits, wherein the second data comprises dCRC CRC bits or dPAD padding bits, dCRC and dPAD both being integers greater than or equal to 0, and dscr=din+dCRC+dPAD; scrambling the second data to obtain third data, which comprises dscr bits; performing first processing on the third data to obtain fourth data, wherein the first processing comprises probabilistic constellation shaping (PCS) processing, interleaving and encoding; and performing second processing on the fourth data to obtain W first dual-polarization symbol streams, wherein W is an integer greater than 1, and the second processing comprises symbol mapping, polarization division and framing.

Description

A data processing method, apparatus and system

[0001] This application claims priority to two Chinese patent applications filed with the State Intellectual Property Office on July 24, 2024, application number 202411003298.1, entitled "A Data Processing Method, Apparatus and System", and on August 15, 2024, application number 202411125282.8, entitled "A Data Processing Method, Apparatus and System", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to a data processing method, apparatus and system. Background Technology

[0003] Driven by 5G, cloud computing, big data, and artificial intelligence, high-speed optical transmission networks are developing towards higher capacity, packetization, and intelligence. Coherent optical communication systems utilize the amplitude, phase, polarization, or frequency of light waves to carry information. Coherent optical communication systems typically employ efficient forward error correction (FEC) codes to combat optical impairments during optical transmission, maintaining a sufficiently low bit error rate over long distances. For example, the Open FEC code (OFEC code) adopted by the current 400ZR+ and 800ZR standards has an overhead (OH) of 15.3% and a soft-decision decoding performance of approximately 2.0E-2 before correction.

[0004] To improve spectral efficiency, multi-level quadrature amplitude modulation (QAM) is commonly used, such as 16QAM, 32QAM, 64QAM, or even higher-order QAM. In traditional QAM modulation, each constellation point on the signal constellation diagram appears with the same probability. Probabilistic constellation shaping (PCS) technology changes the probability of constellation points while keeping their positions constant, making them non-uniformly distributed, thereby improving system transmission performance. As a modulation format optimization technique, PCS has advantages such as approaching the Shannon limit and flexibility, and has been widely researched and applied.

[0005] Considering future scenarios such as metropolitan area telecommunications transmission and data center interconnect (DCI) at speeds of 1.6 terabit per second (Tbps), the baud rate corresponding to a single-wavelength transmission scheme using oFEC coding and DP-16QAM modulation is approximately 240 Gbaud. For transmission schemes employing PCS technology, the corresponding baud rate is even higher, typically greater than 250 Gbaud. At this point, traditional digital signal processing (DSP) becomes highly complex, and enhanced phase noise equalization (EEPN) is costly, representing a pressing issue that needs to be addressed in the future. Summary of the Invention

[0006] This application provides a data processing method and a data processing apparatus applicable to metropolitan area telecommunications transmission and DCI scenarios with speeds of 800 gigabits per second (Gbps) or higher (including 1.2Tbps and 1.6Tbps, etc.).

[0007] Firstly, embodiments of this application provide a data processing method. Specifically, it involves acquiring first data, which includes d in bits, d in The integer is greater than or equal to 1. Cyclic Redundancy Check (CRC) is performed on the first data, or padding bits are inserted to obtain the result including d. scr The second data consists of bits, the second data including d CRC One CRC check bit or d PAD One padding bit, d CRC and d PAD All are integers greater than or equal to 0, d scr =d in +d CRC +d PAD The second data is scrambled to obtain the third data, which includes d. scr The third data is processed in a first step to obtain the fourth data. This first processing includes Probabilistic Constellation Shaping (PCS) processing, interleaving, and coding. The fourth data is then processed in a second step to obtain W first dual-polarization symbol streams, where W is an integer greater than 1. This second processing includes symbol mapping, polarization division, and framing. Alternatively, W can be 1, corresponding to the single-carrier case.

[0008] In this embodiment, the baud rate corresponding to each of the W first dual-polarization symbol streams obtained by the above data processing method is 1 / W of the baud rate of the traditional single-carrier scheme. Therefore, the data processing method provided in this application embodiment can use devices with lower baud rates and is applicable to metropolitan area telecommunications transmission and data center transmission scenarios requiring low power consumption. It also helps to reduce the complexity of dispersion compensation at the receiver, reduce the cost of enhanced equalization phase noise (EEPN), and improve the data transmission rate.

[0009] In some possible implementations, performing a first processing step on the third data to obtain the fourth data includes: acquiring a first bit set from the third data, the first bit set comprising m bits, where m is an integer greater than 1; performing PCS processing on a first subset of the first bit set to obtain a second bit subset; and interleaving and encoding the second bit subset and a third bit subset from the first bit set excluding the first bit subset to obtain a second bit set, wherein the fourth data includes the second bit set. This implementation provides a specific flow of the first processing step, which uses PCS processing to change the probability of constellation points appearing while keeping their positions unchanged, making them non-uniformly distributed, thereby improving system transmission performance.

[0010] In some possible implementations, the fourth data undergoes the second processing to obtain W frames, each of the W first dual-polarization symbol streams comprising one frame from the W frames, the symbol mapping employs 16-ary Quadrature Amplitude Modulation (16QAM) symbol mapping, the second bit set comprises 4096 bits, and each 8×N bit in the fourth data... CW N bits are processed in the second step to obtain one frame. CW =172032. In this embodiment, the first data can be processed by the data processing method provided in this application embodiment to obtain exactly W frames. This data processing method is simple to implement, has low hardware complexity, and lower power consumption.

[0011] In some possible implementations,

[0012] In some possible implementations, d in =q×r,d CP =d CRC +d PAD q = 2056, W = 2, d in r, m and d CPThe following table shows the relationships:

[0013] The table above corresponds to N. CW =172032 and W=2; it can also be used for N CW =86016 and W=4; it can also be used for N CW =43008 and W=8; it can also be used for N CW =344064 and W=1 (single carrier); that is, all other things being equal, only N CW In the above scenarios where the specific value of W differs somewhat from that of d, in r, m and d CP All will satisfy one of the relationships shown in the table above. Furthermore, the table above can be applied to N. CW The scenario is ×W = 344064.

[0014] In some possible implementations, d in =q×r,d CP =d CRC +d PAD q = 2056, W = 4, d in r, m and d CP The following table shows the relationships:

[0015] The table above corresponds to N. CW =172032 and W=4; it can also be used for N CW =344064 and W=2; it can also be used for N CW =86016 and W=8; it can also be used for N CW The scenario is where N = 688128 and W = 1 (single carrier). That is, all other things being equal, only N... CW In the above scenarios where the specific value of W differs somewhat from that of d, in r, m and d CP All will satisfy one of the relationships shown in the table above. Furthermore, the table above can be applied to N. CW The scenario is ×W = 688128.

[0016] In some possible implementations, d in =q×r,d CP =d CRC +d PAD q = 2056, W = 8, d inr, m and d CP The following table shows the relationships:

[0017] The table above corresponds to N. CW =172032 and W=8; it can also be used for N CW =688128 and W=2; it can also be used for N CW =344064 and W=4; it can also be used for N CW The scenario is where N = 1376256 and W = 1 (single carrier). That is, all other things being equal, only N... CW In the above scenarios where the specific value of W differs somewhat from that of d, in r, m and d CP All will satisfy one of the relationships shown in the table above. Furthermore, the table above can be applied to N. CW The scenario is ×W = 1376256.

[0018] In some possible implementations, performing CRC on the first data includes: if r is an integer multiple of 20, performing CRC-32 on every 20 rows (20 × 2056 bits) of the first data to add a CRC check bit of length 32 bits, d CRC = r / 20×32; or, if r is not an integer multiple of 20, perform CRC-32 on every 20 rows (20×2056 bits) in the first 20×(p-1) rows of the first data to add a CRC check bit of length 32 bits, and perform CRC-32 on the last r1 rows (r1×2056 bits) of the first data to add a CRC check bit of length 32 bits, where, r1 = r - 20 × (p - 1), This indicates that 'a' is rounded down.

[0019] In some possible implementations, d in =q×r,d CP =d CRC +d PAD q = 10280, W = 2, d in r, m and d CP The following table shows the relationships:

[0020] The table above also corresponds to N. CW=172032 and W=2; it can also be used for N CW =86016 and W=4; it can also be used for N CW =43008 and W=8; it can also be used for N CW =344064 and W=1 (single carrier); that is, all other things being equal, only N CW In the above scenarios where the specific value of W differs somewhat from that of d, in r, m and d CP All will satisfy one of the relationships shown in the table above. Furthermore, the table above can be applied to N. CW The scenario is ×W = 344064.

[0021] In some possible implementations, d in =q×r,d CP =d CRC +d PAD q = 10280, W = 4, d in r, m and d CP The following table shows the relationships:

[0022] The table above corresponds to N. CW =172032 and W=4; it can also be used for N CW =344064 and W=2; it can also be used for N CW =86016 and W=8; it can also be used for N CW The scenario is where N = 688128 and W = 1 (single carrier). That is, all other things being equal, only N... CW In the above scenarios where the specific value of W differs somewhat from that of d, in r, m and d CP All will satisfy one of the relationships shown in the table above. Furthermore, the table above can be applied to N. CW The scenario is ×W = 688128.

[0023] In some possible implementations, d in =q×r,d CP =d CRC +d PAD q = 10280, W = 8, d in r, m and d CP The following table shows the relationships:

[0024] The table above corresponds to N. CW =172032 and W=8; it can also be used for NCW =688128 and W=2; it can also be used for N CW =344064 and W=4; it can also be used for N CW The scenario is where N = 1376256 and W = 1 (single carrier). That is, all other things being equal, only N... CW In the above scenarios where the specific value of W differs somewhat from that of d, in r, m and d CP All will satisfy one of the relationships shown in the table above. Furthermore, the table above can be applied to N. CW The scenario is ×W = 1376256.

[0025] In some possible implementations, performing CRC on the first data includes: if r is an integer multiple of 4, performing CRC-32 on every 4 rows (4 × 10280 bits) of the first data to add a CRC check bit of length 32 bits, d CRC = r / 4×32; or, if r is not an integer multiple of 4, perform CRC-32 on every 4 rows (4×10280 bits) of the first 4×(p-1) rows of the first data to add a CRC check bit of length 32 bits, and perform CRC-32 on the last r1 rows (r1×10280 bits) of the first data to add a CRC check bit of length 32 bits, where, r1 = r - 4 × (p - 1), This indicates that 'a' is rounded down.

[0026] In some possible implementations, d in =q×r,d CP =d CRC +d PAD q = 5140, W = 2, d in r, m and d CP The following table shows the relationships:

[0027] The table above also corresponds to N. CW =172032 and W=2; it can also be used for N CW =86016 and W=4; it can also be used for N CW =43008 and W=8; it can also be used for N CW =344064 and W=1 (single carrier); that is, all other things being equal, only N CW In the above scenarios where the specific value of W differs somewhat from that of d, in r, m and d CPAll will satisfy one of the relationships shown in the table above. Furthermore, the table above can be applied to N. CW The scenario is ×W = 344064.

[0028] In some possible implementations, d in =q×r,d CP =d CRC +d PAD q = 5140, W = 4, d in r, m and d CP The following table shows the relationships:

[0029] The table above corresponds to N. CW =172032 and W=4; it can also be used for N CW =344064 and W=2; it can also be used for N CW =86016 and W=8; it can also be used for N CW The scenario is where N = 688128 and W = 1 (single carrier). That is, all other things being equal, only N... CW In the above scenarios where the specific value of W differs somewhat from that of d, in r, m and d CP All will satisfy one of the relationships shown in the table above. Furthermore, the table above can be applied to N. CW The scenario is ×W = 688128.

[0030] In some possible implementations, d in =q×r,d CP =d CRC +d PAD q = 5140, W = 8, d in r, m and d CP The following table shows the relationships:

[0031] The table above corresponds to N. CW =172032 and W=8; it can also be used for N CW =688128 and W=2; it can also be used for N CW =344064 and W=4; it can also be used for N CW The scenario is where N = 1376256 and W = 1 (single carrier). That is, all other things being equal, only N... CW In the above scenarios where the specific value of W differs somewhat from that of d, in r, m and dCP All will satisfy one of the relationships shown in the table above. Furthermore, the table above can be applied to N. CW The scenario is ×W = 1376256.

[0032] In some possible implementations, m is an integer multiple of 32.

[0033] In some possible implementations, performing PCS processing on a first subset of bits in the first bit set to obtain a second subset of bits includes: performing PCS processing on every k0 bits in the first subset of bits to obtain n0 bits in the second subset of bits, wherein the first subset of bits includes v = m - 1504 bits, v is an integer multiple of 16, k0 = v / 16, n0 = 128, and the second subset of bits includes 2048 bits. That is, this implementation can divide the PCS processing into 16 PCS sub-processes, making the implementation of PCS processing simpler and reducing the complexity of a single PCS sub-process.

[0034] In some possible implementations, performing PCS processing on a first subset of bits in the first bit set to obtain a second subset of bits includes: performing PCS processing on every k0 bits in the first subset of bits to obtain n0 bits in the second subset of bits, wherein the first subset of bits includes v = m - 1504 bits, v is an integer multiple of 32, k0 = v / 32, n0 = 64, and the second subset of bits includes 2048 bits. That is, this implementation can divide the PCS processing into 32 PCS sub-processes, making the implementation of PCS processing simpler and reducing the complexity of a single PCS sub-process.

[0035] In some possible implementations, the first data comprises r rows and q columns of bits, where r and q are both integers greater than 0.

[0036] In some possible implementations, the fourth data includes M first data streams, where M is an integer greater than 0. The second processing of the fourth data to obtain W first dual-polarization symbol streams includes: performing symbol mapping, polarization division, and framing on the M first data streams respectively to obtain the W first dual-polarization symbol streams, where W = M.

[0037] In some possible implementations, the fourth data includes M first data streams, where M is an integer greater than 0. The second processing of the fourth data to obtain W first dual-polarization symbol streams includes: distributing the M first data streams to obtain W second data streams; and performing symbol mapping, polarization partitioning, and framing on the W second data streams to obtain the W first dual-polarization symbol streams. In this implementation, the data distribution ensures that the data in the M first data streams is more evenly distributed into the W dual-polarization symbol data streams after polarization partitioning and symbol mapping, resulting in better overall performance and better resistance to burst errors.

[0038] In some possible implementations, the fourth data includes M first data streams, where M is an integer greater than 0. The second processing of the fourth data to obtain W first dual-polarization symbol streams includes: performing symbol mapping and polarization partitioning on the M first data streams respectively to obtain M second dual-polarization symbol streams; distributing the M second dual-polarization symbol streams to obtain W third dual-polarization symbol streams; and framing the W third dual-polarization symbol streams respectively to obtain the W first dual-polarization symbol streams. In this implementation, the data distribution ensures that the data in the M first data streams is more evenly distributed into the W dual-polarization symbol data streams after polarization partitioning and symbol mapping, resulting in better overall performance and better resistance to burst errors.

[0039] In some possible implementations, the W first dual-polarization symbol streams are transmitted on W optical signals, with any two of the W optical signals having different wavelengths. Alternatively, the W first dual-polarization symbol streams are transmitted through W optical fibers. It should be understood that the baud rate corresponding to each optical signal or each optical fiber is 1 / W of the baud rate of the traditional single-carrier scheme. In this case, the corresponding data processing method can use devices with lower baud rates, which is suitable for metropolitan area telecommunications transmission and data center transmission scenarios requiring low power consumption. Alternatively, the W first dual-polarization symbol streams are transmitted on W subcarriers, and the W subcarriers are multiplexed to obtain one optical signal to be transmitted. It should be understood that the baud rate corresponding to each subcarrier is 1 / W of the baud rate of the transmitted signal. Compared with the above implementation using W optical signals or W optical fibers, the subcarrier implementation requires devices with higher baud rates, and the device power consumption may be higher. The subcarrier implementation allows the receiving-end DSP to process each subcarrier, which can significantly reduce the complexity of dispersion compensation, reduce the cost of EEPPN, and thus reduce the DSP power consumption.

[0040] Secondly, embodiments of this application provide a data processing apparatus. The data processing apparatus includes: a first processing unit and a second processing unit. The first processing unit is configured to: acquire first data, the first data including d in bits, d in The integer is greater than or equal to 1; perform CRC on the first data or insert padding bits to obtain a result including d. scr The second data consists of bits, the second data including d CRC One CRC check bit or d PAD One padding bit, d CRC and d PAD All are integers greater than or equal to 0, d scr =d in +d CRC +d PAD The second data is scrambled to obtain the third data, which includes d. scr The second processing unit is configured to: perform a first processing on the third data to obtain fourth data, the first processing including PCS processing, interleaving, and encoding; and perform a second processing on the fourth data to obtain W first dual-polarization symbol streams, where W is an integer greater than 1, the second processing including symbol mapping, polarization division, and framing. Alternatively, W can also be 1, corresponding to the single-carrier case.

[0041] In some possible implementations, the second processing unit is specifically used to: acquire a first bit set from the third data, the first bit set comprising m bits, where m is an integer greater than 1; perform PCS processing on a first subset of bits in the first bit set to obtain a second bit subset; and interleave and encode the second bit subset and a third bit subset from the first bit set excluding the first bit subset to obtain a second bit set, wherein the fourth data includes the second bit set. This implementation provides a specific flow of the first processing, which uses PCS processing to change the probability of constellation points appearing while keeping their positions unchanged, making them non-uniformly distributed, thereby improving system transmission performance.

[0042] In some possible implementations, the fourth data undergoes the second processing to obtain W frames, each of the W first dual-polarization symbol streams includes one frame from the W frames, the symbol mapping employs 16QAM symbol mapping, the second bit set includes 4096 bits, and the fourth data is divided into 8×N... CW N bits are processed in the second step to obtain one frame. CW=172032. In this embodiment, the first data can be processed by the data processing method provided in this application embodiment to obtain exactly W frames. This data processing method is simple to implement, has low hardware complexity, and lower power consumption.

[0043] In some possible implementations,

[0044] In some possible implementations, d in =q×r,d CP =d CRC +d PAD q = 2056, W = 2, d in r, m and d CP The following table shows the relationships:

[0045] The table above corresponds to N. CW =172032 and W=2; it can also be used for N CW =86016 and W=4; it can also be used for N CW =43008 and W=8; it can also be used for N CW =344064 and W=1 (single carrier); that is, all other things being equal, only N CW In the above scenarios where the specific value of W differs somewhat from that of d, in r, m and d CP All will satisfy one of the relationships shown in the table above. Furthermore, the table above can be applied to N. CW The scenario is ×W = 344064.

[0046] In some possible implementations, d in =q×r,d CP =d CRC +d PAD q = 2056, W = 4, d in r, m and d CP The following table shows the relationships:

[0047] The table above corresponds to N. CW =172032 and W=4; it can also be used for N CW =344064 and W=2; it can also be used for N CW =86016 and W=8; it can also be used for NCW The scenario is where N = 688128 and W = 1 (single carrier). That is, all other things being equal, only N... CW In the above scenarios where the specific value of W differs somewhat from that of d, in r, m and d CP All will satisfy one of the relationships shown in the table above. Furthermore, the table above can be applied to N. CW The scenario is ×W = 688128.

[0048] In some possible implementations, d in =q×r,d CP =d CRC +d PAD q = 2056, W = 8, d in r, m and d CP The following table shows the relationships:

[0049] The table above corresponds to N. CW =172032 and W=8; it can also be used for N CW =688128 and W=2; it can also be used for N CW =344064 and W=4; it can also be used for N CW The scenario is where N = 1376256 and W = 1 (single carrier). That is, all other things being equal, only N... CW In the above scenarios where the specific value of W differs somewhat from that of d, in r, m and d CP All will satisfy one of the relationships shown in the table above. Furthermore, the table above can be applied to N. CW The scenario is ×W = 1376256.

[0050] In some possible implementations, the first processing unit is specifically used to: if r is an integer multiple of 20, perform CRC-32 on every 20 rows (20 × 2056 bits) of the first data to add a CRC check bit of length 32 bits, d CRC = r / 20×32; or, if r is not an integer multiple of 20, perform CRC-32 on every 20 rows (20×2056 bits) in the first 20×(p-1) rows of the first data to add a CRC check bit of length 32 bits, and perform CRC-32 on the last r1 rows (r1×2056 bits) of the first data to add a CRC check bit of length 32 bits, where, r1 = r - 20 × (p - 1), This indicates that 'a' is rounded down.

[0051] In some possible implementations, d in =q×r,d CP =d CRC +d PAD q = 10280, W = 2, d in r, m and d CP The following table shows the relationships:

[0052] The table above also corresponds to N. CW =172032 and W=2; it can also be used for N CW =86016 and W=4; it can also be used for N CW =43008 and W=8; it can also be used for N CW =344064 and W=1 (single carrier); that is, all other things being equal, only N CW In the above scenarios where the specific value of W differs somewhat from that of d, in r, m and d CP All will satisfy one of the relationships shown in the table above. Furthermore, the table above can be applied to N. CW The scenario is ×W = 344064.

[0053] In some possible implementations, d in =q×r,d CP =d CRC +d PAD q = 10280, W = 4, d in r, m and d CP The following table shows the relationships:

[0054] The table above corresponds to N. CW =172032 and W=4; it can also be used for N CW =344064 and W=2; it can also be used for N CW =86016 and W=8; it can also be used for N CW The scenario is where N = 688128 and W = 1 (single carrier). That is, all other things being equal, only N... CW In the above scenarios where the specific value of W differs somewhat from that of d, in r, m and d CP All will satisfy one of the relationships shown in the table above. Furthermore, the table above can be applied to N. CW The scenario is ×W = 688128.

[0055] In some possible implementations, d in =q×r,d CP =d CRC +d PAD q = 10280, W = 8, d in r, m and d CP The following table shows the relationships:

[0056] The table above corresponds to N. CW =172032 and W=8; it can also be used for N CW =688128 and W=2; it can also be used for N CW =344064 and W=4; it can also be used for N CW The scenario is where N = 1376256 and W = 1 (single carrier). That is, all other things being equal, only N... CW In the above scenarios where the specific value of W differs somewhat from that of d, in r, m and d CP All will satisfy one of the relationships shown in the table above. Furthermore, the table above can be applied to N. CW The scenario is ×W = 1376256.

[0057] In some possible implementations, the first processing unit is specifically used to: if r is an integer multiple of 4, perform CRC-32 on every 4 rows (4 × 10280 bits) of the first data to add a CRC check bit of length 32 bits, d CRC = r / 4×32; or, if r is not an integer multiple of 4, perform CRC-32 on every 4 rows (4×10280 bits) of the first 4×(p-1) rows of the first data to add a CRC check bit of length 32 bits, and perform CRC-32 on the last r1 rows (r1×10280 bits) of the first data to add a CRC check bit of length 32 bits, where, r1 = r - 4 × (p - 1), This indicates that 'a' is rounded down.

[0058] In some possible implementations, d in =q×r,d CP =d CRC +d PAD q = 5140, W = 2, d in r, m and d CP The following table shows the relationships:

[0059] The table above also corresponds to N. CW =172032 and W=2; it can also be used for N CW =86016 and W=4; it can also be used for N CW =43008 and W=8; it can also be used for N CW =344064 and W=1 (single carrier); that is, all other things being equal, only N CW In the above scenarios where the specific value of W differs somewhat from that of d, in r, m and d CP All will satisfy one of the relationships shown in the table above. Furthermore, the table above can be applied to N. CW The scenario is ×W = 344064.

[0060] In some possible implementations, d in =q×r,d CP =d CRC +d PAD q = 5140, W = 4, d in r, m and d CP The following table shows the relationships:

[0061] The table above corresponds to N. CW =172032 and W=4; it can also be used for N CW =344064 and W=2; it can also be used for N CW =86016 and W=8; it can also be used for N CW The scenario is where N = 688128 and W = 1 (single carrier). That is, all other things being equal, only N... CW In the above scenarios where the specific value of W differs somewhat from that of d, in r, m and d CP All will satisfy one of the relationships shown in the table above. Furthermore, the table above can be applied to N. CW The scenario is ×W = 688128.

[0062] In some possible implementations, d in =q×r,d CP =d CRC +d PAD q = 5140, W = 8, d in r, m and d CP The following table shows the relationships:

[0063] The table above corresponds to N. CW =172032 and W=8; it can also be used for N CW =688128 and W=2; it can also be used for N CW =344064 and W=4; it can also be used for N CW The scenario is where N = 1376256 and W = 1 (single carrier). That is, all other things being equal, only N... CW In the above scenarios where the specific value of W differs somewhat from that of d, in r, m and d CP All will satisfy one of the relationships shown in the table above. Furthermore, the table above can be applied to N. CW The scenario is ×W = 1376256.

[0064] In some possible implementations, m is an integer multiple of 32.

[0065] In some possible implementations, the second processing unit is specifically used to: perform PCS processing on every k0 bits in the first bit subset to obtain n0 bits in the second bit subset, wherein the first bit subset includes v = m - 1504 bits, v is an integer multiple of 16, k0 = v / 16, n0 = 128, and the second bit subset includes 2048 bits. That is, this implementation can divide the PCS processing into 16 PCS sub-processes, making the implementation of PCS processing simpler and reducing the complexity of a single PCS sub-process.

[0066] In some possible implementations, the second processing unit is specifically used to: perform PCS processing on every k0 bits in the first bit subset to obtain n0 bits in the second bit subset, wherein the first bit subset includes v = m - 1504 bits, v is an integer multiple of 32, k0 = v / 32, n0 = 64, and the second bit subset includes 2048 bits. That is, this implementation can divide the PCS processing into 32 PCS sub-processes, making the implementation of PCS processing simpler and reducing the complexity of a single PCS sub-process.

[0067] In some possible implementations, the first data comprises r rows and q columns of bits, where r and q are both integers greater than 0.

[0068] In some possible implementations, the fourth data includes M first data streams, where M is an integer greater than 0, and the second processing unit is specifically used to: perform symbol mapping, polarization division, and framing on the M first data streams respectively to obtain the W first dual-polarization symbol streams, where W = M.

[0069] In some possible implementations, the fourth data includes M first data streams, where M is an integer greater than 0. The second processing unit is specifically used to: distribute the M first data streams to obtain W second data streams; and perform symbol mapping, polarization partitioning, and framing on the W second data streams to obtain the W first dual-polarization symbol streams. In this implementation, the data distribution ensures that the data in the M first data streams is distributed more evenly to the W dual-polarization symbol data streams after polarization partitioning and symbol mapping, thereby achieving better overall performance and better resistance to burst errors.

[0070] In some possible implementations, the fourth data includes M first data streams, where M is an integer greater than 0. The second processing unit is specifically configured to: perform symbol mapping and polarization partitioning on the M first data streams to obtain M second dual-polarized symbol streams; distribute the M second dual-polarized symbol streams to obtain W third dual-polarized symbol streams; and frame the W third dual-polarized symbol streams to obtain the W first dual-polarized symbol streams. In this implementation, data distribution ensures that the data in the M first data streams is distributed more evenly to the W dual-polarized symbol data streams after polarization partitioning and symbol mapping, resulting in better overall performance and better resistance to burst errors.

[0071] In some possible implementations, the W first dual-polarization symbol streams are transmitted on W optical signals, with any two of the W optical signals having different wavelengths. Alternatively, the W first dual-polarization symbol streams are transmitted through W optical fibers. It should be understood that the baud rate corresponding to each optical signal or each optical fiber is 1 / W of the baud rate of the traditional single-carrier scheme. In this case, the corresponding data processing method can use devices with lower baud rates, which is suitable for metropolitan area telecommunications transmission and data center transmission scenarios requiring low power consumption. Alternatively, the W first dual-polarization symbol streams are transmitted on W subcarriers, and the W subcarriers are multiplexed to obtain one optical signal to be transmitted. It should be understood that the baud rate corresponding to each subcarrier is 1 / W of the baud rate of the transmitted signal. Compared with the above implementation using W optical signals or W optical fibers, the subcarrier implementation requires devices with higher baud rates, and the device power consumption may be higher. The subcarrier implementation allows the receiving-end DSP to process each subcarrier, which can significantly reduce the complexity of dispersion compensation, reduce the cost of EEPPN, and thus reduce the DSP power consumption.

[0072] Thirdly, a data processing method is provided, comprising: acquiring first data, wherein the first data includes d in bits, d inThe integer is greater than or equal to 1; the first data is subjected to cyclic redundancy check (CRC) or padding bits are inserted to obtain the result including d. scr The second data consists of bits, the second data including d CRC One CRC check bit or d PAD One padding bit, d CRC and d PAD All are integers greater than or equal to 0, d scr =d in +d CRC +d PAD The second data is scrambled to obtain the third data, which includes d. scr 1 bit; the third data is processed in a first process to obtain the fourth data, the first process including probabilistic constellation shaping (PCS) processing, interleaving, and coding; the fourth data is processed in a second process to obtain W first dual-polarization symbol streams, where W is an integer greater than 0, the second process including symbol mapping, polarization division, and framing; wherein, d in =q×r,d CP =d CRC +d PAD , q = 2056, d in r and d CP It satisfies any of the relationships shown in Tables 9, 10 and 19 of the specification.

[0073] The data processing method provided in this application can use devices with lower baud rates, making it suitable for metropolitan area telecommunications and data center transmission scenarios requiring low power consumption. It also helps reduce the complexity of dispersion compensation at the receiving end, lowers the cost of equalization and phase noise enhancement, and increases the data transmission rate.

[0074] In some possible implementations, performing a first processing step on the third data to obtain the fourth data includes: acquiring a first bit set from the third data, the first bit set comprising m bits, where m is an integer greater than 1; performing PCS processing on a first subset of the first bit set to obtain a second bit subset; and interleaving and encoding the second bit subset and a third bit subset from the first bit set excluding the first bit subset to obtain a second bit set, wherein the fourth data includes the second bit set. This implementation provides a specific flow of the first processing step, which uses PCS processing to change the probability of constellation points appearing while keeping their positions unchanged, making them non-uniformly distributed, thereby improving system transmission performance.

[0075] In some possible implementations, the fourth data undergoes the second processing to obtain W frames, each of the W first dual-polarization symbol streams includes one frame from the W frames, the symbol mapping employs 16QAM symbol mapping, the second bit set includes 4096 bits, and the fourth data is divided into 8×N... CW Each bit is processed by the second method to obtain one frame. In this embodiment, the first data can obtain exactly W frames through the data processing method provided in this application. This data processing method is simple to implement, has low hardware complexity, and lower power consumption.

[0076] In some possible implementations,

[0077] In some possible implementations, the value of m is shown in any of Tables 9, 10, and 19 of the specification, and is related to d. in r and d CP The relationship also satisfies the relationship shown in any of Tables 9, 10 and 19 in the specification.

[0078] In some possible implementations, performing CRC on the first data includes: if r is an integer multiple of 20, performing CRC-32 on every 20 rows (20 × 2056 bits) of the first data to add a CRC check bit of length 32 bits, d CRC = r / 20×32; or, if r is not an integer multiple of 20, perform CRC-32 on every 20 rows (20×2056 bits) in the first 20×(p-1) rows of the first data to add a CRC check bit of length 32 bits, and perform CRC-32 on the last r1 rows (r1×2056 bits) of the first data to add a CRC check bit of length 32 bits, where, r1 = r - 20 × (p - 1), This indicates that 'a' is rounded down.

[0079] In some possible implementations, m is an integer multiple of 32.

[0080] In some possible implementations, performing PCS processing on a first subset of bits in the first bit set to obtain a second subset of bits includes: performing PCS processing on every k0 bits in the first subset of bits to obtain n0 bits in the second subset of bits, wherein the first subset of bits includes v = m - 1504 bits, v is an integer multiple of 16, k0 = v / 16, n0 = 128, and the second subset of bits includes 2048 bits. That is, this implementation can divide the PCS processing into 16 PCS sub-processes, making the implementation of PCS processing simpler and reducing the complexity of a single PCS sub-process.

[0081] In some possible implementations, performing PCS processing on a first subset of bits in the first bit set to obtain a second subset of bits includes: performing PCS processing on every k0 bits in the first subset of bits to obtain n0 bits in the second subset of bits, wherein the first subset of bits includes v = m - 1504 bits, v is an integer multiple of 32, k0 = v / 32, n0 = 64, and the second subset of bits includes 2048 bits. That is, this implementation can divide the PCS processing into 32 PCS sub-processes, making the implementation of PCS processing simpler and reducing the complexity of a single PCS sub-process.

[0082] In some possible implementations, the first data comprises r rows and q columns of bits, where r and q are both integers greater than 0.

[0083] In some possible implementations, the fourth data includes M first data streams, where M is an integer greater than 0. The second processing of the fourth data to obtain W first dual-polarization symbol streams includes: performing symbol mapping, polarization division, and framing on the M first data streams to obtain the W first dual-polarization symbol streams, where W = 1.

[0084] In some possible implementations, the fourth data includes M first data streams, where M is an integer greater than 0. The second processing of the fourth data to obtain W first dual-polarization symbol streams includes: performing symbol mapping, polarization division, and framing on the M first data streams respectively to obtain the W first dual-polarization symbol streams, where W = M.

[0085] In some possible implementations, the fourth data includes M first data streams, where M is an integer greater than 0. The second processing of the fourth data to obtain W first dual-polarization symbol streams includes: distributing the M first data streams to obtain W second data streams; and performing symbol mapping, polarization partitioning, and framing on the W second data streams to obtain the W first dual-polarization symbol streams. In this implementation, the data distribution ensures that the data in the M first data streams is more evenly distributed into the W dual-polarization symbol data streams after polarization partitioning and symbol mapping, resulting in better overall performance and better resistance to burst errors.

[0086] In some possible implementations, the fourth data includes M first data streams, where M is an integer greater than 0. The second processing of the fourth data to obtain W first dual-polarization symbol streams includes: performing symbol mapping and polarization partitioning on the M first data streams respectively to obtain M second dual-polarization symbol streams; distributing the M second dual-polarization symbol streams to obtain W third dual-polarization symbol streams; and framing the W third dual-polarization symbol streams respectively to obtain the W first dual-polarization symbol streams. In this implementation, the data distribution ensures that the data in the M first data streams is more evenly distributed into the W dual-polarization symbol data streams after polarization partitioning and symbol mapping, resulting in better overall performance and better resistance to burst errors.

[0087] In some possible implementations, the W first dual-polarization symbol streams are transmitted on W optical signals, with any two of the W optical signals having different wavelengths. Alternatively, the W first dual-polarization symbol streams are transmitted through W optical fibers. It should be understood that the baud rate corresponding to each optical signal or each optical fiber is 1 / W of the baud rate of the traditional single-carrier scheme. In this case, the corresponding data processing method can use devices with lower baud rates, which is suitable for metropolitan area telecommunications transmission and data center transmission scenarios requiring low power consumption. Alternatively, the W first dual-polarization symbol streams are transmitted on W subcarriers, and the W subcarriers are multiplexed to obtain one optical signal to be transmitted. It should be understood that the baud rate corresponding to each subcarrier is 1 / W of the baud rate of the transmitted signal. Compared with the above implementation using W optical signals or W optical fibers, the subcarrier implementation requires devices with higher baud rates, and the device power consumption may be higher. The subcarrier implementation allows the receiving-end DSP to process each subcarrier, which can significantly reduce the complexity of dispersion compensation, reduce the cost of EEPPN, and thus reduce the DSP power consumption.

[0088] Fourthly, embodiments of this application provide a data processing apparatus, including a processing unit, for performing the method described in any embodiment of the third aspect.

[0089] It should be understood that when q = 10280, d in r, m and d CP Satisfy the relationships shown in any of Tables 11, 15, and 20 in the specification; when q = 5140, d in r, m and d CP It satisfies the relationship shown in any of Tables 21, 22 and 23 in the specification.

[0090] Fifthly, embodiments of this application provide a chip for performing the methods described in any of the first or third aspects.

[0091] Sixthly, embodiments of this application provide an optical module, which includes a processor and an interface. The interface is used to transmit and receive signals, and the processor is used to execute the methods described in any of the embodiments of the first or third aspects. For example, the interface is used to transmit signals from the processor or to transmit received signals to the processor.

[0092] In a seventh aspect, embodiments of this application provide a transmitting device. The transmitting device includes a host-side device and an optical module as described in the sixth aspect, the optical module being used to convert electrical signals from the host-side device into optical signals and to transmit the optical signals.

[0093] Eighthly, embodiments of this application provide a communication system including a transmitting device and a receiving device as described in the seventh aspect, wherein the transmitting device is used to transmit an optical signal to the receiving device.

[0094] Ninthly, this application provides a computer-readable storage medium storing instructions that, when executed by a computer, cause the method described in any of the embodiments of the first or third aspect to be implemented.

[0095] In a tenth aspect, this application provides a computer program product including program instructions that, when executed, implement the method described in any of the embodiments of the first or third aspect above. Attached Figure Description

[0096] Figure 1 is a schematic diagram of a communication system applied in an embodiment of this application;

[0097] Figure 2 is a schematic diagram of a data frame structure;

[0098] Figure 3 is a schematic diagram of an implementation of a data processing method in this application;

[0099] Figure 4 is a schematic diagram of an embodiment of the first process in this application;

[0100] Figure 5 is a schematic diagram of one implementation of the second process in an embodiment of this application;

[0101] Figure 6(a) is a schematic diagram of the first implementation method of dual polarization symbol mapping and framing in the embodiments of this application;

[0102] Figure 6(b) is a schematic diagram of the second implementation of dual polarization symbol mapping and framing in the embodiments of this application;

[0103] Figure 6(c) is a schematic diagram of the third implementation method of dual polarization symbol mapping and framing in the embodiments of this application;

[0104] Figure 7(a) is a schematic diagram of another implementation of the second process in the embodiments of this application;

[0105] Figure 7(b) is a schematic diagram of another implementation of the second process in the embodiments of this application;

[0106] Figure 8 is a schematic diagram of one embodiment of the second data processing in this application;

[0107] Figure 9 is a schematic diagram of one embodiment of performing CRC or inserting padding bits on the first data in this application;

[0108] Figure 10 is a schematic diagram of another implementation of CRC or padding bit insertion for the first data in the embodiments of this application;

[0109] Figure 11 is a schematic diagram of another implementation of CRC or padding bit insertion for the first data in the embodiments of this application;

[0110] Figure 12 is a schematic diagram of another implementation of CRC or padding bit insertion for the first data in the embodiments of this application;

[0111] Figure 13 is a schematic diagram of a data processing device in an embodiment of this application;

[0112] Figure 14 is a schematic diagram of a structure of an optical module in an embodiment of this application;

[0113] Figure 15 is a schematic diagram of a transmitting device in an embodiment of this application. Detailed Implementation

[0114] This application provides a data processing method and a data processing apparatus applicable to metropolitan area telecommunications transmission and DCI scenarios with speeds of 800 gigabits per second (Gbps) or higher (including 1.2Tbps and 1.6Tbps, etc.).

[0115] It should be noted that the terms "first," "second," etc., in this application specification, claims, and the accompanying drawings are used to distinguish similar objects, not to limit a specific order or sequence. It should be understood that the above terms can be used interchangeably where appropriate so that the embodiments described in this application can be implemented in a sequence other than that described in this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

[0116] Figure 1 is a schematic diagram of a communication system applied in an embodiment of this application. As shown in Figure 1, at the transmitting end, the source provides a data stream to be transmitted, and the transmitting end data processor receives the data stream. The transmitting end data processor first performs data processing including Probabilistic Constellation Shaping (PCS), encoding, interleaving, symbol mapping, and framing to obtain a symbol data stream, which is then sent to the transmitting end signal processor for signal processing, and then transmitted through the channel to the receiving device. After receiving the distorted signal caused by noise or other impairments in the channel, the receiving device sends it to the receiving end signal processor for dispersion compensation, synchronization, phase recovery, and other operations, and then sends it to the receiving end data processor for demodulation, deinterleaving, decoding, and other operations to recover the original data, and then sends the recovered data to the destination. In some specific applications, the transmitting end data processor can be implemented in an optical module.

[0117] It should be noted that, in the embodiments of this application, unless otherwise stated, "multiple" refers to two or more. The "or" in the embodiments of this application is merely a description of the association relationship between related objects, indicating that three relationships can exist. For example, A or B can be represented as: A existing alone, A and B existing simultaneously, and B existing alone. The instances appearing in the embodiments of this application... The operation represents rounding down 'a', for example... The b%c operation in the embodiments of this application represents taking b modulo c. When b is non-negative, the value of b%c is the remainder when b is divided by c. For example, 8%3 = 2, 2%3 = 2. When b is negative, the value of b%c is b plus an integer multiple of c to obtain a positive integer before taking the modulo, for example, -9%16 = 7, -10%3 = 2.

[0118] It should be noted that the terms "bit set" and "bit subset" in this application specification and claims are concepts introduced for ease of description only. In practical applications, the data stream is a whole and does not involve division; each bit set or bit subset can be considered as one or more bits in the data stream. It should be understood that bit sets and bit subsets can also be presented in the form of matrices, arrays, sequences, etc., and no specific limitation is made here.

[0119] It should be noted that baud, or modulation rate, refers to the rate at which a data signal modulates the carrier wave, that is, the number of times the carrier modulation state changes per unit time. Baud rate represents the number of symbol transmissions per unit time; it is a measure of symbol transmission rate, expressed as the number of times the carrier modulation state changes per unit time. In short, baud rate refers to the number of symbols transmitted per unit time.

[0120] Figure 2 is a schematic diagram of a data frame structure. As shown in Figure 2, a data frame includes multiple rows of bits, with each row containing q bits. It should be understood that this application does not limit the specific type of data frame. In some specific applications, the integer q is an integer multiple of 257; typically, q is 10280, 8224, 5140, 4112, 2570, 2056, or 1028, etc. As an example, an 800G frame contains 256 rows, each containing 10280 bits. As another example, to better adapt to PCS processing, an 800G frame contains 1280 rows, each containing 2056 bits.

[0121] Figure 3 is a schematic diagram illustrating an embodiment of a data processing method according to this application. As shown in Figure 3, the data processing method provided by this application can be divided into two parts, denoted as "first data processing" and "second data processing," respectively. The "first data processing" and "second data processing" will be described in detail below.

[0122] 1) First Data Processing

[0123] As shown in Figure 3, for the first data processing, a Cyclic Redundancy Check (CRC) or padding bits can be performed first, followed by scrambling. It should be understood that in practical applications, at least one of the CRC and padding operations can be performed.

[0124] As an example, the first data includes a total of d in =q×r bits, the first data is subjected to CRC or padding bits to obtain the second data. In the CRC operation, d is added. CRC Each CRC check bit will be inserted during the padding bit insertion operation. PADOne padding bit. Furthermore, for the portion containing d... scr =q×r+d CRC +d PAD The second data of 1 bit is scrambled to obtain a bit count of d. scr The third data. Where, d CRC d is an integer greater than or equal to 0. PAD For integers greater than or equal to 0, we can denote them as d. CP =d CRC +d PAD At this time d scr =q×r+d CP The redundancy corresponding to the CRC check performed on the first data or the insertion of padding bits is OH. CP =(d CRC +d PAD ) / (q×r). It should be noted that in some specific applications, the padding bits are all 0 bits.

[0125] As an example, when d PAD When = 0, the CRC result is q×r+d CRC Instead of inserting padding bits, the bits are directly scrambled, resulting in d bits. scr =q×r+d CRC As another example, to achieve lower latency and lower complexity, CRC is bypassed and replaced with padding bits, i.e., d... CRC =0, therefore d scr =q×r+d PAD .

[0126] It should be noted that in some specific application scenarios, CRC-32 is used. As an example, the first data is subjected to p CRC-32 operations, where p is an integer greater than 1 and the integer r is divisible by p, i.e., r / p is an integer. In this case, d CRC = 32 × p. More specifically, for r lines of data obtained from the data frame, a CRC-32 operation is performed once for every r / p lines (a total of q × r / p bits) to add 32 CRC check bits. This CRC-32 operation is repeated p times to add a total of d CRC check bits. CRC = 32 × p CRC check bits. It should be noted that in some specific implementations, q × r / p = 41120 is chosen. In this case, the CRC-32 encoding and corresponding CRC detection operations can directly adopt the existing CRC-32 operation in the 800G-ZR, where the existing 800G-ZR performs a CRC-32 operation on 4 rows and 10280 columns of data, totaling 41120 bits. In some specific implementations, q = 2056 and r / p = 20 are chosen.

[0127] It should be noted that in some specific application scenarios, the first data undergoes a total of p CRC-32 operations, where the number of CRC-32 operations p is an integer greater than 1, but the integer r is not divisible by p, i.e., r / p is not an integer. In this case, consider r0×(p-1)+r1=r, where the integer r0 is greater than the integer r1. In some specific implementations, the integer... The integer r1 = r - r0 × (p - 1), and r0 > r1. A specific implementation is given below: for r rows of data obtained from the data frame, each r0 row (a total of q × r0 bits) in the first r0 × (p - 1) rows of data is subjected to CRC-32 to add 32 CRC check bits, resulting in a total of 32 × (p - 1) CRC check bits; the last r1 row (a total of q × r1 bits) is subjected to one CRC-32 operation to add 32 CRC check bits; therefore, a total of d is obtained. CRC = 32 × p CRC check bits. It should be noted that in some specific implementations, q × r0 = 41120 is chosen; in this case, the CRC-32 encoding and corresponding CRC detection operations can directly adopt the existing CRC-32 operations in the 800G-ZR. In some specific implementations, q = 2056 and r0 = 20 are chosen.

[0128] It should be noted that in some other specific application scenarios, CRC-24 or other CRC checks may also be used, and this application does not impose any restrictions.

[0129] 2) Second Data Processing

[0130] As shown in Figure 3, the second data processing includes the first processing and the second processing.

[0131] The first process will include d scr The third data of 1 bit is processed by "PCS processing", "interleaving and encoding" to obtain the data containing d. FEC The fourth data consists of d bits. This fourth data is distributed across M first data streams, where M is an integer greater than 1. Typically, each first data stream contains d bits of the fourth data. FEC / M bits. Additionally, W can also be 1, corresponding to the single-carrier case.

[0132] The third data contains L sets of first bits, where the number of bits in each first bit set is m. At this time, d scr =q×r+d CP = L × m, where L is an integer greater than 0. Each first bit set is processed by PCS, interleaved, and encoded to obtain a second bit set, resulting in a total of L second bit sets.

[0133] Figure 4 is a schematic diagram of an implementation of the first processing in an embodiment of this application. As shown in Figure 4, the first bit set includes a first bit subset and a third bit subset. The first bit subset is processed by PCS to obtain a second bit subset; the second bit subset and the third bit subset are processed by interleaving and encoding to obtain the second bit set. It should be understood that this application does not limit the order of execution of interleaving and encoding. For example, interleaving can be performed first and then encoding, or vice versa.

[0134] In one specific implementation, consider that the second bit set has 4096 bits, the second bit subset has 2048 bits, the third bit subset has 1504 bits, and the first bit subset has v = m - 1504 bits. The second and third bit subsets, totaling 2048 + 1504 = 3552 bits, are FEC encoded to obtain 4096 encoded bits. More specifically, these 3552 bits are represented using a 32x111 bit matrix, also known as an information bit matrix. Each row of 111 bits is encoded to add 17 bits, resulting in a 32x128 bit matrix with a total of 4096 encoded bits. This 32x128 bit matrix is ​​also called a codeword bit matrix. The FEC encoding uses spatially coupled encoding, meaning that when encoding 3552 bits to obtain 4096 encoded bits at the current time, it also utilizes the 4096 encoded bits obtained at previous times. For example, oFEC encoding can be used; no specific restrictions are imposed here. It should be understood that m < 3552.

[0135] It should be noted that before FEC encoding, the 3552 bits can be pre-interleaved. This pre-interleaving is also called block mapping, pre-FEC interleaving, or pre-FEC permutation. After FEC encoding, the 4096 encoded bits can be post-interleaved or permuted. Here, pre-interleaving, post-interleaving, and row permutation are collectively referred to as interleaving, without specific limitations. In some possible scenarios, the above-mentioned pre-interleaving and post-interleaving can also be considered as part of PCS processing. It should be noted that the L sets of second bits obtained after the first processing can be interleaved before the second processing, without specific limitations.

[0136] It should be noted that the PCS processing is used to process the input bits so that the probabilities of 0 and 1 appearing in the output bits are not the same. In some specific applications, the PCS processing can also be called Distribution Matching (DM) processing. The PCS processing can be implemented in various ways, such as using arithmetic coding, lookup table (LUT), trellis coding, etc.

[0137] To simplify the implementation of PCS processing, multiple PCS sub-processes are typically used to achieve the desired PCS effect. For each PCS sub-process, the input k0 bits are processed to obtain the output n0 bits, where n0 > k0. It should be noted that a larger value for n0 generally results in better PCS processing performance, but also higher complexity. In practical applications, a trade-off between performance and complexity must be struck.

[0138] In one embodiment, a PCS process is performed on a first subset of bits containing v = m - 1504 bits to obtain a second subset of bits containing 2048 bits. In this embodiment, considering n0 as specifically taking the values ​​128, 64, 32, or 16 facilitates the implementation of the PCS process and has low complexity. That is, v = m - 1504 is an integer multiple of 2048 / 128 = 16, 2048 / 64 = 32, 2048 / 32 = 64, or 2048 / 16 = 128. Here, we consider v = m - 1504 to be an integer multiple of 2048 / 128 = 16, and m < 3552, in which case m is also an integer multiple of 16.

[0139] In some specific applications, PCS processing is performed on a first subset of bits containing v = m - 1504 bits to obtain a second subset of bits containing 2048 bits. The first subset of bits can be divided into 16 groups of input bits, each group containing (m - 1504) / 16 bits. PCS sub-processing is then performed on each of the 16 groups of input bits to obtain 16 groups of output bits corresponding to the 16 groups of input bits. Each group of output bits contains 128 bits, and the 16 groups of output bits total 128 × 16 = 2048 bits, meaning the second subset of bits contains 2048 bits.

[0140] In other specific applications, PCS processing is performed on a first subset of bits containing v = m - 1504 bits to obtain a second subset of bits containing 2048 bits. The first subset of bits can be divided into 32 groups of input bits, each group containing (m - 1504) / 32 bits. PCS sub-processing is then performed on each of the 32 groups of input bits to obtain 32 groups of output bits corresponding to the 32 groups of input bits. Each group of output bits contains 64 bits, and the 32 groups of output bits total 64 × 32 = 2048 bits, meaning the second subset of bits contains 2048 bits.

[0141] As shown in Figure 3, the second processing steps process the M input first data streams to obtain W dual-polarized symbol streams, namely "Dual-polarized symbol stream 0", "Dual-polarized symbol stream 1", ..., "Dual-polarized symbol stream W-1", where W is an integer greater than 1. It should be understood that the specific number of dual-polarized symbols in the W dual-polarized symbol streams depends on the number of bits in the fourth data (i.e., the number of bits in the M first data streams). Correspondingly, the number of bits in the fourth data depends on the number of bits in the third data, the number of bits in the third data depends on the number of bits in the second data, and the number of bits in the second data depends on the number of bits in the first data. For example, given the specific number of bits in the first data, the number of bits in the M first data streams and the number of dual-polarized symbols in the W dual-polarized symbol streams can be determined. That is, the length of the first data stream and the length of the dual-polarized symbol streams can be considered to have definite values. Furthermore, given the specific number of bits in the first data, this embodiment can repeatedly perform first and second data processing on an unlimited number of first data streams. In this case, the length of the first data stream and the length of the dual-polarized symbol streams can be considered to be infinitely long.

[0142] In some specific applications, W dual-polarization symbol streams are transmitted on W optical signals of different wavelengths. Alternatively, the W dual-polarization symbol streams are transmitted separately through W optical fibers. The baud rate corresponding to each optical signal or each optical fiber is 1 / W of the baud rate of a traditional single-carrier scheme. In this case, the corresponding data processing method can use devices with lower baud rates, which is suitable for metropolitan area telecommunications transmission and data center transmission scenarios requiring low power consumption.

[0143] In other specific applications, the W dual-polarization symbol streams are carried on W subcarriers, and the W subcarriers are multiplexed to obtain a single optical signal for transmission. The baud rate corresponding to each subcarrier is 1 / W of the transmitted signal baud rate. Compared with the above-mentioned method using W optical signals or W optical fibers, the subcarrier implementation requires devices with higher baud rates, and the power consumption of the devices may be higher. The subcarrier implementation allows the receiving-end DSP to process each subcarrier, which can significantly reduce the complexity of dispersion compensation and reduce the cost of Enhanced Equalization Phase Noise (EEPN), thus making its DSP power consumption lower.

[0144] It should be noted that, in the above-mentioned methods of this application, whether it is reducing the baud rate, reducing the complexity of dispersion compensation, or reducing the cost of EEPN, the data transmission rate can be improved and adapted to next-generation metropolitan area telecommunications transmission and DCI scenarios.

[0145] The second processing includes dual-polarization (DP) symbol mapping and framing. Typically, dual-polarization symbol mapping includes symbol mapping and polarization distribution processing; for example, 16QAM symbol mapping and polarization distribution can be simply referred to as DP-16QAM symbol mapping or DP-16QAM mapping. 16QAM symbol mapping maps 4 bits into one symbol. DP-16QAM symbol mapping maps 8 bits into one dual-polarization symbol, where one dual-polarization symbol contains one X-polarization direction symbol and one Y-polarization direction symbol. Framing is also called DSP framing. Several possible specific implementations of the second processing are given below.

[0146] Figure 5 is a schematic diagram of one implementation of the second processing in this application embodiment. As shown in Figure 5, the M first data streams are respectively processed by dual polarization symbol mapping and framing to obtain W dual polarization symbol streams, where W = M. For detailed operation of dual polarization symbol mapping and framing, please refer to Figure 6(a), Figure 6(b), or Figure 6(c).

[0147] Figure 6(a) is a schematic diagram of the first implementation of dual-polarization symbol mapping and framing in this application embodiment. As shown in Figure 6(a), the bits in the first data stream are processed by symbol mapping and polarization division to obtain a dual-polarization symbol stream before framing. The framing process includes N... CW A sequence of dual-polarization symbols (also known as a pre-framing symbol sequence) containing N dual-polarization symbols is supplemented with preset symbols to obtain a sequence containing N dual-polarization symbols. FA DSP frame consists of two polarization symbols, and a DSP frame can also be referred to as a frame. Specifically, at least one of the following symbol sequences is inserted in the X-polarization direction and the Y-polarization direction: Frame Alignment Word Sequence (FAW Sequence), Training Symbol Sequence, Reserved Symbol Sequence, and Pilot Symbol Sequence.

[0148] It should be noted that frame synchronization symbols are used for frame synchronization alignment, training symbols are used for link training, pilot symbols are used for carrier phase recovery, and reserved symbols are used for future use and innovation. The values ​​of reserved symbols can be known and unchanging, or they can be randomized; the values ​​of reserved symbols can also be called patterns. In some specific embodiments, the DSP frame contains multiple subframes, and the DSP frame is called a super-frame. In other specific embodiments, the DSP frame can also be called a multi-frame, the reserved symbols can also be called fixed stuff (FS), and the frame synchronization symbols can also be called multi-frame alignment signals (MFAS).

[0149] It should be noted that the framing operation shown in Figure 6(a) is performed on symbols, meaning framing occurs after the dual-polarization symbol mapping operation. Figure 6(b) is a schematic diagram of a second implementation of dual-polarization symbol mapping and framing in this application embodiment. Figure 6(c) is a schematic diagram of a third implementation of dual-polarization symbol mapping and framing in this application embodiment. As shown in Figures 6(b) and 6(c), the framing operation can also be performed on bits, meaning framing occurs before the dual-polarization symbol mapping operation. As shown in Figure 6(b), by first inserting the bits corresponding to the frame synchronization symbol sequence, training symbol sequence, reserved symbol sequence, and pilot symbol sequence, and then performing symbol mapping and polarization division, a DSP frame (also called a superframe) identical to the operation in Figure 6(a) can be obtained. As shown in Figure 6(c), by first inserting the bits corresponding to the frame synchronization symbol sequence, training symbol sequence, reserved symbol sequence, and pilot symbol sequence, and then performing polarization division and symbol mapping, a DSP frame (also called a superframe) identical to the operation in Figure 6(a) can also be obtained. It should be understood that other framing operations are not excluded, and will not be described in detail in this application.

[0150] It should be noted that a single dual-polarization symbol stream can be represented by two symbol data streams, wherein the first stream is the symbol data stream of the dual-polarization symbol stream in the X-polarization direction, and the second stream is the symbol data stream of the dual-polarization symbol stream in the Y-polarization direction. Alternatively, a single dual-polarization symbol stream can also be represented by four data streams, wherein the first stream is the data stream of the I-path component of the dual-polarization symbol stream corresponding to the X-polarization direction (referred to as X...). I The second data stream is the data stream of the Q-path component in the X-polarization direction corresponding to the dual-polarization symbol stream (referred to as X). Q The third item is the data stream of the I-path component in the Y-polarization direction corresponding to the dual-polarization symbol stream (referred to as Y). I The fourth item is the data stream of the Q-path component in the Y-polarization direction corresponding to the dual-polarization symbol stream (referred to as Y). Q (Data flow).

[0151] In some specific implementations, the second processing, in addition to including dual-polarization symbol mapping and framing, also includes data distribution, so that the data in the M first data streams is distributed more evenly to the W dual-polarization symbol data streams after polarization partitioning and symbol mapping. In this case, the data processing method has better overall performance and better resistance to burst errors. Here, the values ​​of W and M can be equal or unequal. The data distribution can also be referred to as interleaving or splitting processing.

[0152] Figure 7(a) is a schematic diagram of another implementation of the second processing in an embodiment of this application. As an example, as shown in Figure 7(a), M first data streams are first distributed to obtain W second data streams, and the W second data streams are respectively processed by dual-polarization symbol mapping and framing to obtain W dual-polarization symbol streams. In this case, the data distribution is also called bit distribution.

[0153] Figure 7(b) is a schematic diagram of another implementation of the second processing in the embodiments of this application. As another example, as shown in Figure 7(b), the M first data streams are first subjected to dual-polarization symbol mapping to obtain M mapped symbol streams, and then data distribution is performed to obtain W distributed symbol streams. The W distributed symbol streams are then subjected to framing processing to obtain W dual-polarization symbol streams. Here, W is equal to M, but W may not be equal to M. In this case, the data distribution is also called symbol distribution.

[0154] In some specific implementations, the framing operation is used to divide each N CW =172032 dual-polarization symbols (symbols before framing) are framed to obtain one DSP frame. In some specific applications, the framing operation is used to divide each N CW=172032 dual-polarization symbols are framed to obtain a sequence containing N F =178176 dual-polarization symbols in DSP frames, with a framing redundancy of h. DSP =178176 / 172032-1=1 / 28≈3.57%. In other specific applications, framing is used to frame every 172032 dual-polarization symbols to obtain a frame containing N F =175104 dual-polarization symbols in DSP frames, with a framing redundancy of h. DSP =175104 / 172032-1=1 / 56≈1.79%.

[0155] It should be noted that in some embodiments, in the X-polarization direction or the Y-polarization direction, every N of the DSP frame G One symbol at a fixed position among the symbols is the pilot symbol. As an example, every N... G The first symbol in the set is the pilot symbol. Typically, N G =32, 64, 96, or 128, etc. In some specific applications, the symbol mapping is called 16QAM mapping. In some specific applications, the symbol mapping uses gray mapping, mapping every 4 bits to one 16QAM symbol; in this case, the symbol mapping is also simply called gray mapping.

[0156] In this embodiment of the application, d is included. in =q×r bits of first data are processed to obtain d scr =q×r+d CP The third data consists of L × m bits. The third data comprises L sets of first bits, each set containing m bits. Each set of first bits is processed by PCS, interleaved, and encoded to obtain a second set of 4096 bits. The fourth data comprises L sets of second bits. The fourth data, after a second processing step, yields W DSP frames, and each of the W dual-polarization symbol streams contains one DSP frame out of the W DSP frames. Therefore, the proposed data processing method is simple to implement, has low hardware complexity, and consumes less power.

[0157] Considering DP-16QAM symbol mapping, the number of dual-polarization symbols before framing in the W DSP frames is W×N. CW Corresponding to 8×W×N CW There are bits. Therefore, the following relationship can be satisfied:

[0158] In this embodiment of the application, N is considered. CW =172032, with d scr= 336 × W × m. The first data includes d. in = q × r bits, typically represented by r rows and q columns of bits. The following describes the three cases: q = 2056, q = 10280, and q = 5140.

[0159] Firstly, consider the case where q = 2056 and W = 2.

[0160] The number of bits in the third data is d. scr =q×r+d CP = 672 × m. It should be understood that d represents the number of bits added as CRC check bits or padding bits. CP The larger the number of redundant OH groups introduced... CP =d CP The larger / (q×r) is, the greater it is. Table 1 below gives the corresponding {d in ,r,m,d CP} Parameter combinations.

[0161] Table 1

[0162] Table 1 also gives {r, m, d} CP Under the parameter combination, the specific value of v / 16 = (m-1504) / 16 is specified. It should be noted that v = m-1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the desired PCS effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain the output n0 = 128 bits. In some specific applications, the 16 PCS sub-processes are implemented using 16 lookup tables (LUTs). In other specific applications, the 16 PCS sub-processes are implemented using 16 trellis coding operations. It should be noted that in some specific embodiments, considering that v = m - 1504 is an integer multiple of 32, when n0 = 64, k0 = v / 32. This means that the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain the output n0 = 64 bits. In some specific applications, the 32 PCS sub-processes are implemented using 32 lookup tables (LUTs). In other specific applications, the 32 PCS sub-processes are implemented using 32 trellis coding operations.

[0163] It should be noted that in some specific applications, the first data processing includes CRC-32 operations. In this case, consider the following first constraint: when the number of rows r is an integer multiple of 20, the number of CRC-32 operations p = r / 20, d CRC =r / 20×32≤d CP This means performing a CRC-32 operation on every 20 rows of data (20 × 2056 = 41120 bits). When the number of rows r is not a multiple of 20, the number of CRC-32 operations is [number missing]. in The operation represents rounding down 'a', i.e., r0 = 20, r1 = r - 20 × (p - 1). CRC-32 is performed on each of the first 20 × (p - 1) rows of data (r0 = 20 bits, totaling q × r0 = 41120 bits), and once on the last r1 rows (q × r1 bits). Consider d. PAD =d CP -d CRC Based on Table 1 and the first constraint mentioned above, Table 2 below gives the corresponding {r, m, d}. CP d PAD The parameters are} and}. It should be noted that the last column of Table 2 also gives the specific values ​​of parameter r1 when the row number r is not a multiple of 20. For row numbers r that are multiples of 20, such as r = 1080 in row 32 of Table 2, the corresponding parameter r1 is represented by a forward slash in the table, indicating that the parameter r1 does not exist.

[0164] Table 2

[0165] Table 2 also gives {r, m, d} CP d PAD Under the parameter combination of , p}, the specific value of v / 16 = (m-1504) / 16 is as follows. It should be noted that v = m-1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that in some specific embodiments, v = m-1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0166] It should be noted that in some specific applications, the first bit set is processed by PCS, interleaving, and encoding to obtain the second bit set. The ratio of the encoded input bit length to the encoded output bit length in the encoding operation is 3552:4096 = 111:128, which is the input-output rate ratio of the interleaving and encoding module shown in Figure 4, which is 111:128. The bit ratio of the first bit set to the second bit set is m:4096 = f1:f2, where the greatest common divisor of integers f1 and f2 is 1. Typically, smaller values ​​for f1 and f2 result in simpler overall hardware implementation, lower complexity, and lower power consumption. Therefore, considering the second constraint that m is an integer multiple of 32, m:4096 = f:128, where the integer f = m / 32, the input-output rate ratio of the overall PCS processing, interleaving, and encoding module shown in Figure 4 is f:128. Combining Table 1 and the above second constraint, Table 3 below gives the corresponding {r, m, d}. CP The combination of parameters f.

[0167] Table 3

[0168] Table 3 also gives {r, m, d} CP Under the parameter combination of and f, the specific value of v / 16 = (m-1504) / 16 is as follows. It should be noted that v = m-1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that in some specific embodiments, v = m-1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0169] It should be noted that in some specific applications, the first and second constraints mentioned above are considered. In this case, combining Table 1 and the first and second constraints mentioned above, Table 4 below gives the corresponding {r, m, d}. CP d PAD The parameters are}f, p}. It should be noted that the last column of Table 4 also gives the specific values ​​of parameter r1 when the row number r is not a multiple of 20. For row numbers r that are multiples of 20, such as r = 940 in row 40 of Table 4, the corresponding parameter r1 is represented by a forward slash in the table, indicating that the parameter r1 does not exist.

[0170] Table 4

[0171] Table 4 also gives {r, m, d} CP d PAD The specific value of v / 16 under the parameter combination {f, p} is as follows. It should be noted that v = m - 1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that in some specific embodiments, v = m - 1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0172] It should be noted that the first aspect mentioned above considers N CW In the case of 172032, q=2056, and W=2, the fourth data contains 172032 × 2 × 8 = 2752512 bits, which, after dual-polarization symbol mapping, yields 344064 dual-polarization 16QAM symbols. The parameter combinations given in Tables 1-4 can be used for N CW The case of 86016, q=2056, and W=4 can also be used for N. CW The case where q = 43008, q = 2056, and W = 8.

[0173] Secondly, consider the case where q = 2056 and W = 4.

[0174] The number of bits in the second data is d. scr =q×r+d CP = 1344 × m. It should be understood that d represents the number of bits d added as CRC check bits or padding bits. CP The larger the number of redundant OH groups introduced... CP =d CP The larger / (q×r) is, the greater the value. Table 5 below gives the corresponding {d}. in ,r,m,d CP} Parameter combinations.

[0175] Table 5

[0176] Table 5 also gives {r, m, d} CP Under the parameter combination, the specific value of v / 16 = (m-1504) / 16 is as follows. It should be noted that v = m-1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that in some specific embodiments, v = m-1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0177] It should be noted that in some specific applications, the first data processing includes CRC-32 operations. Combining Table 5 and the first constraint in the first aspect, Table 6 below gives the corresponding {r, m, d}. CP d PAD The parameters are} and}. It should be noted that the last column of Table 6 also gives the specific values ​​of parameter r1 when the row number r is not a multiple of 20. For row numbers r that are multiples of 20, such as r = 2100 in row 25 of Table 6, the corresponding parameter r1 is represented by a forward slash in the table, indicating that the parameter r1 does not exist.

[0178] Table 6

[0179] Table 6 also gives {r, m, d} CP d PAD The specific value of v / 16 under the parameter combination of , p}. It should be noted that v = m - 1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should be noted that in some specific embodiments, v = m - 1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0180] It should be noted that in some specific applications, the second constraint in the first aspect should be considered. Combining Table 5 and the second constraint in the first aspect, Table 7 below gives the corresponding {r, m, d}. CP The combination of parameters f.

[0181] Table 7

[0182] Table 7 also gives {r, m, d} CP Under the parameter combination of and f, the specific value of v / 16 = (m-1504) / 16 is as follows. It should be noted that v = m-1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that in some specific embodiments, v = m-1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0183] It should be noted that in some specific applications, the first and second constraints in the first aspect are considered. In this case, combining Table 5 and the first and second constraints in the first aspect, Table 8 below gives the corresponding {r, m, d}. CP d PAD The parameters are: f, p, etc. It should be noted that the last column of Table 8 also gives the specific values ​​of parameter r1 when the row number r is not a multiple of 20. For row numbers r that are multiples of 20, such as r = 1880 in row 27 of Table 8, the corresponding parameter r1 is represented by a forward slash in the table, indicating that the parameter r1 does not exist.

[0184] Table 8

[0185] It should be noted that the second aspect mentioned above considers N CW In the case of 172032, q=2056, and W=4, the fourth data contains 172032 × 4 × 8 = 5505024 bits, which, after dual-polarization symbol mapping, yield 688128 dual-polarization 16QAM symbols. The parameter combinations given in Tables 5-8 can be used for N CW The case of 344064, q=2056, and W=2 can also be used for N. CW The case where q = 86016, q = 2056, and W = 8.

[0186] It should be noted that, assuming the bit rate of the data frame is B0 Gbit / s, the corresponding bit rate after the first data processing is B0 × (r × q + d). CP After the first processing in the second data processing (i.e., PCS processing, interleaving, and encoding processing), the corresponding bit rate is B1 = B0 × (r × q + d) Gbit / s. CP ) / (r×q)×(4096 / m). Considering the redundancy of framing in the second data processing as h. DSP That is, the bit rate corresponding to the second processing in the second data processing is B2 = B1 × (1 + h) DSP )=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(1+h DSP The corresponding baud rate (i.e., symbol rate) is B. s =B2 / 8 =B0×(r×q+d) CP ) / (r×q)×(4096 / m)×(1+h DSP ) / 8GBaud. Typically, considering framing redundancy, it is h. DSP The values ​​are 1 / 28 or 1 / 56. It can be seen that the parameter combinations given in Tables 1-8, considering the input data for the first data processing (i.e., the first data) as FlexO-16e or 1.6TZR frame data, all correspond to baud rates less than 300 GBaud. Therefore, it is understandable that the proposed data processing scheme can be well applied to future 1.6T data centers and metropolitan area network scenarios.

[0187] Below, based on the above description of the first and second data processing methods, several specific embodiments are given.

[0188] Example 1:

[0189] Considering W=2, q=2056, and the input data for the first data processing (i.e., the first data) is FlexO-16e or 1.6T ZR frame data, its nominal bit rate is B0≈1609.959013238Gbit / s. It should be noted that in this embodiment, non-integers in the table are only retained to two decimal places. In some specific applications, the non-integers can be described in other forms, such as retaining nine decimal places, etc. Such descriptions are known to those skilled in the art and will not be elaborated here. The first data contains r rows and q=2056 columns, totaling d... in = q × r bits.

[0190] Figure 8 is a schematic diagram of one implementation of the second data processing in this application. As an example, considering M=4, and based on the structure shown in Figure 7(a), as shown in Figure 8, the first bit data contains r rows and q=2056 columns, totaling d. in = q × r bits, after the first data processing, we get d scr L bits. Considering OFEC coding, in some applications, PCS processing, pre-coding interleaving, and post-coding interleaving can be combined into PCS processing, also known as a Probabilistic Constellation Shaper. In some applications, OFEC coding and row permutation can be combined into OFEC coding. It should be noted that the L sets of second bits obtained from the first processing can be interleaved before undergoing a second processing, resulting in W = 2 dual-polarization data streams.

[0191] In some specific applications, the redundancy of framing is considered to be h. DSP =1 / 28, each DSP frame (also known as a superframe or multiframe) contains 178,176 dual-polarization symbols, of which 172,032 dual-polarization symbols in each DSP frame (i.e., symbols before framing) are obtained from the fourth data after symbol mapping and polarization division. At this point, the corresponding bit rate after the second processing is B. 2-28 =B1×(1+h) DSP )=B0×(r×q+d CP The corresponding baud rate (i.e., symbol rate) is B. s-28 =B 2-28 / 8=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(29 / 28) / 8GBaud.

[0192] In other specific applications, the redundancy of framing is considered to be h. DSP =1 / 56, each DSP frame (also known as a superframe or multiframe) contains 175104 dual-polarization symbols, of which 172032 dual-polarization symbols in each DSP frame (i.e., pre-frame symbols) are obtained from the fourth data after symbol mapping and polarization division. At this point, the corresponding bit rate after the second processing is B. 2-56 =B1×(1+h) DSP )=B0×(r×q+d CP The corresponding baud rate (i.e., symbol rate) is B. s-56 =B 2-56 / 8=B0×(r×q+d CP) / (r×q)×(4096 / m)×(57 / 56) / 8GBaud.

[0193] Table 9 below gives the corresponding {d} in ,r,m,d CP v / 16, B1, B 2-28 B s-28 B 2-56 B s-56} Parameter combinations.

[0194] Table 9

[0195] It should be noted that v = m - 1504 is an integer multiple of 16. In some specific implementations, considering n0 = 128, we have k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. In some specific applications, the 16 PCS sub-processes are implemented using 16 lookup tables (LUTs). In other specific applications, the 16 PCS sub-processes are implemented using 16 trellis codings. It should be noted that in other specific embodiments, considering v = m - 1504 is an integer multiple of 32, when n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits. In some specific applications, the 32 PCS subprocesses are implemented using 32 lookup tables (LUTs). In other specific applications, the 32 PCS subprocesses are implemented using 32 trellis codings.

[0196] It can be seen that the parameter combinations given in Embodiment 1, considering that the input data for the first data processing (i.e., the first data) is FlexO-16e or 1600G ZR frame data, all correspond to baud rates less than 300GBaud. It is understood that the proposed data processing scheme can be well applied to future 1.6T data centers and metropolitan area network scenarios. Furthermore, it includes a total of d in The first data of q×r bits, after the first data processing and the second data processing, yields exactly W=2 DSP frames (also known as superframes or multiframes), which makes the proposed data processing method have lower implementation complexity and lower power consumption.

[0197] Based on Table 9, consider the first and second constraints.

[0198] The first data processing involves CRC-32 operations. The CRC-32 encoding and corresponding CRC detection operations can directly utilize the existing CRC-32 operations in the 800G-ZR, which is simple to implement. That is, considering the first constraint as follows: when the number of rows r is an integer multiple of 20, the number of CRC-32 operations p = r / 20, d CRC =r / 20×32≤d CP This means performing a CRC-32 operation on every 20 rows (41120 bits) of data in r rows; when the number of rows r is not an integer multiple of 20, the number of CRC-32 operations is [number missing]. in The operation represents rounding down 'a', i.e., r0 = 20, r1 = r - 20 × (p - 1). CRC-32 is performed on each of the first 20 × (p - 1) rows of data (r0 = 20 bits, totaling q × r0 = 41120 bits), and once on the last r1 rows (q × r1 bits). Consider d. PAD =d CP -d CRC Appropriate values ​​of r and d need to be selected. CP Make d PAD ≥0.

[0199] Consider a first bit set undergoing a first process involving PCS processing, interleaving, and encoding to obtain a second bit set, where the ratio of the encoded input bit length to the encoded output bit length in the encoding operation is 3552:4096 = 111:128. Consider a bit ratio of m:4096 = f1:f2 between the first and second bit sets, where the greatest common divisor of integers f1 and f2 is 1. Typically, smaller values ​​for f1 and f2 result in simpler overall hardware implementation, lower complexity, and lower power consumption. Therefore, consider the following second constraint: m must be an integer multiple of 32, such that m:4096 = f:128, where the integer f = m / 32.

[0200] Taking some parameter combinations in Table 9 as examples, such as the parameter combination in row 23, namely {d in =2298608, r=1118, m=3424, d CP =2320, v / 16=120, B1=1927.88(Gbit / s), B 2-28 =1996.73 (Gbit / s), B s-28 =249.59 (GBaud), B 2-56 =1962.30 (Gbit / s), B s-56=245.29 (GBaud)}, at this time d PAD =528, p=56, r1=18. Figure 9 is a schematic diagram of one embodiment of CRC or padding bit insertion for the first data in this application. As shown in Figure 9, r0=20, and 528b in Figure 9 represents 528 bits. It should be noted that in actual optical transmission applications, the channel spacing C grid GHz, its value C grid (in gigabytes) is smaller than the baud rate value (in gigabytes), C grid Typically, the value is a multiple of 12.5, and a guard band of approximately 10% is considered. In this case, the baud rate corresponding to the parameter combination in line 23 is B. s-28 =249.59 GBaud and B s-56 =245.29 GBaud. In specific optical communication network transmission, the channel spacing that can be used is 287.5 GHz or 275 GHz.

[0201] Example 2:

[0202] Considering W=4, q=2056, and the input data for the first data processing (i.e., the first data) is FlexO-16e or 1.6T ZR frame data, its nominal bit rate is B0≈1609.959013238Gbit / s. It should be noted that in this embodiment, non-integers in the table are only retained to two decimal places. In some specific applications, the non-integers can be described in other forms, such as retaining nine decimal places, etc. Such descriptions are known to those skilled in the art and will not be elaborated here. The first data contains r rows and q=2056 columns, totaling d... in = q × r bits.

[0203] In some specific applications, the redundancy of framing is considered to be h. DSP =1 / 28, each DSP frame (also known as a superframe or multiframe) contains 178,176 dual-polarization symbols, of which 172,032 dual-polarization symbols in each DSP frame (i.e., symbols before framing) are obtained from the fourth data after symbol mapping and polarization division. At this point, the corresponding bit rate after the second processing is B. 2-28 =B1×(1+h) DSP )=B0×(r×q+d CP The corresponding baud rate (i.e., symbol rate) is B. s-28 =B 2-28 / 8=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(29 / 28) / 8GBaud.

[0204] In other specific applications, the redundancy of framing is considered to be h. DSP =1 / 56, each DSP frame (also known as a superframe or multiframe) contains 175104 dual-polarization symbols, of which 172032 dual-polarization symbols in each DSP frame (i.e., pre-frame symbols) are obtained from the fourth data after symbol mapping and polarization division. At this point, the corresponding bit rate after the second processing is B. 2-56 =B1×(1+h) DSP )=B0×(r×q+d CP The corresponding baud rate (i.e., symbol rate) is B. s-56 =B 2-56 / 8=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(57 / 56) / 8GBaud.

[0205] Table 10 below gives the corresponding {d} in ,r,m,d CP v / 16, B1, B 2-28 B s-28 B 2-56 B s-56} Parameter combinations.

[0206] Table 10

[0207] It should be noted that v = m - 1504 is an integer multiple of 16. In some specific implementations, considering n0 = 128, we have k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. In some specific applications, the 16 PCS sub-processes are implemented using 16 lookup tables (LUTs). In other specific applications, the 16 PCS sub-processes are implemented using 16 trellis codings. It should be noted that in other specific embodiments, considering v = m - 1504 is an integer multiple of 32, when n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits. In some specific applications, the 32 PCS subprocesses are implemented using 32 lookup tables (LUTs). In other specific applications, the 32 PCS subprocesses are implemented using 32 trellis codings.

[0208] It can be seen that the parameter combinations given in Embodiment 2, considering that the input data for the first data processing (i.e., the first data) is FlexO-16e or 1600G ZR frame data, all correspond to baud rates less than 300GBaud. It is understood that the proposed data processing scheme can be well applied to future 1.6T data centers and metropolitan area network scenarios. Furthermore, it includes a total of d in The first data of q×r bits, after the first data processing and the second data processing, yields exactly W=4 DSP frames (also known as superframes or multiframes), which makes the proposed data processing method have lower implementation complexity and lower power consumption.

[0209] Based on Table 10, consider the first and second constraints.

[0210] The first data processing involves CRC-32 operations. The CRC-32 encoding and corresponding CRC detection operations can directly utilize the existing CRC-32 operations in the 800G-ZR, which is simple to implement. That is, considering the first constraint as follows: when the number of rows r is an integer multiple of 20, the number of CRC-32 operations p = r / 20, d CRC =r / 20×32≤d CP This means performing a CRC-32 operation on every 20 rows (41120 bits) of data in r rows; when the number of rows r is not an integer multiple of 20, the number of CRC-32 operations is [number missing]. in The operation represents rounding down 'a', i.e., r0 = 20, r1 = r - 20 × (p - 1). CRC-32 is performed on each of the first 20 × (p - 1) rows of data (r0 = 20 bits, totaling q × r0 = 41120 bits), and once on the last r1 rows (q × r1 bits). Consider d. PAD =d CP -d CRC Appropriate values ​​of r and d need to be selected. CP Make d PAD ≥0.

[0211] Consider a first bit set undergoing a first process involving PCS processing, interleaving, and encoding to obtain a second bit set. The ratio of the encoded input bit length to the encoded output bit length in the encoding operation is 3552:4096 = 111:128. The bit ratio of the first bit set to the second bit set is m:4096 = f1:f2, where the greatest common divisor of integers f1 and f2 is 1. Typically, smaller values ​​for f1 and f2 result in simpler overall hardware implementation, lower complexity, and lower power consumption. Therefore, consider the following second constraint: m must be an integer multiple of 32, such that m:4096 = f:128, where the integer f = m / 32.

[0212] Taking some parameter combinations in Table 10 as examples, such as the parameter combination in row 9, namely {d in =4704128, r=2288, m=3504, d CP =5248, v / 16=125, B1=1884.06(Gbit / s), B 2-28 =1951.35 (Gbit / s), B s-28 =243.92 (GBaud), B 2-56 =1917.70 (Gbit / s), B s-56 =239.71 (GBaud)}, at this time, d PAD =1568, p=115, r1=8. Figure 10 is a schematic diagram of another implementation of CRC or padding bit insertion for the first data in this application embodiment. As shown in Figure 10, r0=20, and 1568b in Figure 10 represents 1568 bits. It should be noted that in actual optical transmission applications, the channel spacing C grid GHz, its value C grid (in gigabytes) is smaller than the baud rate value (in gigabytes), C grid Typically, the value is a multiple of 12.5, and a guardband of approximately 10% is considered. In this case, the baud rate corresponding to the parameter combination in line 7 is B. s-28=243.92 GBaud and B s-56 =239.71 GBaud, and in the corresponding specific optical communication network transmission, the channel spacing that can be used is 275 GHz.

[0213] Thirdly, consider the case where q = 10280 and W = 2.

[0214] The number of bits in the second data is d. scr =q×r+d CP = 672 × m. It should be understood that d represents the number of bits added as CRC check bits or padding bits. CP The larger the number of redundant OH groups introduced... CP =d CP The larger / (q×r) is, the greater it is. Table 11 below gives the corresponding {d in ,r,m,d CP} Parameter combinations.

[0215] Table 11

[0216] Table 11 also gives {r, m, d} CP The specific value of v / 16 under the parameter combination is as follows. It should be noted that v = m - 1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that in some specific embodiments, v = m - 1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0217] It should be noted that in some specific applications, the first data processing includes CRC-32 operations. In this case, consider the following third constraint: when the number of rows r is a multiple of 4, the number of CRC-32 operations p = r / 4, d CRC =r / 4×32≤d CP This means performing a CRC-32 operation on every 4 rows (4 × 10280 = 41120 bits) of data in r rows; when the number of rows r is not an integer multiple of 4, the number of CRC-32 operations is [number missing]. in The operation represents rounding down 'a', i.e., r0 = 4, r1 = r - 4 × (p - 1). CRC-32 is performed on each of the first 4 × (p - 1) rows of data (r0 = 4 rows, totaling q × r0 = 41120 bits), and then on the last r1 rows (q × r1 bits). Consider d. PAD =d CP -d CRC Combining Table 11 and the third constraint mentioned above, Table 12 below gives the corresponding {r, m, d}. CP d PAD The parameters are} and}. It should be noted that the last column of Table 12 also gives the specific values ​​of parameter r1 when the row number r is not a multiple of 4. For row numbers r that are multiples of 4, such as r = 224 in the third row of Table 12, the corresponding parameter r1 is represented by a forward slash in the table, indicating that the parameter r1 does not exist.

[0218] Table 12

[0219] It should be noted that in some specific applications, a first bit set containing m bits is subjected to a first processing step involving PCS processing, interleaving, and encoding to obtain a second bit set containing 4096 bits, where the ratio of the encoded input bit length to the encoded output bit length in the encoding operation is 111:128. For ease of hardware implementation, the fourth constraint is considered, i.e., m is an integer multiple of 32, such that the ratio of the input bit length to the output bit length of the first processing step is f:128, where the integer f = m / 32. Combining Table 11 and the aforementioned fourth constraint, Table 13 below gives the corresponding {r, m, d}. CP The combination of parameters f.

[0220] Table 13

[0221] Table 13 also gives {r, m, d} CPThe specific value of v / 16 under the parameter combination of and f is as follows. It should be noted that v = m - 1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that in some specific embodiments, v = m - 1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0222] It should be noted that in some specific applications, the third and fourth constraints mentioned above are considered. In this case, combining Table 11 with the third and fourth constraints, Table 14 below gives the corresponding {r, m, d}. CP d PAD The parameters are: f, p, etc. It should be noted that the last column of Table 14 also gives the specific values ​​of parameter r1 when the row number r is not a multiple of 4. When the row number r is a multiple of 4, such as r = 204 in row 10 of Table 14, the corresponding parameter r1 is represented by a forward slash in the table, indicating that the parameter r1 does not exist.

[0223] Table 14

[0224] Table 14 also gives {r, m, d} CP d PAD The specific value of v / 16 under the parameter combination of {f} and {p}. It should be noted that v = m - 1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, that is, the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process performs PCS sub-processing on the input k0 = v / 16 bits to obtain the output n0 = 128 bits.

[0225] It should be noted that the third aspect mentioned above considers N. CW In the case of 172032, q=10280, and W=2, the fourth data contains 172032 × 2 × 8 = 2752512 bits, which, after dual-polarization symbol mapping, yields 344064 dual-polarization 16QAM symbols. The parameter combinations given in Tables 11-14 can be used for N... CW The case of =86016, q=10280, and W=4 can also be used for N. CW The case where q = 43008, q = 10280, and W = 8.

[0226] Fourthly, consider the case where q = 10280 and W = 4.

[0227] The number of bits in the second data is d. scr =q×r+d CP = 1344 × m. It should be understood that d represents the number of bits d added as CRC check bits or padding bits. CP The larger the number of redundant OH groups introduced... CP =d CP The larger / (q×r) is, the greater the value. Table 15 below gives the corresponding {d} in ,r,m,d CP} Parameter combinations.

[0228] Table 15

[0229] Table 15 also gives {r, m, d} CP The specific value of v / 16 under the parameter combination is as follows. It should be noted that v = m - 1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that in some specific embodiments, v = m - 1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0230] It should be noted that in some specific applications, the first data processing includes CRC-32 operations. Combining Table 15 and the third constraint in the third aspect, Table 16 below gives the corresponding {r, m, d}. CP d PAD The parameters are} and}. It should be noted that the last column of Table 16 also gives the specific values ​​of parameter r1 when the row number r is not a multiple of 4. For row numbers r that are multiples of 4, such as r = 428 in row 9 of Table 16, the corresponding parameter r1 is represented by a forward slash in the table, indicating that the parameter r1 does not exist.

[0231] Table 16

[0232] It should be noted that in some specific applications, the fourth constraint in the third aspect is considered. Combining Table 17 and the fourth constraint in the third aspect, Table 17 below gives the corresponding {r, m, d}. CP The combination of parameters f.

[0233] Table 17

[0234] Table 17 also gives {r, m, d} CP The specific value of v / 16 under the parameter combination of and f is as follows. It should be noted that v = m - 1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that in some specific embodiments, v = m - 1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0235] It should be noted that in some specific applications, the third and fourth constraints in the third aspect are considered. In this case, combining Table 15 and the aforementioned third and fourth constraints, Table 18 below gives the corresponding {r, m, d}. CP d PAD The parameters are: f, p, etc. It should be noted that the last column of Table 18 also gives the specific values ​​of parameter r1 when the row number r is not a multiple of 4. When the row number r is a multiple of 4, such as r = 204 in row 10 of Table 18, the corresponding parameter r1 is represented by a forward slash in the table, indicating that the parameter r1 does not exist.

[0236] Table 18

[0237] Table 18 also gives {r, m, d} CP d PADThe specific value of v / 16 under the parameter combination {f, p}. It should be noted that v = m - 1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that v = m - 1504 is an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0238] It should be noted that the fourth aspect mentioned above considers N. CW In the case of 172032, q=10280, and W=4, the fourth data contains 172032 × 4 × 8 = 5505024 bits, which, after dual-polarization symbol mapping, yields 688128 dual-polarization 16QAM symbols. The parameter combinations given in Tables 15-18 can be used for N CW The case of 344064, q=10280, and W=2 can also be used for N. CW The case where q = 86016, q = 10280, and W = 8.

[0239] Below, based on the above description of the first and second data processing methods, several specific embodiments are given.

[0240] Example 3:

[0241] Considering W=2, q=10280, and the input data of the first data processing (i.e. the first data) is FlexO-16e or 1.6T ZR frame data, its nominal bit rate is B0≈1609.959013238Gbit / s.

[0242] In some specific applications, the redundancy of framing is considered to be h. DSP =1 / 28, and the corresponding bit rate after the second processing is B. 2-28 =B1×(1+h) DSP )=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(29 / 28), corresponding to a baud rate of B s-28 =B 2-28 / 8GBaud. In other specific applications, the framing redundancy is considered to be h. DSP =1 / 56, and the corresponding bit rate after the second processing is B. 2-56 =B1×(1+h)DSP )=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(57 / 56), corresponding to a baud rate of B. s-56 =B 2-56 / 8GBaud. Considering the parameter combinations in Table 11, the corresponding baud rate B s-28 and B s-56 All are less than 300 GBaud. Understandably, the proposed data processing scheme can be well applied to future 1.6T data centers and metropolitan area network scenarios. Furthermore, it contains a total of d in The first data of q×r bits, after the first data processing and the second data processing, yields exactly W=2 DSP frames (also known as superframes or multiframes), which makes the proposed data processing method have lower implementation complexity and lower power consumption.

[0243] Based on Table 11, consider the third and fourth constraints. Taking some parameter combinations in Table 11 as examples, for instance, the parameter combination in row 16, namely {d} in =2210200, r=215, m=3296, d CP =4712, v / 16=112}, at this time, B1=2004.99 (Gbit / s), B 2-28 =2076.60 (Gbit / s), B s-28 =259.57 (GBaud), B 2-56 =2040.79 (Gbit / s), B s-56 =255.10 (GBaud), d PAD =2984, p=54, r1=3. Figure 11 is a schematic diagram of another implementation of CRC or padding bit insertion for the first data in this application embodiment. As shown in Figure 11, r0=4, and 2984b in Figure 11 represents 2984 bits. It should be noted that in actual optical transmission applications, the channel spacing C grid GHz, its value C grid (in gigabytes) is smaller than the baud rate value (in gigabytes), C grid Typically, the value is a multiple of 12.5, and a guard band of approximately 10% is considered. In this case, the baud rate corresponding to the parameter combination in line 16 is B. s-28 =259.57 GBaud and B s-56 =255.10 GBaud. In specific optical communication network transmission, the channel spacing that can be used is 300 GHz or 287.5 GHz.

[0244] Example 4:

[0245] Considering W=4, q=10280, and the input data of the first data processing (i.e. the first data) is FlexO-16e or 1.6T ZR frame data, its nominal bit rate is B0≈1609.959013238Gbit / s.

[0246] In some specific applications, the redundancy of framing is considered to be h. DSP =1 / 28, and the corresponding bit rate after the second processing is B. 2-28 =B1×(1+h) DSP )=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(29 / 28), corresponding to a baud rate of B s-28 =B 2-28 / 8GBaud. In other specific applications, the framing redundancy is considered to be h. DSP =1 / 56, and the corresponding bit rate after the second processing is B. 2-56 =B1×(1+h) DSP )=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(57 / 56), corresponding to a baud rate of B. s-56 =B 2-56 / 8GBaud. Considering the parameter combinations in Table 15, the corresponding baud rate B s-28 and B s-56 All are less than 300 GBaud. Understandably, the proposed data processing scheme can be well applied to future 1.6T data centers and metropolitan area network scenarios. Furthermore, it contains a total of d in The first data of q×r bits, after the first data processing and the second data processing, yields exactly W=4 DSP frames (also known as superframes or multiframes), which makes the proposed data processing method have lower implementation complexity and lower power consumption.

[0247] Based on Table 15, consider the third and fourth constraints. Taking some parameter combinations in Table 15 as examples, for instance, the parameter combination in row 9, namely {d} in =4574600, r=445, m=3408, d CP =5752, v / 16=119}, at this time, B1=1937.41 (Gbit / s), B 2-28 =2006.60 (Gbit / s), B s-28 =250.83 (GBaud), B 2-56 =1972.00 (Gbit / s), B s-56 =246.50 (GBaud), d PAD=2168, p=112, r1=1. Figure 12 is a schematic diagram of another implementation of CRC or padding bit insertion for the first data in this application embodiment. As shown in Figure 12, r0=4, and 21684b in Figure 12 represents 2168 bits. It should be noted that in actual optical transmission applications, the channel spacing C grid GHz, its value C grid (in gigabytes) is smaller than the baud rate value (in gigabytes), C grid Typically, the value is a multiple of 12.5, and a guard band of approximately 10% is considered. In this case, the baud rate corresponding to the parameter combination in line 9 is B. s-28 =250.83 GBaud and B s-56 =246.50 GBaud. In the corresponding specific optical communication network transmission, the channel spacing that can be used is 287.5 GHz or 275 GHz.

[0248] Fifthly, consider the case where q = 2056 and W = 8.

[0249] The number of bits in the second data is d. scr =q×r+d CP = 2688 × m. It should be understood that d represents the number of bits (d) added as CRC check bits or padding bits. CP The larger the number of redundant OH groups introduced... CP =d CP The larger / (q×r) is, the greater it is. Table 19 below gives the corresponding {d in ,r,m,d CP} Parameter combinations.

[0250] Table 19

[0251] Table 19 also gives {r, m, d} CPThe specific value of v / 16 under the parameter combination is as follows. It should be noted that v = m - 1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that in some specific embodiments, v = m - 1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0252] It should be noted that the fifth aspect mentioned above considers N. CW In the case of 172032, q=2056, and W=8, the fourth data contains 172032 × 8 × 8 = 11010048 bits, which, after dual-polarization symbol mapping, yields 1376256 dual-polarization 16QAM symbols. The parameter combinations given in Table 19 can be used for N CW The case of 344064, q=2056, and W=4 can also be used for N. CW The case where q = 688128, q = 2056, and W = 2.

[0253] Sixthly, consider the case where q = 10280 and W = 8.

[0254] The number of bits in the second data is d. scr =q×r+d CP = 2688 × m. It should be understood that d represents the number of bits (d) added as CRC check bits or padding bits. CP The larger the number of redundant OH groups introduced... CP =d CP The larger / (q×r) is, the greater it is. Table 20 below gives the corresponding {d in ,r,m,d CP} Parameter combinations.

[0255] Table 20

[0256] Table 20 also gives {r, m, d} CPThe specific value of v / 16 under the parameter combination is as follows. It should be noted that v = m - 1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that in some specific embodiments, v = m - 1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0257] It should be noted that the sixth aspect mentioned above considers N. CW In the case of 172032, q = 10280, and W = 8, the fourth data contains 172032 × 8 × 8 = 11010048 bits, which, after dual-polarization symbol mapping, yields 1376256 dual-polarization 16QAM symbols. The parameter combinations given in Table 20 can be used for N CW The case of 344064, q=10280, and W=4 can also be used for N. CW The case where q = 688128, q = 10280, and W = 2.

[0258] Seventhly, consider the case where q = 5140 and W = 2.

[0259] The number of bits in the second data is d. scr =q×r+d CP = 672 × m. It should be understood that d represents the number of bits added as CRC check bits or padding bits. CP The larger the number of redundant OH groups introduced... CP =d CP The larger / (q×r) is, the greater the value. Table 21 below gives the corresponding {d} in ,r,m,d CP} Parameter combinations.

[0260] Table 21

[0261] Table 21 also gives {r, m, d} CPThe specific value of v / 16 under the parameter combination is as follows. It should be noted that v = m - 1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that in some specific embodiments, v = m - 1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0262] It should be noted that the seventh aspect mentioned above considers N. CW In the case of 172032, q=5140, and W=2, the fourth data contains 172032 × 2 × 8 = 2752512 bits, which, after dual-polarization symbol mapping, yield 344064 dual-polarization 16QAM symbols. The parameter combinations given in Table 21 can be used for N... CW The case of 86016, q=5140, and W=4 can also be used for N. CW The case where q = 43008, q = 5140, and W = 8.

[0263] Eighthly, consider the case where q = 5140 and W = 4.

[0264] The number of bits in the second data is d. scr =q×r+d CP = 1344 × m. It should be understood that d represents the number of bits d added as CRC check bits or padding bits. CP The larger the number of redundant OH groups introduced... CP =d CP The larger / (q×r) is, the larger it becomes. Table 22 below gives the corresponding {d in ,r,m,d CP} Parameter combinations.

[0265] Table 22

[0266] Table 22 also gives {r, m, d} CPThe specific value of v / 16 under the parameter combination is as follows. It should be noted that v = m - 1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that in some specific embodiments, v = m - 1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0267] It should be noted that the eighth aspect mentioned above considers N. CW In the case of 172032, q=5140, and W=4, the fourth data contains 172032 × 4 × 8 = 2752512 bits, which, after dual-polarization symbol mapping, yield 344064 dual-polarization 16QAM symbols. The parameter combinations given in Table 22 can be used for N CW The case of 344064, q=5140, and W=2 can also be used for N. CW The case where q = 86016, q = 5140, and W = 8.

[0268] Ninthly, consider the case where q = 5140 and W = 8.

[0269] The number of bits in the second data is d. scr =q×r+d CP = 2688 × m. It should be understood that d represents the number of bits (d) added as CRC check bits or padding bits. CP The larger the number of redundant OH groups introduced... CP =d CP The larger / (q×r) is, the greater it is. Table 23 below gives the corresponding {d in ,r,m,d CP} Parameter combinations.

[0270] Table 23

[0271] Table 23 also gives {r, m, d} CPThe specific value of v / 16 under the parameter combination is as follows. It should be noted that v = m - 1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that in some specific embodiments, v = m - 1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0272] It should be noted that the ninth aspect mentioned above considers N. CW In the case of 172032, q=5140, and W=8, the fourth data contains 172032 × 8 × 8 = 11010048 bits, which, after dual-polarization symbol mapping, yield 1376256 dual-polarization 16QAM symbols. The parameter combinations given in Table 23 can be used for N CW The case of 344064, q=5140, and W=4 can also be used for N. CW The case where q = 688128, q = 5140, and W = 2.

[0273] Example 5:

[0274] Considering W=8, q=2056, and the input data of the first data processing (i.e. the first data) is FlexO-16e or 1.6T ZR frame data, its nominal bit rate is B0≈1609.959013238Gbit / s.

[0275] In some specific applications, the redundancy of framing is considered to be h. DSP =1 / 28, and the corresponding bit rate after the second processing is B. 2-28 =B1×(1+h) DSP )=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(29 / 28), corresponding to a baud rate of B s-28 =B 2-28 / 8GBaud. In other specific applications, the framing redundancy is considered to be h. DSP =1 / 56, and the corresponding bit rate after the second processing is B. 2-56 =B1×(1+h) DSP )=B0×(r×q+d CP) / (r×q)×(4096 / m)×(57 / 56), corresponding to a baud rate of B. s-56 =B 2-56 / 8GBaud. Considering the parameter combinations in Table 19, the corresponding baud rate B s-28 and B s-56 All are less than 300 GBaud. Understandably, the proposed data processing scheme can be well applied to future 1.6T data centers and metropolitan area network scenarios. Furthermore, it contains a total of d in The first data of q×r bits, after the first data processing and the second data processing, yields exactly W=8 DSP frames (also known as superframes or multiframes), which makes the proposed data processing method have lower implementation complexity and lower power consumption.

[0276] Based on Table 19, consider the first and second constraints. Taking some parameter combinations in Table 19 as examples, such as the parameter combination in row 40, i.e., {d} in =9194432, r=4472, m=3424}, at this time, d CP =9280, v / 16=120, B1=1927.88(Gbit / s), B 2-28 =1996.73 (Gbit / s), B s-28 =249.59 (GBaud), B 2-56 =1962.30 (Gbit / s), B s-56 =245.29 (GBaud), d PAD =2112, p=224, r1=12. It should be noted that in practical optical transmission applications, the channel spacing C... grid GHz, its value C grid (in gigabytes) is smaller than the baud rate value (in gigabytes), C grid Typically, the value is a multiple of 12.5, and a guard band of approximately 10% is considered. In this case, the baud rate corresponding to the parameter combination in line 40 is B. s-28 =249.59 GBaud and B s-56 =245.29 GBaud. In specific optical communication network transmission, the channel spacing that can be used is 287.5 GHz or 275 GHz.

[0277] Example 6:

[0278] Considering W=8, q=10280, and the input data of the first data processing (i.e. the first data) is FlexO-16e or 1.6T ZR frame data, its nominal bit rate is B0≈1609.959013238Gbit / s.

[0279] In some specific applications, the redundancy of framing is considered to be h. DSP =1 / 28, and the corresponding bit rate after the second processing is B. 2-28 =B1×(1+h) DSP )=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(29 / 28), corresponding to a baud rate of B s-28 =B 2-28 / 8GBaud. In other specific applications, the framing redundancy is considered to be h. DSP =1 / 56, and the corresponding bit rate after the second processing is B. 2-56 =B1×(1+h) DSP )=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(57 / 56), corresponding to a baud rate of B. s-56 =B 2-56 / 8GBaud. Considering the parameter combinations in Table 20, the corresponding baud rate B s-28 and B s-56 All are less than 300 GBaud. Understandably, the proposed data processing scheme can be well applied to future 1.6T data centers and metropolitan area network scenarios. Furthermore, it contains a total of d in The first data of q×r bits, after the first data processing and the second data processing, yields exactly W=8 DSP frames (also known as superframes or multiframes), which makes the proposed data processing method have lower implementation complexity and lower power consumption.

[0280] Based on Table 20, consider the third and fourth constraints. Taking some parameter combinations in Table 20 as examples, for instance, the parameter combination in row 10, namely {d} in =9108080, r=886, m=3392, d CP =9616, v / 16=118}, at this time, B1=1946.15 (Gbit / s), B 2-28 =2015.66 (Gbit / s), B s-28 =251.96 (GBaud), B 2-56 =1980.91 (Gbit / s), B s-56 =247.61 (GBaud), d PAD =2512, p=222, r1=2. It should be noted that in practical optical transmission applications, the channel spacing C... grid GHz, its value C grid (in gigabytes) is smaller than the baud rate value (in gigabytes), C gridTypically, the value is a multiple of 12.5, and a guard band of approximately 10% is considered. In this case, the baud rate corresponding to the parameter combination in line 10 is B. s-28 =251.96 GBaud and B s-56 =247.61 GBaud, and in the corresponding specific optical communication network transmission, the channel spacing that can be used is 287.5 GHz.

[0281] Example 7:

[0282] Considering W=2, q=5140, and the input data of the first data processing (i.e. the first data) is FlexO-16e or 1.6T ZR frame data, its nominal bit rate is B0≈1609.959013238Gbit / s.

[0283] In some specific applications, the redundancy of framing is considered to be h. DSP =1 / 28, and the corresponding bit rate after the second processing is B. 2-28 =B1×(1+h) DSP )=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(29 / 28), corresponding to a baud rate of B s-28 =B 2-28 / 8GBaud. In other specific applications, the framing redundancy is considered to be h. DSP =1 / 56, and the corresponding bit rate after the second processing is B. 2-56 =B1×(1+h) DSP )=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(57 / 56), corresponding to a baud rate of B. s-56 =B 2-56 / 8GBaud. Considering the parameter combinations in Table 21, the corresponding baud rate B s-28 and B s-56 All are less than 300 GBaud. Understandably, the proposed data processing scheme can be well applied to future 1.6T data centers and metropolitan area network scenarios. Furthermore, it contains a total of d in The first data of q×r bits, after the first data processing and the second data processing, yields exactly W=2 DSP frames (also known as superframes or multiframes), which makes the proposed data processing method have lower implementation complexity and lower power consumption.

[0284] Based on Table 28, consider the following fifth and sixth constraints.

[0285] The first data processing step involves adding a Cyclic Redundancy Check (CRC-32) operation. The CRC-32 encoding and corresponding CRC detection operations can directly utilize the existing CRC-32 operations in the 800G-ZR, which is simple to implement. That is, considering the fifth constraint as follows: when the number of rows r is an integer multiple of 8, the number of CRC-32 operations p = r / 8, d CRC =r / 8×32≤d CP This means performing a CRC-32 operation on every 8 rows (41120 bits) of data in r rows; when the number of rows r is not an integer multiple of 8, the number of CRC-32 operations is [number missing]. in The operation represents rounding down 'a', i.e., r0 = 8, r1 = r - 8 × (p - 1). CRC-32 is performed on each of the first 8 × (p - 1) rows of data (r0 = 8 bits, totaling q × r0 = 41120 bits), and then once on the last r1 rows (q × r1 bits). Consider d. PAD =d CP -d CRC Appropriate values ​​of r and d need to be selected. CP Make d PAD ≥0.

[0286] Consider a first bit set undergoing a first process involving PCS, interleaving, and encoding to obtain a second bit set, where the ratio of the encoded input bit length to the encoded output bit length in the encoding operation is 3552:4096 = 111:128. Consider a bit ratio of m:4096 = f1:f2 between the first and second bit sets, where the greatest common divisor of integers f1 and f2 is 1. Typically, smaller values ​​for f1 and f2 result in simpler overall hardware implementation, lower complexity, and lower power consumption. Therefore, consider the following sixth constraint: m must be an integer multiple of 32, such that m:4096 = f:128, where the integer f = m / 32.

[0287] Taking some parameter combinations in Table 21 as examples, such as the parameter combination in row 24, namely {d in =2251320, r=438, m=3360, d CP =6600, v / 16=116}, at this time, B1=1968.37 (Gbit / s), B 2-28 =2038.67 (Gbit / s), B s-28 =254.83 (GBaud), B 2-56 =2003.52 (Gbit / s), B s-56 =250.44 (GBaud), d PAD=4840, p=55, r1=6. It should be noted that in practical optical transmission applications, the channel spacing C... grid GHz, its value C grid (in gigabytes) is smaller than the baud rate value (in gigabytes), C grid Typically, the value is a multiple of 12.5, and a guard band of approximately 10% is considered. In this case, the baud rate corresponding to the parameter combination in line 24 is B. s-28 =254.83 GBaud and B s-56 =250.44 GBaud, and in the corresponding specific optical communication network transmission, the channel spacing that can be used is 287.5 GHz.

[0288] Example 8:

[0289] Considering W=4, q=5140, and the input data of the first data processing (i.e. the first data) is FlexO-16e or 1.6T ZR frame data, its nominal bit rate is B0≈1609.959013238Gbit / s.

[0290] In some specific applications, the redundancy of framing is considered to be h. DSP =1 / 28, and the corresponding bit rate after the second processing is B. 2-28 =B1×(1+h) DSP )=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(29 / 28), corresponding to a baud rate of B s-28 =B 2-28 / 8GBaud. In other specific applications, the framing redundancy is considered to be h. DSP =1 / 56, and the corresponding bit rate after the second processing is B. 2-56 =B1×(1+h) DSP )=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(57 / 56), corresponding to a baud rate of B. s-56 =B 2-56 / 8GBaud. Considering the parameter combinations in Table 22, the corresponding baud rate B s-28 and B s-56 All are less than 300 GBaud. Understandably, the proposed data processing scheme can be well applied to future 1.6T data centers and metropolitan area network scenarios. Furthermore, it contains a total of d in The first data of q×r bits, after the first data processing and the second data processing, yields exactly W=4 DSP frames (also known as superframes or multiframes), which makes the proposed data processing method have lower implementation complexity and lower power consumption.

[0291] Based on Table 22, consider the fifth and sixth constraints. Taking some parameter combinations in Table 22 as examples, for instance, the parameter combination in row 16, namely {d} in =4595160, r=894, m=3424, d CP =6696, v / 16=120}, at this time, B1=1928.74 (Gbit / s), B 2-28 =1997.62 (Gbit / s), B s-28 =249.70 (GBaud), B 2-56 =1963.18 (Gbit / s), B s-56 =245.40 (GBaud), d PAD =3112, p=112, r1=6. It should be noted that in practical optical transmission applications, the channel spacing C... grid GHz, its value C grid (in gigabytes) is smaller than the baud rate value (in gigabytes), C grid Typically, the value is a multiple of 12.5, and a guard band of approximately 10% is considered. In this case, the baud rate corresponding to the parameter combination in line 16 is B. s-28 =249.70 GBaud and B s-56 =245.40 GBaud. In specific optical communication network transmission, the channel spacing that can be used is 287.5 GHz or 275 GHz.

[0292] Example 9:

[0293] Considering W=8, q=5140, and the input data of the first data processing (i.e. the first data) is FlexO-16e or 1.6T ZR frame data, its nominal bit rate is B0≈1609.959013238Gbit / s.

[0294] In some specific applications, the redundancy of framing is considered to be h. DSP =1 / 28, and the corresponding bit rate after the second processing is B. 2-28 =B1×(1+h) DSP )=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(29 / 28), corresponding to a baud rate of B s-28 =B 2-28 / 8GBaud. In other specific applications, the framing redundancy is considered to be h. DSP =1 / 56, and the corresponding bit rate after the second processing is B. 2-56=B1×(1+h) DSP )=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(57 / 56), corresponding to a baud rate of B. s-56 =B 2-56 / 8GBaud. Considering the parameter combinations in Table 23, the corresponding baud rate B s-28 and B s-56 All are less than 300 GBaud. Understandably, the proposed data processing scheme can be well applied to future 1.6T data centers and metropolitan area network scenarios. Furthermore, it contains a total of d in The first data of q×r bits, after the first data processing and the second data processing, yields exactly W=8 DSP frames (also known as superframes or multiframes), which makes the proposed data processing method have lower implementation complexity and lower power consumption.

[0295] Based on Table 23, consider the fifth and sixth constraints. Taking some parameter combinations in Table 23 as examples, for instance, the parameter combination in row 29, namely {d... in =9108080, r=1772, m=3392, d CP =9616, v / 16=118}, at this time, B1=1946.15 (Gbit / s), B 2-28 =2015.66 (Gbit / s), B s-28 =251.96 (GBaud), B 2-56 =1980.91 (Gbit / s), B s-56 =247.61 (GBaud), d PAD =2512, p=222, r1=4. It should be noted that in practical optical transmission applications, the channel spacing C... grid GHz, its value C grid (in gigabytes) is smaller than the baud rate value (in gigabytes), C grid Typically, the value is a multiple of 12.5, and a guard band of approximately 10% is considered. In this case, the baud rate corresponding to the parameter combination in line 29 is B. s-28 =251.96 GBaud and B s-56 =247.61 GBaud, and in the corresponding specific optical communication network transmission, the channel spacing that can be used is 287.5 GHz.

[0296] It should be noted that the above embodiments consider the input data for the first data processing (i.e., the first data) to be FlexO-16e or 1600GZR frame data, with a nominal bit rate of B0 ≈ 1609.959013238Gbit / s. The parameter combinations given in the above embodiments can also be applied to other data types, such as data with rates of 1.2T, 2.4T, and 3.2T. For example, in some specific applications, the input data for the first data processing (i.e., the first data) is FlexO-12e data, with a nominal bit rate of B0 ≈ 1207.469Gbit / s. The bit rate corresponding to the first and second data processing can be expressed as B2 = B0 × (r × q + d). CP ) / (r×q)×(4096 / m)×(1+h DSP The corresponding baud rate (i.e., DP-16QAM symbol rate) is calculated using B. s =B2 / 8 =B0×(r×q+d) CP ) / (r×q)×(4096 / m)×(1+h DSP The value is obtained by calculation of ) / 8GBaud, and the specific calculation is known to those skilled in the art, so it will not be described in detail here.

[0297] Example 10:

[0298] Considering W=2, q=2056, and the input data for the first data processing (i.e., the first data) is FlexO-12e frame data, its nominal bit rate is B0≈1207.47Gbit / s. It should be noted that in this embodiment, non-integers are only retained to two decimal places. In some specific applications, the non-integers can be described in other forms, such as retaining nine decimal places, etc. Such descriptions are known to those skilled in the art and will not be elaborated here. The first data contains r rows and q=2056 columns, totaling d... in = q × r bits.

[0299] Based on Table 1, Table 24 provides more corresponding {d} in ,r,m,d CP The parameter combination is v / 16.

[0300] Table 24

[0301] In some specific applications, the redundancy of framing is considered to be h. DSP =1 / 28, and the corresponding bit rate after the second processing is B. 2-28 =B1×(1+h) DSP)=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(29 / 28), corresponding to a baud rate of B s-28 =B 2-28 / 8GBaud. In other specific applications, the framing redundancy is considered to be h. DSP =1 / 56, and the corresponding bit rate after the second processing is B. 2-56 =B1×(1+h) DSP )=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(57 / 56), corresponding to a baud rate of B. s-56 =B 2-56 / 8GBaud.

[0302] Considering the parameter combinations in Table 1 and using B0≈1207.47Gbit / s, the corresponding baud rate B s-28 and B s-56 All are less than 260 GBaud. Understandably, the proposed data processing scheme can be well applied to future 1.2T data centers and metropolitan area network scenarios. Furthermore, it contains a total of d in The first data of q×r bits, after the first data processing and the second data processing, yields exactly W=2 DSP frames (also known as superframes or multiframes), which makes the proposed data processing method have lower implementation complexity and lower power consumption.

[0303] Based on Tables 1 and 24, considering the first and second constraints and using B0≈1207.47Gbit / s, let's take some parameter combinations from Tables 1 and 24 as examples, such as the parameter combination in row 5 of Table 1, i.e., {d in =2362344, r=1149, m=3520, d CP =3096, v / 16=126}, at this time, B1=1406.90 (Gbit / s), B 2-28 =1457.14 (Gbit / s), B s-28 =182.14 (GBaud), B 2-56 =1432.02 (Gbit / s), B s-56 =179.00 (GBaud), d PAD =1240, p=58, r1=9. It should be noted that in practical optical transmission applications, the channel spacing C... grid GHz, its value C grid (in gigabytes) is smaller than the baud rate value (in gigabytes), C gridTypically, the value is a multiple of 12.5, and a guardband of approximately 10% is considered. In this case, the baud rate corresponding to the parameter combination in row 5 of Table 1 is B. s-28 =182.14 GBaud and B s-56 =179.00 GBaud, and in the corresponding specific optical communication network transmission, the channel spacing that can be used is 212.5 GHz or 200 GHz.

[0304] Example 11:

[0305] Considering W=4, q=2056, and the input data for the first data processing (i.e., the first data) is FlexO-12e frame data, its nominal bit rate is B0≈1207.47Gbit / s. It should be noted that in this embodiment, non-integers in the table are only retained to two decimal places. In some specific applications, the non-integers can be described in other forms, such as retaining nine decimal places, etc. Such descriptions are known to those skilled in the art and will not be elaborated here. The first data contains r rows and q=2056 columns, totaling d... in = q × r bits.

[0306] Based on Table 5, Table 25 provides more corresponding {d} in ,r,m,d CP The parameter combination is v / 16.

[0307] Table 25

[0308] In some specific applications, the redundancy of framing is considered to be h. DSP =1 / 28, and the corresponding bit rate after the second processing is B. 2-28 =B1×(1+h) DSP )=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(29 / 28), corresponding to a baud rate of B s-28 =B 2-28 / 8GBaud. In other specific applications, the framing redundancy is considered to be h. DSP =1 / 56, and the corresponding bit rate after the second processing is B. 2-56 =B1×(1+h) DSP )=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(57 / 56), corresponding to a baud rate of B. s-56 =B 2-56 / 8GBaud.

[0309] Considering the parameter combinations in Table 5 and using B0≈1207.47Gbit / s, the corresponding baud rate B s-28 and B s-56 All are less than 260 GBaud. Understandably, the proposed data processing scheme can be well applied to future 1.2T data centers and metropolitan area network scenarios. Furthermore, it contains a total of d in The first data of q×r bits, after the first data processing and the second data processing, yields exactly W=4 DSP frames (also known as superframes or multiframes), which makes the proposed data processing method have lower implementation complexity and lower power consumption.

[0310] Based on Tables 5 and 25, considering the first and second constraints and using B0≈1207.47Gbit / s, let's take some parameter combinations from Tables 5 and 25 as examples, such as the parameter combination in row 96 of Table 5, i.e., {d in =4081160, r=1985, m=3040, d CP =4600, v / 16=96}, at this time, B1=1628.74 (Gbit / s), B 2-28 =1686.91 (Gbit / s), B s-28 =210.86 (GBaud), B 2-56 =1657.82 (Gbit / s), B s-56 =207.23 (GBaud), d PAD =1256, p=111, r1=15. It should be noted that in practical optical transmission applications, the channel spacing C... grid GHz, its value C grid (in gigabytes) is smaller than the baud rate value (in gigabytes), C grid Typically, the value is a multiple of 12.5, and a guardband of approximately 10% is considered. In this case, the baud rate corresponding to the parameter combination in row 96 of Table 5 is B. s-28 =210.86 GBaud and B s-56 =207.23 GBaud, and in the corresponding specific optical communication network transmission, the channel spacing that can be used is 237.5 GHz.

[0311] Example 12:

[0312] Considering W=8, q=2056, and the input data for the first data processing (i.e., the first data) is FlexO-12e frame data, its nominal bit rate is B0≈1207.47Gbit / s. It should be noted that in this embodiment, non-integers in the table are only retained to two decimal places. In some specific applications, the non-integers can be described in other forms, such as retaining nine decimal places, etc. Such descriptions are known to those skilled in the art and will not be elaborated here. The first data contains r rows and q=2056 columns, totaling d... in = q × r bits.

[0313] Based on Table 19, Table 26 provides more corresponding {d} in ,r,m,d CP The parameter combination is v / 16.

[0314] Table 26

[0315] In some specific applications, the redundancy of framing is considered to be h. DSP =1 / 28, and the corresponding bit rate after the second processing is B. 2-28 =B1×(1+h) DSP )=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(29 / 28), corresponding to a baud rate of B s-28 =B 2-28 / 8GBaud. In other specific applications, the framing redundancy is considered to be h. DSP =1 / 56, and the corresponding bit rate after the second processing is B. 2-56 =B1×(1+h) DSP )=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(57 / 56), corresponding to a baud rate of B. s-56 =B 2-56 / 8GBaud.

[0316] Considering the parameter combinations in the table and using B0≈1207.47Gbit / s, the corresponding baud rate B s-28 and B s-56 All are less than 260 GBaud. Understandably, the proposed data processing scheme can be well applied to future 1.2T data centers and metropolitan area network scenarios. Furthermore, it contains a total of d inThe first data of q×r bits, after the first data processing and the second data processing, yields exactly W=8 DSP frames (also known as superframes or multiframes), which makes the proposed data processing method have lower implementation complexity and lower power consumption.

[0317] Based on Tables 19 and 26, considering the first and second constraints and using B0≈1207.47Gbit / s, let's take some parameter combinations from Tables 19 and 26 as examples, such as the parameter combination in row 159 of Table 19, i.e., {d in =8164376, r=3971, m=3040, d CP =7144, v / 16=96}, at this time, B1=1628.33 (Gbit / s), B 2-28 =1686.48 (Gbit / s), B s-28 =210.81 (GBaud), B 2-56 =1657.41 (Gbit / s), B s-56 =207.18 (GBaud), d PAD =776, p=199, r1=11. It should be noted that in practical optical transmission applications, the channel spacing C... grid GHz, its value C grid (in gigabytes) is smaller than the baud rate value (in gigabytes), C grid Typically, the value is a multiple of 12.5, and a guardband of approximately 10% is considered. In this case, the baud rate corresponding to the parameter combination in row 159 of Table 19 is B. s-28 =210.81 GBaud and B s-56 =207.18 GBaud, and in the corresponding specific optical communication network transmission, the channel spacing that can be used is 237.5 GHz.

[0318] Example 13:

[0319] Considering W=2, q=10280, and the input data for the first data processing (i.e., the first data) is FlexO-12e frame data, its nominal bit rate is B0≈1207.47Gbit / s. It should be noted that in this embodiment, non-integers in the table are only retained to two decimal places. In some specific applications, the non-integers can be described in other forms, such as retaining nine decimal places, etc. Such descriptions are known to those skilled in the art and will not be elaborated here. The first data contains r rows and q=2056 columns, totaling d... in = q × r bits.

[0320] Based on Table 11, Table 27 provides more corresponding {d}in ,r,m,d CP The parameter combination is v / 16.

[0321] Table 27

[0322] In some specific applications, the redundancy of framing is considered to be h. DSP =1 / 28, and the corresponding bit rate after the second processing is B. 2-28 =B1×(1+h) DSP )=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(29 / 28), corresponding to a baud rate of B s-28 =B 2-28 / 8GBaud. In other specific applications, the framing redundancy is considered to be h. DSP =1 / 56, and the corresponding bit rate after the second processing is B. 2-56 =B1×(1+h) DSP )=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(57 / 56), corresponding to a baud rate of B. s-56 =B 2-56 / 8GBaud.

[0323] Considering the parameter combinations in the table and using B0≈1207.47Gbit / s, the corresponding baud rate B s-28 and B s-56 All are less than 260 GBaud. Understandably, the proposed data processing scheme can be well applied to future 1.2T data centers and metropolitan area network scenarios. Furthermore, it contains a total of d in The first data of q×r bits, after the first data processing and the second data processing, yields exactly W=8 DSP frames (also known as superframes or multiframes), which makes the proposed data processing method have lower implementation complexity and lower power consumption.

[0324] Based on Tables 11 and 27, considering the third and fourth constraints and using B0≈1207.47Gbit / s, let's take some parameter combinations from Tables 11 and 27 as examples, such as the parameter combination in row 32 of Table 11, i.e., {d in =2035440, r=198, m=3040, d CP =7440, v / 16=96}, at this time, B1=1632.85 (Gbit / s), B 2-28 =1691.17 (Gbit / s), B s-28 =211.40 (GBaud), B 2-56=1662.01 (Gbit / s), B s-56 =207.75 (GBaud), d PAD =5840, p=50, r1=2. It should be noted that in practical optical transmission applications, the channel spacing C... grid GHz, its value C grid (in gigabytes) is smaller than the baud rate value (in gigabytes), C grid Typically, the value is an integer multiple of 12.5, and a guardband of approximately 10% is considered. In this case, the baud rate corresponding to the parameter combination in row 32 of Table 11 is B. s-28 =211.40 GBaud and B s-56 =207.75 GBaud, and in the corresponding specific optical communication network transmission, the channel spacing that can be used is 237.5 GHz.

[0325] Example 14:

[0326] Considering W=4, q=10280, and the input data for the first data processing (i.e., the first data) is FlexO-12e frame data, its nominal bit rate is B0≈1207.47Gbit / s. It should be noted that in this embodiment, non-integers in the table are only retained to two decimal places. In some specific applications, the non-integers can be described in other forms, such as retaining nine decimal places, etc. Such descriptions are known to those skilled in the art and will not be elaborated here. The first data contains r rows and q=2056 columns, totaling d... in = q × r bits.

[0327] Based on Table 15, Table 28 provides more corresponding {d} in ,r,m,d CP The parameter combination is v / 16.

[0328] Table 28

[0329] In some specific applications, the redundancy of framing is considered to be h. DSP =1 / 28, and the corresponding bit rate after the second processing is B. 2-28 =B1×(1+h) DSP )=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(29 / 28), corresponding to a baud rate of B s-28 =B 2-28 / 8GBaud. In other specific applications, the framing redundancy is considered to be h. DSP=1 / 56, and the corresponding bit rate after the second processing is B. 2-56 =B1×(1+h) DSP )=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(57 / 56), corresponding to a baud rate of B. s-56 =B 2-56 / 8GBaud.

[0330] Considering the parameter combinations in the table and using B0≈1207.47Gbit / s, the corresponding baud rate B s-28 and B s-56 All are less than 260 GBaud. Understandably, the proposed data processing scheme can be well applied to future 1.2T data centers and metropolitan area network scenarios. Furthermore, it contains a total of d in The first data of q×r bits, after the first data processing and the second data processing, yields exactly W=8 DSP frames (also known as superframes or multiframes), which makes the proposed data processing method have lower implementation complexity and lower power consumption.

[0331] Based on Tables 15 and 28, considering the third and fourth constraints and using B0≈1207.47Gbit / s, let's take some parameter combinations from Tables 15 and 28 as examples, such as the parameter combination in row 32 of Table 19, i.e., {d in =4081160, r=397, m=3040, d CP =4600, v / 16=96}, at this time, B1=1628.74 (Gbit / s), B 2-28 =1686.91 (Gbit / s), B s-28 =210.86 (GBaud), B 2-56 =1657.82 (Gbit / s), B s-56 =207.23 (GBaud), d PAD =1400, p=100, r1=1. It should be noted that in practical optical transmission applications, the channel spacing C... grid GHz, its value C grid (in gigabytes) is smaller than the baud rate value (in gigabytes), C grid Typically, the value is a multiple of 12.5, and a guardband of approximately 10% is considered. In this case, the baud rate corresponding to the parameter combination in row 32 of Table 15 is B. s-28 =210.86 GBaud and B s-56 =207.23 GBaud, and in the corresponding specific optical communication network transmission, the usable channel spacing is 237.5 GHz.

[0332] Example 15:

[0333] Considering W=8, q=10280, and the input data for the first data processing (i.e., the first data) is FlexO-12e frame data, its nominal bit rate is B0≈1207.47Gbit / s. It should be noted that in this embodiment, non-integers in the table are only retained to two decimal places. In some specific applications, the non-integers can be described in other forms, such as retaining nine decimal places, etc. Such descriptions are known to those skilled in the art and will not be elaborated here. The first data contains r rows and q=2056 columns, totaling d... in = q × r bits.

[0334] Based on Table 20, Table 29 provides more corresponding {d} in ,r,m,d CP The parameter combination is v / 16.

[0335] Table 29

[0336] In some specific applications, the redundancy of framing is considered to be h. DSP =1 / 28, and the corresponding bit rate after the second processing is B. 2-28 =B1×(1+h) DSP )=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(29 / 28), corresponding to a baud rate of B s-28 =B 2-28 / 8GBaud. In other specific applications, the framing redundancy is considered to be h. DSP =1 / 56, and the corresponding bit rate after the second processing is B. 2-56 =B1×(1+h) DSP )=B0×(r×q+d CP ) / (r×q)×(4096 / m)×(57 / 56), corresponding to a baud rate of B. s-56 =B 2-56 / 8GBaud.

[0337] Considering the parameter combinations in the table and using B0≈1207.47Gbit / s, the corresponding baud rate B s-28 and B s-56 All are less than 260 GBaud. Understandably, the proposed data processing scheme can be well applied to future 1.2T data centers and metropolitan area network scenarios. Furthermore, it contains a total of d inThe first data of q×r bits, after the first data processing and the second data processing, yields exactly W=8 DSP frames (also known as superframes or multiframes), which makes the proposed data processing method have lower implementation complexity and lower power consumption.

[0338] Based on Tables 20 and 29, considering the third and fourth constraints and using B0≈1207.47Gbit / s, let's take some parameter combinations from Tables 20 and 29 as examples, such as the parameter combination in row 63 of Table 20, i.e., {d in =8162320, r=794, m=3040, d CP =9200, v / 16=96}, at this time, B1=1628.74 (Gbit / s), B 2-28 =1686.91 (Gbit / s), B s-28 =210.86 (GBaud), B 2-56 =1657.82 (Gbit / s), B s-56 =207.23 (GBaud), d PAD =2832, p=199, r1=2. It should be noted that in practical optical transmission applications, the channel spacing C... grid GHz, its value C grid (in gigabytes) is smaller than the baud rate value (in gigabytes), C grid Typically, the value is a multiple of 12.5, and a guardband of approximately 10% is considered. In this case, the baud rate corresponding to the parameter combination in row 63 of Table 20 is B. s-28 =210.86 GBaud and B s-56 =207.23 GBaud, and in the corresponding specific optical communication network transmission, the channel spacing that can be used is 237.5 GHz.

[0339] It should be noted that the first to ninth aspects can also be used in single-carrier transmission scenarios, that is, the second processing processes the input M first data streams to obtain W=1 dual-polarization symbol streams. The specific operation is as follows: First data is acquired, the first data including d... in bits, d in The integer is greater than or equal to 1; the first data is subjected to cyclic redundancy check (CRC) or padding bits are inserted to obtain the result including d. scr The second data consists of bits, the second data including d CRC One CRC check bit or d PAD One padding bit, d CRC and d PAD All are integers greater than or equal to 0, d scr =d in+d CRC +d PAD The second data is scrambled to obtain the third data, which includes d. scr The third data is processed by a first process to obtain the fourth data, the first process including probabilistic constellation shaping (PCS) processing, interleaving, and encoding; the fourth data is then processed by a second process to obtain a DSP frame (also called a superframe or multiframe) in a first dual-polarization symbol stream of W=1, the second process including symbol mapping, polarization partitioning, and framing. Considering the use of hexadecimal quadrature amplitude modulation (16QAM), the fourth data contains 8×N bits. CW Each bit is processed in the second step to obtain one DSP frame (also known as a superframe or multiple frames).

[0340] Tenth aspect, considering q = 2056, N CW =344064, W=1.

[0341] The number of bits in the third data is d. scr =q×r+d CP = 672 × m. It should be understood that d represents the number of bits added as CRC check bits or padding bits. CP The larger the number of redundant OH groups introduced... CP =d CP The larger / (q×r) is, the greater the corresponding {d}. in ,r,m,d CP The parameter combinations are shown in Table 1 above.

[0342] It should be noted that Table 1 also provides {r, m, d} CPUnder the parameter combination, the specific value of v / 16 = (m-1504) / 16 is determined. For v = m-1504, which is an integer multiple of 16, when n0 = 128, k0 = v / 16. This means the PCS processing uses 16 PCS sub-processes to achieve the desired effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain the output n0 = 128 bits. In some specific applications, the 16 PCS sub-processes are implemented using 16 lookup tables (LUTs). In other specific applications, the 16 PCS sub-processes are implemented using 16 trellis coding operations. It should be noted that in some specific embodiments, considering that v = m - 1504 is an integer multiple of 32, when n0 = 64, k0 = v / 32. This means that the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain the output n0 = 64 bits. In some specific applications, the 32 PCS sub-processes are implemented using 32 lookup tables (LUTs). In other specific applications, the 32 PCS sub-processes are implemented using 32 trellis coding operations.

[0343] It should be noted that in some specific applications, the first data processing includes CRC-32 operations. In this case, considering the first constraint, that is: when the number of rows r is an integer multiple of 20, the number of CRC-32 operations p = r / 20, d CRC =r / 20×32≤d CP This means performing a CRC-32 operation on every 20 rows of data (20 × 2056 = 41120 bits). When the number of rows r is not a multiple of 20, the number of CRC-32 operations is [number missing]. in The operation represents rounding down 'a', i.e., r0 = 20, r1 = r - 20 × (p - 1). CRC-32 is performed on each of the first 20 × (p - 1) rows of data (r0 = 20 bits, totaling q × r0 = 41120 bits), and once on the last r1 rows (q × r1 bits). Consider d. PAD =d CP -d CRC Based on Table 1 and the first constraint, Table 2 gives the corresponding {r, m, d}. CP d PADThe parameters are} and}. It should be noted that the last column of Table 2 also gives the specific values ​​of parameter r1 when the row number r is not a multiple of 20. For row numbers r that are multiples of 20, such as r = 1080 in row 32 of Table 2, the corresponding parameter r1 is represented by a forward slash in the table, indicating that the parameter r1 does not exist.

[0344] Table 2 also gives {r, m, d} CP d PAD Under the parameter combination of , p}, the specific value of v / 16 = (m-1504) / 16 is as follows. It should be noted that v = m-1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that in some specific embodiments, v = m-1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0345] It should be noted that in some specific applications, the first bit set is processed through PCS, interleaving, and encoding to obtain the second bit set. The ratio of the encoded input bit length to the encoded output bit length in the encoding operation is 3552:4096 = 111:128, which is the input-output rate ratio of the interleaving and encoding modules shown in Figure 4, which is 111:128. The bit ratio of the first bit set to the second bit set is m:4096 = f1:f2, where the greatest common divisor of integers f1 and f2 is 1. Typically, smaller values ​​for f1 and f2 result in simpler overall hardware implementation, lower complexity, and lower power consumption. Therefore, considering the second constraint mentioned above, i.e., m is an integer multiple of 32, m:4096 = f:128, where the integer f = m / 32, which is the input-output rate ratio of the overall processing module for PCS processing, interleaving, and encoding shown in Figure 4, which is f:128. Combining Table 1 and the second constraint, Table 3 gives the corresponding {r, m, d}. CP The combination of parameters f.

[0346] It should be noted that in some specific applications, both the first and second constraints are considered. In this case, referring to Table 1 and the first and second constraints, the corresponding {r, m, d}... CP d PAD The parameter combinations of {f, p} are shown in Table 4.

[0347] Table 4 also gives {r, m, d} CP d PAD The specific value of v / 16 under the parameter combination {f, p} is as follows. It should be noted that v = m - 1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that in some specific embodiments, v = m - 1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0348] Eleventhly, consider q = 2056 and N. CW =688128, W=1.

[0349] The number of bits in the third data is d. scr =q×r+d CP = 1344 × m. It should be understood that d represents the number of bits d added as CRC check bits or padding bits. CP The larger the number of redundant OH groups introduced... CP =d CP The larger / (q×r) is, the greater the corresponding {d}. in ,r,m,d CP The parameter combinations are shown in Table 5 above.

[0350] It should be noted that Table 5 also provides {r, m, d} CPUnder the parameter combination, the specific value of v / 16 = (m-1504) / 16 is determined. For v = m-1504, which is an integer multiple of 16, when n0 = 128, k0 = v / 16. This means the PCS processing uses 16 PCS sub-processes to achieve the desired effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain the output n0 = 128 bits. In some specific applications, the 16 PCS sub-processes are implemented using 16 lookup tables (LUTs). In other specific applications, the 16 PCS sub-processes are implemented using 16 trellis coding operations. It should be noted that in some specific embodiments, considering that v = m - 1504 is an integer multiple of 32, when n0 = 64, k0 = v / 32. This means that the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain the output n0 = 64 bits. In some specific applications, the 32 PCS sub-processes are implemented using 32 lookup tables (LUTs). In other specific applications, the 32 PCS sub-processes are implemented using 32 trellis coding operations.

[0351] It should be noted that in some specific applications, the first data processing includes CRC-32 operations. In this case, considering the first constraint, that is: when the number of rows r is an integer multiple of 20, the number of CRC-32 operations p = r / 20, d CRC =r / 20×32≤d CP This means performing a CRC-32 operation on every 20 rows of data (20 × 2056 = 41120 bits). When the number of rows r is not a multiple of 20, the number of CRC-32 operations is [number missing]. in The operation represents rounding down 'a', i.e., r0 = 20, r1 = r - 20 × (p - 1). CRC-32 is performed on each of the first 20 × (p - 1) rows of data (r0 = 20 bits, totaling q × r0 = 41120 bits), and once on the last r1 rows (q × r1 bits). Consider d. PAD =d CP -d CRC Based on Table 5 and the first constraint, Table 6 gives the corresponding {r, m, d}. CP d PADThe parameters are} and}. It should be noted that the last column of Table 6 also gives the specific values ​​of parameter r1 when the row number r is not a multiple of 20. For row numbers r that are multiples of 20, such as r = 2100 in row 25 of Table 6, the corresponding parameter r1 is represented by a forward slash in the table, indicating that the parameter r1 does not exist.

[0352] Table 6 also gives {r, m, d} CP d PAD Under the parameter combination of , p}, the specific value of v / 16 = (m-1504) / 16 is as follows. It should be noted that v = m-1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that in some specific embodiments, v = m-1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0353] It should be noted that in some specific applications, the first bit set is processed through PCS, interleaving, and encoding to obtain the second bit set. The ratio of the encoded input bit length to the encoded output bit length in the encoding operation is 3552:4096 = 111:128, which is the input-output rate ratio of the interleaving and encoding modules shown in Figure 4, which is 111:128. The bit ratio of the first bit set to the second bit set is m:4096 = f1:f2, where the greatest common divisor of integers f1 and f2 is 1. Typically, smaller values ​​for f1 and f2 result in simpler overall hardware implementation, lower complexity, and lower power consumption. Therefore, considering the second constraint mentioned above, i.e., m is an integer multiple of 32, m:4096 = f:128, where the integer f = m / 32, which is the input-output rate ratio of the overall processing module for PCS processing, interleaving, and encoding shown in Figure 4, which is f:128. Combining Table 5 and the second constraint, Table 7 gives the corresponding {r, m, d}. CP The combination of parameters f.

[0354] It should be noted that in some specific applications, both the first and second constraints are considered. In this case, referring to Table 5 and the first and second constraints, the corresponding {r, m, d}... CP d PAD The parameter combinations of {f, p} are shown in Table 8.

[0355] Table 8 also gives {r, m, d} CP d PAD The specific value of v / 16 under the parameter combination {f, p} is as follows. It should be noted that v = m - 1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that in some specific embodiments, v = m - 1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0356] In the twelfth aspect, consider q = 10280 and N. CW =344064, W=1.

[0357] The number of bits in the third data is d. scr =q×r+d CP = 672 × m. It should be understood that d represents the number of bits added as CRC check bits or padding bits. CP The larger the number of redundant OH groups introduced... CP =d CP The larger / (q×r) is, the greater the corresponding {d}. in ,r,m,d CP The parameter combinations are shown in Table 11 above.

[0358] It should be noted that in some specific applications, the first data processing includes CRC-32 operations. Consider d PAD =d CP -d CRC Combining Table 11 and the third constraint mentioned above, the corresponding {r, m, d} CP d PAD The parameter combinations for 'p' are shown in Table 12 above.

[0359] It should be noted that in some specific applications, a first bit set containing m bits undergoes a first processing step involving PCS processing, interleaving, and encoding to obtain a second bit set containing 4096 bits, where the ratio of the encoded input bit length to the encoded output bit length in the encoding operation is 111:128. Combining Table 11 and the fourth constraint mentioned above, the corresponding {r, m, d}... CP The parameter combinations for f are shown in Table 13 above.

[0360] It should be noted that in some specific applications, the third and fourth constraints mentioned above are considered. In this case, referring to Table 11 and the third and fourth constraints mentioned above, the corresponding {r, m, d}... CP d PAD The parameter combinations of {f, p} are shown in Table 14 above.

[0361] Tables 11, 12, 13, and 14 also provide the specific values ​​of v / 16 = (m-1504) / 16 for specific parameter combinations. It should be noted that v = m-1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that in some specific embodiments, v = m-1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0362] Thirteenth aspect, considering q = 10280, N CW =688128, W=1.

[0363] The number of bits in the third data is d. scr =q×r+d CP = 1344 × m. It should be understood that d represents the number of bits d added as CRC check bits or padding bits. CP The larger the number of redundant OH groups introduced... CP =d CP The larger / (q×r) is, the greater the corresponding {d}. in ,r,m,d CP The parameter combinations are shown in Table 15 above.

[0364] It should be noted that in some specific applications, the first data processing includes CRC-32 operations. Consider d PAD =d CP -d CRC Combining Table 15 and the third constraint mentioned above, the corresponding {r, m, d} CP d PAD The parameter combinations for 'p' are shown in Table 16 above.

[0365] It should be noted that in some specific applications, a first bit set containing m bits undergoes PCS processing, interleaving, and encoding to obtain a second bit set containing 4096 bits, where the ratio of the encoded input bit length to the encoded output bit length in the encoding operation is 111:128. Combining Table 15 and the fourth constraint mentioned above, the corresponding {r, m, d}... CP The parameter combinations for f are shown in Table 17 above.

[0366] It should be noted that in some specific applications, the third and fourth constraints mentioned above are considered. In this case, referring to Table 15 and the third and fourth constraints mentioned above, the corresponding {r, m, d}... CP d PAD The parameter combinations of {f} and {p} are shown in Table 18 above.

[0367] Tables 15, 16, 17, and 18 also provide the specific values ​​of v / 16 = (m-1504) / 16 for specific parameter combinations. It should be noted that v = m-1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that in some specific embodiments, v = m-1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0368] Fourteenth aspect, considering q = 2056, N CW =1376256, W=1.

[0369] The number of bits in the third data is d. scr =q×r+d CP = 2688 × m. It should be understood that d represents the number of bits (d) added as CRC check bits or padding bits. CP The larger the number of redundant OH groups introduced... CP =d CP The larger / (q×r) is, the greater the corresponding {d}. in ,r,m,d CP The parameter combinations are shown in Table 19 above.

[0370] Table 19 also gives {r, m, d} CPUnder the parameter combination, the specific value of v / 16 = (m-1504) / 16 is as follows. It should be noted that v = m-1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that in some specific embodiments, v = m-1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0371] The fifteenth aspect considers q = 10280 and N. CW =1376256, W=1.

[0372] The number of bits in the third data is d. scr =q×r+d CP = 2688 × m. It should be understood that d represents the number of bits (d) added as CRC check bits or padding bits. CP The larger the number of redundant OH groups introduced... CP =d CP The larger / (q×r) is, the greater the corresponding {d}. in ,r,m,d CP The parameter combinations are shown in Table 20 above.

[0373] Table 20 also gives {r, m, d} CP Under the parameter combination, the specific value of v / 16 = (m-1504) / 16 is as follows. It should be noted that v = m-1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that in some specific embodiments, v = m-1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0374] The sixteenth aspect considers q = 5140 and N. CW =344064, W=1.

[0375] The number of bits in the third data is d. scr =q×r+d CP = 672 × m. It should be understood that d represents the number of bits added as CRC check bits or padding bits. CP The larger the number of redundant OH groups introduced... CP =d CP The larger / (q×r) is, the greater the corresponding {d}. in ,r,m,d CP The parameter combinations are shown in Table 21 above.

[0376] Table 21 also gives {r, m, d} CP Under the parameter combination, the specific value of v / 16 = (m-1504) / 16 is as follows. It should be noted that v = m-1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that in some specific embodiments, v = m-1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0377] Seventeenth aspect, considering q = 5140, N CW =688128, W=1.

[0378] The number of bits in the third data is d. scr =q×r+d CP = 1344 × m. It should be understood that d represents the number of bits d added as CRC check bits or padding bits. CP The larger the number of redundant OH groups introduced... CP =d CP The larger / (q×r) is, the greater the corresponding {d}. in ,r,m,d CP The parameter combinations are shown in Table 22 above.

[0379] Table 22 also gives {r, m, d} CPUnder the parameter combination, the specific value of v / 16 = (m-1504) / 16 is as follows. It should be noted that v = m-1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that in some specific embodiments, v = m-1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0380] Eighteenth aspect, considering q = 5140, N CW =1376256, W=1.

[0381] The number of bits in the third data is d. scr =q×r+d CP = 2688 × m. It should be understood that d represents the number of bits (d) added as CRC check bits or padding bits. CP The larger the number of redundant OH groups introduced... CP =d CP The larger / (q×r) is, the greater the corresponding {d}. in ,r,m,d CP The parameter combinations are shown in Table 23 above.

[0382] Table 23 also gives {r, m, d} CP Under the parameter combination, the specific value of v / 16 = (m-1504) / 16 is as follows. It should be noted that v = m-1504 is an integer multiple of 16. When n0 = 128, k0 = v / 16, meaning the PCS processing uses 16 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 16 bits to obtain an output n0 = 128 bits. It should also be noted that in some specific embodiments, v = m-1504 is considered to be an integer multiple of 32. When n0 = 64, k0 = v / 32, meaning the PCS processing uses 32 PCS sub-processes to achieve the PCS processing effect. Each PCS sub-process processes the input k0 = v / 32 bits to obtain an output n0 = 64 bits.

[0383] Example 15:

[0384] Consider q = 2056, N CW=344064 and the input data of the first data processing (i.e. the first data) is FlexO-16e or 1.6TZR frame data, with a nominal bit rate of B0≈1609.959013238Gbit / s.

[0385] The corresponding {d in ,r,m,d CP v / 16, B1, B 2-28 B s-28 B 2-56 B s-56 The parameter combinations are shown in Table 9 above. It can be seen that the parameter combinations given in this embodiment, considering that the input data for the first data processing (i.e., the first data) is FlexO-16e or 1600GZR frame data, all correspond to baud rates less than 300GBaud. It is understood that the proposed data processing scheme can be well applied to future 1.6T data centers and metropolitan area network scenarios. Moreover, it includes a total of d in The first data of q×r bits, after the first data processing and the second data processing, is exactly one DSP frame (also known as a superframe or multiple frames), which makes the proposed data processing method have lower implementation complexity and lower power consumption.

[0386] Based on Table 9, consider the first and second constraints. Taking some parameter combinations in Table 9 as examples, such as the parameter combination in row 11, i.e., {d} in =2341784, r=1139, m=3488, d CP =2152, v / 16=124, B1=1892.33(Gbit / s), B 2-28 =1959.91 (Gbit / s), B s-28 =244.99 (GBaud), B 2-56 =1926.12 (Gbit / s), B s-56 =240.77 (GBaud)}, at this time d PAD =328, p=57, r1=19. It should be noted that in practical optical transmission applications, the channel spacing C... grid GHz, its value C grid (in gigabytes) is smaller than the baud rate value (in gigabytes), C grid Typically, the value is a multiple of 12.5, and a guard band of approximately 10% is considered. In this case, the baud rate corresponding to the parameter combination in line 11 is B. s-28 =244.99 GBaud and B s-56=240.77 GBaud, and in the corresponding specific optical communication network transmission, the channel spacing that can be used is 275 GHz.

[0387] Example 16:

[0388] Consider q = 10280, N CW =344064 and the input data for the first data processing (i.e., the first data) is FlexO-16e or 1.6TZR frame data, with a nominal bit rate of B0≈1609.959013238Gbit / s.

[0389] Considering the parameter combinations in Table 11, the corresponding baud rate B s-28 and B s-56 All are less than 300 GBaud. Understandably, the proposed data processing scheme can be well applied to future 1.6T data centers and metropolitan area network scenarios. Furthermore, it contains a total of d in The first data of q×r bits, after the first data processing and the second data processing, is exactly one DSP frame (also known as a superframe or multiple frames), which makes the proposed data processing method have lower implementation complexity and lower power consumption.

[0390] Based on Table 11, consider the third and fourth constraints. Taking some parameter combinations in Table 11 as examples, for instance, the parameter combination in row 18, namely {d} in =2189640, r=213, m=3264, d CP =3768, v / 16=110}, at this time, B1=2023.82 (Gbit / s), B 2-28 =2096.10 (Gbit / s), B s-28 =262.01 (GBaud), B 2-56 =2059.96 (Gbit / s), B s-56 =257.49 (GBaud), d PAD =2040, p=54, r1=1. It should be noted that in practical optical transmission applications, the channel spacing C... grid GHz, its value C grid (in gigabytes) is smaller than the baud rate value (in gigabytes), C grid Typically, the value is a multiple of 12.5, and a guard band of approximately 10% is considered. In this case, the baud rate corresponding to the parameter combination in line 16 is B. s-28 =262.01 GBaud and B s-56=257.49 GBaud. In specific optical communication network transmission, the channel spacing that can be used is 300 GHz or 287.5 GHz.

[0391] Example 17:

[0392] Consider q = 5140, N CW =344064 and the input data for the first data processing (i.e., the first data) is FlexO-16e or 1.6TZR frame data, with a nominal bit rate of B0≈1609.959013238Gbit / s.

[0393] Considering the parameter combinations in Table 21, the corresponding baud rate B s-28 and B s-56 All are less than 300 GBaud. Understandably, the proposed data processing scheme can be well applied to future 1.6T data centers and metropolitan area network scenarios. Furthermore, it contains a total of d in The first data of q×r bits, after the first data processing and the second data processing, is exactly one DSP frame (also known as a superframe or multiple frames), which makes the proposed data processing method have lower implementation complexity and lower power consumption.

[0394] Based on Table 21, consider the fifth and sixth constraints. Taking some parameter combinations in Table 21 as examples, such as the parameter combination in row 19, i.e., {d} in =2277020, r=443, m=3392, d CP =2404, v / 16=118}, at this time, B1=1946.15 (Gbit / s), B 2-28 =2015.66 (Gbit / s), B s-28 =251.96 (GBaud), B 2-56 =1980.91 (Gbit / s), B s-56 =247.61 (GBaud), d PAD =612, p=56, r1=3. It should be noted that in practical optical transmission applications, the channel spacing C... grid GHz, its value C grid (in gigabytes) is smaller than the baud rate value (in gigabytes), C grid Typically, the value is a multiple of 12.5, and a guardband of approximately 10% is considered. In this case, the baud rate corresponding to the parameter combination in line 19 is B. s-28 =251.96 GBaud and B s-56=247.61 GBaud, and in the corresponding specific optical communication network transmission, the channel spacing that can be used is 287.5 GHz.

[0395] Example 18:

[0396] Consider q = 2056, N CW =688128 and the input data of the first data processing (i.e. the first data) is FlexO-16e or 1.6TZR frame data, with a nominal bit rate of B0≈1609.959013238Gbit / s.

[0397] The corresponding {d in ,r,m,d CP v / 16, B1, B 2-28 B s-28 B 2-56 B s-56 The parameter combinations are shown in Table 10 above. It can be seen that the parameter combinations given in this embodiment, considering that the input data for the first data processing (i.e., the first data) is FlexO-16e or 1600GZR frame data, all correspond to baud rates less than 300GBaud. It is understood that the proposed data processing scheme can be well applied to future 1.6T data centers and metropolitan area network scenarios. Moreover, it includes a total of d in The first data of q×r bits, after the first data processing and the second data processing, is exactly one DSP frame (also known as a superframe or multiple frames), which makes the proposed data processing method have lower implementation complexity and lower power consumption.

[0398] Based on Table 10, consider the first and second constraints. Taking some parameter combinations in Table 10 as examples, such as the parameter combination in row 24, i.e., {d} in =4597216, r=2236, m=3424, d CP =4640, v / 16=120, B1=1927.88(Gbit / s), B 2-28 =1996.73 (Gbit / s), B s-28 =249.59 (GBaud), B 2-56 =1962.30 (Gbit / s), B s-56 =245.29 (GBaud)}, at this time d PAD =1056, p=112, r1=16. It should be noted that in practical optical transmission applications, the channel spacing C... grid GHz, its value C grid (in gigabytes) is smaller than the baud rate value (in gigabytes), C gridTypically, the value is a multiple of 12.5, and a guard band of approximately 10% is considered. In this case, the baud rate corresponding to the parameter combination in line 24 is B. s-28 =249.59 GBaud and B s-56 =245.29 GBaud. In specific optical communication network transmission, the channel spacing that can be used is 287.5 GHz or 275 GHz.

[0399] Example 19:

[0400] Consider q = 2056, N CW The input data of 1376256 (i.e., the first data) is FlexO-16e or 1.6T ZR frame data, with a nominal bit rate of B0≈1609.959013238Gbit / s.

[0401] Considering the parameter combinations in Table 19, the corresponding baud rate B s-28 and B s-56 All are less than 300 GBaud. Understandably, the proposed data processing scheme can be well applied to future 1.6T data centers and metropolitan area network scenarios. Furthermore, it contains a total of d in The first data of q×r bits, after the first data processing and the second data processing, is exactly one DSP frame (also known as a superframe or multiple frames), which makes the proposed data processing method have lower implementation complexity and lower power consumption.

[0402] Based on Table 19, consider the first and second constraints. Taking some parameter combinations from Table 19 as examples, such as the parameter combination in row 30, i.e., {d} in =928078, m=4514, d CP =3456, v / 16=122}, at this time, B1=1909.94 (Gbit / s), B 2-28 =1978.15 (Gbit / s), B s-28 =247.27 (GBaud), B 2-56 =1944.04 (Gbit / s), B s-56 =243.01 (GBaud), d PAD =1712, p=226, r1=14. It should be noted that in practical optical transmission applications, the channel spacing C... grid GHz, its value C grid (in gigabytes) is smaller than the baud rate value (in gigabytes), C gridTypically, the value is a multiple of 12.5, and a guardband of approximately 10% is considered. In this case, the baud rate corresponding to the parameter combination in line 30 is B. s-28 =247.27 GBaud and B s-56 =243.01 GBaud, and in the corresponding specific optical communication network transmission, the channel spacing that can be used is 275 GHz.

[0403] Example 20:

[0404] Consider q = 2056, N CW The input data of 344064 (i.e., the first data) is FlexO-12e frame data, and its nominal bit rate is B0≈1207.47Gbit / s.

[0405] Considering the parameter combinations in Table 1, the corresponding baud rate B s-28 and B s-56 All are less than 260 GBaud. Understandably, the proposed data processing scheme can be well applied to future 1.2T data centers and metropolitan area network scenarios. Furthermore, it contains a total of d in The first data of q×r bits, after the first data processing and the second data processing, is exactly one DSP frame (also known as a superframe or multiple frames), which makes the proposed data processing method have lower implementation complexity and lower power consumption.

[0406] Based on Tables 1 and 24, consider the first and second constraints. Taking some parameter combinations from Tables 1 and 24 as examples, for instance, the parameter combination in row 23 of Table 1, namely {d... in =2298608, r=1118, m=3424, d CP =2320, v / 16=120}, at this time, B1=1445.91 (Gbit / s), B 2-28 =1497.55 (Gbit / s), B s-28 =187.19 (GBaud), B 2-56 =1471.73 (Gbit / s), B s-56 =183.97 (GBaud), d PAD =528, p=56, r1=18. It should be noted that in practical optical transmission applications, the channel spacing C... grid GHz, its value C grid (in gigabytes) is smaller than the baud rate value (in gigabytes), C grid Typically, the value is a multiple of 12.5, and a guardband of approximately 10% is considered. In this case, the baud rate corresponding to the parameter combination in row 23 of Table 1 is B.s-28 =187.19 GBaud and B s-56 =183.97 GBaud, and in the corresponding specific optical communication network transmission, the channel spacing that can be used is 212.5 GHz.

[0407] Figure 13 is a schematic diagram of a data processing device according to an embodiment of this application. As shown in Figure 13, the data processing device includes a first processing unit 101 and a second processing unit 102. The first processing unit 101 is used to perform the "first data processing" operation in the above embodiment, and the second processing unit 102 is used to perform the "second data processing" operation in the above embodiment.

[0408] It should be understood that the data processing apparatus provided in this application can also be implemented in other ways. For example, the unit division in the above apparatus is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system. In addition, the functional units in the various embodiments of this application may be integrated into one processing unit, or they may be independent physical units, or two or more functional units may be integrated into one processing unit. The integrated units described above can be implemented in hardware or as software functional units.

[0409] Figure 14 is a schematic diagram of an optical module structure according to an embodiment of this application. As shown in Figure 14, the optical module includes a processor 201 and an interface 202. The interface 202 can be a transceiver or an input / output interface. The interface 202 is used to receive signals from other devices and transmit them to the processor 201 or to send signals from the processor 201 to other devices. Optionally, the optical module may also include a memory 203, wherein the memory 203 is used to store program instructions and data. Specifically, the processor 201 is used to execute the operations of "first data processing" and "second data processing" in the above embodiments. For example, the processor 201 includes the first processing unit 101 and the second processing unit 102 shown in Figure 13. As an example, the processor 201 executes the operations of "first data processing" and "second data processing" in the above embodiments to obtain W dual-polarization symbol streams and sends the W dual-polarization symbol streams through the interface 202. In this example, the interface 202 may specifically refer to an electrical interface. As another example, processor 201 performs the "first data processing" and "second data processing" operations in the above embodiments to obtain W dual-polarization symbol streams. The modulator in the optical module performs signal processing such as electro-optic conversion based on the W dual-polarization symbol streams to obtain optical signals, and then sends the optical signals through interface 202. In this example, interface 202 can specifically refer to an optical interface.

[0410] Typically, an optical module consists of optoelectronic devices, a processor, and an interface. The optoelectronic devices include transmitting and receiving devices. The transmitting end of the optical module converts electrical signals into optical signals and transmits them through optical fibers. The receiving end of the optical module receives the optical signals and converts them back into electrical signals.

[0411] It should be noted that the types of optical modules in this application embodiment include, but are not limited to, normal optical modules, near package optics (NPO) modules, and co-packaged optics (CPO) modules. Normal optical modules can perform functions including, but not limited to, digital signal processing (DSP) and clock data recovery (CDR). For example, a normal optical module converts analog signals to digital signals, performs DSP on the digital signals, and then converts them back to analog signals before sending them to the host device. Because DSP requires retiming, a normal optical module can also be called a retimed module. Normal optical modules are connected to the host device via an attachment unit interface (AUI). NPO and CPO modules do not have pluggable physical packaging and are closer to the host device. NPO and CPO modules can also be called optical engines. NPO or CPO technology is a technology that "packages" the host device (or host chip) and the optical engine. When NPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called an NPO module. When CPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called a CPO module.

[0412] Figure 15 is a schematic diagram of a transmitting device according to an embodiment of this application. As shown in Figure 15, the transmitting device includes a host-side device 301 and an optical module 302. The host-side device 301 is used to send electrical signals to the optical module 302, and the optical module 302 converts the electrical signals into optical signals and transmits the optical signals through a channel. For example, the host-side device 301 may specifically be a switch, router, or server. This transmitting device can be a communication device including the host-side device 301 and the optical module 302. It should also be understood that the transmitting devices in this embodiment are named based on the data flow direction and do not limit the function of the device. For example, the transmitting device may also have a receiving function.

[0413] This application also provides an Optical Transport Network (OTN) device, which includes line-side equipment and client-side equipment. The client-side equipment may also be referred to as a tributary-side equipment in some scenarios. The line-side equipment includes a processor and an interface. In one possible scenario, the processor is used to perform the "first data processing" and "second data processing" operations described in the above embodiments. The interface can be a transceiver or an input / output interface, used to receive signals from other devices outside the line-side equipment and transmit them to the processor, or to send signals from the processor to other devices outside the line-side equipment.

[0414] This application also provides a chip. The chip integrates circuitry for implementing the functions of the processor 201 described above, and one or more interfaces. As an example, the chip integrates a memory. As another example, when the chip does not integrate a memory, it can be connected to an external memory via the interface. The chip can perform the method steps of any one or more of the foregoing embodiments. Alternatively, the chip can implement the actions performed by the data processing device in the foregoing embodiments based on program code stored in the memory.

[0415] As an example, the chip in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0416] This application also provides a computer-readable storage medium including a program or instructions that, when run on a computer, cause the method performed as described in the above method embodiments to be implemented.

[0417] It should be understood that the processor mentioned in the embodiments of this application can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc. When implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. The memory can exist independently and be connected to the processor, or the memory can be integrated with the processor.

[0418] As an example, the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0419] In embodiments of this application, the memory may be random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium may also be a component of the processor. The processor and storage medium may reside in an ASIC. Additionally, the ASIC may reside in a network device or a terminal device. Alternatively, the processor and storage medium may exist as discrete components in the network device or terminal device.

[0420] In the above embodiments, it can be implemented entirely or partially by software, hardware, firmware, or any combination thereof.

[0421] When implemented in hardware, the data processing method provided in this application embodiment may be implemented without reading software code or instructions. For example, it may be implemented by CPU, DSP, ASIC, FPGA, other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0422] When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, all or part of the processes or functions of the embodiments of this application are performed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a terminal device, or other programmable device. The computer program or instructions can be stored in or transmitted through a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a Digital Versatile Disc (DVD); or it can be a semiconductor medium, such as a solid-state disk (SSD).

[0423] Finally, it should be noted that the above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data processing method, characterized by, Comprising: acquiring first data, the first data including d in bits, d in being an integer greater than or equal to 1; performing a cyclic redundancy check (CRC) on the first data or inserting padding bits to obtain second data including d scr bits, the second data including d CRC CRC check bits or d PAD padding bits, d CRC and d PAD are integers greater than or equal to 0, d scr = d in + d CRC + d PAD ; scrambling the second data to obtain third data, the third data comprising d scr bits; performing first processing on the third data to obtain fourth data, the first processing comprising probability constellation shaping (PCS) processing, interleaving and encoding; performing second processing on the fourth data to obtain W first dual-polarization symbol streams, W being an integer greater than 1, the second processing comprising symbol mapping, polarization division and framing.

2. The method of claim 1, wherein, The performing first processing on the third data to obtain fourth data comprises: obtaining a first bit set in the third data, the first bit set comprising m bits, m being an integer greater than 1; performing probability constellation shaping (PCS) processing on a first bit subset in the first bit set to obtain a second bit subset; performing interleaving and encoding on the second bit subset and a third bit subset in the first bit set other than the first bit subset to obtain a second bit set, the fourth data comprising the second bit set.

3. The method of claim 2, wherein, The fourth data is processed by the second processing to obtain W frames, each of the W first dual-polarization symbol streams comprises one of the W frames, the symbol mapping adopts 16 quadrature amplitude modulation (16QAM) symbol mapping, the second bit set comprises 4096 bits, and every 8xN CW bits in the fourth data are processed by the second processing to obtain one frame, and N CW =172032.

4. The method of claim 3, wherein, 5. The method according to any one of claims 2 to 4, characterized in that, d in = q x r, d CP = d CRC + d PAD , q = 2056, W = 2, d in , r, m and d CP satisfy the following table:

6. The method according to any one of claims 2 to 4, characterized in that, d in = q x r, d CP = d CRC + d PAD , q = 2056, W = 4, d in , r, m and d CP satisfy the following table:

7. The method according to any one of claims 2 to 4, characterized in that, d in = q x r, d CP = d CRC + d PAD , q = 2056, W = 8, d in , r, m and d CP satisfy the following table:

8. The method according to any one of claims 5 to 7, characterized in that, The performing CRC on the first data comprises: If r is an integer multiple of 20, CRC-32 is performed on 20 x 2056 bits per 20 rows of the first data to add CRC check bits of length 32 bits, d CRC = r / 20 x 32; or, If r is not an integer multiple of 20, CRC-32 is performed on every 20 rows of the first data in the first 20 x (p - 1) rows to add CRC check bits of length 32 bits, and CRC-32 is performed on the last r1 rows of the first data to add CRC check bits of length 32 bits, wherein, r1＝r-20×(p-1)， denotes rounding a down.

9. The method according to any one of claims 2 to 4, characterized in that, d in = q x r, d CP = d CRC + d PAD , q = 10280, W = 2, d in , r, m and d CP satisfy the following table:

10. The method according to any one of claims 2 to 4, characterized in that, d in = q x r, d CP = d CRC + d PAD , q = 10280, W = 4, d in , r, m and d CP satisfy the following table:

11. The method according to any one of claims 2 to 4, characterized in that, d in = q x r, d CP = d CRC + d PAD , q = 10280, W = 8, d in , r, m and d CP satisfy the following table:

12. The method according to any one of claims 9 to 11, characterized in that, The performing CRC on the first data comprises: If r is an integer multiple of 4, CRC-32 is performed on every 4 rows of 4 x 10280 bits in the first data to add CRC check bits of length 32 bits, d CRC = r / 4 x 32; or, If r is not an integer multiple of 4, CRC-32 is performed on every 4 rows of the first data for a total of 4 x 10280 bits to add CRC check bits of length 32 bits, and CRC-32 is performed on the last r1 rows of the first data for a total of r1 x 10280 bits to add CRC check bits of length 32 bits, wherein, r1＝r-4×(p-1)， denotes rounding a down.

13. The method of any one of claims 2 to 4, wherein, d in = q x r, d CP = d CRC + d PAD , q = 5140, W = 2, d in , r, m and d CP satisfy the following table:

14. The method of any one of claims 2 to 4, wherein, d in = q x r, d CP = d CRC + d PAD , q = 5140, W = 4, d in , r, m and d CP satisfy the following table:

15. The method of any one of claims 2 to 4, wherein, d in = q x r, d CP = d CRC + d PAD , q = 5140, W = 8, d in , r, m and d CP satisfy the following table:

16. The method according to any one of claims 2 to 15, characterized in that, m is an integer multiple of 32.

17. The method according to any one of claims 2 to 16, characterized in that, The performing PCS processing on a first bit subset in the first bit set to obtain a second bit subset comprises: performing PCS processing on every k0 bits in the first bit subset to obtain n0 bits in the second bit subset, wherein the first bit subset comprises v = m - 1504 bits, v being an integer multiple of 16, k0 = v / 16, n0 = 128, and the second bit subset comprises 2048 bits.

18. The method of any one of claims 2 to 16, wherein, The performing PCS processing on a first bit subset in the first bit set to obtain a second bit subset comprises: performing PCS processing on every k0 bits in the first bit subset to obtain n0 bits in the second bit subset, wherein the first bit subset comprises v = m - 1504 bits, v being an integer multiple of 32, k0 = v / 32, n0 = 64, and the second bit subset comprises 2048 bits.

19. The method of any one of claims 1 to 18, wherein, The first data comprises r rows of q columns of bits, r and q each being an integer greater than 0.

20. The method of any one of claims 1 to 19, wherein, The fourth data comprises M first data streams, M being an integer greater than 0, and the performing second processing on the fourth data to obtain W first dual-polarization symbol streams comprises: performing symbol mapping, polarization division and framing on the M first data streams respectively to obtain the W first dual-polarization symbol streams, wherein W = M.

21. The method of any one of claims 1 to 19, wherein, The fourth data comprises M first data streams, M being an integer greater than 0, and the performing second processing on the fourth data to obtain W first dual-polarization symbol streams comprises: performing data distribution on the M first data streams to obtain W second data streams; performing symbol mapping, polarization division and framing on the W second data streams respectively to obtain the W first dual-polarization symbol streams.

22. The method of any one of claims 1 to 19, wherein, The fourth data comprises M first data streams, M being an integer greater than 0, and the performing second processing on the fourth data to obtain W first dual-polarization symbol streams comprises: performing symbol mapping and polarization division on the M first data streams respectively to obtain M second dual-polarization symbol streams; performing data distribution on the M second dual-polarization symbol streams to obtain W third dual-polarization symbol streams; respectively performing framing on the W third dual-polarization symbol streams to obtain the W first dual-polarization symbol streams.

23. The method of any one of claims 1 to 22, wherein, The W first dual-polarization symbol streams are respectively carried on W optical signals, and any two of the W optical signals have different wavelengths. Alternatively, the W first dual-polarization symbol streams are respectively transmitted through W optical fibers; or the W first dual-polarization symbol streams are respectively carried on W subcarriers, and the W subcarriers are multiplexed to obtain one optical signal to be transmitted.

24. A data processing apparatus, characterized by: Comprise: a first processing unit and a second processing unit; The first processing unit is configured to acquire first data, the first data including d in bits, d in being an integer greater than or equal to 1. performing a cyclic redundancy check (CRC) on the first data or inserting padding bits to obtain second data including d scr bits, the second data including d CRC CRC check bits or d PAD padding bits, d CRC and d PAD are integers greater than or equal to 0, d scr = d in + d CRC + d PAD ; scrambling the second data to obtain third data, the third data comprising d scr bits; The second processing unit is configured to perform first processing on the third data to obtain fourth data, and the first processing comprises probability constellation shaping (PCS) processing, interleaving, and encoding. performing second processing on the fourth data to obtain W first dual-polarization symbol streams, W being an integer greater than 1, and the second processing comprising symbol mapping, polarization division, and framing.

25. A chip, characterized by The chip is configured to perform the method of any one of claims 1-23.

26. An optical module characterized by comprising: The optical module comprises a processor and an interface, the processor is configured to perform the method of any one of claims 1-23, and the interface is configured to send signals.

27. A transmitting device, comprising: The sending device comprises a host-side device and an optical module as claimed in claim 26, the optical module is configured to convert electrical signals from the host-side device into optical signals, and send the optical signals.

28. A communication system, characterized by Comprise: The sending device and the receiving device as claimed in claim 27, the sending device is configured to send optical signals to the receiving device.

29. A data processing method, characterized by, Comprise: acquiring first data, the first data including d in bits, d in being an integer greater than or equal to 1; performing a cyclic redundancy check (CRC) on the first data or inserting padding bits to obtain second data including d scr bits, the second data including d CRC CRC check bits or d PAD padding bits, d CRC and d PAD are integers greater than or equal to 0, d scr = d in + d CRC + d PAD ; scrambling the second data to obtain third data, the third data comprising d scr bits; performing first processing on the third data to obtain fourth data, and the first processing comprises probability constellation shaping (PCS) processing, interleaving, and encoding. performing second processing on the fourth data to obtain W first dual-polarization symbol streams, W being an integer greater than 0, and the second processing comprising symbol mapping, polarization division, and framing. where d in = q x r, d CP = d CRC + d PAD , q = 2056, d in , r and d CP satisfy the following table:

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