Method for communication, device, storage medium, and program product

Abstract

Embodiments of the present application provide a method for communication, a device, a storage medium, and a program product. In the method, a decoding apparatus decodes a low density parity check (LDPC) code on the basis of a belief propagation (BP) algorithm to obtain an initial bit sequence that does not satisfy a parity-check equation set. In addition, the decoding apparatus performs multiple bit flipping operations on a predetermined bit range of the initial bit sequence to obtain a plurality of flipped bit sequences. In one bit flipping operation, at least one bit in the predetermined bit range is flipped. In addition, the decoding apparatus performs LDPC encoding on the plurality of flipped bit sequences to obtain a plurality of candidate bit sequences. Furthermore, the decoding apparatus determines, from among the plurality of candidate bit sequences, a target bit sequence meeting a predetermined condition as a decoding result of the LDPC code. In this way, a certain degree of randomness is introduced by performing bit flipping within the predetermined bit range, thereby resisting the influence of noise or interference, improving decoding performance, and reducing complexity.

Description

A method, apparatus, storage medium, and program product for communication.

[0001] This application claims priority to Chinese Patent Application No. 202411002658.6, filed on July 24, 2024, entitled “A method, apparatus, storage medium and program product for communication”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The embodiments of this application generally relate to the field of communications, and more specifically to a method, apparatus, computer-readable storage medium, and computer program product for communication. Background Technology

[0003] Mobile or wireless communication networks can be viewed as facilities that enable wireless communication between two or more communication devices or provide wireless access to data networks for communication devices. To achieve interconnection and interoperability between communication devices such as network devices and terminal devices, corresponding communication standards have been developed, such as those established by the 3rd Generation Partnership Project (3GPP). rd Standards developed by the Generation Partnership Project (3GPP) or the European Telecommunications Standards Institute (ETSI) are examples of such standards, including 5G (5G) standards. th Generation (5G) standards, future wireless communication standards, etc. Low-density parity check (LDPC) codes can be used in various communication scenarios. However, some aspects of LDPC codes still require further optimization. Summary of the Invention

[0004] The embodiments of this application provide a technical solution for communication, and particularly relate to a technical solution for LDPC decoding or encoding.

[0005] Firstly, a decoding method is provided. The execution entity of this method can be a decoding device or a chip applied within the decoding device. The following description uses a decoding device as the execution entity. Unless otherwise specified, "decoding device" in this application can refer to the decoding device itself, a component within the decoding device (e.g., a communication module, processor, circuit, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of the decoding device. The following description uses a decoding device as the execution entity. In this method, the decoding device decodes a low-density parity-check (LDPC) code based on the belief propagation (BP) algorithm to obtain an initial bit sequence that does not satisfy the parity-check equation set. Furthermore, the decoding device performs multiple bit-flipping operations on a predetermined bit range of the initial bit sequence to obtain multiple flipped bit sequences. In one bit-flipping operation, at least one bit in the predetermined bit range is flipped. Additionally, the decoding device performs LDPC encoding on the multiple flipped bit sequences to obtain multiple candidate bit sequences. Furthermore, the decoding device determines the target bit sequence that meets predetermined conditions from multiple candidate bit sequences, which serves as the decoding result of the LDPC code. The confidence propagation algorithm can include algorithms such as BP and Min-Sum. The initial bit sequence can be the bit sequence obtained after hard-decision of the variable node values ​​in BP decoding. Thus, by introducing a certain degree of randomness through bit flipping within a predetermined bit range, the effects of noise or interference are resisted, decoding performance is improved, and complexity is reduced.

[0006] In some implementations, the number of at least one bit flipped in a single bit-flipping operation is greater than or equal to 1 and less than or equal to a predetermined flip order. Thus, multiple bits can be flipped within the limits of decoding delay, improving decoding performance.

[0007] In some implementations, the predetermined flip order is determined by the decoding device or indicated at the physical layer. This improves decoding flexibility.

[0008] In some implementations, the decoding device performs multiple bit-flipping operations, including: The decoding device performs a first set of bit-flipping operations on a predetermined bit range to obtain a first set of flipped bit sequences. In the first set of bit-flipping operations, N distinct bits within the predetermined bit range are flipped. Furthermore, the decoding device performs a second set of bit-flipping operations on the predetermined bit range to obtain a second set of flipped bit sequences. In the second set of bit-flipping operations, N+1 distinct bits within the predetermined bit range are flipped. N is greater than or equal to 1 and less than a predetermined flip order. In this way, the number of flipped bits can be increased successively, resulting in more candidate bit sequences and improved decoding performance.

[0009] In some implementations, the decoding device performs the second set of bit-flipping operations by performing a second set of bit-flipping operations on a predetermined bit range, based on the determination that the candidate bit sequence corresponding to the first set of flipped bit sequences fails the cyclic redundancy check (CRC). This stops flipping higher bit numbers when the CRC check passes, thereby reducing computational complexity.

[0010] In some implementations, the decoding device determines the target bit sequence by: determining the target bit sequence from multiple candidate bit sequences based on an index associated with the set of channel probability information values ​​corresponding to the LDPC code. Thus, given that multiple candidate bit sequences satisfy the set of parity check equations, an optimal candidate can be selected to determine the target bit sequence, thereby improving decoding performance.

[0011] In some implementations, the index associated with the set of channel probability information values ​​corresponding to the LDPC code includes two unequal numbers of bits: (i) the candidate bit sequence, and (ii) the hard-decision bit sequence obtained by hard-decision analysis of the set of channel probability information values. Thus, selection from the candidate bit sequence determines the candidate target bit sequence, improving decoding performance.

[0012] In some implementations, the base matrix of the LDPC code includes an information column region, a core parity column region, and an extended parity column region, and the predetermined bit range includes: the bit range corresponding to the information column region of the base matrix; or the bit range corresponding to both the information column region and the core parity column region of the base matrix. This reduces the bit flipping range and lowers computational complexity.

[0013] In some implementations, the predetermined bit range includes the bit range corresponding to the information column region. The decoding device acquires multiple candidate bit sequences by: acquiring a core parity bit sequence based on the flipped information bit sequence from among multiple flipped bit sequences; furthermore, the decoding device performs a bit XOR operation on the flipped information bit sequence and the core parity bit sequence according to the order of the extended parity columns to acquire an extended parity bit sequence; and finally, the decoding device acquires a candidate bit sequence from among multiple candidate bit sequences based on the flipped information bit sequence, the core parity bit sequence, and the extended parity bit sequence. In this way, the flipped information bit sequence can be quickly recoded using LDPC to obtain candidate bit sequences, improving decoding speed.

[0014] In some implementations, the predetermined bit range includes the bit ranges corresponding to the information column region and the core parity column region. The decoding device acquires multiple candidate bit sequences by performing a bit XOR operation on the flipped information bit sequence and the core parity bit sequence from multiple flipped bit sequences, following the order of the extended parity columns, to obtain the extended parity bit sequence. Furthermore, the decoding device acquires a candidate bit sequence from multiple candidate bit sequences based on the flipped information bit sequence, the core parity bit sequence, and the extended parity bit sequence. In this way, the flipped information bits and the core parity bit sequence can be quickly recoded using LDPC to obtain the candidate bit sequence, improving the decoding speed.

[0015] In some implementations, the basis matrix of an LDPC code consists of an information column region and a parity column region, with the parity column region including a lower triangular matrix. This simplifies LDPC code design and reduces decoding computational complexity.

[0016] In some implementations, the check column region includes the identity matrix. This allows for fast computation using methods such as parallel computing, reducing decoding computational complexity and improving efficiency.

[0017] In some implementations, the predetermined bit range includes the bit range corresponding to the information column region of the base matrix. This reduces the range of bit flips, lowers the decoding computational complexity, and improves efficiency.

[0018] In some implementations, the decoding device obtains multiple candidate bit sequences by: XORing the flipped bit sequences from multiple flipped bit sequences according to the parity column order to obtain a parity bit sequence. Furthermore, the decoding device obtains candidate bit sequences based on the flipped bit sequences and the parity bit sequences. In this way, the flipped information bit sequences can be quickly recoded using LDPC to obtain candidate bit sequences, improving decoding speed.

[0019] In some implementations, the column weights of the information column region in the basis matrix are greater than those of the parity column region. This ensures that the information column portion has the highest reliability, and after the BP decoding iteration, only the information column needs to be flipped to achieve the effect of ordered statistic decoding (OSD), eliminating the need for Gaussian elimination and improving computational efficiency.

[0020] In some implementations, column weight includes average column weight, total column weight, maximum column weight, or minimum column weight. This allows for multiple ways to implement column weight, improving flexibility.

[0021] In some implementations, the minimum column weight of the information column region is greater than the maximum column weight of the check column region. This allows the column weight of any information column to be higher than the column weight of any check column, improving the fault tolerance of the decoding and increasing computational efficiency.

[0022] Secondly, an encoding method is provided. The execution subject of this method can be an encoding device or a chip applied within the encoding device. The following description uses an encoding device as the execution subject. Unless otherwise specified, "encoding device" in this application can refer to the encoding device itself, a component within the encoding device (e.g., a communication module, processor, circuit, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of the encoding device. The following description uses an encoding device as the execution subject. In this method, the encoding device performs LDPC encoding based on the base matrix of a low-density parity-check (LDPC) code. The base matrix consists of an information column region and a parity column region, and the parity column region includes a lower triangular matrix. This simplifies LDPC code design and reduces the computational complexity of encoding.

[0023] In some implementations, the check column region includes the identity matrix. This allows for fast computation using methods such as parallel computing, reducing the computational complexity of the encoding and improving efficiency.

[0024] In some implementations, the column weights of the information column region in the basis matrix are greater than those of the parity column region. This ensures that the information column portion has the highest reliability, and after the BP decoding iteration, only the information column needs to be flipped to achieve the effect of ordered statistic decoding (OSD), eliminating the need for Gaussian elimination and improving computational efficiency.

[0025] In some implementations, column weight includes average column weight, total column weight, maximum column weight, or minimum column weight. This allows for multiple ways to implement column weight, improving flexibility.

[0026] In some implementations, the minimum column weight of the information column region is greater than the maximum column weight of the check column region. This ensures that the column weight of all information columns is higher than that of the check column, improving the fault tolerance of the decoding process and increasing computational efficiency.

[0027] Thirdly, a decoding apparatus is provided. This decoding apparatus can be a decoding device or a chip applied within a decoding device. Unless otherwise specified, the term "decoding apparatus" in this application can refer to the decoding device itself, a component within the decoding device (e.g., a communication module, processor, circuit, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of the decoding device. The following description uses a decoding device as an example. The decoding apparatus includes an acquisition module for decoding a low-density parity-check (LDPC) code based on a belief propagation (BP) algorithm to acquire an initial bit sequence that does not satisfy the parity-check equation set. The decoding apparatus also includes an execution module for performing multiple bit-flipping operations on a predetermined bit range of the initial bit sequence to obtain multiple flipped bit sequences. In one bit-flipping operation, at least one bit in the predetermined bit range is flipped. The decoding apparatus also includes an encoding module for performing LDPC encoding on the multiple flipped bit sequences to obtain multiple candidate bit sequences. The decoding device also includes a determination module, used to determine a target bit sequence that meets predetermined conditions from multiple candidate bit sequences, as the decoding result of the LDPC code. Thus, by introducing a certain degree of randomness through bit flipping within a predetermined bit range, the device resists the effects of noise or interference, improves decoding performance, and reduces complexity.

[0028] Fourthly, an encoding device is provided. This encoding device can be an encoding apparatus or a chip applied within an encoding apparatus. Unless otherwise specified, the term "encoding device" in this application can refer to the encoding apparatus itself, a component within the encoding apparatus (e.g., a communication module, processor, circuit, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of a decoding apparatus. The following description uses an encoding apparatus as an example. The encoding device includes an encoding module for performing LDPC encoding based on the base matrix of a low-density parity-check (LDPC) code. The base matrix consists of an information column region and a parity column region, and the parity column region includes a lower triangular matrix. This simplifies LDPC code design and reduces the computational complexity of encoding.

[0029] Fifthly, a computer-readable storage medium is provided. The computer-readable storage medium stores instructions. When executed by a communication device, the instructions cause the communication device to perform the method of the first aspect.

[0030] In a sixth aspect, a computer-readable storage medium is provided. The computer-readable storage medium stores instructions. When executed by a communication device, the instructions cause the communication device to perform the method of the second aspect.

[0031] In a seventh aspect, a chip is provided. The chip includes processing circuitry. The processing circuitry is configured to perform the method of the first aspect.

[0032] Eighthly, a chip is provided. The chip includes processing circuitry. The processing circuitry is configured to perform the method of the second aspect. Attached Figure Description

[0033] Figure 1A illustrates a communication system that can be implemented according to an embodiment of this application.

[0034] Figure 1B illustrates another communication system that can be implemented in accordance with embodiments of this application.

[0035] Figure 2 shows a schematic diagram of a Tanner diagram in relation to an embodiment of this application.

[0036] Figure 3 shows a schematic diagram of a cyclic shift in relation to an embodiment of this application.

[0037] Figure 4 shows a schematic diagram of the LDPC code base matrix in relation to an embodiment of this application.

[0038] Figure 5 shows another schematic diagram of the LDPC code base matrix in relation to an embodiment of this application.

[0039] Figure 6 shows a flowchart of the decoding device in an embodiment of this application.

[0040] Figure 7 shows a schematic diagram of the two-block structure of the LDPC code in an embodiment of this application.

[0041] Figure 8 shows a flowchart of the encoding device in an embodiment of this application.

[0042] Figure 9 shows a schematic diagram of the decoding performance in an embodiment of this application.

[0043] Figure 10 shows a block diagram of the device in an embodiment of this application.

[0044] Figure 11 shows a schematic diagram of the structure of a device that can be used to implement a decoding device in an embodiment of this application.

[0045] Figure 12 shows a schematic diagram of the structure of a device that can be used to implement an encoding device in an embodiment of this application. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operating methods and functional descriptions in the method embodiments can also be applied to the device embodiments or system embodiments.

[0047] As mentioned above, low-density parity check (LDPC) codes can be used in various communication scenarios, but the decoding of LDPC codes needs to be optimized.

[0048] Embodiments of this application provide a technical solution for decoding, wherein the decoding device decodes a low-density parity-check (LDPC) code based on the belief propagation (BP) algorithm to obtain an initial bit sequence that does not satisfy the parity-check equation set. Furthermore, the decoding device obtains multiple candidate bit sequences by performing multiple bit-flipping operations on the initial bit sequence. In each bit-flipping operation, at least one bit of the initial bit sequence is flipped. Additionally, the decoding device determines a target bit sequence that satisfies predetermined conditions from the multiple candidate bit sequences, which is then used as the decoding result of the LDPC code. Thus, by introducing a certain degree of randomness through bit-flipping, the effects of noise or interference are resisted, thereby improving decoding performance.

[0049] Figure 1A illustrates a communication system that can be implemented according to an embodiment of this application.

[0050] In embodiment 100, the communication system includes a source 105, a source coding 110, an encoding device 120 (e.g., channel coding), a modulation 125, a demodulation 130, a decoding device 140 (e.g., channel decoding), a source recovery 145, and a sink 150. The encoding device 120 performs a channel coding operation, for example, LDPC coding. The decoding device 140 performs a channel decoding operation, for example, LDPC coding.

[0051] Figure 1B illustrates another communication system that can be implemented in accordance with embodiments of this application.

[0052] In embodiment 160, the communication system includes, for example, a network device 165 and terminal devices 170 and 175, such as a base station. The network device 165 and the terminal devices 170 and 175 communicate via uplinks 180 and 185, respectively. The terminal devices 170 and 175 can also communicate with each other via a side link 190. In embodiment 160, an encoding device 120 may be located in the network device 165 and the terminal devices 170 and 175 to perform transmit-side LDPC encoding on the uplinks 180 and 185 and the side link 190. A decoding device 140 may be located in the network device 165 and the terminal devices 170 and 175 to perform receive-side LDPC decoding on the uplinks 180 and 185 and the side link 190.

[0053] The wireless communication systems 100 and 160 in this application embodiment can be applied to the three major application scenarios of 5G mobile communication systems, such as eMBB, URLLC and eMTC, or communication system scenarios such as 5G advanced, 6G, and future communication networks.

[0054] It should be understood that the above wireless communication systems are applicable to both high-frequency scenarios (above 6G) and low-frequency scenarios (sub-6G), such as millimeter waves. Application scenarios for these wireless communication systems include, but are not limited to, existing communication systems such as fifth-generation systems (5G) and new radio (NR) communication systems, or future evolved public land mobile network (PLMN) systems.

[0055] The terminal devices 170 and 175 shown above can be user equipment (UE), terminals, access terminals, terminal units, terminal stations, mobile stations (MS), remote stations, remote terminals, mobile terminals, wireless communication equipment, terminal agents, or other terminal equipment. Terminal devices 170 and 175 can also be communication chips with communication modules, vehicles with communication functions, or in-vehicle equipment (such as in-vehicle communication devices or in-vehicle communication chips). These terminal devices 170 and 175 can have wireless transceiver capabilities, enabling them to communicate (e.g., wirelessly) with one or more network devices in one or more communication systems and receive network services provided by these network devices, including but not limited to the network device 165 shown in the diagram.

[0056] Among them, terminal devices 170 and 175 can be cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistant (PDA) devices, handheld devices with wireless communication capabilities, computing devices or other processing devices connected to wireless modems, in-vehicle devices, wearable devices, terminal devices in 5G networks, or terminal devices in future evolved PLMN networks, etc.

[0057] Specifically, the terminal devices 170 and 175 can be mobile phones, tablets, computers with wireless transceiver capabilities, virtual reality (VR) terminals, augmented reality (AR) terminals, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical care, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, etc.

[0058] Additionally, terminal devices 170 and 175 can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; terminal devices 170 and 175 can also be deployed on water (such as ships); terminal devices 170 and 175 can also be deployed in the air (such as airplanes, balloons, and satellites). Network device 165 can be an access network device (or access site). Access network device refers to equipment that provides network access functionality, such as radio access network (RAN) base stations, etc. For example, network device 165 of the access network device may specifically include a base station (BS), or include a base station and radio resource management equipment for controlling the base station, etc. For example, network device 165 of the access network device may also include relay stations (relay equipment), access points, and base stations in 5G networks or NR base stations, base stations in future PLMN networks, etc. Access network device (165) can be a wearable device or a vehicle-mounted device. For example, network device 165 of the access network device can also be a communication chip with a communication module.

[0059] For example, network equipment 165 in cellular system access network equipment includes, but is not limited to: base stations (gnodeB, gNB) in 5G, evolved node B (eNB) in long term evolution (LTE) systems, radio network controller (RNC), radio controller, base station controller (BSC) in cloud radio access network (CRAN) systems, home base station (e.g., home evolved nodeB, or home node B, HNB), baseband unit (BBU), transmitting and receiving point (TRP), transmitting point (TP), mobile switching center, and can also be evolved NB (eNB or eNodeB) in LTE, base station equipment in future 5G networks or access network equipment in future evolved PLMN networks, and can also be wearable devices or vehicle-mounted devices.

[0060] In some deployments, such as cellular system access network equipment 165, network devices may include centralized units (CUs) and distributed units (DUs). Network devices may also include active antenna units (AAUs). The CU implements some of the network device's functions, and the DU implements others. For example, the CU is responsible for handling non-real-time protocols and services, implementing radio resource control (RRC) and packet data convergence protocol (PDCP) layer functions. The DU is responsible for handling physical layer protocols and real-time services, implementing radio link control (RLC), media access control (MAC), and physical (PHY) layer functions. The AAU implements some physical layer processing functions, radio frequency processing, and active antenna-related functions. Since RRC layer information ultimately becomes PHY layer information, or is derived from PHY layer information, in this architecture, higher-layer signaling, such as RRC layer signaling, can also be considered as being sent by the DU, or by the DU+AAU. It is understood that network devices can be one or more of the following: CU nodes, DU nodes, and AAU nodes. Furthermore, a CU can be classified as a network device in the radio access network (RAN) or a network device in the core network (CN); this application does not limit this classification. Examples of network devices include, but are not limited to, NodeB (or NB), evolved NodeB (eNodeB or eNB), next-generation NodeB (gNB), Transmitter Receiver Point (TRP), Remote Radio Unit (RRU), Radio Head (RH), Remote Radio Head (RRH), IAB nodes, low-power nodes such as femtonodes, piconodes, reconfigurable smart surfaces (RIS), and network-controlled repeaters. For example, the network device 165 of a base station can include a Baseband Unit (BBU) and a Remote Radio Unit (RRU). The BBU and RRU can be placed in different locations; for example, the RRU can be deployed remotely to a high-traffic area, while the BBU is placed in the central equipment room. Alternatively, the BBU and RRU can be placed in the same equipment room. BBU and RRU can also be different components under the same rack.

[0061] Furthermore, network equipment 165, for example, in a cellular system access network device, can connect to a core network (CN) device. The core network device can provide core network services to access network equipment 165 and terminal devices 170 and 175. The core network device can correspond to different devices in different systems. For example, in 3G, the core network device can correspond to a Serving GPRS Support Node (SGSN) and / or a Gateway GPRS Support Node (GGSN). In 4G, the core network device can correspond to a Mobility Management Entity (MME) and / or a Serving Gateway (S-GW). In 5G, the core network device can correspond to the Access and Mobility Management Function (AMF), Session Management Function (SMF), or User Plane Function (UPF), etc.

[0062] Examples 100 and 160 can be used in various application scenarios, such as enhanced mobile broadband (eMBB), ultra-reliable low latency communications (URLLC), and enhanced machine-type communication (eMTC).

[0063] Low-density parity-check (LDPC) codes are a channel coding scheme that is very close to the Shannon limit. They have the characteristics of good performance and low complexity, and have been selected by 3GPP as the 5G data channel coding scheme.

[0064] LDPC codes are encoded using a generator matrix. LDPC codes have a quasi-cyclic (QC) structure, which avoids bad structures such as short cycles and improves the code distance by setting the translation amount of each block. Currently, the main decoding algorithms for LDPC codes are Min-Sum (MS) and Belief Propagation (BP) decoding algorithms. BP decoding theoretically has better performance, but it requires a larger information storage capacity (m...). c→vThe computational complexity of BP (Backpropagation) decoding makes it difficult to implement in hardware. Therefore, offset-MS (Offset-MS) and normalized-MS (Normalized-MS) decoding algorithms are currently used in practical communication systems. BP algorithms, such as Offset-MS and Normalized-MS, can be considered simplified versions of the backpropagation (BP) algorithm.

[0065] The QC-LDPC code used in practice is represented by a base matrix BG, where elements are either 0 or 1. The 1s in the base matrix BG are expanded into a cyclic shift matrix, and the 0s are expanded into a zero matrix of the corresponding size. After expansion, the parity check matrix is ​​obtained. The BG graph model of the QC-LDPC code is BG = (X, Y, F), where X corresponds to the variables in the BG graph, Y corresponds to the parity check equation, and F represents the edge relationships. The expansion factor is Z. c After QC expansion, we obtain the Tanner graph, which is a bipartite graph G = (V, C, E), where V is the variable node, C is the check node, and E is its edge relationship.

[0066] For example, in Embodiment 200 of Figure 2, the variable nodes are V1(235), ..., V12(290), and the verification nodes are C1(205), ..., C6(230). There is an edge connection 295 between C1(230) and V1(235). The number of variable nodes, verification nodes, and edge connections in Embodiment 200 are exemplary and do not constitute a limitation on this application. The number of variable nodes corresponds to the number of columns in the verification matrix N = |V| = Z. c |X|, the number of check nodes corresponds to the number of rows in the check matrix M = |C| = Z c The number of non-zero elements in the parity check matrix is ​​|E|=Z|F|.

[0067] BG can also be written in matrix form as H. BG Based on the basis matrix H BG And the lifting value Zc (lifting size) can be used to transform the basis matrix H BG It is expanded into a complete parity-check matrix for encoding or decoding. Zc can also be called the expansion factor, boost factor, expansion value, expansion coefficient, boost size, etc.

[0068] The lifting process is to transform matrix H BG The elements in the matrix are promoted to a Zc×Zc square matrix, where 0 is promoted to a Zc×Zc 0 matrix, and 1 is promoted to an identity matrix cyclically shifted P to the right. i,j The matrix, where P i,jThe shifting value (SV value) is the value corresponding to the i-th row and j-th column. The variable nodes, check nodes, and edge relationships of the improved complete check matrix can also be shown in Figure 2. The number of variable nodes, check nodes, and edge relationships are exemplary and do not constitute a limitation of this application.

[0069] Figure 3 shows a schematic diagram of cyclic shifting in relation to an embodiment of this application. The results of cyclically shifting a 4x4 identity matrix to the right 1, 2, and 3 times are shown in figures 305, 310, and 315, respectively.

[0070] The LDPC code base graphs for 5G are BG1 and BG2, which share a common matrix structure, as shown in Example 400 of Figure 4. In Example 400, part A corresponds to the high-bitrate information column region, and part B corresponds to the high-bitrate core check region. Part C is a zero matrix, part D is the incremental redundancy part of the matrix, corresponding to the low-bitrate matrix, and part E is the incremental redundancy region, which is an identity matrix structure. The base matrix takes values ​​of 0 and 1, where 0 represents an empty element and 1 represents an edge in the base graph, or an association between a check node and a variable node.

[0071] Related to the embodiments of this application, a flexible-rate QC-LDPC code can be used. The entire matrix is ​​designed according to the lowest code rate. When different code rates need to be supported, the upper left part of the matrix is ​​used, as shown in Figure 4. Regions A and B constitute the highest code rate matrix. In 5G, the number of columns in part A of BG1 is 22, the number of columns in part B is 4, and the number of punched columns is 2. The supported code rate is 22 / (22+4-2)=11 / 12≈0.917.

[0072] When lower bitrates are required, a row and a column are added to the matrix region to be used until the lowest bitrate is reached. As shown in Example 500 of Figure 5, based on the high bitrate region, a row and a column are added successively in the check region with a column weight of 1, and a row is added successively in the incremental redundancy region to obtain the lower bitrate LDPC code until the lowest bitrate is reached. For example, the dashed line 505 represents the truncated matrix region under different bitrates.

[0073] Related to the embodiments of this application, a belief propagation decoding algorithm or a minimum sum decoding algorithm is used. Let the log-likelihood ratio (LLR) value received by the decoding device 140 be y, and decoding is performed iteratively. In the l-th iteration, let the information transmitted from the variable node to the check node be... The information that the verification node passes to the variable node is It can make The variable nodes then transmit information in the following manner:

[0074] Where y v To receive the value corresponding to the variable node v in the LLR.

[0075] During BP decoding, the information passed from check node c to variable node v is:

[0076] In the minimum sum decoding algorithm, equation (2) can be simplified, and the approximate amplitude can be calculated in the following way.

[0077] After each iteration, all v-node information is summarized as follows: And the hard decision is represented by the symbol t. v .

[0078] When the number of iteration rounds reaches the upper limit, or t v Decoding terminates when all check equations in the set pass, and t is taken. v As a result of decoding.

[0079] The belief propagation decoding method has good performance and complexity advantages on long, low-density LDPC codes, but its efficiency is low on short codes, especially on short-cycle, dense matrices where performance is not optimized. The belief propagation algorithm is prone to getting trapped in a certain trap set and failing to decode correctly, thus exhibiting an error plane and making it difficult to adapt to ultra-high reliability communication.

[0080] Related to the embodiments of this application, GRAND bit-flipping decoding may involve a parity check matrix H and a received LLR value. The symbol w can be obtained by hard-checking the LLR value. GRAND decoding can employ the following process.

[0081] 1. Verify w. If the result of H*w is all 0, then the verification is passed and the decoding ends.

[0082] 2. If the verification fails, randomly flip one position of w (i.e., 0->1 or 1->0), and verify the flipped w1. If the verification passes, the decoding ends. Otherwise, flip another position of w and verify it until a flipped vector that passes the verification is found, or flip any position of w once.

[0083] 3. If the verification fails after flipping any position of w once, flip any two positions of w and then check if the verification passes.

[0084] 4. After trying all the combinations of flipping two positions, proceed to the combination of flipping 3, 4, 5, ... positions, and keep flipping until the result is verified to be correct.

[0085] Therefore, GRAND decoding is a decoding method that finds the codeword closest to the received symbol by continuously trying to flip 1, 2, 3, ... symbols and uses it as the decoding result.

[0086] The advantage of GRAND decoding is that it only requires a parity check matrix for decoding, can be used for any code, and can always find the codeword with the closest Hamming distance to the received symbol as the decoding result. For example, TBCC and TURBO codes in 4G, and Polar and LDPC codes in 5G, GRAND can quickly obtain decoding results for extremely high code rates or extremely short code lengths. However, when the code rate decreases slightly or the code length increases slightly, its average and maximum decoding complexity increase by the order of combinatorial numbers. Therefore, its application scope is limited and it is not suitable for current mainstream communication systems.

[0087] Figure 6 shows a flowchart of the decoding device in an embodiment of this application. In process 600, at 610, the decoding device 140 decodes the low-density parity-check (LDPC) code based on the belief propagation (BP) algorithm to obtain an initial bit sequence that does not satisfy the parity-check equation set. At 620, the decoding device 140 performs multiple bit-flipping operations on a predetermined bit range of the initial bit sequence to obtain multiple flipped bit sequences. In one bit-flipping operation, at least one bit in the predetermined bit range is flipped. At 630, the decoding device 140 performs LDPC encoding on the multiple flipped bit sequences to obtain multiple candidate bit sequences. At 640, the decoding device 140 determines the target bit sequence that satisfies the predetermined conditions from the multiple candidate bit sequences, which is taken as the decoding result of the LDPC code. The belief propagation algorithm may include algorithms such as BP and Min-Sum. The initial bit sequence may be a bit sequence obtained after hard decision of the variable node values ​​in BP decoding. In this way, by introducing a certain degree of randomness by performing bit flipping within a predetermined bit range, the influence of noise or interference is resisted, the decoding performance is improved, and the complexity is reduced.

[0088] As can be seen, the embodiments of this application can use a random noise guessing decoding method based on confidence propagation decoding. As an example, this method can employ the following steps or operations to specifically implement process 600.

[0089] In step 1, the channel LLR value y received by the decoding device 140 is decoded by BP (or Min-sum) to obtain the decoding result t. The code length of t can be N, where the information bits are the 1-k bits. If t cannot satisfy all the parity check equations in the parity check set, then t is set as the initial bit sequence, i.e., the current decoding result. The decoding device 140 records the number of bits x1 that are not equal to the symbol determined by hard checking between t and the channel LLR value, and executes the following process.

[0090] In step 2, the decoding device 140 flips the first bit of t within a predetermined bit range, and sets the flipped symbol to t′. The bits of t′ within the predetermined bit range are used for LDPC encoding to obtain all the codeword bits t″.

[0091] In some implementations, the decoding device 140 determines the target bit sequence in the following manner: Based on an index associated with the set of channel probability information values ​​corresponding to the LDPC code, the decoding device 140 determines the target bit sequence from multiple candidate bit sequences. The channel LLR value y received by the decoding device 140 corresponds to the set of channel probability information values ​​corresponding to the LDPC code. Thus, given that multiple candidate bit sequences satisfy the set of check equations, an optimal sequence can be selected from among them to determine the target bit sequence, thereby improving decoding performance.

[0092] In some implementations, the index associated with the set of channel probability information values ​​corresponding to the LDPC code includes two unequal numbers of bits: (i) the candidate bit sequence, and (ii) the hard-decision bit sequence obtained by hard-decision analysis of the set of channel probability information values. Thus, selection from the candidate bit sequence determines the candidate target bit sequence, improving decoding performance.

[0093] In step 3, the decoding device 140 records the number of bits x′1 that are not equal to the symbol determined by the hard judgment of the channel LLR value, and decides whether to update the decoding result t to t″ according to the judgment rule, while updating x1 to x′1.

[0094] In step 4, the decoding device 140 flips the 2nd, 3rd, 4th... bits of t within a predetermined bit range, and repeats steps 2 and 3.

[0095] In some implementations, the decoding device 140 performs multiple bit-flipping operations in the following manner: The decoding device 140 obtains a first set of flipped bit sequences by performing a first set of bit-flipping operations on a predetermined bit range. In the first set of bit-flipping operations, N distinct bits within the predetermined bit range are flipped. Furthermore, the decoding device 140 performs a second set of bit-flipping operations on the predetermined bit range to obtain a second set of flipped bit sequences. In the second set of bit-flipping operations, N+1 distinct bits within the predetermined bit range are flipped. N is greater than or equal to 1 and less than a predetermined flip order. In this way, the number of flipped bits can be increased successively, resulting in more candidate bit sequences and improved decoding performance.

[0096] In step 5, the decoding device 140 selects two bits of t within a predetermined bit range and flips them, and repeats steps 2 and 3, cycling through this step until the combination of the selected two bits is complete.

[0097] The decoding device 140 can perform the second set of bit-flipping operations in the following manner: Based on the determination that the candidate bit sequence corresponding to the first set of flipped bit sequences cannot pass the cyclic redundancy check (CRC), the decoding device 140 performs the second set of bit-flipping operations on a predetermined bit range. In this way, higher bit-number flips are stopped when the CRC check is passed, thereby reducing computational complexity.

[0098] In step 6, the decoding device 140 selects 3, 4, 5...0 bits of t within a predetermined bit range for flipping, and repeats steps 2 and 3, cycling through this process until the selected number of bits are combined. Here, 0 represents the maximum flip order, or a predetermined flip order. In this embodiment, the sequence obtained after each flip of the initial bit sequence t corresponds to the candidate bit sequence.

[0099] In this embodiment, in a single bit-flipping operation, the number of at least one bit flipped is greater than or equal to 1 and less than or equal to a predetermined flip order 0. Thus, multiple bits can be flipped within the limits of acceptable decoding latency, improving decoding performance. In this embodiment, the predetermined flip order 0 is determined by the decoding device 140 or indicated at the physical layer, for example, by the encoding device 120 at the physical layer. This improves decoding flexibility.

[0100] In step 7, the decoding result t currently retained by the decoding device 140 is taken as the final decoding result.

[0101] In the embodiments of this application, the complexity and error correction performance of the above-mentioned random flip noise decoding method depend on the maximum flip order O, which is determined by the BER (bit error rate) of the received symbol. Directly using the symbols of the channel LLR for flipping has high complexity and poor performance. However, after BP iteration, even if the correct codeword cannot be obtained, the BER can be significantly reduced. On this basis, random flipping can achieve high-order performance with a low maximum flip order.

[0102] Under the same constraint of a maximum flip order of O, the method of flipping bits within a predetermined bit range and then determining the total number of codeword bits is far more efficient than directly flipping to obtain the number of codewords. Furthermore, the method described above can encompass all the flip results of conventional GRAND techniques. Therefore, its performance can be consistent with or even exceed that of conventional solutions.

[0103] Those skilled in the art will understand that BP decoding can also be Min-Sum decoding, offset-Min-Sum, or scale-Min-Sum decoding methods, and this application does not limit it.

[0104] In the embodiments of this application, the predetermined bit range can be refined to optimize the decoding performance of LDPC codes.

[0105] In this embodiment, the base matrix of the LDPC code can be partitioned as shown in Figure 4. The details of each partition are described below. The LDPC base matrix 405 can be an X-row × Y-column matrix, comprising submatrix A, submatrix B, submatrix C (region C is an all-zero matrix), submatrix D, and submatrix E. Region E is a lower triangular matrix, containing only 1 elements at and below the diagonal, with all other positions containing 0 elements. Further, region E can be an identity matrix, meaning it contains only 1 elements at the diagonal and all other positions containing 0 elements. Submatrix A is the first to x1 rows and the first to y1 columns of the LDPC base matrix 405; submatrix B is the first to x1 rows and the y1+1 to y2 columns of the LDPC base matrix 405; submatrix C is the first to x1 rows and the y2+1 to Y columns of the LDPC base matrix 405; submatrix D is the first to x1 rows and the first to y2 columns of the LDPC base matrix 405; submatrix E is the first to x1 rows and the y2+1 to Y columns of the LDPC base matrix 405, where 1 ≤ x1 ≤ X, 1 ≤ y1 ≤ y2 ≤ Y, and x1, X, y1, y2, and Y are all integers.

[0106] In this embodiment of the application, for the base matrix 405, columns 1 to y1 are information columns, columns y1+1 to y2 are core verification columns, columns 1 to y2 are referred to as core columns, and columns y2+1 to Y are extended verification columns.

[0107] In this embodiment, the LDPC code's base matrix 405 includes an information column region, a core check column region, and an extended check column region. The predetermined bit range includes: the bit range corresponding to the information column region of the base matrix 405, or the bit range corresponding to both the information column region and the core check column region of the base matrix. This reduces the bit flipping range and lowers computational complexity.

[0108] In this embodiment, the predetermined bit range includes the bit range corresponding to the information column region and the core check column region. The decoding device 140 can obtain multiple candidate bit sequences in the following manner: Based on the flipped information bit sequence and the core check bit sequence among multiple flipped bit sequences, the decoding device 140 performs a bit XOR operation according to the order of the extended check columns to obtain the extended check bit sequence. Furthermore, the decoding device 140 obtains a candidate bit sequence among multiple candidate bit sequences based on the flipped information bit sequence, the core check bit sequence, and the extended check bit sequence. In this way, the flipped information bits and the core check bit sequence can be quickly recoded using LDPC to obtain the candidate bit sequence, improving the decoding speed.

[0109] Specifically, in this embodiment, the predetermined bit range is defined as the core column, i.e., column 1-y2 in Figure 4, which includes the information column and the core parity column. Bit flipping is only performed within this range, and the process of obtaining t″ from the flipped symbol bit t′ can be the process of determining the extended parity bit. Since the E region of the base matrix 405 is a lower triangular region, the extended parity bits can be determined according to the order of the corresponding bits in columns y2+1 to Y, thus completing the LDPC recoding process and obtaining the candidate bit sequence. The advantage of this implementation is that the process of obtaining the candidate codeword bit sequence based on the bits of the predetermined bit range is relatively simple, and can be achieved by performing a simple XOR operation according to the order of the extended parity bits, saving computation and improving computational efficiency. Furthermore, if the E region of the base matrix 405 is an identity matrix, the extended parity bit sequence can be obtained by parallel computation, further saving computation and improving computational efficiency.

[0110] In some implementations, the predetermined bit range includes the bit range corresponding to the information column region. The decoding device 140 can obtain multiple candidate bit sequences in the following manner: The decoding device 140 obtains a core parity bit sequence based on the flipped information bit sequence among multiple flipped bit sequences. Furthermore, the decoding device 140 performs a bit XOR operation on the flipped information bit sequence and the core parity bit sequence according to the order of the extended parity columns to obtain an extended parity bit sequence. Additionally, the decoding device 140 obtains a candidate bit sequence among multiple candidate bit sequences based on the flipped information bit sequence, the core parity bit sequence, and the extended parity bit sequence. In this way, the flipped information bit sequence can be quickly recoded using LDPC to obtain the candidate bit sequence, improving the decoding speed.

[0111] Specifically, in this embodiment, the predetermined bit range is defined as the information column, i.e., column 1-y1 in Figure 4. The decoding device 140 first obtains the core parity bits, corresponding to columns y1+1 to y2 of the base matrix 405; then, it determines the extended parity bits according to the order of the bits corresponding to columns y2+1 to Y, corresponding to columns y2+1 to Y of the base matrix 405. Thus, the LDPC recoding process is completed, and the candidate bit sequence is obtained. The advantage of this implementation is that it can further narrow the range of flipped bits, reducing complexity, while the process of obtaining all codeword bits from the information bits within the predetermined bit range slightly increases complexity.

[0112] In this embodiment, the block structure of the LDPC code is not the 5-block form shown in Figure 4, but a simpler 2-block form, as shown in Figure 7.

[0113] In this embodiment, the base matrix of the LDPC code consists of an information column region and a parity column region, and the parity column region includes a lower triangular matrix. This simplifies LDPC code design and reduces decoding computational complexity.

[0114] Specifically, in embodiment 700, the LDPC base matrix 705 is a matrix of T rows × Z columns. The matrix is ​​divided into two regions: region A1 is the region corresponding to all information columns, that is, all T rows and columns 1 to z1. Region B1 is the region corresponding to all check columns, that is, all T rows and columns z1+1 to Z, where region B1 is a lower triangular matrix.

[0115] In this embodiment, the predetermined bit range includes the bit range corresponding to the information column region of the base matrix 705. This reduces the range of bit flips, lowers the decoding computational complexity, and improves efficiency.

[0116] In this embodiment, the decoding device 140 can obtain multiple candidate bit sequences in the following manner: Based on the flipped bit sequence among the multiple flipped bit sequences, the decoding device 140 performs a bit XOR operation according to the order of the parity column to obtain a parity bit sequence. Furthermore, the decoding device 140 obtains candidate bit sequences based on the flipped bit sequence and the parity bit sequence. In this way, the flipped information bit sequence can be quickly recoded using LDPC to obtain candidate bit sequences, improving the decoding speed.

[0117] In this implementation, the predetermined bit range is defined as the information column, i.e., columns 1 to z1 of the base matrix 705. LDPC recoding is then performed according to the order of the bits corresponding to columns z1+1 to Z to determine the complete codeword bits. The advantage of this implementation is that it can further reduce the range of flipped bits, lowering complexity. Furthermore, due to the simplified encoding structure, the process of obtaining all codeword bits from the bits within the predetermined bit range does not add any additional complexity.

[0118] In this embodiment, the column weight of the information column region of the base matrix is ​​greater than the column weight of the parity column region. This ensures that the information column portion has the highest reliability. After BP decoding iteration, only flipping is needed in the information column to achieve the effect of ordered statistic decoding (OSD), eliminating the need for Gaussian elimination and improving computational efficiency.

[0119] In the embodiments of this application, column weight includes average column weight, total column weight, maximum column weight, or minimum column weight. Thus, column weight can be implemented in multiple ways, improving flexibility.

[0120] In this embodiment, the minimum column weight of the information column region is greater than the maximum column weight of the check column region. This ensures that the column weight of any information column is higher than that of any check column, improving the fault tolerance of the decoding process and increasing computational efficiency.

[0121] Specifically, in the base matrix 705, the column weight of region A1 is greater than that of region B1. This column weight can be the average column weight, the total column weight, the maximum column weight, the minimum column weight, or the minimum column weight of region A1 being greater than the maximum column weight of region B1. The advantage of this implementation is that it ensures that the information column is the most reliable column. After the BP decoding iteration, only the information column needs to be flipped to achieve the OSD effect, without the need for Gaussian elimination, which greatly improves hardware efficiency.

[0122] In this embodiment, the check column region includes an identity matrix. This allows for rapid computation using methods such as parallel computing, reducing decoding computational complexity and improving efficiency. Specifically, in the base matrix 705, region B1 is an identity matrix, allowing all codeword bits to be obtained in parallel from a preset range of bits, thus improving efficiency.

[0123] Corresponding to the 2-region basis matrix in Figure 7, the LDPC encoding side also adopts a corresponding encoding method.

[0124] Figure 8 shows a flowchart of the encoding device in an embodiment of this application. In process 800, at 810, the encoding device 120 performs LDPC encoding based on the base matrix of a low-density parity-check (LDPC) code. The base matrix consists of an information column region and a parity column region, and the parity column region includes a lower triangular matrix. This simplifies LDPC code design and reduces the computational complexity of encoding.

[0125] Figure 9 illustrates a schematic diagram of the decoding performance in an embodiment of this application. Specifically, embodiment 900 is a simulation of the LDPC decoding performance.

[0126] In Example 900, the horizontal axis represents the signal-to-noise ratio (SNR), and the vertical axis represents the block error ratio (BLER). The simulated code length is 128, the code rate is 1 / 2, the code distance is 22, and the maximum GRAND order can reach 10. Curve 905 represents the performance of 5th-order GRAND decoding (GRAND5), curve 910 represents the performance of 20-iteration BP decoding (BP), curve 915 represents the performance of 10th-order GRAND decoding (GRAND10), and curve 920 represents the performance of 20-iteration BP + 5th-order GRAND decoding (BP + GRAND 5). A comparison of the curves shows that the performance, from worst to best, is: GRAND5, BP, GRAND10, and BP + GRAND 5. Example 900 demonstrates that performing GRAND decoding on the results of BP can significantly improve the decoding performance of GRAND. Regarding computational complexity, the complexity of BP 20 iterations is 30,000 basic operations, the number of flips for GRAND 5 is 15,000, and the number of flips for GRAND 10 is 185,000. In reality, a single GRAND flip also includes verification complexity. Even without counting this complexity, the complexity of BP + GRAND 5 is far lower than that of GRAND 10 (approximately 1 / 4).

[0127] Figure 10 is a block diagram of a device 1000 that can be used to implement some embodiments of the present application. The encoding device 120 and the decoding device 140 can be implemented within the device 1000, for example, they can be part of the device 1000. The encoding device 120 and the decoding device 140 can be implemented as a single chip, or a combination of several chips, or as hardware circuits, or partially implemented as hardware circuits and partially implemented as software, firmware, or other forms; the present application does not limit this. In some embodiments, device 1000 may be a component of a communication network infrastructure, such as a base station (e.g., NodeB, evolved NodeB (eNodeB or eNB), next-generation NodeB (sometimes called next-generation NodeB, gNodeB or gNB), home subscriber server (HSS), gateway (GW), such as packet gateway (PGW) or serving gateway (SGW), or various other nodes or functions within a core network (CN) or Public Land Mobility Network (PLMN). In other embodiments, device 1000 may be a device connected to the network infrastructure via a wireless interface, such as a mobile phone, smartphone, or other such device that can be classified as user equipment (UE). In some embodiments, device 1000 may be a machine-type communication device. Communications (MTC) devices (also known as machine-to-machine (M2M) devices), or other devices that, although not providing direct service to users, can be classified as UEs. In some embodiments, device 1000 may be a roadside unit (RSU), a vehicle UE (V-UE), a pedestrian UE (P-UE), or an infrastructure UE (I-UE). In some scenarios, device 800 may also be referred to as a mobile device, a term intended to reflect a device connected to a mobile network, regardless of whether the device itself is designed for or capable of being mobile. A particular device may utilize all or only a subset of the components shown, and the level of integration may vary depending on the device. Furthermore, device 800 may contain multiple instances of components, such as multiple processors, memories, transmitters, receivers, etc.

[0128] Device 1000 typically includes a processor 1002, such as a central processing unit (CPU), and may further include a dedicated processor, such as a graphics processing unit (GPU) or other such processor, memory 1004, a network interface 1006, and a bus 1008 for connecting the components of device 1000. Optionally, device 1000 may also include components such as a mass storage device 1010, a video adapter 1012, and an I / O interface 1016 (shown in dashed lines).

[0129] Memory 1004 may include any type of non-transitory system memory readable by processor 1002, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), read-only memory (ROM), or combinations thereof. In one embodiment, memory 1004 may include more than one type of memory, such as ROM used at startup and DRAM used for program and data storage during program execution. Bus 808 may be one or more of a plurality of bus architectures of any type, including a memory bus or memory controller, a peripheral bus, or a video bus.

[0130] Device 1000 may also include one or more network interfaces 1006, which may include at least one of wired network interfaces and wireless network interfaces. As shown in FIG10, network interface 1006 may include a wired network interface for connecting to network 1022, and may also include a wireless access network interface 1020 for connecting to other devices via a wireless link. When device 1000 is a network infrastructure element, the wireless access network interface 1020 may be omitted for nodes or functions that are elements of a PLMN rather than elements at the wireless edge. When device 1000 is infrastructure at the wireless edge of a network, both wired and wireless network interfaces may be included. When device 1000 is a wirelessly connected device, such as a user equipment, the wireless access network interface 1020 may be present and may be supplemented by other wireless interfaces such as a WiFi network interface. Network interface 1006 allows device 1000 to communicate with remote entities such as those connected to network 1022.

[0131] Mass storage 1010 may include any type of non-transitory storage device configured to store data, programs, and other information and make the data, programs, and other information accessible via bus 808. Mass storage 1010 may include, for example, one or more of a solid-state drive, hard disk drive, disk drive, or optical disk drive. In some embodiments, mass storage 1010 may be located remotely from device 1000 and may be accessed using a network interface such as interface 1006. In the illustrated embodiment, mass storage 1010 is distinct from the memory 1004 that includes it, and mass storage 1010 typically performs storage tasks compatible with higher latency but typically provides low or no fluctuation. In some embodiments, mass storage 1010 may be integrated with heterogeneous memory 804.

[0132] Optional video adapter 1012 and I / O interface 1016 (shown in dashed lines) provide interfaces for coupling device 1000 to external input and output devices. Examples of input and output devices include a display 1014 coupled to video adapter 1012 and an I / O device 1018, such as a touchscreen, coupled to I / O interface 1016. Other devices may be coupled to device 1000 and may utilize additional or fewer interfaces. For example, a serial interface such as Universal Serial Bus (USB) (not shown) may be used to provide interfaces for external devices. Those skilled in the art will understand that in embodiments where device 1000 is part of a data center, I / O interface 1016 and video adapter 1012 may be virtualized and provided via network interface 1006.

[0133] Figure 11 is a schematic diagram of the structure of a device 1100 according to some embodiments of this application. In some examples, device 1100 can be used to implement the decoding device 140 in the embodiments of this application. As shown in Figure 11, device 1100 includes an acquisition module 1102, an execution module 1104, an encoding module 1106, and a determination module 1108. Device 1100 can be applied to the communication system shown in Figures 1 and 2, and can implement any decoding method provided in the foregoing embodiments. Optionally, the physical manifestation of device 1100 can be a communication device, such as a network device or a terminal device. Alternatively, device 1100 can be other devices capable of implementing the functions of a communication device, such as a processor or chip inside the communication device. Specifically, device 1100 can be a programmable chip, such as a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), an application-specific integrated circuit (ASIC), or a system on a chip (SOC).

[0134] In some embodiments, the acquisition module 1102 can be configured to decode a low-density parity-check (LDPC) code based on a belief propagation (BP) algorithm to obtain an initial bit sequence that does not satisfy the set of parity-check equations. The execution module 1104 performs multiple bit-flipping operations on a predetermined bit range of the initial bit sequence to obtain multiple flipped bit sequences. In each bit-flipping operation, at least one bit in the predetermined bit range is flipped. The encoding module 1106 performs LDPC encoding on the multiple flipped bit sequences to obtain multiple candidate bit sequences. The determination module 1108 determines the target bit sequence that satisfies predetermined conditions from the multiple candidate bit sequences, which is taken as the decoding result of the LDPC code.

[0135] In some other embodiments, apparatus 1100 may include various other units or modules that can be configured to perform the various operations or functions described with respect to the foregoing method embodiments. Specific details can be obtained by referring to the detailed description of the foregoing method embodiments, and will not be repeated here.

[0136] Figure 12 is a schematic diagram of the structure of a device 1200 according to some embodiments of this application. In some examples, device 1200 can be used to implement the encoding device 120 in the embodiments of this application. As shown in Figure 12, device 1200 includes an encoding module 1202. Device 1200 can be applied to the communication system shown in Figures 1 and 2, and can implement any encoding method provided in the foregoing embodiments. Optionally, the physical manifestation of device 1200 can be a communication device, such as a network device or a terminal device. Alternatively, device 1200 can be other devices capable of implementing the functions of a communication device, such as a processor or chip inside the communication device. Specifically, device 1200 can be a programmable chip, such as a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), an application-specific integrated circuit (ASIC), or a system on a chip (SOC).

[0137] In some embodiments, the encoding module 1202 can be configured to perform LDPC encoding based on a base matrix of a low-density parity-check (LDPC) code. The base matrix consists of an information column region and a parity column region, and the parity column region includes a lower triangular matrix.

[0138] In some other embodiments, the apparatus 1200 may include various other units or modules that can be configured to perform the various operations or functions described with respect to the foregoing method embodiments. Specific details can be obtained by referring to the detailed description of the foregoing method embodiments, and will not be repeated here.

[0139] It should be noted that the module division in the above embodiments of this application is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, exist as separate physical units, or be integrated into one unit by two or more units. The integrated units described above can be implemented in hardware or as software functional units.

[0140] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, or all or part of it, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0141] Based on the above embodiments, this application also provides a computer program that, when run on a computer, causes the computer to execute any of the methods provided in the above embodiments.

[0142] Based on the above embodiments, this application also provides a computer-readable storage medium storing a computer program. When the computer program is executed by a computer, it causes the computer to perform any of the methods provided in the above embodiments. The storage medium can be any available medium that can be accessed by a computer. By way of example, but not limited to, a computer-readable medium may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code having the form of instructions or data structures and that can be accessed by a computer.

[0143] Based on the above embodiments, this application also provides a chip for reading a computer program stored in a memory and implementing any of the methods provided in the above embodiments.

[0144] Based on the above embodiments, this application provides a chip system including a processor for supporting a computer device in implementing the functions involved in the communication devices in the above embodiments. In one possible design, the chip system further includes a memory for storing necessary programs and data of the computer device. This chip system may be composed of chips or may include chips and other discrete components.

[0145] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0146] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0147] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0148] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0149] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of protection of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method of decoding, comprising: decoding a low-density parity-check (LDPC) code based on a belief propagation (BP) algorithm to obtain an initial bit sequence that does not satisfy a set of check equations; performing a plurality of bit flipping operations on a predetermined bit range of the initial bit sequence to obtain a plurality of flipped bit sequences, wherein in one bit flipping operation, at least one bit in the predetermined bit range is flipped; performing LDPC encoding on the plurality of flipped bit sequences to obtain a plurality of candidate bit sequences; and determining a target bit sequence that satisfies a predetermined condition from the plurality of candidate bit sequences as a decoding result of the LDPC code. 2.The method of claim 1, wherein in one bit flipping operation, a number of the at least one bit that is flipped is greater than or equal to 1 and less than or equal to a predetermined flipping order. 3.The method of claim 2, wherein the predetermined flipping order is determined by a decoding device or indicated at a physical layer. 4.The method of any one of claims 1-3, wherein performing the plurality of bit flipping operations comprises: obtaining a first set of flipped bit sequences based on performing a first set of bit flipping operations on the predetermined bit range, wherein in the first set of bit flipping operations, different N bits in the predetermined bit range are flipped; and obtaining a second set of flipped bit sequences based on performing a second set of bit flipping operations on the predetermined bit range, wherein in the second set of bit flipping operations, different N+1 bits in the predetermined bit range are flipped, wherein N is greater than or equal to 1 and less than the predetermined flipping order. 5.The method of claim 4, wherein performing the second set of bit flipping operations comprises: performing the second set of bit flipping operations on the predetermined bit range based on determining that a candidate bit sequence corresponding to the first set of flipped bit sequences fails a cyclic redundancy check (CRC). 6.The method of any one of claims 1-5, wherein determining the target bit sequence comprises: determining the target bit sequence from the plurality of candidate bit sequences based on an indicator associated with a set of channel probability information values corresponding to the LDPC code. 7.The method of claim 6, wherein the indicator comprises a number of bits that are not equal between (i) a candidate bit sequence and (ii) a hard decision bit sequence obtained by performing hard decision on the set of channel probability information values. 8.The method of any one of claims 1-7, wherein a base matrix of the LDPC code comprises an information column region, a core check column region, and an extension check column region, and wherein the predetermined bit range comprises: a bit range corresponding to the information column region of the base matrix; or a bit range corresponding to the information column region and the core check column region of the base matrix. 9.The method of claim 8, wherein the predetermined bit range comprises the bit range corresponding to the information column region, and wherein obtaining the plurality of candidate bit sequences comprises: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ based on the flipped information bit sequence and the core check bit sequence, obtaining the candidate bit sequence. based on the flipped information bit sequence and the core check bit sequence, obtaining the candidate bit sequence. and based on the flipped information bit sequence, the core check bit sequence, and the extension check bit sequence, obtaining the candidate bit sequence of the plurality of candidate bit sequences.

10. The method of claim 8, wherein the predetermined bit range comprises a bit range corresponding to the information column region and the core check column region, and wherein obtaining the plurality of candidate bit sequences comprises: based on the flipped information bit sequence and the core check bit sequence, obtaining the candidate bit sequence. and based on the flipped information bit sequence, the core check bit sequence, and the extension check bit sequence, obtaining the candidate bit sequence of the plurality of candidate bit sequences.

11. The method of any one of claims 1-7, wherein a base matrix of the LDPC code is composed of an information column region and a check column region, and the check column region comprises a lower triangular matrix.

12. The method of claim 11, wherein the check column region comprises an identity matrix.

13. The method of claim 11 or 12, wherein the predetermined bit range comprises a bit range corresponding to the information column region of the base matrix.

14. The method of claim 13, wherein obtaining the plurality of candidate bit sequences comprises: based on the flipped information bit sequence and the core check bit sequence, obtaining the candidate bit sequence. and based on the flipped information bit sequence, the core check bit sequence, and the extension check bit sequence, obtaining the candidate bit sequence of the plurality of candidate bit sequences.

15. The method of any one of claims 11-14, wherein a column weight of the information column region of the base matrix is greater than a column weight of the check column region.

16. The method of claim 15, wherein the column weight comprises an average column weight, a total column weight, a maximum column weight, or a minimum column weight.

17. The method of claim 15, wherein a minimum column weight of the information column region is greater than a maximum column weight of the check column region.

18. A method of encoding, comprising: performing low-density parity-check (LDPC) encoding based on a base matrix of an LDPC code, wherein the base matrix is composed of an information column region and a check column region, and the check column region comprises a lower triangular matrix.

19. The method of claim 18, wherein the check column region comprises an identity matrix.

20. The method of any one of claims 18 or 19, wherein a column weight of the information column region of the base matrix is greater than a column weight of the check column region.

21. The method of claim 20, wherein the column weight comprises an average column weight, a total column weight, a maximum column weight, or a minimum column weight.

22. The method of claim 20, wherein a minimum column weight of the information column region is greater than a maximum column weight of the check column region.

23. An apparatus for decoding, comprising: an obtaining module configured to obtain an initial bit sequence that does not satisfy a set of check equations based on belief propagation (BP) algorithm for decoding a low-density parity-check (LDPC) code; an executing module configured to perform a plurality of bit flipping operations on a predetermined bit range of the initial bit sequence, wherein at least one bit in the predetermined bit range is flipped in one bit flipping operation, and obtain a plurality of flipped bit sequences; an encoding module configured to perform LDPC encoding on the plurality of flipped bit sequences, and obtain a plurality of candidate bit sequences; and a determining module configured to determine a target bit sequence that satisfies a predetermined condition from the plurality of candidate bit sequences as a decoding result of the LDPC code.

24. An apparatus for encoding, comprising: an encoding module configured to perform low-density parity-check (LDPC) encoding based on a base matrix of the LDPC code, wherein the base matrix is composed of an information column region and a check column region, and the check column region comprises a lower triangular matrix.

25. A computer-readable storage medium storing instructions that, when executed by a communication device, cause the communication device to perform the method of any one of claims 1-17.

26. A computer-readable storage medium storing instructions that, when executed by a communication device, cause the communication device to perform the method of any one of claims 18-22.

27. A chip comprising processing circuitry configured to perform the method of any one of claims 1-17.

28. A chip comprising processing circuitry configured to perform the method of any one of claims 18-22. ​

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