Message sending buffer device and chip

Abstract

The present application relates to a message sending buffer device, comprising: a sending instruction interface (1), configured to receive and parse a message sending instruction to obtain instruction information; a sending state control module (2), configured to determine, on the basis of the instruction information, the number of clock cycles required for reading a target message and a data reading direction, wherein the data reading direction is one of sequential reading, reverse-order reading, or reverse-order reading followed by sequential reading; a read address generation module (3), configured to generate a read address of a current clock cycle on the basis of the instruction information, the number of clock cycles required for reading the target message, and the data reading direction; a memory (4), configured to store message data and output read data of the current clock cycle on the basis of the read address of the current clock cycle; a readout data processing module (5), configured to process the read data of the current clock cycle outputted by the memory (4) and then output same; and a bus interface (6), configured to send the data outputted by the readout data processing module (5) to a peer device.

Description

A message transmission buffer device and chip

[0001] Related applications

[0002] This application claims priority to Chinese patent application filed on July 25, 2024, with application number 2024110078133, entitled "A Message Transmission Buffer Device and Chip", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of integrated circuit technology, specifically to a message transmission buffer device and chip. Background Technology

[0004] As an intermediate node in network packet processing, the Data Processing Unit (DPU) performs operations such as decapsulation, encapsulation, header addition, header removal, and field update on network packets. The network packet processing process involves assembling new packet headers, and the encapsulation methods for network packets of different service data streams differ during the assembly of new packet headers.

[0005] Some business data streams encapsulate network packets from the inside out. For example, starting with the packet payload data, the outer packet header is added step by step. This approach is suitable for scenarios where the payload data needs to be processed first, and then the packet header for network transmission is added step by step.

[0006] Some business data flow network packets are encapsulated from the outside in. For example, the outermost packet header is built first, and then the information of the next layer is added step by step. This method is usually used in scenarios where the transmission details of the packet in the network need to be determined first, and then the payload data is processed.

[0007] Some business data flow network packets are encapsulated first from the inside out, and then from the outside in. This method combines the two methods mentioned above. In the first stage, the packet is encapsulated from the inside out, and in the second stage, based on the packet portion encapsulated in the first stage, it is further encapsulated from the outside in to obtain the final network packet. The encapsulation and transmission of network packets are performed in the packet transmission buffer (out-buffer) of the DPU. After the network packet is encapsulated, it is temporarily stored in the out-buffer's memory to await transmission.

[0008] Currently, the design of message sending buffer devices for DPUs mainly involves designing message sending buffer devices with different functions based on different service data flows. There is no message sending buffer device that can be simultaneously applied to the encapsulation and sending of network messages with different message encapsulation methods. Summary of the Invention

[0009] According to various embodiments of this application, a message transmission buffer device (out-buffer) and a chip are provided.

[0010] To achieve the above objectives, according to a first aspect of this application, a message transmission buffer (out-buffer) is provided, comprising:

[0011] The command sending interface is used to receive and parse message sending commands to obtain command information;

[0012] The sending status control module is used to determine the number of frames required to read the target message and the data reading direction according to the instruction information; wherein, the data reading direction is one of forward reading, reverse reading, and reverse reading followed by forward reading;

[0013] The read address generation module is used to generate the read address for the current frame based on the instruction information, the number of frames required to read the target message, and the data reading direction.

[0014] The memory is used to store message data and output the read data of the current frame according to the read address of the current frame.

[0015] The read data processing module is used to process and output the read data of the current frame output by the memory;

[0016] The bus interface is used to send the data output by the read data processing module to the peer device.

[0017] In one embodiment, the memory is divided into multiple storage spaces, each storage space being defined as a buffer;

[0018] The instruction information includes a start pointer indicating the start position of data reading, a stop pointer indicating the end position of data reading, and buffer information. The buffer information is the identifier of the buffer where the target message is located, and the start position and the end position are both one byte in the buffer where the target message is located.

[0019] In one embodiment, the memory is divided into multiple buffers, which are used to store different messages or message fragments.

[0020] In one embodiment, the transmission status control module is further configured to:

[0021] When the starting position is the first byte in the buffer, and the starting position and the ending position are different, the data reading direction is determined to be forward reading, and the target message to be read is the data between the starting position and the ending position in the buffer.

[0022] When the start position and the end position are the same, the data reading direction of the target message is determined to be reverse reading, and the target message to be read is the data between the start position and the first byte in the buffer.

[0023] When the starting position is between the first byte in the buffer and the ending position, the data reading direction is determined to be first reading in reverse order and then reading in forward order. The target message for reverse reading is the data between the starting position and the first byte, and the target message for forward reading is the data between the next byte of the starting position and the ending position.

[0024] In one embodiment, the memory is formed by splicing a first memory bank and a second memory bank, each of which includes a plurality of memory cells arranged in rows, and the bit width of each memory cell is the same as the bus bit width.

[0025] In one embodiment, a data caching module is also included;

[0026] When the data reading direction is first reverse reading and then forward reading, if the starting position is not the highest byte of any storage unit of the first storage bank or the second storage bank, the read data processing module is further used to receive the first storage unit data output by the first storage bank and the second storage unit data output by the second storage bank in the first step of reverse reading, concatenate part of the data in the first storage unit data and part of the data in the second storage unit data to obtain a bus width data, send the bus width data to the bus interface, and output the remaining data in the storage unit data where the starting position is located that has not been sent to the data cache module for temporary storage;

[0027] The read data processing module is further configured to receive the third storage unit data output by the first storage bank in the last step of reverse reading, concatenate the unsent data in the third storage unit data with the remaining data temporarily stored in the data cache module to obtain a bus width data, and send the bus width data to the bus interface.

[0028] In one embodiment, when the data reading direction is first reverse reading and then forward reading, if it takes at least three steps to complete the reverse reading, the read data processing module is further used to receive and obtain a bus width data based on a storage unit data output by the first storage bank and a storage unit data output by the second storage bank in the middle of the reverse reading, and send it to the bus interface.

[0029] In one embodiment, the read data processing module is further configured to, when the data reading direction is forward or reverse, receive and obtain a bus width data based on a storage cell data output by the first storage bank and a storage cell data output by the second storage bank at each step of forward or reverse reading, and send it to the bus interface.

[0030] In one embodiment, the read data processing module is further configured to place the data read in reverse order in little-endian byte order within a bus width data, and to place the data read in forward order in big-endian byte order within a bus width data.

[0031] In one embodiment, the placement according to little-endian byte order includes: the smallest byte in the bus width data is placed at the beginning of the bus width data, the largest byte in the bus width data is placed at the end of the bus width data, and all bytes in the bus width data are placed in high-low order.

[0032] In one embodiment, the placement according to big-endian byte order includes: the largest byte in the bus width data is placed at the beginning of the bus width data, the smallest byte in the bus width data is placed at the end of the bus width data, and all bytes in the bus width data are placed in high-low order.

[0033] In one embodiment, it also includes:

[0034] A write data interface is used to receive write commands and write the data to be written to the corresponding storage location in the memory according to the write commands;

[0035] The status reporting module is used to obtain the real-time status information of the message sending buffer device and report the real-time status information to the control status register of the network processor.

[0036] In one embodiment, the real-time status information includes the current usage of the message transmission buffer, the status of the memory, or the status of data transmission.

[0037] In one embodiment, the read address generation module is further configured to determine the storage address of the data in the target message based on the instruction information, the number of steps required to read the target message, and the data reading direction. The storage address includes the storage address of data read in forward order and the storage address of data read in reverse order. The module generates a read address for each step and sends the read address for each step to the memory.

[0038] According to a second aspect of this application, a chip is provided, including a message transmission buffer as described in the first aspect.

[0039] Details of one or more embodiments of this application are set forth in the following drawings and description. Other features, objects, and advantages of this application will become apparent from the specification, drawings, and claims. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the disclosed drawings without creative effort.

[0041] Figure 1 is a circuit diagram of a message transmission buffer device in one embodiment of this application.

[0042] Figure 2 is a schematic diagram of the start pointer, end pointer, and buffer for reading data in ascending order in one embodiment of this application.

[0043] Figure 3 is a schematic diagram of the start pointer, end pointer, and buffer for reverse data reading in one embodiment of this application.

[0044] Figure 4 is a schematic diagram of the start pointer, end pointer, and buffer for reading data in reverse order and then in forward order in one embodiment of this application.

[0045] Figure 5 is a schematic diagram of the memory structure in one embodiment of this application.

[0046] Figure 6 is a circuit diagram of a message transmission buffer device in another embodiment of this application.

[0047] In the diagram, the following are the markings: 1 is the command sending interface, 2 is the command sending status control module, 3 is the read address generation module, 4 is the memory, 5 is the read data processing module, 6 is the bus interface, 7 is the data cache module, and 8 is the write data interface. Detailed Implementation

[0048] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0049] The detailed description of the accompanying drawings is intended to illustrate some embodiments of this application and is not intended to represent only the forms in which this application can be implemented. It should be understood that the same or equivalent functions can be accomplished by different embodiments intended to be included within the spirit and scope of this application.

[0050] One embodiment of this application provides a message transmission buffer device (out-buffer). Referring to FIG1, the out-buffer of this embodiment includes a transmission command interface, a transmission status control module, a read address generation module, a memory, a read data processing module, and a bus interface.

[0051] The sending instruction interface is used to receive and parse message sending instructions to obtain instruction information;

[0052] Specifically, the message sending instructions are issued by the control logic of the DPU. These instructions are used to indicate how to read and send the target message, including but not limited to the storage address of the target message in the out-buffer, the message data size, information related to the data reading direction, and the peer device information; the target message refers to the network message that has been encapsulated and stored in the memory of the out-buffer.

[0053] The sending status control module is used to determine the number of frames required to read the target message and the data reading direction according to the instruction information; wherein, the data reading direction is one of forward reading, reverse reading, and reverse reading followed by forward reading; the target message is one of encapsulation from the inside out, encapsulation from the outside in, and encapsulation from the inside out followed by encapsulation from the outside in.

[0054] Specifically, the number of clock cycles refers to the number of clock cycles required to read the target message. The amount of data read in each clock cycle is limited, usually depending on the bus width design. For example, if the bus width is 32 bytes, then the message data read in each clock cycle is 32 bytes. This is because only one 32-byte data can be sent to the peer device through the bus in each clock cycle. Therefore, a 64-byte network message needs to go through two clock cycles to be fully read and sent.

[0055] The data reading direction refers to the order in which data is read from the target message. Forward reading means starting from the beginning of the message and reading the data one by one in the natural order. Reverse reading means starting from the end of the message and reading the data one by one in reverse order. Reverse reading followed by forward reading means starting from the end of the message and reading a portion of the data in reverse order, and then starting from the beginning of the message and reading the remaining data in forward order.

[0056] It should be noted that reading in forward order refers to reading network packet data from the inside out, while reading in reverse order refers to reading network packet data from the outside in. Reading in reverse order followed by reading in forward order corresponds to reading network packet data from the inside out first, then from the outside in. Through this correspondence, the packet sending buffer can adopt the appropriate data reading direction according to different packet encapsulation requirements, thereby achieving flexible packet encapsulation and transmission. This design makes the packet sending buffer applicable to various network packet processing scenarios, improving the versatility and efficiency of the out-buffer.

[0057] The read address generation module is used to generate the read address for the current frame based on the instruction information, the number of frames required to read the target message, and the data reading direction.

[0058] Specifically, the read address generation module, based on the instruction information, the number of read cycles required to read the target message, and the data reading direction, can determine which addresses in the target message store data that needs to be read in forward order and which addresses store data that needs to be read in reverse order, and generate the corresponding read address for each cycle, and then send it to the memory. For example, if the message is encapsulated from the inside out and needs to be read in forward order, the read address generation module will start from the starting address of the message payload and generate the read address for each cycle in sequence. As another example, if the message is encapsulated from the outside in and needs to be read in reverse order, the read address generation module will start from the address of the outermost header of the message and generate the read address for each cycle in reverse order.

[0059] Since the memory can only respond to one read address and output the corresponding read data in each clock cycle, the read address generation module generates a read address and sends it to the memory in each clock cycle until the entire target message data is read.

[0060] The memory is used to store message data and output the read data of the current frame according to the read address of the current frame;

[0061] Specifically, the memory is a part of the out-buffer used to temporarily store the message data to be sent. When the message is ready to be sent, it is stored in this memory. The memory reads the data from the correct position according to the read address of the current frame provided by the read address generation module, and outputs the read data of the current frame.

[0062] The read data processing module is used to process and output the read data of the current frame output by the memory;

[0063] Specifically, the read data processing module is responsible for processing the data read from the memory to ensure that the read data is arranged on the bus in the correct format and order to meet specific network protocols and transmission requirements, such as whether the data needs to be swapped or shifted.

[0064] The bus interface is used to send the data output by the read data processing module to the peer device;

[0065] Specifically, the bus interface is the interface between the out-buffer and external devices (such as network interface cards, other processing units, etc.). The bus interface is responsible for sending the processed data output by the read data processing module to the peer device through the bus network. The peer device refers to the device that requests the target message.

[0066] Furthermore, in some more specific embodiments, the memory is divided into multiple storage spaces, each storage space being defined as a buffer;

[0067] The instruction information includes a start pointer indicating the start position of data reading, a stop pointer indicating the end position of data reading, and buffer information. The buffer information is the identifier of the buffer where the target message is located, and the start position and the end position are both one byte in the buffer where the target message is located.

[0068] Specifically, the multiple buffers can be used to store different messages or message fragments. In this embodiment, the start pointer is a pointer that indicates the starting position of data reading. It points to a specific byte of the target message in a particular buffer, and the start pointer tells the read address generation module where to start reading message data in the forward or reverse direction.

[0069] The termination pointer is a pointer that indicates the end position of data reading. It points to a specific byte of the target message in a specific buffer and tells the read address generation module where to end the data reading.

[0070] Buffer information is identification information about the buffer where the target message is located. When the memory is divided into multiple buffers, each buffer will have a unique identifier. Buffer information indicates which buffer the read address generation module and the memory access to read message data.

[0071] When a message needs to be sent, the send command interface receives a message send command. Based on this command, the start pointer, end pointer, and buffer information can be extracted. The send status control module and read address generation module use this information to determine the address and order / direction of the data to be read at each clock cycle. The memory reads the data from the correct buffer according to the generated address, and after processing by the read data processing module, it is sent to the network through the bus interface.

[0072] Furthermore, in some more specific embodiments, the transmission status control module is further configured to:

[0073] When the starting position is the first byte in the buffer, and the starting position and the ending position are different, the data reading direction is determined to be forward order reading, and the target message to be read is the data in the buffer between the starting position and the ending position. Specifically, as shown in Figure 2, when the starting position indicated by the start pointer is the first byte (byte0) in the buffer, and the starting position and the ending position indicated by the end pointer are different, the sending status control module will determine the data reading direction to be forward order reading. Forward order reading means starting from the starting position of the stored data and reading the data one by one in the natural order until the ending position of the data is reached. In this mode, the target message to be read is all the data in the buffer from the starting position to the ending position. This configuration is used to process those messages that are stored continuously in the buffer and need to be read in order from start to end. This is the most common data reading method and is suitable for the transmission of most network messages.

[0074] When the start position and the end position are the same, the data reading direction of the target message is determined to be reverse order reading. The target message to be read is the data from the start position to the first byte (byte0) in the buffer. Specifically, as shown in Figure 3, when the start position indicated by the start pointer and the end position indicated by the end pointer are the same, the transmission status control module will determine the data reading direction to be reverse order reading. Reverse order reading means starting from the start position of the data and reading the data one by one in reverse order until the first byte (byte0) of the buffer is reached. In this mode, the target message to be read is all the data in the buffer from the start position (which is also the end position) to the first byte (byte0). This situation is usually used to process messages that need to be read from the end. For example, in some specific protocols, the header information of the message may be located at the end of the message, and the header information needs to be read first to determine how to process the subsequent data. Reverse order reading ensures that it is possible to read from the end of the message until the beginning of the message.

[0075] When the starting position is between the first byte and the ending position in the buffer, the data reading direction is determined to be reverse reading followed by forward reading. The target message for reverse reading is the data between the starting position and the first byte, and the target message for forward reading is the data between the next byte from the starting position and the ending position. Specifically, as shown in Figure 4, when the starting position indicated by the start pointer is between the first byte (byte0) and the ending position indicated by the end pointer in the buffer, the transmission status control module determines that the data reading direction is reverse reading followed by forward reading. Specifically, this process is divided into a reverse reading stage and a forward reading stage. In the reverse reading stage, data is read in reverse order from the starting position to the first byte (byte0) of the buffer. In the forward reading stage, data is read in forward order from the next byte (starting position + 1) to the ending position.

[0076] Furthermore, in some more specific embodiments, as shown in Figure 5, the memory is formed by splicing together a first memory bank (bank0) and a second memory bank (bank1). Both the first and second memory banks include multiple memory cells arranged in rows. In each memory bank, the number of memory cells is the depth of the memory bank (the depth in Figure 5 is 4, and each bank includes 4 memory cells). The bit width of each memory cell is the same as the bus bit width. Bank0 and bank1 output one memory cell data at a time. That is, the read address generation module generates two read addresses and assigns them to bank0 and bank1 respectively. The read address is the address of the memory cell (i.e., adr: 0~3 in Figure 5), which can also be understood as the depth of the memory bank. Each memory cell includes multiple bytes. Figure 5 shows an 8-byte memory cell.

[0077] Specifically, by designing the memory as a structure formed by splicing two memory banks, the bus bandwidth can be effectively utilized. If there is only a single memory bank, when a bus width data data_a needs to be stored at different depth addresses in the memory bank, it takes two clock cycles to send the entire bus width data data_a during output. However, by designing it as a structure formed by splicing two memory banks, the bus width data data_a can be split into two parts, stored in different memory banks, and then read from the two memory banks in parallel in the same clock cycle before being spliced ​​and output.

[0078] Furthermore, in some more specific embodiments, as shown in FIG6, a data caching module is also included;

[0079] When the data reading direction is first reverse reading and then forward reading, if the reverse reading only requires one clock cycle, the read data processing module is further used to receive and, based on the data of the storage unit where the starting position is output by the first storage bank, obtain a bus width data based on the storage unit data and send it to the bus interface in the first clock cycle of the reverse reading. If the starting position is the highest byte of the storage unit, the data of the storage unit is directly output as the bus width data. If the starting position is not the highest byte of the storage unit, and some data in the storage unit data needs to be read in reverse order and some data needs to be read in forward order, the data read in reverse order is placed in a bus width data in little-endian byte order, and the data read in forward order is placed in a bus width data in big-endian byte order.

[0080] When the data reading direction is first reverse reading and then forward reading, if it takes at least two clock cycles to complete the reverse reading, and if the starting position is not the highest byte of any storage unit of the first storage bank or the second storage bank, then the read data processing module is further used to receive the first storage unit data output by the first storage bank and the second storage unit data output by the second storage bank in the first clock cycle of the reverse reading, concatenate part of the data in the first storage unit data and part of the data in the second storage unit data to obtain a bus width data, send the bus width data to the bus interface, and output the remaining data in the storage unit data where the starting position is located that has not been sent to the data cache module for temporary storage;

[0081] The read data processing module is further configured to receive the third storage unit data output by the first storage bank in the last step of reverse reading, concatenate the unsent data in the third storage unit data with the remaining data temporarily stored in the data cache module to obtain a bus width data, and send the bus width data to the bus interface.

[0082] When the data reading direction is first reverse reading and then forward reading, if it takes at least three steps to complete the reverse reading, the read data processing module is further used to receive and obtain a bus width data based on a storage unit data output by the first storage bank and a storage unit data output by the second storage bank in the middle of the reverse reading, and send it to the bus interface.

[0083] Specifically, the middle byte of the storage unit refers to all bytes in the storage unit other than the highest byte. An example of the method in this embodiment is shown in Figure 5. The width of bank0 and bank1 is 8 bytes. One storage unit of bank0 includes bytes 0 to 7, where byte 7 is the highest byte of the storage unit. The start pointer points to byte 44 of the buffer, and the end pointer points to byte 58 of the buffer. However, byte 44 is not the highest byte (i.e., 47) of a storage unit of bank1. In this case, data concatenation occurs, and reading data in reverse order requires 6 steps to complete the reading. Specifically, in this example, in the first step of reverse reading, bank0 outputs storage unit data of bytes 39 to 32, and bank1 outputs storage unit data of bytes 47 to 40. Then, the 4 bytes of data of bytes 43 to 40 are concatenated with the 4 bytes of data of bytes 39 to 36 to obtain an 8-byte (bytes 43 to 36) bus width data (in reverse order) and output to the bus interface. The 4 bytes of data of bytes 44 to 47 (in forward order) are output to the data buffer module for temporary storage, and the 4 bytes of data of bytes 45 to 32 are discarded.

[0084] Furthermore, in the second step of the reverse read, bank0 outputs storage unit data of bytes 39-32, and bank1 outputs storage unit data of bytes 31-24; then, the four bytes of data of bytes 35-32 are concatenated with the four bytes of data of bytes 31-28 to obtain an 8-byte (bytes 35-28) bus width data and output to the bus interface; and so on, in the third step of the reverse read, an 8-byte (bytes 27-20) bus width data is obtained and output to the bus interface, until byte 0 (the first byte) of the buffer is reached; in the last step of the reverse read, bank0 outputs storage unit data of bytes 7-0; then, bytes 3-0 are concatenated with the storage unit data of bytes 7-0. The four bytes of data (in reverse order) are concatenated with the four bytes of data (in ascending order) temporarily stored in the data cache module (bytes 44-47) to obtain a bus width data, which is then output to the bus interface and enters the ascending order reading process. The ascending order reading reads the data of bytes 48-59, which takes a total of two steps. In the first step of the ascending order reading, the bus width data of bytes 48-55 is output to the bus interface; in the second step, the bus width data of bytes 56-63 is output to the bus interface. In this way, the number of data transmissions can be effectively reduced, the occupation of network resources can be reduced, bandwidth can be utilized more effectively, and unnecessary data transmission can be reduced.

[0085] It should be noted that the above description pertains to an embodiment where the starting position is not the highest byte of any storage unit in the first or second storage bank. If the starting position is the highest byte of any storage unit in the first or second storage bank, then no data concatenation occurs. In each clock cycle, whether in reverse or forward order, the data from the storage unit output by bank0 or bank1 can be output to the bus interface. Therefore, it is not necessary to store part of the data in the data cache module in the first clock cycle of reverse reading. The lowest byte of any storage unit in any storage bank follows the same principle.

[0086] Furthermore, in some more specific embodiments, the read data processing module is further configured to, when the data reading direction is forward or reverse, receive and obtain a bus width data based on a storage cell data output by the first storage bank and a storage cell data output by the second storage bank at each step of forward or reverse reading, and send it to the bus interface.

[0087] It should be noted that when the data reading direction is forward or reverse, the reading method can be referred to the example in Figure 5. For example, in each step, a portion of the data in the storage unit output by bank0 is concatenated with a portion of the data in the storage unit output by bank1 to obtain an 8-byte bus width data. This process continues until the last byte of data is read in forward or reverse order.

[0088] Furthermore, in some more specific embodiments, the read data processing module is further configured to place the data read in reverse order in little-endian byte order within a bus width data, and to place the data read in forward order in big-endian byte order within a bus width data.

[0089] In a more specific embodiment, the read data processing module uses a specific byte order to place data read in reverse order and data read in forward order to ensure data correctness and compatibility.

[0090] Data read in reverse order is placed in a bus width data, arranged in little-endian byte order. This means that the bus width data consists of multiple bytes. The smallest byte (i.e., the low-order byte of the memory output) is placed at the beginning of the bus width data, while the largest byte (i.e., the high-order byte of the memory output) is placed at the end of the bus width data. All bytes are placed in high-low order.

[0091] Data read in ascending order is placed in a bus width data, arranged in big-endian byte order. This means that the bus width data consists of multiple bytes. The largest byte (i.e., the most significant byte output from memory) is placed at the beginning of the bus width data, while the smallest byte (i.e., the least significant byte output from memory) is placed at the end of the bus width data. All bytes are placed in high-low order.

[0092] Furthermore, in some more specific embodiments, the memory is a memory formed by splicing together multiple memory banks;

[0093] Specifically, multiple memory banks can work in parallel, improving the read and write speed of the memory. Each memory bank can process data independently, reducing data transmission bottlenecks and thus improving overall performance.

[0094] Furthermore, in some more specific embodiments, it also includes:

[0095] A write data interface is used to receive write commands and write the data to be written to the corresponding storage location in the memory according to the write commands.

[0096] Specifically, when new message data needs to be stored in the buffer, this data can be written to the specified storage location through the write data interface.

[0097] Furthermore, in some more specific embodiments, it also includes:

[0098] The status reporting module is used to obtain the real-time status information of the message sending buffer device and report the real-time status information to the control status register of the network processor.

[0099] Specifically, the status reporting module is responsible for monitoring the status of the out-buffer and collecting relevant real-time status information. This information reflects the operating status and performance indicators of the out-buffer, and may include, but is not limited to, the current usage of the out-buffer, the status of the memory, and the status of data transmission.

[0100] The control status register is a register in the network processor used to store and manage system status information. By reporting real-time status information to this register, the network processor can monitor and control the operation of the packet transmission buffer. Through this status reporting module, the out-buffer can exchange status information with the network processor. The network processor can then use this real-time status information to adjust system configuration, optimize data transmission strategies, or perform fault diagnosis.

[0101] This application also provides a chip, including the message transmission buffer device described in the above embodiments.

[0102] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technological improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0103] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A message sending buffer apparatus, characterized by comprising: The application relates to a packet sending device, which comprises the following parts: a sending instruction interface for receiving and analyzing packet sending instructions to obtain instruction information; a sending state control module for determining the number of taps required for reading target packets and a data reading direction according to the instruction information; wherein the data reading direction is one of forward reading, reverse reading and forward reading after reverse reading; the target packet is one of inside-out encapsulation, outside-in encapsulation and inside-out encapsulation after outside-in encapsulation; a read address generation module for generating a read address of a current tap according to the instruction information, the number of taps required for reading target packets and the data reading direction; a memory for storing packet data and outputting read data of a current tap according to the read address of the current tap; a read data processing module for processing and outputting the read data of the current tap output by the memory; a bus interface for sending data output by the read data processing module to a peer device.

2. The message transmission buffering apparatus of claim 1, wherein The memory is divided into a plurality of storage spaces, and each storage space is defined as a buffer; the instruction information comprises a start pointer indicating a data reading start position, an end pointer indicating a data reading end position and buffer information, the buffer information is the identification of a buffer where the target packet is located, and the start position and the end position are both a byte in the buffer where the target packet is located.

3. The message transmission buffering apparatus of claim 2, wherein, The memory is divided into a plurality of buffers, and the plurality of buffers are used for storing different packets or packet segments.

4. The message transmission buffering apparatus of claim 2, wherein The sending state control module is further used for: when the start position is the first byte in the buffer and the start position and the end position are different, determining that the data reading direction is forward reading, and the target packet read is the data between the start position and the end position in the buffer; when the start position and the end position are the same, determining that the data reading direction of the target packet is reverse reading, and the target packet read is the data between the start position and the first byte in the buffer; when the start position is between the first byte and the end position in the buffer, determining that the data reading direction is forward reading after reverse reading, the target packet of reverse reading is the data between the start position and the first byte, and the target packet of forward reading is the data between the next byte of the start position and the end position.

5. The message transmission buffering apparatus of claim 4, wherein, The memory is formed by splicing a first memory bank and a second memory bank, and the first memory bank and the second memory bank both comprise a plurality of storage units arranged in rows, and the bit width of each storage unit is the same as the bus bit width.

6. The message transmission buffering apparatus of claim 5, wherein, The application further comprises a data caching module. When the data reading direction is first reverse order reading and then normal order reading, if the start position is not the highest byte of any memory cell of the first memory bank or the second memory bank, the read data processing module is further configured to receive, in the first beat of reverse order reading, first memory cell data output by the first memory bank and second memory cell data output by the second memory bank, splice part of the first memory cell data and part of the second memory cell data to obtain one bus bit width data, send the one bus bit width data to the bus interface, and output the remaining part of the memory cell data at the start position to the data cache module for temporary storage. The read data processing module is further configured to receive, in the last beat of reverse order reading, third memory cell data output by the first memory bank, splice the data not sent in the third memory cell data and the remaining part of the data temporarily stored in the data cache module to obtain one bus bit width data, and send the one bus bit width data to the bus interface.

7. The message transmission buffering apparatus of claim 6, wherein, When the data reading direction is first reverse order reading and then normal order reading, if at least three beats are required to complete reverse order reading, the read data processing module is further configured to, in the middle beat of reverse order reading, receive one memory cell data output by the first memory bank and one memory cell data output by the second memory bank, obtain one bus bit width data, and send the one bus bit width data to the bus interface.

8. The message transmission buffering apparatus of claim 5, wherein, The read data processing module is further configured to, when the data reading direction is normal order reading or reverse order reading, receive one memory cell data output by the first memory bank and one memory cell data output by the second memory bank in each beat of normal order reading or reverse order reading, obtain one bus bit width data, and send the one bus bit width data to the bus interface.

9. The message transmission buffering apparatus of claim 1, wherein, The read data processing module is further configured to place the data of reverse order reading in one bus bit width data in little-endian byte order, and place the data of normal order reading in one bus bit width data in big-endian byte order.

10. The message transmission buffering apparatus of claim 9, wherein, The placement in little-endian byte order comprises that the smallest byte data in the bus bit width data is placed at the start position of the bus bit width data, the largest byte data in the bus bit width data is placed at the end position of the bus bit width data, and all byte data in the bus bit width data is placed in order of high and low bits.

11. The message transmission buffering apparatus of claim 9, wherein, The placement in big-endian byte order comprises that the largest byte data in the bus bit width data is placed at the start position of the bus bit width data, the smallest byte data in the bus bit width data is placed at the end position of the bus bit width data, and all byte data in the bus bit width data is placed in order of high and low bits.

12. The message transmission buffering apparatus according to any one of claims 1 to 11, characterized by Further comprising: a write data interface configured to receive a write command and write to-be-written data into a corresponding storage position in the memory according to the write command; a state reporting module configured to obtain real-time state information of the message sending buffer device and report the real-time state information to a control state register of a network processor.

13. The message transmission buffering apparatus of claim 12, wherein, The real-time status information includes current usage of the packet sending buffer device, status of the memory, or status of data transmission.

14. The message buffering apparatus of claim 1, wherein The read address generation module is further configured to determine storage addresses of data in the target packet according to the instruction information, the number of beats required for reading the target packet, and a data reading direction, the storage addresses including a storage address of data read in a forward order and a storage address of data read in a reverse order; generate a read address of each beat and send the read address of each beat to the memory.

15. A chip, characterized by The packet sending buffer device according to any one of claims 1-14.

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