Photodetection element and photodetection device

Abstract

In the present invention, an information processing device is capable of generating sub-images to be sequentially displayed, and comprises: a first processing unit that, on the basis of a frame image, is capable of generating two or more sub-images among a plurality of sub-images having a plurality of pixel values and arranged in a predetermined arrangement pattern in the frame image; a detection unit that detects detection pixels to be processed, on the basis of the display order of corresponding pixels of the two or more sub-images and the pixel value difference between the pixels in the display order and on the basis of the coordinates of the frame image; and a second processing unit that executes processing for reducing the pixel value difference between corresponding pixels in the detection pixels.

Description

Photodetection element and photodetection device

[0001] The present disclosure relates to a light detection element and a light detection device.

[0002] Conventionally, imaging devices have been used in which a plurality of pixels are arranged in a matrix to capture image data. For example, a photodetector device has been proposed in which a single-photon avalanche diode (SPAD) and a detection circuit that generates a pulse signal based on the potential of the cathode are provided for each pixel, and the pixels are arranged in a matrix (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2023-59522

[0004] In such a photodetector, pixel recharge processing is performed for each row, but if the timing of the recharge processing overlaps between rows, the peak current in the photodetector may become excessively large.

[0005] Therefore, the present disclosure provides a photodetector element and a photodetector device that can suppress the peak of the current in the photodetector element.

[0006] In order to solve the above-mentioned problems, according to the present disclosure, there is provided a photodetector element including a pixel array unit in which a plurality of pixels are arranged in a matrix, and a control circuit that controls the plurality of pixels, wherein the pixels each include: a photoelectric conversion unit in which a cathode potential varies in response to incidence of photons; a detection circuit that generates a pulse signal when the cathode potential varies from an initial value; a recharge circuit that outputs the cathode potential to the detection circuit based on the input timing of a control signal output from the control circuit, and resets the cathode potential to the initial value; and a count circuit that counts the number of the pulse signals, and the control circuit is configured to be able to change a period, which is the interval between output timings of the control signals, for each output timing.

[0007] The control circuit may further include a period setting register in which a plurality of different periods are set, and an order setting register that sets the order in which the periods are set, and output the control signal in accordance with the order in which the periods are set by the order setting register.

[0008] The sequence setting register may be capable of setting the cycles in a different sequence for each row of the pixel array unit.

[0009] The sequence setting register may be set for each column of the pixel array unit so that output periods of control signals do not overlap.

[0010] The sequence setting register may be configured such that the period is set randomly.

[0011] The order setting register may be set in order so that the lengths of successive periods alternate in succession.

[0012] The control signals may include a first control signal that causes the detection circuit to output the cathode potential, and a second control signal that causes the cathode potential to be set to the initial value, and the pixel may further include a mask circuit that stops output of at least one of the first control signal and the second control signal.

[0013] The cycle setting register may be capable of mask setting to stop output of at least one of the first control signal and the second control signal for each cycle.

[0014] When the order setting register is set so that the lengths of consecutive periods alternate between long and short, the period setting register may be set to a mask that stops the second control signal on the longer period side.

[0015] The order setting register may set a different cycle order for each pixel group in the same row.

[0016] The plurality of pixels may be provided with color filters of different colors, and the sequence setting register may set a periodic order for each of the different colors.

[0017] Color filters of different colors may be arranged in a plurality of pixels in the same row of the pixel array unit, and a periodic order may be set for each of the different colors in the order setting register.

[0018] The control circuit may further include: a basic period setting unit that generates a basic period pulse; a period setting unit that generates a recharge period pulse based on the basic period pulse in accordance with the period order of the order setting register; and a pulse generating unit that generates the second control signal based on the recharge period pulse.

[0019] The circuit may have a plurality of the period setting sections, and generate recharge periodic pulses in accordance with a plurality of period orders.

[0020] The cycle setting section may be capable of outputting the recharge cycle pulse to a plurality of the pulse generating sections.

[0021] The basic period setting unit may have a basic signal counter circuit that generates a basic signal counter, which is a count value specified by the register setting of the period setting register, and a basic signal generation circuit that generates a basic period pulse with the same period by repeating the operation of generating a pulse in accordance with the basic signal counter generated by the basic signal counter circuit.

[0022] The cycle setting section may include a cycle counter circuit that generates a cycle counter that is a count value according to the cycle order of the order setting register, and generates the recharge cycle pulse when the counter reaches a cycle in the cycle order.

[0023] The pulse generating unit may include: a clock gate circuit that generates a pulse clock enable signal that inputs a clock only for a certain period from the recharge period pulse generated by the cycle counter circuit; and a pulse generation counter circuit that counts the recharge period pulses during the valid period of the pulse clock enable signal to generate a pulse counter that is a count value, and generates the second control signal when the pulse counter reaches a predetermined value.

[0024] The photoelectric conversion unit may be an avalanche photodiode.

[0025] In order to solve the above-mentioned problems, according to the present disclosure, there is provided a photodetection device comprising: a pixel array unit in which a plurality of pixels are arranged in a matrix; a control circuit that controls the plurality of pixels; and a recording unit that records the count numbers output by the plurality of pixels, wherein the pixels each have: a photoelectric conversion unit in which a cathode potential varies in response to incidence of photons; a detection circuit that generates a pulse signal when the cathode potential varies from an initial value; a recharge circuit that outputs the cathode potential to the detection circuit based on the input timing of a control signal output from the control circuit, and resets the cathode potential to the initial value; and a count circuit that counts the number of the pulse signals, and the control circuit is configured to be able to change a period, which is the interval between output timings of the control signals, for each output timing.

[0026] 12 is a block diagram showing an example of the configuration of an imaging device according to an embodiment of the present technology. FIG. 13 is a block diagram showing an example of the configuration of a solid-state imaging element according to a first embodiment. FIG. 14 is a block diagram showing an example of the configuration of a pixel according to the first embodiment. FIG. 15 is a diagram showing an example of the configuration of a light receiving unit. FIG. 16 is a circuit diagram showing an example of the configuration of a light receiving unit according to the present embodiment. FIG. 17 is a table showing example setting information of a period setting register. FIG. 18 is a table showing an example of selecting and setting measurement periods for pixels in cycle order within an exposure period. FIG. 19 is a timing chart showing an example of operation of a solid-state imaging element in a first mode. FIG. 19 is a time chart showing the relationship between setting information of an order setting register and control signals in a second mode. FIG. 19 is a diagram showing an example of the configuration of a pixel according to a second embodiment. FIG. 19 is a table showing example setting information of a period setting register according to the second embodiment. FIG. 19 is a time chart showing an example of generating control signals for all periods as a comparative example. FIG. 19 is a time chart showing an example of generating control signals according to setting information of the mask register shown in FIG. 11. FIG. 19 is a block diagram showing an example of the configuration of a pulse generating unit according to a third embodiment. FIG. 19 is a timing chart of signals generated by a pulse generating circuit. FIG. 19 is a block diagram showing the relationship between a plurality of cycle counter circuits, a plurality of generation pulse counter circuits, a clock gate circuit, and a pixel group within a control circuit. FIG. 19 is a diagram showing an example of the configuration of four pixels of a pixel group in a Bayer array. 1 is a block diagram showing an example of a vehicle control system according to an embodiment of the present invention; FIG. 2 is a timing chart showing an example of the operation of four pixels in a pixel group in a Bayer array; FIG. 3 is a block diagram showing an example of a schematic configuration of a vehicle control system; and FIG. 4 is an explanatory diagram showing an example of the installation positions of an outside-of-vehicle information detection unit and an imaging unit.

[0027] Hereinafter, embodiments of an information processing device and a display device will be described with reference to the drawings. The following description will focus on the main components of the display device, but the display device may have components or functions that are not shown or described. The following description does not exclude components or functions that are not shown or described.

[0028] 1 is a block diagram showing an example configuration of an imaging device 100 according to an embodiment of the present technology. The imaging device 100 captures image data and includes an imaging lens 110, a solid-state imaging element 200, a recording unit 120, and an imaging control unit 130. The imaging device 100 may be, for example, a smartphone, a digital camera, a personal computer, an in-vehicle camera, or an IoT (Internet of Things) camera.

[0029] The imaging lens 110 collects incident light and guides it to the solid-state imaging element 200. The solid-state imaging element 200 captures image data under the control of the imaging control unit 130. The solid-state imaging element 200 supplies the counter number for each pixel to the recording unit 120 via a signal line 209. The recording unit 120 records the counter number. The solid-state imaging element 200 is an example of a photodetection element.

[0030] The imaging control unit 130 controls the solid-state imaging element 200 to capture image data. The imaging control unit 130 supplies a synchronization signal, such as a vertical synchronization signal, to the solid-state imaging element 200 via a signal line 139.

[0031] The imaging device 100 may further include an interface through which image data can be transmitted to an external device, or may further include a display unit on which image data can be displayed. The imaging device 100 is an example of a light detection device.

[0032] 2 is a block diagram showing an example of the configuration of a solid-state imaging device 200 according to the first embodiment. The solid-state imaging device 200 includes a control circuit 210, a pixel array unit 220, a signal processing unit 230, a cycle setting register 260, and a sequence setting register 262. These circuits are arranged on a single semiconductor substrate, for example.

[0033] A plurality of pixels 300 are arranged in a two-dimensional lattice in the pixel array unit 220. Hereinafter, a group of pixels 300 arranged in a predetermined direction (such as the horizontal direction) will be referred to as a "row," and a group of pixels 300 arranged in a direction perpendicular to the rows will be referred to as a "column." In other words, a plurality of pixels 300 are arranged in a two-dimensional matrix.

[0034] The control circuit 210 controls the pixels 300 row by row in synchronization with a vertical synchronization signal in accordance with the setting information of the period setting register 260 and the order setting register 262. For example, the control circuit 210 controls the generation of pulses in accordance with the settings of the period setting register 260 and the order setting register 262. The period setting register 260 defines a plurality of periods. The order setting register 262 sets the order in which the period settings are to be generated. Details of the period setting register 260 and the order setting register 262 will be described later.

[0035] The pixel 300 counts the number of times that photons are incident within the exposure period and outputs data indicating the count value as pixel data to the signal processing unit 230. The signal processing unit 230 performs various signal processing on the image data in which the pixel data is arranged. The signal processing unit 230 outputs the processed image data to the recording unit 120.

[0036] 3 is a block diagram showing an example of the configuration of a pixel 300 according to the first embodiment. The pixel 300 includes a light receiving unit 310, a counter 350, and a selection switch 361.

[0037] The light receiving unit 310 generates a pulse signal PLS in response to incident photons and supplies the signal to the counter 350. The counter 350 counts the number of pulses in the pulse signal PLS. The counter 350 supplies pixel data indicating the count value to the selection switch 361. The count value of the counter 350 is initialized by a reset signal RSTc from the control circuit 210. The selection switch 361 supplies the pixel data to the signal processing unit 230 in accordance with the selection signal SEL from the control circuit 210.

[0038] 4 is a diagram showing an example of the configuration of the light receiving unit 310. As shown in FIG. 4, the light receiving unit 310 has a SPAD 311, a recharge circuit 320, and a detection circuit 330. The SPAD 311 is a photoelectric conversion element capable of detecting photons. When a photon is incident on the SPAD 311, avalanche multiplication occurs, and the cathode potential drops from the initial potential to a constant potential. The SPAD 311 is an avalanche photodiode.

[0039] The recharge circuit 320 controls the output node of the SPAD 311 to a recharge state using a control signal. More specifically, the recharge circuit 320 outputs a potential corresponding to a change in the cathode potential of the SPAD 311 to the detection circuit 330. The recharge circuit 320 also resets the cathode potential of the SPAD 311 to an initial potential.

[0040] The detection circuit 330 generates a pulse signal in response to a decrease in the cathode potential of the photon of the SPAD 311. That is, the detection circuit 330 detects the incidence of a photon on the SPAD 311 and generates a pulse signal.

[0041] 5 is a circuit diagram showing an example of the configuration of the light receiving unit 310 according to this embodiment. The recharge circuit 320 has a clip transistor 312, an inverter 313, and a recharge transistor 321. The detection circuit 330 has a pMOS transistor 331, an nMOS (n-channel MOS) transistor 332, an inverter 333, and an inverter 334.

[0042] The clip transistor 312 and the recharge transistor 321 are, for example, pMOS (p-channel Metal Oxide Semiconductor) transistors.

[0043] The anode of the SPAD 311 is connected to a predetermined potential lower than the power supply voltage VDD, and the cathode is connected to the clip transistor 312. The cathode potential of this SPAD 311 is set to Vk1.

[0044] The clip transistor 312 and the recharge transistor 321 are connected in series with the recharge transistor 321 on the power supply side between the power supply voltage VDD and the cathode of the SPAD 311. The connection node between the clip transistor 312 and the recharge transistor 321 is hereinafter referred to as a detection node 314, and its potential is Vk3.

[0045] Furthermore, a control signal CLIP from the control circuit 210 is input to the gate of the clip transistor 312. A control signal XRST from the control circuit 210 is input to the gate of the recharge transistor 321 and to the inverter 313. The inverter 313 inverts the control signal XRST and supplies it to the detection circuit 330. The control signals CLIP and XRST are generated as control pulse signals.

[0046] The pMOS transistor 331 and nMOS transistor 332 of the detection circuit 330 are connected in series between the power supply voltage VDD and the ground voltage, with the pMOS transistor 331 on the power supply side. The gate of the pMOS transistor 331 is connected to the detection node 314, and an inverted signal from the inverter 313 is input to the gate of the nMOS transistor 332. A signal at the potential of a connection node 335 between the pMOS transistor 331 and the nMOS transistor 332 is set as the detection signal DET.

[0047] The inverter 333 inverts the detection signal DET. The inverter 334 inverts the inverted signal from the inverter 333 and supplies the inverted signal to the counter 350 as a pulse signal PLS.

[0048] Furthermore, setting information for controlling the pixels 300 is input to the control circuit 210 from a period setting register 260 and an order setting register 262. This setting information includes setting values ​​for the measurement period and cycle. The measurement period and cycle are set for each row of the pixel array section 220. Here, the measurement period is the period for measuring the incidence of photons, and the cycle indicates the order of the measurement period.

[0049] In the first mode, equivalent control information is set for each row of the pixel array unit 220. For example, in the normal mode, the set value of the measurement period in all cycles is set to A. If the number of repetitions of all cycles is set to a, A×a is the same value as the exposure period.

[0050] In the second mode, the control information is set so that the output timing of the control signal XRST does not overlap for each row of the pixel array unit 220. Also, in the second mode, it is possible to change the measurement cycle of the pixels 300 within the exposure period in cycle order. For example, the control information is set so that the output timing of the control signal XRST for each pixel 300 is uniform in time and space within the two-dimensional plane of the pixel array unit 220.

[0051] In the second mode, for example, the measurement period is set so that a long period follows a short period, thereby more efficiently setting the output timing of the control signal XRST to each pixel 300 to be uniform in time and space within the two-dimensional plane of the pixel array unit 220.

[0052] In the second mode, the measurement period of the sequence setting register 262 can be set randomly in the cycle order, so that the output timing of the control signal XRST to each pixel 300 within the exposure period is set to be uniform in time and space within the two-dimensional plane of the pixel array unit 220.

[0053] 6 is a table showing an example of setting information of the cycle setting register 260. The selection cycle is the cycle for measuring the incidence of photons, and is set, for example, to 0 to 7. The cycle corresponds to the number of clocks, for example.

[0054] For example, if the selection period is 0, the period is 1 clock. Similarly, if the selection period is 1, the period is 4 clocks, if the selection period is 2, the period is 16 clocks, and if the selection period is 3, the period is 64 clocks. Similarly, if the selection period is 4, the period is 128 clocks, if the selection period is 5, the period is 256 clocks, if the selection period is 6, the period is 1024 clocks, and if the selection period is 7, the period is 4096 clocks. In this way, the setting information of the period setting register 260 ranges from 0 to 7, for example, and values ​​corresponding to 0: 1 clk, 1: 4 clk, 2: 16 clk, 3: 64 clk, 4: 64 clk, 5: 256 clk, 6: 1024 clk, and 7: 4096 clk are set, respectively.

[0055] FIG. 7 is a table showing an example in which measurement periods for the pixels 300 are selected and set in cycle order within an exposure period. The order setting register 262 is set to determine the order in which the periods are generated. For example, measurement periods ranging from 0 to 127 cycles are set for each row of the pixel array unit 220. The exposure period is the sum of the selection periods ranging from 0 to 127 cycles. The number of cycles can be set arbitrarily to match the exposure period. As described above, the selection periods for each row ranging from 0 to 127 cycles can be set differently.

[0056] 5, during the measurement period, the control circuit 210 sets the control signal CLIP to high level and then to low level. During the period during the measurement period when the control signal CLIP is high level, the detection node 314 is disconnected from the cathode of the SPAD 311, and this period will be referred to as the "standby period" during which the detection node 314 waits for the incidence of photons. On the other hand, during the period during the measurement period when the control signal CLIP is low level, the detection node 314 is connected to the SPAD 311, and this period will be referred to as the "connection period."

[0057] When a photon is incident during the standby period, avalanche multiplication occurs in the SPAD 311, and its cathode potential Vk1 drops to a certain potential. During the subsequent connection period, the clip transistor 312 connects the detection node 314 to the SPAD 311. Therefore, if a photon is incident during the standby period, charge is transferred to the detection node 314 during the connection period, and the pulse signal PLS becomes high level.

[0058] Furthermore, the control circuit 210 sets the control signal XRST to low level for a predetermined period from a predetermined recharge start timing within the connection period. This causes the recharge transistor 321 to supply the power supply voltage VDD to the detection node 314. Because this detection node 314 is connected to the cathode, a recharge operation is performed to return the cathode potential Vk1 to the power supply voltage VDD. Furthermore, the low-level control signal XRST initializes the detection circuit 330.

[0059] 8 is a timing chart showing an example of the operation of the solid-state imaging device 200 in the first mode. In the initial state, the cathode potential Vk1 and the potential Vk3 of the detection node are both the power supply voltage VDD. As described above, the first mode is an example in which measurement periods are repeated at equal intervals.

[0060] Of the measurement period from timing T0 to T3, the period up to timing T1 corresponds to the standby period, and the period from timing T1 to timing T3 corresponds to the connection period. During the standby period, the control circuit 210 sets the control signal CLIP to high level. Furthermore, the control signal XRST is controlled to be high level for a certain period from a predetermined timing within the standby period.

[0061] Assume that a photon is incident during the waiting period from timing T0 to T1. In the figure, the arrow indicates the timing of the photon's incidence. The incidence of the photon causes avalanche multiplication in the SPAD 311, causing the cathode potential Vk1 to drop to a certain potential, at which point the avalanche multiplication stops. During the waiting period, the detection node 314 is disconnected, so the potential Vk3 does not oscillate.

[0062] At timing T1, when the cathode of SPAD 311 is connected to the detection node 314, part of the charge at the cathode moves to the detection node 314. As a result, the potential Vk3 of the detection node 314 drops, and the cathode potential Vk1 rises by the amount of the transferred charge. Furthermore, when the potential Vk3 becomes equal to or lower than the threshold value of the pMOS transistor 331, the pMOS transistor 331 turns on, and the pulse signal PLS rises.

[0063] The control circuit 210 keeps the control signal XRST at low level for a predetermined period starting from timing T2 within the connection period. That is, the control signal XRST goes low at a timing (T3-T2) before the timing at which the control signal CLIP goes from low to high, which is timing T3 when the measurement period starts, and goes from low to high at a timing (T2-T1) after timing T3 when the measurement period starts. As a result, the power supply voltage VDD is supplied, and the potential Vk3 of the detection node 314 is initialized to the power supply voltage VDD. Furthermore, because the detection node 314 is connected to the cathode, the cathode potential Vk1 is also initialized to the power supply voltage VDD. At the same time, the detection circuit 330 is initialized, and the pulse signal PLS falls.

[0064] As described above, during the connection period, the pixel 300 transitions to a detection state in which photons are detected during the period from timing T1 to T2, and transitions to a recharge state during the period from timing T2 to T3. Furthermore, by repeating the control within the measurement period described above, one pulse can be generated when one or more photons are incident during the standby period for each measurement period. For example, during the measurement period from timing T3 to T4, no photons are incident during the standby period, so no pulse is generated during that connection period. On the other hand, during the measurement period from timing T4 to T5, two photons are incident, so one pulse is generated.

[0065] 9 is a time chart showing the relationship between the setting information of the sequence setting register 262 and the control signal XRST in the second mode. From the top, the chart shows the selection period set in the sequence setting register 262, the period indicated by the number of clocks, and the output timing of the control signal XRST. The horizontal axis represents time.

[0066] As shown in FIG. 9 , the control circuit 210 converts the measurement period into the number of clocks using the setting information of the cycle setting register 260 (see FIG. 6 ) in accordance with the setting information of the sequence setting register 262 (see FIG. 7 ). The control circuit 210 then outputs the control signal XRST to the pixel 300 in accordance with the measurement period indicated by the number of clocks. In FIG. 9 , the start of the period is shown as the timing when the control signal CLIP (see FIG. 8 ) changes from high level to low level. That is, the control circuit 210 outputs the control signal XRST to the pixel 300 after (T2-T1) (see FIG. 8 ) from the timing when the control signal CLIP (see FIG. 8 ) changes from high level to low level.

[0067] The falling edge of the control signal CLIP corresponds to the start timing of the connection period, and the falling edge of the control signal XRST corresponds to the start timing of recharge. If these start timings were made the same for each row, IR drop would occur, which could prevent the control signals from being transmitted or prevent sufficient recharge. In contrast, in the second mode, the start timings of the connection period and the recharge start timing are set in the sequence setting register 262 so that they do not match for each row. As a result, the start timings and the recharge start timings do not match for each row, making it possible to suppress peak currents within the imaging device 100.

[0068] As described above, according to this embodiment, the measurement cycle of the pixels 300 within the exposure period can be set to any period in cycle order in the sequence setting register 262 for each row of the pixel array unit 220, and the control circuit 210 controls the pixel array unit 220 in accordance with the setting in the sequence setting register 262. This makes it possible for the sequence setting register 262 to control the connection period start timing and the recharge start timing so that they do not coincide for each row of the pixel array unit 220, making it possible to suppress peak currents in the imaging device 100.

[0069] Second Embodiment An imaging device 100 according to a second embodiment differs from the imaging device 100 according to the first embodiment in that it further includes a mask circuit 371, which makes it possible to mask the control signals CLIP and XRST for each pixel 300 under predetermined conditions. The differences from the imaging device 100 according to the first embodiment will be described below.

[0070] 10 is a diagram showing an example of the configuration of a pixel 300 according to the second embodiment. As shown in FIG. 10, a mask circuit 371 of the pixel 300 masks the signals CLIP and XRST in accordance with a mask signal MASK_SIB output from the control circuit 210. Note that the mask circuit 371 according to the second embodiment is configured within the pixel 300, but is not limited to this. For example, the mask circuit 371 may be configured for each control unit of the pixel array unit 220 within the control circuit 210.

[0071] 11 is a table showing an example of setting information of the cycle setting register 260 according to the second embodiment. The cycle setting register 260 according to the second embodiment further has a processing function as a mask register.

[0072] Fig. 11A is a table showing an example in which setting information of the mask signal MASK_SIB as a mask register is added to the setting information of the cycle setting register 260. Fig. 11B is a table showing an example of setting the mask signal MASK_SIB.

[0073] As shown in FIG. 11B, the setting information of the mask signal MASK_SIB indicates non-transmission (disable) of pulses. The period setting register 260 sets 00 (pulse generation), 01 (pulse stop), 10 (fixed low), and 11 (fixed high) for each period. For example, in this embodiment, the control signal CLIP is set to 00 (pulse generation) for all periods. On the other hand, the control signal XRST is set to 01 (pulse generation stop) for period settings of 4:64 clk, 5:256 clk, 6:1024 clk, and 7:4096 clk. In this case, no pulses are generated when the period setting is set to 01.

[0074] 10 , the control circuit 210 outputs a signal including information to the mask circuit 371 to disable the mask signal MASK_SIB and the control signal XRST by setting it to 01 (pulse generation stopped) for period settings of 4:64 clk, 5:256 clk, 6:1024 clk, and 7:4096 clk. As a result, a pulse-like signal of the control signal XRST is not generated for period settings of 4:128 clk, 5:256 clk, 6:1024 clk, and 7:4096 clk. In this way, the control signal XRST according to this embodiment is generated for period settings of 0:1 clk, 1:4 clk, 2:16 clk, and 3:64 clk, which are the first group of short periods. On the other hand, the control signal XRST according to this embodiment is not generated in the second group of longer cycle settings of 4:128 clk, 5:256 clk, 6:1024 clk, and 7:4096 clk.

[0075] On the other hand, the control signal CLIP is set to 00 (pulse generation) for all periods. The control circuit 210 outputs a signal including information to transmit (disable) the control signal CLIP as 00 (pulse generation) as the mask signal MASK_SIB to the mask circuit 371 for period settings of 0:1 clk, 1:4 clk, 2:16 clk, 3:64 clk, 4:128 clk, 5:256 clk, 6:1024 clk, and 7:4096 clk. As a result, pulse-shaped signals of the control signal CLIP corresponding to the period settings of 0:1 clk, 1:4 clk, 2:16 clk, 3:64 clk, 4:64 clk, 5:256 clk, 6:1024 clk, and 7:4096 clk are generated.

[0076] An example of operation in this embodiment will be described below. Fig. 12 is a time chart showing an example of generating control signals CLIP and XRST in all periods as a comparative example. Fig. 13 is a time chart showing an example of generating control signals CLIP and XRST in accordance with the setting information of the mask register shown in Fig. 11. From the top, the control signal CLIP, the control signal XRST, the potential Vk3, and the pulse signal PLS are shown.

[0077] The rising time T0A of the control signal CLIP from low level to high level corresponds to the period setting 0:1 clk, the rising time T0B corresponds to the period setting 1:4 clk, the rising time T0C corresponds to the period setting 2:16 clk, the rising time T0D corresponds to the period setting 4:128 clk, the rising time T0E corresponds to the period setting 5:256 clk, and the rising time T0F corresponds to the period setting 6:1024 clk. Also, the incident timings 121 to 128 are indicated by arrows to show the incident timings of photons.

[0078] 12, the potential Vk3 drops from the reference potential to a predetermined bottom potential in accordance with the incident timings 121 to 128 at which photons are incident on the pixel 300. When the control signal CLIP is input to the pixel 300 while the potential Vk3 has dropped to the predetermined bottom potential, a pulse signal PLS is generated. The predetermined bottom potential is then recharged by the input of the control signal XRST, returning to the reference potential. In this way, in the comparative example, the pulse signal PLS is generated in accordance with the incident timings 121 to 128, and the potential Vk3 is recharged and returned to the reference potential.

[0079] 13, in this embodiment, the periods of the rising times T0A, T0B, and T0C, which are the first group of periods with shorter periods, are set before the periods of the rising times T0D, T0E, and T0F, which are the second group of periods with longer periods, respectively. Furthermore, during the periods of the rising times T0D, T0E, and T0F, which are the second group of periods with longer periods, the control signal XRST is masked and not generated.

[0080] With this setting, for example, when a photon is incident at incident timing 122 in the cycle of time point T0B, the potential Vk3 is maintained in a state where it has dropped to a predetermined potential even in the cycle of rising time point T0F. As a result, when the control signal CLIP is input to the pixel 300, the pulse signal PLS is generated even in the cycle of rising time point T0F, which is the second group of cycles with a longer period.

[0081] On the other hand, if no photons are incident in the period of time T0A, for example, the potential Vk3 is maintained at the reference potential. As a result, in the period of the next rising time T0E, when a photon is incident at the incidence timing 121, the potential Vk3 drops to a predetermined potential. Therefore, in the period of the next rising time T0E, a pulse signal PLS is generated. On the other hand, if no photons are incident in the period of the next rising time T0E, the potential Vk3 is maintained at the reference potential, and the pulse signal PLS is not generated.

[0082] Thus, when photons are incident during the period of rising points T0A, T0B, and T0C, which is the first group on the short side of the cycle, the potential Vk3 drops to a predetermined potential, and this state is maintained during the period of rising points T0D, T0E, and T0F, which is the second group on the long side of the cycle. As a result, when the control signal CLIP is input to the pixel 300 during the period of rising points T0D, T0E, and T0F, which is the second group on the long side of the cycle, the pulse signal PLS is generated. In other words, during the period of rising points T0D, T0E, and T0F, which is the second group on the long side of the cycle, if photons were incident on the pixel 300 during the previous period, the pulse signal PLS is generated even when the control signal XRST is masked. With this setting, when photons are incident during the period before the long cycle, recharging is not performed, and the pulse signal PLS is output even during the long cycle, and counting is performed twice.

[0083] As described above, according to this embodiment, a short measurement period is set before a long measurement period, and recharge is not performed during the long measurement period. As a result, if the ratio of the short period to the long period is sufficiently large, when photons are incident during the short period, photons are also incident during the long period, resulting in the same count value as in the comparative example. Furthermore, if photons are incident only during the long period, one detection pulse is output, just as in the case where recharge is not reduced. Therefore, in cases where photons are incident frequently, a control operation is performed to reduce the number of recharges, thereby reducing power consumption.

[0084] Third Embodiment The imaging device 100 according to the third embodiment differs from the imaging device 100 according to the first embodiment in that it may further include a pulse generating unit 215 that can generate a control pulse according to a set value. The differences from the imaging device 100 according to the first embodiment will be described below.

[0085] The pulse generating unit 215 according to the third embodiment will be described with reference to FIGS. 14 and 15. FIG. 14 is a block diagram showing an example of the configuration of the pulse generating unit 215 according to the third embodiment. As shown in FIG. 14, the pulse generating unit 215 has a basic period setting unit 400, a period setting unit 410, and a pulse generating unit 420. The basic period setting unit 400 generates a basic period pulse. The basic period setting unit 400 has a basic signal counter (Base_Sig_Counter) circuit 402 and a basic signal generating circuit 404. The pulse generating unit 215 is configured within the control circuit 210, for example.

[0086] The cycle setting section 410 generates a recharge cycle pulse in accordance with the measurement cycle in the cycle order of the sequence setting register 262. The cycle setting section 410 includes a cycle counter (Cycle_Counter) circuit 412.

[0087] The pulse generating section 420 generates a control signal XRST as a control pulse, and includes a clock gate (CLK GATE) circuit 422 and a generated pulse counter (PG_Counter) circuit 424.

[0088] 15 is a timing chart of signals generated by the pulse generating unit 215. From the top, there are shown a basic signal counter, a basic periodic pulse, a periodic counter, a recharge periodic pulse, a pulse clock valid signal, a pulse counter, and a control pulse.

[0089] 15, the basic signal counter circuit 402 generates a basic signal counter, which is a count value defined by the register setting of the period setting register 260. The basic signal generation circuit 404 generates a basic period pulse with the same period by repeating the operation of generating pulses in accordance with the basic signal counter generated by the basic signal counter circuit 402.

[0090] The cycle counter circuit 412 of the cycle setting unit 410 generates a cycle counter, which is a count value, in accordance with the measurement cycle in the cycle order of the sequence setting register 262. Then, when the cycle counter reaches the measurement cycle in the cycle order, the cycle counter circuit 412 generates a recharge cycle pulse.

[0091] The clock gate circuit 422 of the pulse generating unit 420 generates a pulse clock enable signal that causes a clock to be input to the generated pulse counter circuit 424 only for a certain period from the recharge period pulse generated by the cycle counter circuit 412. At this time, the CLK is controlled to reach the pulse generating unit 420 only for a certain period from the recharge period pulse.

[0092] The generated pulse counter circuit 424 of the pulse generating unit 420 counts the recharge period pulses during the valid period of the pulse clock valid signal to generate a pulse counter value. When the pulse counter reaches a predetermined value, the generated pulse counter circuit 424 generates a control pulse, the control signal XRST. That is, the generated pulse counter circuit 424 generates a control pulse by raising or lowering the pulse when the counter value reaches the value of the falling edge or rising edge of the pulse. In this way, the clock gate circuit 422 counts only the recharge period pulses according to the measurement period in the cycle order of the sequence setting register 262 to generate the control signal XRST. This allows for a reduction in the number of register bits, circuit size, and power consumption in the generating circuit unit.

[0093] Fourth Embodiment An imaging device 100 according to a fourth embodiment differs from the imaging device 100 according to the third embodiment in that it may include a plurality of period setting units 410 capable of generating control pulses according to set values ​​for each pixel group, and a plurality of pulse generating units 420. The differences from the imaging device 100 according to the third embodiment will be described below.

[0094] 16 is a block diagram showing the relationship between the multiple cycle counter circuits 412a-412d, the multiple generation pulse counter circuits 414a-414d, the clock gate circuits 422a-422d, and the pixel group 500 within the control circuit 210. As shown in FIG. 16, the pixel array section 220 has multiple red pixels 300A, multiple green pixels 300B and 300C, and multiple blue pixels 300D. The red pixels 300A, the green pixels 300B and 300C, and the blue pixels 300D constitute a pixel group 500 in a Bayer array. The pixel array section 220 has the pixel group 500 in a matrix. The red pixels 300A are imaged through a red filter, the green pixels 300B and 300C are imaged through a green filter, and the blue pixel 300D is imaged through a blue filter.

[0095] The control circuit 210 also includes a cycle counter (Cycle_CounterA) circuit 412a, a clock gate (CLK GATE) circuit 422a, and a generation pulse counter circuit (PG_CounterA) 424a for the multiple red pixels 300A. Similarly, the control circuit 210 also includes a cycle counter (Cycle_CounterB) circuit 412b, a clock gate (CLK GATE) circuit 422b, and a generation pulse counter circuit (PG_CounterB) 424b for the multiple green pixels 300B. Similarly, the control circuit 210 also includes a cycle counter (Cycle_CounterC) circuit 412c, a clock gate (CLK GATE) circuit 422c, and a generation pulse counter circuit (PG_CounterC) 424c for the multiple green pixels 300C. Similarly, the blue pixels 300D include a cycle counter (Cycle_Counter D) circuit 412d, a clock gate (CLK GATE) circuit 422d, and a generated pulse counter circuit (PG_Counter D) 424d.

[0096] The sequence setting register 262 (see FIG. 2) has set therein a measurement period in cyclic order for a plurality of red pixels 300A, a measurement period in cyclic order for a plurality of green pixels 300B, a measurement period in cyclic order for a plurality of green pixels 300C, and a measurement period in cyclic order for a plurality of blue pixels 300D.

[0097] This configuration makes it possible to control the multiple red pixels 300A, the multiple green pixels 300B, the multiple green pixels 300C, and the multiple blue pixels 300D at different measurement cycles. The same color pixels are driven at the same time, while different colors are driven at different timings. This allows the input / output characteristics to be changed for each color, making it possible to correct sensitivity differences between colors.

[0098] Fifth Embodiment An image capturing apparatus 100 according to a fifth embodiment differs from the image capturing apparatus 100 according to the fourth embodiment in that it is possible to add up the count numbers of pulses detected by four pixels of a pixel group 500 in a Bayer array. The differences from the image capturing apparatus 100 according to the fourth embodiment will be described below.

[0099] 17 is a diagram showing an example of the configuration of four pixels in a Bayer array pixel group 500. Each Bayer array pixel group 500 (see FIG. 16) further includes an OR circuit 342 and four multiplexers 344A, 344B, 344C, and 344D. The outputs of the light receiving unit 310A of the red pixel 300A, the light receiving unit 310B of the green pixel 300B, the light receiving unit 310C of the green pixel 300C, and the light receiving unit 310D of the blue pixel 300D are connected to four connection terminals of the OR circuit 342.

[0100] The output terminal of the light receiving unit 310A and the output terminal of the OR circuit 342 are connected to the input terminal of a multiplexer 344A. The output terminal of the multiplexer 344A is connected to one input terminal of a multiplexer 344B via a counter 350A. The output terminal of the light receiving unit 310B is connected to the other input terminal of the multiplexer 344B.

[0101] Similarly, the output terminal of the multiplexer 344B is connected to one input terminal of the multiplexer 344C via the counter 350B. The output terminal of the light receiving unit 310C is connected to the other input terminal of the multiplexer 344C.

[0102] Similarly, the output terminal of multiplexer 344C is connected to one input terminal of multiplexer 344D via counter 350C. The output terminal of light receiving unit 310D is connected to the other input terminal of multiplexer 344D. The output terminal of multiplexer 344D is connected to counter 350D and is connected to signal processing unit 230 via a connection switch.

[0103] 18 is a time chart showing an example of the operation of four pixels in the Bayer array pixel group 500. From the top, the chart shows the control signal XRST_A, control signal CLIP_A, pulse signal PLS_A, and potential Vk3_A of the red pixel 300A. Next, from the top, the chart shows the control signal XRST_B, control signal CLIP_B, pulse signal PLS_B, and potential Vk3_B of the green pixel 300B. Next, from the top, the chart shows the control signal XRST_C, control signal CLIP_C, pulse signal PLS_C, and potential Vk3_C of the green pixel 300C. Next, from the top, the chart shows the control signal XRST_D, control signal CLIP_D, pulse signal PLS_D, potential Vk3_D, and output of the counter 350D of the blue pixel 300D.

[0104] 18 , a pulse signal PLS_A is generated in response to fluctuations in potential Vk3_A, a pulse signal PLS_B is generated in response to fluctuations in potential Vk3_B, a pulse signal PLS_C is generated in response to fluctuations in potential Vk3_C, and a pulse signal PLS_D is generated in response to fluctuations in potential Vk3_D. The output PLS_OR of the OR circuit 342 is thus the logical sum of the pulse signals PLS_A, PLS_B, PLS_C, and PLS_D.

[0105] 17 , when a 0 signal is input to the multiplexers 344A, 344B, 344C, and 344D, the counters 350A, B, C, and D count the pulse signals PLS_A, PLS_B, PLS_C, and PLS_D, respectively. On the other hand, when a 1 signal is input to the multiplexers 344A, 344B, 344C, and 344D, the counters 350A, B, C, and D count the output PLS_OR of the OR circuit 342. In this way, by changing the timing at which pulses are detected for every four pixels of the pixel group 500, it is possible to perform an addition operation with a simple circuit configuration.

[0106] <Application to a Mobile Body> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0107] FIG. 19 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0108] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 19, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0109] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0110] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0111] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0112] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0113] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0114] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0115] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0116] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0117] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 19, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0118] FIG. 20 is a diagram showing an example of the installation position of the imaging unit 12031.

[0119] In FIG. 20, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0120] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0121] 20 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0122] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0123] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0124] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0125] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0126] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the image capture unit 12031 and the like among the components described above.

[0127] The present technology can be configured as follows:

[0128] (1) A photodetector element comprising: a pixel array section in which a plurality of pixels are arranged in a matrix; and a control circuit that controls the plurality of pixels, wherein the pixels each have: a photoelectric conversion section in which a cathode potential varies in response to incidence of a photon; a detection circuit that generates a pulse signal when the cathode potential varies from an initial value; a recharge circuit that outputs the cathode potential to the detection circuit based on the input timing of a control signal output from the control circuit, and resets the cathode potential to the initial value; and a count circuit that counts the number of the pulse signals, wherein the control circuit is configured to be able to change a period, which is the interval between output timings of the control signal, for each output timing.

[0129] (2) The photodetector element according to (1), further comprising: a period setting register in which a plurality of different periods are set; and an order setting register that sets the order in which the periods are set; and the control circuit outputs the control signal in accordance with the period setting order set by the order setting register.

[0130] (3) The photodetector element according to (2), wherein the sequence setting register is capable of setting the cycles in a different sequence for each row of the pixel array unit.

[0131] (4) The photodetector element according to (2) or (3), wherein the sequence setting register is set for each column of the pixel array unit so that output periods of control signals do not overlap.

[0132] (5) The photodetector element according to (2) or (3), wherein the sequence setting register randomly sets the period.

[0133] (6) The photodetector element according to (2) or (3), wherein the order setting register is set in order so that the lengths of successive periods alternate in successive periods.

[0134] (7) The light detection element according to (2) or (3), wherein the control signals include a first control signal that causes the detection circuit to output the cathode potential and a second control signal that causes the cathode potential to be set to the initial value, and further includes a mask circuit that stops output of at least one of the first control signal and the second control signal to the pixel.

[0135] (8) The photodetector element according to (7), wherein the cycle setting register is capable of mask setting to stop output of at least one of the first control signal and the second control signal for each cycle.

[0136] (9) The photodetector element according to (8), wherein, when the order setting register is set in order so that the lengths of consecutive periods alternate between long and short, the period setting register is set to a mask setting that stops the second control signal on the long period side.

[0137] (10) The photodetector element according to (9), wherein a different periodic order is set in the order setting register for each pixel group in the same row.

[0138] (11) The photodetector element according to (9) or (10), wherein color filters of different colors are arranged in the plurality of pixels, and a periodic order is set for each of the different colors in the order setting register.

[0139] (12) The photodetector element according to (11), wherein color filters of different colors are arranged in a plurality of pixels in the same row of the pixel array unit, and a periodic order is set for each different color in the order setting register.

[0140] (13) The light detection element described in (12), wherein the control circuit further includes: a basic period setting unit that generates a basic period pulse; a period setting unit that generates a recharge period pulse based on the basic period pulse in accordance with the period order of the order setting register; and a pulse generating unit that generates the second control signal based on the recharge period pulse.

[0141] (14) The photodetector element according to (13), which has a plurality of the period setting units and generates recharge periodic pulses in accordance with a plurality of period orders.

[0142] (15) The photodetector element according to (14), wherein the cycle setting unit is capable of outputting the recharge cycle pulse to a plurality of the pulse generating units.

[0143] (16) The photodetector element described in (15), wherein the basic period setting unit includes: a basic signal counter circuit that generates a basic signal counter that is a count value defined by the register setting of the period setting register; and a basic signal generation circuit that generates a basic period pulse with the same period by repeating the operation of generating a pulse according to the basic signal counter generated by the basic signal counter circuit.

[0144] (17) The photodetector element according to (16), wherein the period setting unit has a cycle counter circuit that generates a period counter, which is a count value, according to the period order of the order setting register, and generates the recharge period pulse when the counter reaches a period in the period order.

[0145] (18) The photodetector element described in (17), wherein the pulse generating unit includes: a clock gate circuit that generates a pulse clock enable signal that inputs a clock only for a certain period from the recharge period pulse generated by the cycle counter circuit; and a pulse generation counter circuit that counts the recharge period pulses during the valid period of the pulse clock enable signal, generates a pulse counter that is a count value, and generates the second control signal when the pulse counter reaches a predetermined value.

[0146] (19) The photodetector element according to (1), wherein the photoelectric conversion unit is an avalanche photodiode.

[0147] (20) A photodetector comprising: a pixel array unit in which a plurality of pixels are arranged in a matrix; a control circuit for controlling the plurality of pixels; and a recording unit for recording count numbers output by the plurality of pixels, wherein the pixels each have: a photoelectric conversion unit in which a cathode potential varies in response to incidence of a photon; a detection circuit for generating a pulse signal when the cathode potential varies from an initial value; a recharge circuit for outputting the cathode potential to the detection circuit based on an input timing of a control signal output from the control circuit and resetting the cathode potential to the initial value; and a count circuit for counting the number of the pulse signals, wherein the control circuit is configured to be able to change a period, which is the interval between output timings of the control signal, for each output timing.

[0148] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and intent of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

[0149] 100: imaging device, 120: recording unit, 200: solid-state imaging element, 210: control circuit, 220: pixel array unit, 260: cycle setting register, 262: sequence setting register, 300: pixel, 311: SPAD, 320: recharge circuit, 350: counter, 400: basic cycle setting unit, 402: basic signal counter circuit, 410: cycle setting unit, 412: cycle counter circuit, 420: pulse generation unit, 422: clock gate circuit, 424: generated pulse counter circuit

Claims

1. A photodetector element comprising: a pixel array section in which a plurality of pixels are arranged in a matrix; and a control circuit that controls the plurality of pixels, wherein the pixels each have: a photoelectric conversion section in which a cathode potential varies in response to incidence of photons; a detection circuit that generates a pulse signal when the cathode potential varies from an initial value; a recharge circuit that outputs the cathode potential to the detection circuit based on the input timing of a control signal output from the control circuit, and resets the cathode potential to the initial value; and a count circuit that counts the number of pulse signals, wherein the control circuit is configured to be able to change the period, which is the interval between the output timings of the control signals, for each output timing.

2. The photodetector element according to claim 1, further comprising: a period setting register in which a plurality of different periods are set; and an order setting register that sets the order in which the periods are set; and the control circuit outputs the control signal in accordance with the periods in the order set by the order setting register.

3. The photodetector element according to claim 2, wherein the sequence setting register is capable of setting the cycles in a different sequence for each row of the pixel array section.

4. The photodetector element according to claim 2, wherein the sequence setting register is set for each column of the pixel array section so that the output periods of the control signals do not overlap.

5. The photodetector element according to claim 2, wherein the period in the sequence setting register is set randomly.

6. The photodetector element according to claim 2, wherein the sequence setting register is set in sequence so that the lengths of successive periods alternate between long and short periods.

7. The photodetector element of claim 2, wherein the control signals include a first control signal that causes the detection circuit to output the cathode potential and a second control signal that causes the cathode potential to be set to the initial value, and further comprising a mask circuit that stops output of at least one of the first control signal and the second control signal to the pixel.

8. The photodetector element according to claim 7, wherein the cycle setting register is capable of mask setting to stop output of at least one of the first control signal and the second control signal for each cycle.

9. The photodetector element according to claim 8, wherein when the order setting register is set so that the lengths of consecutive periods alternate between long and short, the period setting register is set to a mask setting that stops the second control signal on the long period side.

10. The photodetector element according to claim 9, wherein a different cycle order is set in the order setting register for each pixel group in the same row.

11. The photodetector element according to claim 9, wherein color filters of different colors are arranged in the plurality of pixels, and a periodic order is set for each different color in the order setting register.

12. The photodetector element according to claim 11, wherein color filters of different colors are arranged in a plurality of pixels in the same row of said pixel array section, and a periodic order is set for each different color in said order setting register.

13. The photodetector element according to claim 12, wherein the control circuit further comprises: a basic period setting unit that generates a basic period pulse; a period setting unit that generates a recharge period pulse based on the basic period pulse in accordance with the period order of the sequence setting register; and a pulse generation unit that generates the second control signal based on the recharge period pulse.

14. The photodetector element according to claim 13, which has a plurality of the period setting sections and generates recharge period pulses in accordance with a plurality of period orders.

15. The photodetector element according to claim 14, wherein the cycle setting section is capable of outputting the recharge cycle pulse to a plurality of the pulse generating sections.

16. The photodetector element of claim 15, wherein the basic period setting unit comprises: a basic signal counter circuit that generates a basic signal counter whose count value is specified by the register setting of the period setting register; and a basic signal generation circuit that generates a basic period pulse with the same period by repeating the operation of generating pulses in accordance with the basic signal counter generated by the basic signal counter circuit.

17. The photodetector element according to claim 16, wherein the period setting unit has a cycle counter circuit that generates a period counter, which is a count value, in accordance with the period order of the order setting register, and generates the recharge period pulse when the counter reaches a period in the period order.

18. The photodetector element of claim 17, wherein the pulse generating section comprises: a clock gate circuit that generates a pulse clock enable signal that inputs a clock only for a fixed period from the recharge period pulse generated by the cycle counter circuit; and a pulse generation counter circuit that counts the recharge period pulses during the valid period of the pulse clock enable signal, generates a pulse counter that is a count value, and generates the second control signal when the pulse counter reaches a predetermined value.

19. The photodetector element according to claim 1, wherein the photoelectric conversion section is an avalanche photodiode.

20. A photodetector comprising: a pixel array section in which a plurality of pixels are arranged in a matrix; a control circuit for controlling the plurality of pixels; and a recording section for recording the count numbers output by the plurality of pixels, wherein the pixels each have: a photoelectric conversion section in which a cathode potential varies in response to incidence of photons; a detection circuit for generating a pulse signal when the cathode potential varies from an initial value; a recharge circuit for outputting the cathode potential to the detection circuit based on the input timing of a control signal output from the control circuit and resetting the cathode potential to the initial value; and a count circuit for counting the number of pulse signals, wherein the control circuit is configured to be able to change the period, which is the interval between the output timings of the control signals, for each output timing.

Images