Ceramic circuit substrate comprising unidirectional porous metal layer, and power module equipped with same

Abstract

The present invention provides: a ceramic circuit substrate comprising a unidirectional porous metal layer, which exhibits excellent heat dissipation performance by having a unidirectional porous metal applied thereto; and a power module equipped with the ceramic circuit substrate. The ceramic circuit substrate according to an embodiment of the present invention comprises: a ceramic layer; a substrate copper layer disposed over a first surface of the ceramic layer; a unidirectional porous metal layer disposed over a second surface of the ceramic layer and having a plurality of pores extending unidirectionally in the vertical direction from the ceramic layer; a first active metal brazing layer interposed between the ceramic layer and the substrate copper layer; and a second active metal brazing layer interposed between the ceramic layer and the unidirectional porous metal layer.

Description

Ceramic circuit board including a unidirectional porous metal layer and power module having the same

[0001] The technical idea of ​​the present invention relates to a ceramic circuit board, and more specifically, to a ceramic circuit board including a unidirectional porous metal layer and a power module having the same.

[0002] Higher performance, miniaturization, and weight reduction of electronic devices require higher density and integration of semiconductor packages. However, higher integration generates more heat, which degrades semiconductor device performance and can lead to defects such as substrate deterioration, thereby reducing product reliability and lifespan. In particular, high-voltage power conversion electrical components for eco-friendly automobiles are used in extremely harsh operating environments, including high-temperature heat generation and thermal shock conditions. Therefore, securing more efficient heat-dissipating materials and structures is essential. Therefore, research on heat-dissipating materials and technologies that can effectively dissipate generated heat while improving semiconductor device performance and suppressing degradation of product performance and reliability is increasingly important.

[0003] For example, power conversion semiconductors used in electric vehicles are crucial components for converting, controlling, and transmitting high-voltage and high-current electric power, and the demand for power modules made of power conversion semiconductors continues to grow. Typically, power modules generate significant heat during operation. For example, IGBT devices generate heat due to switching losses during turn-on / turn-off switching, and because they use silicon as their base material, the operating temperature at the junction must be limited to 150°C or less. Therefore, to ensure the reliability of power semiconductor devices and power modules, it is essential to address the heat generation issue of IGBTs, and a cooling method must be developed.

[0004] For example, insulated gate bipolar transistor (IGBT) devices, which are silicon (Si)-based power conversion semiconductors, must not only control the amount of heat generated by switching losses due to frequency changes when power is supplied, but also effectively control the thermal shock that creates the problem of residual stress asymmetry that causes cracks in the power module joints, while effectively controlling the parasitic inductance of the power conversion device. Thermal and electrical materials and manufacturing methods must be developed to effectively control the amount of heat generated by lowering the junction temperature to below 150℃ due to different heat generation conditions according to switching off-state losses and on-state losses.

[0005] In addition, SiC-based MOSFET (metal oxide semiconductor field effect transistor) devices with a wide bandgap compared to silicon (Si)-based devices can be miniaturized compared to IGBT devices, and the devices themselves can be operated without problems even when the operating temperature of the junction is 400℃ or higher. However, in order to secure stable operation reliability of solder and other passive and active devices used for mounting the gate driver board, the junction temperature must be controlled below 200℃, and thermal and electrical materials and manufacturing methods that can resolve the thermal shock slope that causes cracks in the power module junction due to the operation characteristic that the switching frequency is up to 10 times higher than that of the IGBT and the parasitic inductance caused by the high switching frequency must be prepared.

[0006] The technical problem to be achieved by the technical idea of ​​the present invention is to provide a ceramic circuit board including a one-way porous metal layer having excellent heat dissipation performance by applying a one-way porous metal body, and a power module having the same.

[0007] However, these tasks are exemplary and the technical idea of ​​the present invention is not limited thereto.

[0008] According to one aspect of the present invention, a ceramic circuit board including a one-way porous metal layer having excellent heat dissipation performance by applying a one-way porous metal body and a power module having the same are provided.

[0009] According to one embodiment of the present invention, the ceramic circuit board may include: a ceramic layer; a substrate copper layer disposed on a first surface of the ceramic layer; a unidirectional porous metal layer disposed on a second surface of the ceramic layer and having a plurality of pores extending in one direction in a vertical direction from the ceramic layer; a first active metal brazing layer interposed between the ceramic layer and the substrate copper layer; and a second active metal brazing layer interposed between the ceramic layer and the unidirectional porous metal layer.

[0010] According to one embodiment of the present invention, the one-way porous metal layer may have a porosity in the range of 1% by volume to 70% by volume.

[0011] According to one embodiment of the present invention, the one-way porous metal layer may be formed of a metal casting body including copper or a copper alloy and formed using a mold casting method, a continuous melting zone method, a continuous casting method, or a centrifugal casting method.

[0012] According to one embodiment of the present invention, the one-way porous metal layer may be formed of a metal molded body including copper or a copper alloy, and formed by press forming, rolling, and then perforating, laser processing, or selective etching a metal material in the shape of a sheet, plate, sheet, or foil.

[0013] According to one embodiment of the present invention, the present invention may further include a first spacer disposed on a portion of the substrate copper layer; and a second spacer disposed on a portion of the substrate copper layer and having a greater height than the first spacer.

[0014] According to one embodiment of the present invention, at least one of the first spacer and the second spacer may be formed of a unidirectional porous metal body having a plurality of pores extending in one direction in a vertical direction from the substrate copper layer.

[0015] According to one embodiment of the present invention, all or part of the pores of the one-way porous metal layer may be filled with a filler.

[0016] According to one embodiment of the present invention, the substrate copper layer may be composed of a unidirectional porous metal body having a plurality of pores extending in one direction in a vertical direction from the ceramic layer.

[0017] According to one embodiment of the present invention, the power module may include a ceramic circuit board including a ceramic layer, a substrate copper layer, a unidirectional porous metal layer disposed on the ceramic layer and having a plurality of pores extending in one direction in a vertical direction from the ceramic layer, a first active metal brazing layer interposed between the ceramic layer and the substrate copper layer, and a second active metal brazing layer interposed between the ceramic layer and the unidirectional porous metal layer; at least one semiconductor element disposed on the substrate copper layer; and a mold layer covering the semiconductor element.

[0018] According to one embodiment of the present invention, a heat sink may be further included disposed on the one-way porous metal layer.

[0019] According to one embodiment of the present invention, a base plate may be further included disposed on the one-way porous metal layer.

[0020] According to one embodiment of the present invention, all or part of the pores of the one-way porous metal layer may be filled with a filler.

[0021] According to one embodiment of the present invention, the power module comprises: an upper ceramic substrate including an upper ceramic layer, an upper substrate copper layer, and an upper unidirectional porous metal layer disposed on the upper ceramic layer and having a plurality of pores extending in one direction in a vertical direction from the upper ceramic layer, an upper first active metal brazing layer interposed between the upper ceramic layer and the upper substrate copper layer, and an upper second active metal brazing layer interposed between the upper ceramic layer and the upper unidirectional porous metal layer; an upper first spacer disposed on a portion of the upper substrate copper layer; and an upper second spacer disposed on a portion of the upper substrate copper layer and having a greater height than the upper first spacer; A lower ceramic circuit board including a lower ceramic layer, a lower substrate copper layer, and a lower unidirectional porous metal layer disposed on the lower ceramic layer and having a plurality of pores extending in one direction in a vertical direction from the lower ceramic layer, a lower first active metal brazing layer interposed between the lower ceramic layer and the lower substrate copper layer, and a lower second active metal brazing layer interposed between the lower ceramic layer and the lower unidirectional porous metal layer; a first semiconductor element disposed between the upper first spacer and the lower substrate copper layer; a second semiconductor element disposed between the upper second spacer and the lower substrate copper layer and having a thickness smaller than that of the first semiconductor element; and a mold layer filling a space between the upper ceramic circuit board and the lower ceramic circuit board to cover the first semiconductor element and the second semiconductor element.

[0022] According to one embodiment of the present invention, at least one of an upper heat sink disposed on the outside of the upper ceramic circuit board and a lower heat sink disposed on the outside of the lower ceramic circuit board may be further included.

[0023] According to one embodiment of the present invention, at least one of an upper base plate disposed on the upper unidirectional porous metal layer and a lower base plate disposed on the lower unidirectional porous metal layer may be further included.

[0024] According to one embodiment of the present invention, all or part of the pores of the upper one-way porous metal layer may be filled with a filler, and all or part of the pores of the lower one-way porous metal layer may be filled with a filler.

[0025] According to one embodiment of the present invention, the power module comprises: an upper ceramic substrate including an upper ceramic layer, an upper substrate copper layer, and an upper unidirectional porous metal layer disposed on the upper ceramic layer and having a plurality of pores extending in one direction in a vertical direction from the upper ceramic layer; an upper first spacer disposed on a portion of the upper substrate copper layer; and an upper second spacer disposed on a portion of the upper substrate copper layer and having a greater height than the upper first spacer; a lower ceramic substrate including a lower ceramic layer, a lower substrate copper layer, and a lower unidirectional porous metal layer disposed on the lower ceramic layer and having a plurality of pores extending in one direction in a vertical direction from the lower ceramic layer; a lower first spacer disposed on a portion of the lower substrate copper layer; and a lower second spacer disposed on a portion of the lower substrate copper layer and having a greater height than the lower first spacer; It may include a first semiconductor element disposed between the upper first spacer and the lower first spacer; a second semiconductor element disposed between the upper second spacer and the lower second spacer and having a smaller thickness than the first semiconductor element; and a mold layer that fills the space between the upper ceramic circuit board and the lower ceramic circuit board and covers the first semiconductor element and the second semiconductor element.

[0026] According to one embodiment of the present invention, at least one of an upper heat sink disposed on the outside of the upper ceramic circuit board and a lower heat sink disposed on the outside of the lower ceramic circuit board may be further included.

[0027] According to one embodiment of the present invention, at least one of an upper base plate disposed on the upper unidirectional porous metal layer and a lower base plate disposed on the lower unidirectional porous metal layer may be further included.

[0028] According to one embodiment of the present invention, all or part of the pores of the upper one-way porous metal layer may be filled with a filler, and all or part of the pores of the lower one-way porous metal layer may be filled with a filler.

[0029] The ceramic circuit board according to the present invention can mitigate various mechanical shocks caused by differences in thermal expansion coefficients between dissimilar materials by forming the lower copper layer of the AMB type board as a unidirectional porous metal body.

[0030] The AMB type substrate to which this unidirectional porous metal body is applied can use the manufacturing process of conventional power modules, and can increase the reliability of the joint by reducing the elastic modulus while maintaining the thermal cooling performance and alleviating the horizontal residual stress, and can improve the switching frequency of the power conversion semiconductor to reduce switching loss and improve the cooling efficiency due to the reduction in thermal resistance, which not only improves the efficiency and reliability of the power conversion module but also lowers the temperature of the bus bar connected to the motor and the DC-link film capacitor, thereby improving the efficiency of the entire high-voltage power conversion system. In addition, the unidirectional pores can be controlled by methods such as press forming, perforation after rolling, laser processing or selective etching.

[0031] In addition, the problem of deterioration of thermal control characteristics due to cracks and pores in case of high switching frequency operation due to the difference in elastic modulus between ceramic and copper in the conventional copper plate type AMB bonding method can be fundamentally solved.

[0032] The effects of the present invention described above are illustrative, and the scope of the present invention is not limited by these effects.

[0033] FIG. 1 is a top view illustrating a unidirectional porous metal body applied to a ceramic circuit board according to one embodiment of the present invention.

[0034] FIG. 2 is a cross-sectional view taken along line AA of the one-way porous metal body of FIG. 1 according to one embodiment of the present invention.

[0035] Figures 3 and 4 are cross-sectional views of a ceramic circuit board according to one embodiment of the present invention.

[0036] FIG. 5 is a cross-sectional view illustrating a cross-sectional cooling power module according to one embodiment of the present invention.

[0037] Figures 6 and 7 are cross-sectional views illustrating a double-sided cooling power module according to one embodiment of the present invention.

[0038] FIG. 8 is a cross-sectional view illustrating a case where the pores of a unidirectional porous metal layer applied to a ceramic circuit board and power module according to one embodiment of the present invention are filled with a filler.

[0039] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. Embodiments of the present invention are provided to more completely explain the technical idea of ​​the present invention to those skilled in the art. The following embodiments may be modified in various different forms, and the scope of the technical idea of ​​the present invention is not limited to the following embodiments. Rather, these embodiments are provided to more faithfully and completely convey the technical idea of ​​the present invention to those skilled in the art. Like reference numerals throughout this specification denote like elements. Furthermore, various elements and areas in the drawings are schematically drawn. Therefore, the technical idea of ​​the present invention is not limited by the relative sizes or intervals drawn in the attached drawings.

[0040] In this specification, a layer formed "on" another layer may refer to a layer formed directly above the other layer, or may refer to an intermediate layer or layers formed on another layer. It should be noted that the meanings of "upper" and "lower" in this specification are relative, and the direction upward from the ceramic substrate is described as "upper", and the direction downward is described as "lower."

[0041] In the rapidly growing electric vehicle market, power semiconductors are used to variably control the AC voltage and frequency required to drive a three-phase AC motor from the power source, a high-voltage DC battery. Materials and designs that ensure the reliability of power modules in power conversion semiconductors are crucial. This is because both silicon-based IGBTs and SiC-based MOSFETs require control of the junction temperature generated during variable voltage and frequency switching. Furthermore, the heat generated from power conversion semiconductors can induce thermal and mechanical stresses on the solder, passive components, and other active components that make up the package, potentially leading to joint failure and deterioration due to thermal fatigue. Furthermore, high-frequency switching to accommodate the high-speed rotation of the motor can generate thermal shock and parasitic inductance. Therefore, thermal and electrical materials and manufacturing technologies that can effectively control these factors are crucial.

[0042] Recently, with the emergence of wide bandgap power modules such as SiC or GaN, they have higher operating temperatures than conventional silicon-based power modules. To improve heat dissipation of power modules, a double-sided cooling structure has been adopted. In conventional single-sided cooling power modules, the heat dissipation path of the semiconductor device is limited to one direction, whereas a double-sided cooling power module has an upper and lower substrate placed above and below the semiconductor device, which expands the heat dissipation path in two directions and improves heat dissipation capacity. Double-sided cooling structure, planar packaging structure, plate bonded power module, and metal-post interconnected parallel plate structure (MPIPPS) are terms that refer to double-sided cooling structures.

[0043] To maintain the high current / voltage and excellent heat dissipation characteristics described above, the bonding technology of power modules also plays a crucial role. Substrates for bonding power semiconductor devices include direct bonding copper (DBC) substrates and active metal brazing (AMB) substrates. DBC substrates are formed by directly bonding a copper (Cu) layer with an oxide film formed on a ceramic layer using eutectic bonding. However, because ceramics have low wettability with metals, pores can form at the bonding interface between the ceramic and copper, and cracks can easily form and propagate from these pores due to repeated stress.

[0044] To address these issues, a method has been introduced for manufacturing substrates using the AMB method, which utilizes active metals such as titanium (Ti) and chromium (Cr). Compared to DBC substrates bonded using conventional bonding processes, AMB substrates exhibit lower electrical resistance and superior electrical conductivity, minimizing power loss and enabling efficient connections. Furthermore, since bonding occurs at a relatively low temperature of around 800°C, power module components are protected from exposure to high temperatures.

[0045] Despite these advancements, the AMB substrate utilizes a bond between dissimilar materials—ceramic and copper—and thus can generate mechanical thermal stress when heat is applied due to differences in their coefficients of thermal expansion. Because the difference in coefficients of thermal expansion between ceramic and copper is significant, heat generated during power module operation can lead to problems such as cracking or weakening of the joint.

[0046] Therefore, the technical idea of ​​the present invention is to apply a unidirectional porous metal body to an AMB substrate to reduce thermal stress and, in particular, to solve the problem of residual stress in the vertical direction. The unidirectional porous metal body refers to a metal in which cylindrical pores are arranged in one direction. Unlike existing isotropic porous metals, the material has the characteristic of exhibiting anisotropy in its properties. In particular, it has the advantage of excellent heat transfer performance in the pore direction and a thermal stress relief effect. The unidirectional porous metal body has a Young's modulus of about 1 / 10 that of general bulk copper, and can also reduce residual stress to about 1 / 10.

[0047] Thermal shock cycle test results show that bulk copper exhibits higher shear strength during the first cycle, but this decreases rapidly with increasing cycling. After approximately five cycles, the shear strength of the unidirectional porous metal material becomes higher and remains high thereafter. Therefore, the low elastic modulus of the unidirectional porous metal material is interpreted as alleviating residual stresses when heated.

[0048] In addition, the copper-based unidirectional porous metal body with a porosity of 40% has an elastic modulus of about 30 GPa, which is about 1 / 4 that of a copper plate without pores. The target thickness of the unidirectional porous metal body may be about 1 / 3 that of the copper plate. The unidirectional porous metal body with a reduced thickness can reduce horizontal residual stress due to the difference in thermal expansion coefficient. As a result, the cooling performance is improved, and the problem of cracking at the joint interface due to the difference in tensile and compressive residual stress when manufacturing a thin plate and the problem of reduced joint strength that is vulnerable to mechanical vibration can be solved. In addition, the parasitic inductance can be reduced at a high switching frequency, thereby improving switching efficiency and overall system efficiency.

[0049] Solder or adhesive may be used as a bonding material for bonding various components such as semiconductor devices, or, for example, Ag based filler sintering or transient liquid phase bonding may be applied to wide bandgap power modules.

[0050] Hereinafter, a one-way porous metal body according to the technical idea of ​​the present invention will be described in detail.

[0051] FIG. 1 is a top view illustrating a unidirectional porous metal body applied to a ceramic circuit board according to one embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line AA of the unidirectional porous metal body of FIG. 1 according to one embodiment of the present invention.

[0052] Referring to FIGS. 1 and 2, the unidirectional porous metal body (1) has a metal body (2) and a plurality of unidirectional pores (2) formed to extend along a pore extending direction within the metal body (2). The unidirectional porous metal body (1) may be referred to as a lotus structure. The unidirectional pores (3) may be formed to a depth that penetrates the metal body (2) or may be formed to a depth that does not penetrate the metal body (2).

[0053] The unidirectional porous metal body (1) can exhibit anisotropic properties, unlike conventional porous metals that include pores in an isotropic manner, since it includes unidirectional pores (3) arranged in one direction. In particular, it has excellent heat transfer performance in the pore direction and a thermal stress relief effect.

[0054] The manufacturing method for forming a one-way porous metal body (1) can be carried out in various ways. For example, in the case of a casting method, there are a mold casting method, a continuous melt zone method, a continuous casting method, a centrifugal casting method, etc., and in the case of a forming method, there are press forming, rolling, perforation, laser processing, or selective etching of a metal material in the shape of a sheet, plate, sheet, or foil.

[0055] The one-way porous metal body (1) can be formed as a metal casting body using a mold casting method, a continuous melting zone method, a continuous casting method, or a centrifugal casting method.

[0056] Alternatively, the one-way porous metal body (1) may be formed as a metal molded body formed by using press forming, rolling, and then perforating, laser processing, or selective etching of a metal material in the shape of a sheet, plate, sheet, or foil.

[0057] The pore characteristics of a unidirectional porous metal body (1) of a casting method can be controlled by the pressure of the injected hydrogen gas, the solidification speed, etc. As the hydrogen gas pressure and the solidification speed increase, the porosity and pore size can decrease. The unidirectional porous metal body (1) can have a porosity in the range of, for example, 1 vol% to 70 vol%.

[0058] A unidirectional porous metal body (1) refers to a metal in which cylindrical pores are arranged in one direction. In addition, if necessary, the unidirectional porous metal body can be utilized as a composite material composed of other materials.

[0059] A unidirectional porous metal body (1) is a form in which unidirectional pores are contained within the metal. It has the characteristic of anisotropic thermal, electrical, and mechanical properties. This anisotropic characteristic is what differentiates it from other porous metals. For example, the unidirectional porous metal body (1) may have anisotropic elastic modulus, thermal conductivity, and electrical conductivity.

[0060] The one-way porous metal body (1) may include various metals, for example, copper or a copper alloy.

[0061] Table 1 shows the anisotropic thermal, electrical, and mechanical properties of a unidirectional porous metal body (1) composed of copper according to the porosity. In Table 1, “∥” means a direction parallel to the extension direction of the pores, and “⊥” means a direction parallel to the extension direction of the pores.

[0062] Porosity (%)Elasticity modulus (GPa)Thermal conductivity (W / mK)Electrical conductivity (x10 6 Ω -1 m -1 )E ∥ E ⊥ K ∥ K ⊥ σ ∥ σ ⊥0759534034015.015.01067~7480~9430527013.512.02060~6660~7927022012.09.73052~5943~5923517010.57.84045~5130~422001409.05.25037~4420~291651207.54.06030~3613~19130806.02.27022~298~1295504.51.28015~214~760303.00.7

[0063] Referring to Table 1, the elastic modulus, thermal conductivity, and electrical conductivity of a unidirectional porous metal body (1) composed of copper decrease as the porosity increases. In addition, the elastic modulus, thermal conductivity, and electrical conductivity exhibit anisotropy in that they decrease more in the vertical direction than in the direction parallel to the extension direction of the pores as the porosity increases.

[0064] When comparing a copper structure without pores and a unidirectional porous metal body composed of copper, their coefficients of thermal expansion are almost the same. On the other hand, the thermal stress of the unidirectional porous metal body composed of copper is significantly reduced for the same strain, so that mechanical thermal stress can be alleviated. In addition, since the elastic modulus of the unidirectional porous metal body in both the vertical and horizontal directions decreases with respect to external stress, the shock absorption capacity can be improved. Although the thermal conductivity and electrical conductivity of the unidirectional porous metal body composed of copper decrease as the porosity increases, they are higher than those of molybdenum.

[0065] The unidirectional porous metal body described above can hinder the propagation path of cracks occurring at the joint through the pores provided therein. When a crack propagating along the interface encounters the pores, the direction of the path changes, thereby increasing the joint strength.

[0066] By inserting other materials into the pores of the above-mentioned one-way porous metal body, the properties of a composite material can be obtained. Accordingly, properties such as elastic modulus, thermal conductivity, electrical conductivity, and parasitic inductance can be changed, and if necessary, improved.

[0067] Figures 3 and 4 are cross-sectional views of a ceramic circuit board according to one embodiment of the present invention.

[0068] Referring to FIG. 3, the ceramic circuit board (200) may include a ceramic substrate (210).

[0069] Referring to FIG. 4, the ceramic circuit board (200a) may include a ceramic substrate (210), a first spacer (220), and a second spacer (230).

[0070] Hereinafter, components of the ceramic circuit board will be described in detail with reference to FIGS. 3 and 4.

[0071] The ceramic substrate (210) may include a ceramic layer (211), a substrate copper layer (212), a unidirectional porous metal layer (213), a first active metal brazing layer (214), and a second active metal brazing layer (215).

[0072] The ceramic layer (211) may have a first surface (218) and a second surface (219) that face each other. In FIGS. 3 and 4 , the first surface (218) is illustrated as the upper surface and the second surface (219) is illustrated as the lower surface of the ceramic layer (211). The ceramic layer (211) may have excellent thermal conductivity and electrical insulation. The ceramic layer (211) may be formed of a ceramic material, and may include, for example, at least one of Al2O3, AlN, Zirconia Toughened Alumina (ZTA), and Si3N4.

[0073] A substrate copper layer (212) may be disposed on a first surface (218) of a ceramic layer (211). The substrate copper layer (212) may be patterned to function as a circuit structure for a semiconductor device. The substrate copper layer (212) may be formed as a single layer or may be formed as a plurality of layers. The substrate copper layer (212) may include copper or a copper alloy. The substrate copper layer (212) may have a total thickness in the range of, for example, 100 μm to 1000 μm, and may have a total thickness of, for example, about 300 μm.

[0074] The unidirectional porous metal layer (213) may be disposed on a second surface (219) opposite to the first surface (218) of the ceramic layer (211). The unidirectional porous metal layer (213) may function as a warpage prevention layer that prevents the ceramic layer (211) from warping. In addition, the unidirectional porous metal layer (213) may provide a path for dissipating heat generated from the semiconductor element to the outside. For this purpose, a heat dissipation structure may be attached to the unidirectional porous metal layer (213). The unidirectional porous metal layer (213) may have a total thickness of, for example, 100 μm to 1000 μm, and may have a total thickness of, for example, about 300 μm.

[0075] The unidirectional porous metal layer (213) may be composed of a unidirectional porous metal (UPM) having a plurality of unidirectional pores extending vertically from the ceramic layer (211). The unidirectional porous metal layer (213) may have a porosity in the range of 1% to 70% by volume. The unidirectional porous metal layer (213) may be formed of a metal casting, or may be manufactured by various methods such as press molding and laser processing. The unidirectional porous metal layer (213) may be formed of copper or a copper alloy. However, these materials are exemplary and the technical idea of ​​the present invention is not limited thereto.

[0076] In addition, the substrate copper layer (212) may be composed of a unidirectional porous metal body constituting a unidirectional porous metal body layer (213), and may be composed of a unidirectional porous metal body having a plurality of unidirectional pores extending in a vertical direction from the ceramic layer (211).

[0077] The substrate copper layer (212) may be formed of an active metal brazing (AMB) copper layer formed using an AMB technique. The AMB technique may refer to a technique of bonding a ceramic layer and a copper layer using an active metal foil. An active metal foil and a copper foil are sequentially placed on a first surface (218) of the ceramic layer (211), and heated to melt the active metal foil, thereby bonding the ceramic layer (211) and the copper foil to each other by forming a first active metal brazing layer (214). The first active metal brazing layer (214) may serve to bond the ceramic layer (211) and the substrate copper layer (212). Subsequently, if necessary, the substrate copper layer (212) may be patterned using an etching process.

[0078] In addition, the one-way porous metal layer (213) sequentially arranges an active metal foil and a one-way porous metal body on the second surface (219) of the ceramic layer (211), heats the active metal foil to melt it, and forms a second active metal brazing layer (215), thereby bonding the ceramic layer (211) and the one-way porous metal body to each other. The second active metal brazing layer (215) can serve to bond the ceramic layer (211) and the one-way porous metal body layer (213).

[0079] The first active metal brazing layer (214) and the second active metal brazing layer (215) may include a metal or metal alloy having a lower melting point than the copper constituting the copper foil and the one-way porous metal body, and may include, for example, an active metal alloy in which copper, aluminum, nickel, or silver is added to titanium, hafnium, nickel, molybdenum, or zirconium, which are active toward oxygen, to reduce the melting point. The first active metal brazing layer (214) and the second active metal brazing layer (215) may include, for example, an alloy including at least one of silver (Ag), copper (Cu), and titanium (Ti). However, this is exemplary, and the first active metal brazing layer (214) and the second active metal brazing layer (215) may include at least one of aluminum (Al), titanium (Ti), nickel (Ni), niobium (Nb), and molybdenum (Mo).

[0080] As illustrated in FIG. 4, the first active metal brazing layer (214) may be disposed on the first surface (218) of the ceramic layer (211). The substrate copper layer (212) may be disposed on the first active metal brazing layer (214). That is, the first active metal brazing layer (214) may be interposed between the ceramic layer (211) and the substrate copper layer (212), thereby bonding the ceramic layer (211) and the substrate copper layer (212) to each other.

[0081] The second active metal brazing layer (215) may be disposed on the second surface (219) of the ceramic layer (211). The unidirectional porous metal layer (213) may be disposed on the second active metal brazing layer (215). That is, the second active metal brazing layer (215) is interposed between the ceramic layer (211) and the unidirectional porous metal layer (213), thereby bonding the ceramic layer (211) and the unidirectional porous metal layer (213) to each other.

[0082] In addition, a case where the substrate copper layer (212) is composed of a unidirectional porous metal body is also included in the technical idea of ​​the present invention.

[0083] Referring to FIG. 4, the first spacer (220) may be placed on a portion of the ceramic substrate (210), for example, on a portion of the substrate copper layer (212). The first spacer (220) may be bonded to the substrate copper layer (212) by a first spacer adhesive layer (222).

[0084] The first spacer (220) may have a first height. The first spacers (220) may be arranged in multiples, and may all have substantially the same height. The first height may refer to the height from the ceramic substrate (210), for example, the height from the substrate copper layer (212).

[0085] The second spacer (230) may be placed on a portion of the ceramic substrate (210), for example, on a portion of the substrate copper layer (212). The second spacer (230) may be bonded to the substrate copper layer (212) by a second spacer adhesive layer (232).

[0086] The second spacer (230) may have a greater height than the first spacer (220), for example, may have a second height greater than the first height. The second spacers (230) may be arranged in multiples, and may all have substantially the same height. The second height may refer to the height from the ceramic substrate (210), for example, the height from the substrate copper layer (212).

[0087] The first spacer (220) and the second spacer (230) can provide a space for mounting a semiconductor element and can perform the function of a spacer for correcting a thickness deviation of the semiconductor element. The height at which the semiconductor element is mounted can be changed by the arrangement of the first spacer (220) and the second spacer (230). That is, as the first spacer (220) is arranged in some areas of the ceramic substrate (210) and the second spacer (230) is arranged in other areas of the ceramic substrate (210), the mounting height provided by the second spacer (230) can be greater than the mounting height provided by the first spacer (220). Accordingly, the thickness deviation of semiconductor elements having different thicknesses can be corrected. Here, the semiconductor devices placed on the first spacer (220) and the second spacer (230) may include various semiconductor devices such as power semiconductor devices, memory semiconductor devices, switching semiconductor devices, and diode semiconductor devices.

[0088] The first spacer (220) and the second spacer (230) may have the same planar area or different planar areas, which may have various planar areas corresponding to the semiconductor elements to be mounted.

[0089] Additionally, at least one of the first spacer (220) and the second spacer (230) may additionally perform the function of wiring that provides an electrical path to the semiconductor element.

[0090] The first spacer (220) and the second spacer (230) may be formed of a metal working material that does not include pores inside, such as a copper structure, a copper molybdenum alloy structure, etc.

[0091] Alternatively, at least one of the first spacer (220) and the second spacer (230) may be formed of a unidirectional porous metal (UPM) having a plurality of unidirectional pores extending in one direction from the substrate copper layer (212). The first spacer (220) and the second spacer (230) may be formed of a metal casting, or may be manufactured by various methods such as press forming and laser processing. The first spacer (220) and the second spacer (230) may include copper or a copper alloy. However, this is merely exemplary, and the technical idea of ​​the present invention is not limited thereto.

[0092] The first spacer (220) may have a plurality of pores extending in one direction in a vertical direction from the ceramic substrate (210), for example, from the substrate copper layer (212). The first spacer (220) may have a porosity in a range of, for example, 1% to 70% by volume. The second spacer (230) may have a plurality of pores extending in one direction in a vertical direction from the ceramic substrate (210), for example, from the substrate copper layer (212). The second spacer (230) may have a porosity in a range of, for example, 1% to 70% by volume.

[0093] When the first spacer (220) and the second spacer (230) are formed of a metal processing material that does not contain pores inside, the porosity is approximately 0%, so they can have high thermal stress and low thermal fatigue fracture characteristics. On the other hand, when the first spacer (220) and the second spacer (230) are formed of a unidirectional porous metal body, they can have low thermal stress, increased crack propagation resistance, and increased shock absorption capacity.

[0094] The first and second spacer adhesive layers (222, 232) may include various materials that function to adhere the first spacer (220) and the second spacer (230), and may be, for example, a solder layer or an adhesive layer. However, this is merely exemplary and the technical concept of the present invention is not limited thereto.

[0095] Hereinafter, a power module to which a ceramic circuit board according to one embodiment of the present invention is applied will be described.

[0096] FIG. 5 is a cross-sectional view illustrating a cross-sectional cooling power module according to one embodiment of the present invention.

[0097] Referring to FIG. 5, a power module (2000) may include a ceramic circuit board (200), a first semiconductor element (270), a second semiconductor element (280), a mold layer (290), a base plate (250), and a heat sink (240). The ceramic circuit board (200) may include a ceramic substrate (210) including a ceramic layer (211), a substrate copper layer (212), a unidirectional porous metal layer (213), a first active metal brazing layer (214), and a second active metal brazing layer (215).

[0098] At least one semiconductor element may be disposed on a substrate copper layer (212). A first semiconductor element (270) may be bonded to the substrate copper layer (212) by a first element adhesive layer (272). A second semiconductor element (280) may be bonded to the substrate copper layer (212) by a second element adhesive layer (282). The first element adhesive layer (272) and the second element adhesive layer (282) may be solder layers or adhesive layers, which are exemplary and the technical idea of ​​the present invention is not limited thereto.

[0099] The first semiconductor element (270) and the second semiconductor element (280) may be power semiconductor elements, and may be, for example, a gate turn-off thyristor (GTO) semiconductor element, an insulated gate bipolar mode transistor (IGBT) semiconductor element, a SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) semiconductor element, a GaN MOSFET semiconductor element, etc., and may perform an operation of converting and supplying power supplied from a power supply unit such as a battery into power for driving a motor through a switching operation. In addition, the first semiconductor element (270) and the second semiconductor element (280) may include electrode members formed on the upper or lower portions. The second semiconductor element (280) may have a smaller thickness than the first semiconductor element (270). However, this is exemplary, and a case in which the power module (2000) includes semiconductor elements of the same height, for example, a case in which it includes only the first semiconductor element (270), is also included in the technical idea of ​​the present invention.

[0100] The mold layer (290) may be arranged to cover the first semiconductor element (270) and the second semiconductor element (280) on the ceramic circuit board (200). The mold layer (290) may insulate the first semiconductor element (270) and the second semiconductor element (280). The mold layer (290) may be composed of, for example, EMC (epoxy molding compound).

[0101] Optionally, the power module (2000) may further include a base plate (250) disposed between the ceramic circuit board (200) and the heat sink (240) for structural stability. The base plate (250) may include a metal, for example, copper or a copper alloy. The base plate (250) may be formed of a metal plate, for example, a copper plate. In addition, a case where the base plate (250) is formed of a unidirectional porous metal body is also included in the technical concept of the present invention.

[0102] A heat sink (240) may be placed on a one-way porous metal layer (213). The heat sink (240) may include a material having excellent heat transfer properties, such as aluminum or copper. The heat sink (240) may be bonded to the one-way porous metal layer (213) or the base plate (250) using a suitable adhesive material, such as solder or an adhesive.

[0103] The unidirectional porous metal layer (213) can perform a function of dissipating heat generated from the first semiconductor element (270) and the second semiconductor element (280) to the outside. For this heat dissipation, the unidirectional porous metal layer (213) can efficiently transfer the heat generated from the first semiconductor element (270) and the second semiconductor element (280) to the heat sink (240). The unidirectional porous metal layer (213) can reduce mechanical thermal stress and provide excellent shock absorption capability by including unidirectional pores along with excellent thermal conductivity and electrical conductivity.

[0104] Figures 6 and 7 are cross-sectional views illustrating a double-sided cooling power module according to one embodiment of the present invention.

[0105] Referring to FIG. 6, the power module (2000a) may include an upper ceramic circuit board (200a_U), a lower ceramic circuit board (200_D), a first semiconductor element (270), a second semiconductor element (280), a mold layer (290), an upper heat sink (240_U), and a lower heat sink (240_D).

[0106] Additionally, the power module (2000a) may further include at least one of an upper base plate (250_U) and a lower base plate (250_D).

[0107] The upper ceramic circuit board (200a_U) may include an upper ceramic substrate (210_U) including an upper ceramic layer (211_U), an upper substrate copper layer (212_U), an upper unidirectional porous metal layer (213_U), an upper first active metal brazing layer (214_U), and an upper second active metal brazing layer (215_U). The upper ceramic circuit board (200a_U) may further include an upper first spacer (220_U) and an upper second spacer (230_U).

[0108] The lower ceramic circuit board (200_D) may include a lower ceramic substrate (210_D) including a lower ceramic layer (211_D), a lower substrate copper layer (212_D), a lower unidirectional porous metal layer (213_D), a lower first active metal brazing layer (214_D), and a lower second active metal brazing layer (215_D). Here, the lower ceramic circuit board (200_D) does not include a spacer.

[0109] The upper ceramic circuit board (200a_U) and the lower ceramic circuit board (200_D) can be placed facing each other.

[0110] The upper first spacer (220_U) may be attached to the upper substrate copper layer (212_U) by the first spacer adhesive layer (222). The upper second spacer (230_U) may be attached to the upper substrate copper layer (212_U) by the second spacer adhesive layer (232). The upper first spacer (220_U) and the upper second spacer (230_U) may be composed of a unidirectional porous metal body.

[0111] The first semiconductor element (270) may be placed between the upper first spacer (220_U) and the lower substrate copper layer (212_D). The first semiconductor element (270) may be bonded to the upper first spacer (220_U) and the lower substrate copper layer (212_D) by the first element adhesive layer (272).

[0112] The second semiconductor element (280) may be placed between the upper second spacer (230_U) and the lower substrate copper layer (212_D). The second semiconductor element (280) may be bonded to the upper first spacer (220_U) and the lower substrate copper layer (212_D) by a second element adhesive layer (282).

[0113] The second semiconductor element (280) may have a smaller thickness than the first semiconductor element (270). Therefore, a first upper spacer (220_U) having a relatively small thickness may be placed on the upper side of the first semiconductor element (270), and a second upper spacer (230_U) having a relatively large thickness may be placed on the upper side of the second semiconductor element (280), thereby correcting the thickness difference between the second semiconductor element (280) and the first semiconductor element (270).

[0114] The first element adhesive layer (272) and the second element adhesive layer (282) may be a solder layer or an adhesive layer, which are exemplary and the technical idea of ​​the present invention is not limited thereto.

[0115] The mold layer (290) can fill the space between the upper ceramic circuit board (200a_U) and the lower ceramic circuit board (200_D). Accordingly, the first semiconductor element (270) and the second semiconductor element (280) can be covered by the mold layer (290). The mold layer (290) can insulate the first semiconductor element (270) and the second semiconductor element (280). The mold layer (290) can be composed of, for example, EMC (epoxy molding compound).

[0116] The power module (2000a) includes an upper first spacer (220_U) and an upper second spacer (230_U), and does not include a spacer at the bottom, so it may have an asymmetrical structure with respect to the first semiconductor element (270) and the second semiconductor element (280).

[0117] The upper base plate (250_U) may be placed on the upper unidirectional porous metal layer (213_U). The lower base plate (250_D) may be placed on the lower unidirectional porous metal layer (213_D).

[0118] Additionally, for efficient heat dissipation to the outside, an upper heat sink (240_U) may be placed on an upper base plate (250_U) on the outside of the upper ceramic circuit board (200a_U). Additionally, a lower heat sink (240_D) may be placed on a lower base plate (250_D) on the outside of the lower ceramic circuit board (200_U).

[0119] The upper ceramic circuit board (200a_U) and the lower ceramic circuit board (200_D) can perform the function of discharging heat generated from the first semiconductor element (270) and the second semiconductor element (280) to the outside.

[0120] For this heat dissipation, the upper unidirectional porous metal layer (213_U) and the lower unidirectional porous metal layer (213_D) can perform the function of dissipating heat generated from the first semiconductor element (270) and the second semiconductor element (280) to the outside. For this heat dissipation, the upper unidirectional porous metal layer (213_U) and the lower unidirectional porous metal layer (213_D) can efficiently transfer heat generated from the first semiconductor element (270) and the second semiconductor element (280) to the heat sink (240). The upper unidirectional porous metal layer (213_U) and the lower unidirectional porous metal layer (213_D) have excellent thermal conductivity and electrical conductivity, and can reduce mechanical thermal stress and provide excellent shock absorption capability by including unidirectional pores.

[0121] In addition, the upper base plate (250_U) and the lower base plate (250_D) can efficiently transfer heat generated from the first semiconductor element (270) and the second semiconductor element (280) to the upper heat sink (240_U) and the lower heat sink (240_D), respectively. In addition, the upper base plate (250_U) and the lower base plate (250_D) can provide structural stability to the power module (2000a).

[0122] In addition, the upper first spacer (220_U) and the upper second spacer (230_U) can efficiently transfer heat generated from the first semiconductor element (270) and the second semiconductor element (280) to the upper ceramic circuit board (200a_U), respectively.

[0123] Below, descriptions of components identical or similar to those in the embodiment of Fig. 6 will be omitted.

[0124] Referring to FIG. 7, the power module (2000b) may include an upper ceramic circuit board (200a_U), a lower ceramic circuit board (200a_D), a first semiconductor element (270), a second semiconductor element (280), a mold layer (290), an upper heat sink (240_U), and a lower heat sink (240_D).

[0125] Additionally, the power module (2000b) may further include at least one of an upper base plate (250_U) and a lower base plate (250_D).

[0126] The upper ceramic circuit board (200a_U) may include an upper ceramic substrate (210_U) including an upper ceramic layer (211_U), an upper substrate copper layer (212_U), an upper unidirectional porous metal layer (213_U), an upper first active metal brazing layer (214_U), and an upper second active metal brazing layer (215_U). The upper ceramic circuit board (200a_U) may further include an upper first spacer (220_U) and an upper second spacer (230_U).

[0127] The lower ceramic circuit board (200a_D) may include a lower ceramic substrate (210_D) including a lower ceramic layer (211_D), a lower substrate copper layer (212_D), a lower unidirectional porous metal layer (213_D), a lower first active metal brazing layer (214_D), and a lower second active metal brazing layer (215_D). The lower ceramic circuit board (200a_U) may further include a lower first spacer (220_D) and a lower second spacer (230_D).

[0128] The upper ceramic circuit board (200a_U) and the lower ceramic circuit board (200a_D) can be placed facing each other.

[0129] The upper first spacer (220_U) may be attached to the upper substrate copper layer (212_U) by the first spacer adhesive layer (222). The upper second spacer (230_U) may be attached to the upper substrate copper layer (212_U) by the second spacer adhesive layer (232). The upper first spacer (220_U) and the upper second spacer (230_U) may be composed of a unidirectional porous metal body.

[0130] The lower first spacer (220_D) may be attached to the lower substrate copper layer (212_D) by the first spacer adhesive layer (222). The lower second spacer (230_D) may be attached to the lower substrate copper layer (212_D) by the second spacer adhesive layer (232). The lower first spacer (220_D) and the lower second spacer (230_D) may be formed of a unidirectional porous metal body.

[0131] The first semiconductor element (270) may be placed between the upper first spacer (220_U) and the lower first spacer (220_D). The first semiconductor element (270) may be bonded to the upper first spacer (220_U) and the lower first spacer (220_D) by a first element adhesive layer (272).

[0132] The second semiconductor element (280) may be placed between the upper second spacer (230_U) and the lower second spacer (230_D). The second semiconductor element (280) may be bonded to the upper first spacer (220_U) and the lower second spacer (230_D) by a second element adhesive layer (282).

[0133] The second semiconductor element (280) may have a smaller thickness than the first semiconductor element (270). Therefore, an upper first spacer (220_U) having a relatively smaller thickness is disposed on the upper side of the first semiconductor element (270), a lower first spacer (220_D) is disposed on the lower side of the first semiconductor element (270), an upper second spacer (230_U) having a relatively larger thickness is disposed on the upper side of the second semiconductor element (280), and a lower second spacer (230_D) is disposed on the lower side of the second semiconductor element (280), thereby correcting the thickness deviation between the second semiconductor element (280) and the first semiconductor element (270).

[0134] The mold layer (290) can fill the space between the upper ceramic circuit board (200a_U) and the lower ceramic circuit board (200a_D). Accordingly, the first semiconductor element (270) and the second semiconductor element (280) can be covered by the mold layer (290).

[0135] Compared to the power module (2000a) of FIG. 6, the power module (2000b) of FIG. 7 has a difference in that it includes a lower ceramic circuit board (200a_D) instead of the lower ceramic circuit board (200_D).

[0136] The power module (2000b) may have a symmetrical structure with respect to the first semiconductor element (270) and the second semiconductor element (280). That is, the upper first spacer (220_U), the lower first spacer (220_D), the upper second spacer (230_U), and the lower second spacer (230_D) may be arranged symmetrically with respect to the first semiconductor element (270) and the second semiconductor element (280). However, this is merely exemplary, and the technical idea of ​​the present invention is not limited thereto. For example, the upper first spacer (220_U) and the lower first spacer (220_D) may have different heights. In addition, the upper second spacer (230_U) and the lower second spacer (230_D) may have different heights.

[0137] The upper first spacer (220_U) and the upper second spacer (230_U) can efficiently transfer heat generated from the first semiconductor element (270) and the second semiconductor element (280) to the upper ceramic circuit board (200a_U), respectively. The lower first spacer (220_D) and the lower second spacer (230_D) can efficiently transfer heat generated from the first semiconductor element (270) and the second semiconductor element (280) to the lower ceramic circuit board (200a_D), respectively.

[0138] FIG. 8 is a cross-sectional view illustrating a case where the pores of a unidirectional porous metal layer applied to a ceramic circuit board and power module according to one embodiment of the present invention are filled with a filler.

[0139] Referring to FIG. 8, in the unidirectional porous metal layer (213, 213_D, 213_U) applied to the ceramic circuit board of FIG. 3 and FIG. 4 and the power module of FIG. 6 and FIG. 7, there is shown a case where all or part of the pores are filled by a filler (2130).

[0140] The filler (2130) may be, for example, a metal, for example, a low-melting-point metal having a melting point in the range of 100°C to 400°C, and may include, for example, tin or a tin alloy. The low-melting-point metal may react with a high-melting-point metal such as copper to form at least one of a eutectic alloy, a peritectic alloy, a eutectoid alloy, and an intermetallic compound. For example, an intermetallic compound such as Cu6Sn5 or Cu3Sn in a Cu-Sn system, Ni3Sn4 in a Ni-Sn system, or Ag3Sn in a Ag-Sn system may be formed in the bonding region. Accordingly, a transient liquid phase (TLP) bonding may be formed. The above-mentioned transition liquid phase diffusion bonding is a technology that combines soldering bonding and diffusion bonding, in which a low-melting-point metal layer is interposed between high-melting-point metal layers, and the low-melting-point metal layer is melted at a certain temperature and diffuses into the high-melting-point metal layer to form an intermetallic compound while bonding.

[0141] Accordingly, the one-way porous metal layer (213) is made into a composite material, which can improve the mechanical bonding strength with the base plate (250) and enhance the thermal and electrical performance of the power module.

[0142] It will be apparent to a person skilled in the art to which the technical idea of ​​the present invention pertains that the technical idea of ​​the present invention described above is not limited to the above-described embodiments and the attached drawings, and that various substitutions, modifications, and changes are possible within a scope that does not depart from the technical idea of ​​the present invention.

Claims

1. Ceramic layer; A substrate copper layer disposed on the first surface of the ceramic layer; A unidirectional porous metal layer disposed on a second surface of the ceramic layer and having a plurality of pores extending in one direction in a vertical direction from the ceramic layer; A first active metal brazing layer interposed between the ceramic layer and the substrate copper layer; and A second active metal brazing layer interposed between the ceramic layer and the unidirectional porous metal layer, Ceramic circuit board.

2. In paragraph 1, The above one-way porous metal layer is, Having a porosity ranging from 1% by volume to 70% by volume, Ceramic circuit board.

3. In paragraph 1, The above one-way porous metal layer is, A metal casting comprising copper or a copper alloy and formed using a mold casting method, a continuous melting zone method, a continuous casting method, or a centrifugal casting method. Ceramic circuit board.

4. In paragraph 1, The above one-way porous metal layer is, A metal molded body formed by press forming, rolling, and then perforating, laser processing or selective etching a metal material in the form of a sheet, plate, sheet or foil containing copper or a copper alloy. Ceramic circuit board.

5. In paragraph 1, A first spacer disposed on a portion of the copper layer of the substrate; and further comprising a second spacer disposed on a portion of the substrate copper layer and having a greater height than the first spacer; Ceramic circuit board.

6. In paragraph 5, At least one of the first spacer and the second spacer, A unidirectional porous metal body having a plurality of pores extending in one direction in a vertical direction from the above substrate copper layer. Ceramic circuit board.

7. In paragraph 1, All or part of the pores of the above one-way porous metal layer are filled with a filler. Ceramic circuit board.

8. In paragraph 1, The above substrate copper layer is, Consisting of a unidirectional porous metal body having a plurality of pores extending in one direction in a vertical direction from the above ceramic layer, Ceramic circuit board.

9. A ceramic circuit board comprising a ceramic layer, a substrate copper layer, a unidirectional porous metal layer disposed on the ceramic layer and having a plurality of pores extending in one direction in a vertical direction from the ceramic layer, a first active metal brazing layer interposed between the ceramic layer and the substrate copper layer, and a second active metal brazing layer interposed between the ceramic layer and the unidirectional porous metal layer; At least one semiconductor element disposed on the copper layer of the substrate; and Including a mold layer covering the semiconductor element, Power module.

10. In paragraph 9, Further comprising a heat sink disposed on the above unidirectional porous metal layer, Power module.

11. In paragraph 9, Further comprising a base plate disposed on the above one-way porous metal layer, Power module.

12. In paragraph 9, All or part of the pores of the above one-way porous metal layer are filled with a filler. Power module.

13. An upper ceramic circuit board comprising: an upper ceramic layer, an upper substrate copper layer, and an upper unidirectional porous metal layer disposed on the upper ceramic layer and having a plurality of pores extending in one direction in a vertical direction from the upper ceramic layer; an upper first active metal brazing layer interposed between the upper ceramic layer and the upper substrate copper layer; and an upper second active metal brazing layer interposed between the upper ceramic layer and the upper unidirectional porous metal layer; an upper first spacer disposed on a portion of the upper substrate copper layer; and an upper second spacer disposed on a portion of the upper substrate copper layer and having a greater height than the upper first spacer; A lower ceramic circuit board comprising a lower ceramic layer, a lower substrate copper layer, and a lower unidirectional porous metal layer disposed on the lower ceramic layer and having a plurality of pores extending in one direction in a vertical direction from the lower ceramic layer, a lower first active metal brazing layer interposed between the lower ceramic layer and the lower substrate copper layer, and a lower second active metal brazing layer interposed between the lower ceramic layer and the lower unidirectional porous metal layer; A first semiconductor element disposed between the upper first spacer and the lower substrate copper layer; A second semiconductor element disposed between the upper second spacer and the lower substrate copper layer and having a smaller thickness than the first semiconductor element; and A mold layer that fills the space between the upper ceramic circuit board and the lower ceramic circuit board and covers the first semiconductor element and the second semiconductor element, Power module.

14. In paragraph 13, an upper heat sink disposed on the outside of the upper ceramic circuit board; and Further comprising at least one lower heat sink disposed on the outer side of the lower ceramic circuit board; Power module.

15. In paragraph 13, an upper base plate disposed on the upper one-way porous metal layer; and Further comprising at least one of the lower base plates disposed on the lower one-way porous metal layer, Power module.

16. In paragraph 13, All or part of the pores of the upper one-way porous metal layer are filled with a filler, All or part of the pores of the above lower one-way porous metal layer are filled with filler. Power module.

17. An upper ceramic circuit board comprising: an upper ceramic layer, an upper substrate copper layer, and an upper unidirectional porous metal layer disposed on the upper ceramic layer and having a plurality of pores extending in one direction in a vertical direction from the upper ceramic layer; an upper first spacer disposed on a portion of the upper substrate copper layer; and an upper second spacer disposed on a portion of the upper substrate copper layer and having a greater height than the upper first spacer; A lower ceramic circuit board comprising: a lower ceramic layer, a lower substrate copper layer, and a lower unidirectional porous metal layer disposed on the lower ceramic layer and having a plurality of pores extending in one direction in a vertical direction from the lower ceramic layer; a lower first spacer disposed on a portion of the lower substrate copper layer; and a lower second spacer disposed on a portion of the lower substrate copper layer and having a greater height than the lower first spacer; A first semiconductor element disposed between the upper first spacer and the lower first spacer; A second semiconductor element disposed between the upper second spacer and the lower second spacer and having a smaller thickness than the first semiconductor element; and A mold layer that fills the space between the upper ceramic circuit board and the lower ceramic circuit board and covers the first semiconductor element and the second semiconductor element, Power module.

18. In paragraph 17, an upper heat sink disposed on the outside of the upper ceramic circuit board; and Further comprising at least one lower heat sink disposed on the outer side of the lower ceramic circuit board; Power module.

19. In paragraph 17, an upper base plate disposed on the upper one-way porous metal layer; and Further comprising at least one of the lower base plates disposed on the lower one-way porous metal layer, Power module.

20. In paragraph 17, All or part of the pores of the upper one-way porous metal layer are filled with a filler, All or part of the pores of the above lower one-way porous metal layer are filled with filler. Power module.

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