Circuit board and semiconductor package

Abstract

This circuit board comprises: a core layer; a first insulating layer disposed on the core layer and including a first through-hole; and a second insulating layer disposed on the first insulating layer and including a second through-hole overlapping the first through-hole in a vertical direction, wherein a first inner wall of the first through-hole forms a first angle with an upper surface of the core layer; a second inner wall of the second through-hole and an upper surface of the first insulating layer form a second angle; the first angle and the second angle are different; and the thickness in a vertical direction of the first insulating layer is different from the thickness in a vertical direction of the second insulating layer.

Description

Circuit boards and semiconductor packages

[0001] This embodiment relates to a circuit board and a semiconductor package.

[0002]

[0003] Recently, electronic technology, such as AI and servers, is moving toward multi-functionality and high-speed operation. To respond to this trend, semiconductor chip manufacturing technology is also rapidly developing.

[0004] In particular, the thickness of circuit boards used for miniaturization of finished electronic products is also decreasing, and technologies related to multilayer circuit boards that configure more circuit layers within a circuit board of the same thickness are being actively researched. In addition, as the pitch of semiconductor chips becomes narrower and the size of chips increases, chiplet technology, which separates semiconductor chips by function, is being researched. Technologies for connecting separated chiplets on circuit boards are also being actively researched. Furthermore, technologies for connecting the separated chiplets on circuit boards are being actively researched. Technologies for the connection relationship between circuit boards and semiconductor chips are also being actively researched, such as connecting semiconductor chips with different functions on a circuit board, which was previously considered only from the perspective of a semiconductor package.

[0005] A circuit board is a substrate made by printing a circuit line pattern with a conductive material, such as copper, onto an electrically insulating substrate. It is a general term for a board immediately before electronic components are mounted. To densely mount numerous electronic components on a flat surface, the mounting locations of each component are determined, and the circuit patterns connecting the components are printed and secured onto the flat surface.

[0006] Conventional embedded printed circuit boards form cavities for embedding components using drill bits, use auxiliary materials such as release films to secure components, or use sandblasting to form cavities for embedding components.

[0007] In the past, there was no great difficulty in embedding the terminals of the devices in the circuit board and connecting them to the circuits of the circuit board due to the pitch (size and / or spacing) of the terminals. However, recently, as the terminal pitch of the devices to be embedded has become increasingly narrow, the positional alignment of the devices when embedding the devices and the circuit patterns surrounding the embedded devices have become more complex, and thus, the technology for the structure of the cavity that determines the location of the devices to be embedded has become important.

[0008]

[0009] The present embodiment provides a circuit board and semiconductor package capable of variously adjusting the shape of a cavity depending on the intended use, sufficiently securing space for arranging electronic components within a circuit board in an embedded structure, improving the positional alignment of electronic components to minimize manufacturing defects, and increasing the degree of freedom in circuit pattern design around electronic components.

[0010]

[0011] A circuit board according to the present embodiment comprises: a core layer; a first insulating layer disposed on the core layer and including a first through hole; and a second insulating layer disposed on the first insulating layer and including a second through hole vertically overlapping the first through hole, wherein a first inner wall of the first through hole forms a first angle with a top surface of the core layer, a second inner wall of the second through hole and a top surface of the first insulating layer form a second angle, and the first angle and the second angle are different, and a vertical thickness of the first insulating layer is different than a vertical thickness of the second insulating layer.

[0012] The above first angle may be smaller than the above second angle.

[0013] The above first angle may be greater than the above second angle.

[0014] A third inner wall is included between the first inner wall and the second inner wall, and the third inner wall can form a third angle different from the first angle and the second angle with the upper surface of the core layer.

[0015] The above third angle may be smaller than the above first angle and the above second angle.

[0016] The third angle above may have an obtuse angle.

[0017] The third inner wall may be parallel to the upper surface of the core layer.

[0018] The above third inner wall can form the inner wall of the above first through hole.

[0019] The first through hole and the second through hole form a cavity and include a connection pad arranged on the bottom surface of the cavity, and the connection pad can be spaced apart from the first inner wall in a horizontal direction.

[0020] A semiconductor package according to the present embodiment comprises: a core layer; a first insulating layer disposed on the core layer and including a first through hole; a second insulating layer disposed on the first insulating layer and including a second through hole vertically overlapping the first through hole; and a first electronic element disposed in a cavity formed by the first through hole and the second through hole, wherein a first inner wall of the first through hole forms a first angle with a top surface of the core layer, a second inner wall of the second through hole and a top surface of the first insulating layer form a second angle, and the first angle and the second angle are different, and a vertical thickness of the first insulating layer is different from a vertical thickness of the second insulating layer.

[0021]

[0022] Through this embodiment, the formation of the inner wall of the cavity can be variously controlled according to various changes in process conditions, thereby securing a wider space for arranging electronic components, precisely controlling the position for arranging electronic components, and greatly improving the positional alignment of electronic components, so that the process of joining electronic components can be performed more easily.

[0023] In addition, since air bubbles in the bonding member can be easily discharged to the outside by securing a gap between the electronic component and the inner wall of the cavity, the bonding strength of the electronic component can be further strengthened.

[0024] In addition, due to the multiple inner wall structure with different slope angles within the multiple insulating layers, there is an advantage in that the bonding force between the multiple insulating layers can be maintained more firmly.

[0025] Additionally, it has the advantage of increasing the degree of freedom in circuit design around electronic components, thereby improving power transmission and signal transmission characteristics of semiconductor chips.

[0026]

[0027] Figure 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention.

[0028] Figure 2 is a drawing of the inner wall of a cavity according to the first embodiment of the present invention.

[0029] Figure 3 is a drawing showing a modified example of the cavity shape according to the first embodiment of the present invention.

[0030] Figure 4 is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention.

[0031] Figure 5 is a cross-sectional view of a circuit board according to a second embodiment of the present invention.

[0032] Figure 6 is a drawing of the inner wall of a cavity according to the second embodiment of the present invention.

[0033] Figure 7 is a drawing showing a first modified example of the inner wall of a cavity according to the second embodiment of the present invention.

[0034] Figure 8 is a drawing of a second modified example of the inner wall of a cavity according to the second embodiment of the present invention.

[0035] Figure 9 is a cross-sectional view of a semiconductor package according to a second embodiment of the present invention.

[0036] Figure 10 is a table comparing the shapes of cavities according to various process conditions according to an embodiment of the present invention.

[0037] Fig. 11 is a cross-sectional view of a semiconductor package according to a third embodiment of the present invention.

[0038]

[0039] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0040] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0041] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0042] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as "A and / or at least one (or more) of B, C," it may include one or more of all combinations that can be combined with A, B, and C.

[0043] Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0044] These terms are intended only to distinguish one component from another, and are not intended to limit the nature, order, or sequence of the component.

[0045] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0046] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Also, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0047] Additionally, the expression that configuration A is positioned between configurations B and C should also include the meaning that configuration A is positioned so that it overlaps configurations B and C at least partially in the horizontal and / or vertical directions.

[0048] Expressions referring to directions include horizontal directions, vertical directions, and include a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. These are referred to as a first horizontal direction (X-axis), a second horizontal direction (Y-axis), and a vertical direction (Z-axis) according to the Cartesian coordinate system, and the meaning of overlapping along the horizontal direction should also include the meaning of overlapping along the first horizontal direction and / or overlapping along the second horizontal direction.

[0049] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0050] Additionally, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood to be in "direct contact" with a component B, it is described as being in "direct contact."

[0051] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0052] FIG. 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention, and FIG. 2 is a drawing photographing the inner wall of a cavity according to the first embodiment of the present invention.

[0053] Referring to FIGS. 1 and 2, a circuit board (10) according to a first embodiment of the present invention may include a core layer (110), a first insulating layer (112), a second insulating layer (114), a third insulating layer (116), a fourth insulating layer (118), a plurality of wiring portions, and a plurality of via portions.

[0054] The core layer (110) and the first to fourth insulating layers (112, 114, 116, 118) may be arranged along the vertical direction. With the core layer (110) as the center, the first build-up layer is arranged on top of the core layer (110), and the first build-up layer may include a first insulating layer (112) and a second insulating layer (114) that are stacked along the vertical direction. The second build-up layer is arranged below the core layer (110), and the second build-up layer may include a third insulating layer (116) and a fourth insulating layer (118) that are stacked along the vertical direction. Here, the number of stacked insulating layers in the first build-up layer and the second build-up layer is exemplary, and the first and second build-up layers may have a freely stacked structure, unlike the embodiment.

[0055] The core layer (110) may be a member forming the basis of the circuit board (10). The core layer (110) may be provided as an insulating layer. For example, the core layer (110) may have a structure in which glass fibers are laminated in a plurality of layers along a vertical direction, and may have a structure in which prepreg (PPG) with one layer of glass fiber embedded is laminated in a plurality of layers. In addition, the core layer (110) may be provided as a glass substrate. The core layer (110) may be provided as an insulating layer having a stiffer structure than the insulating layer provided in the first build-up layer and / or the second build-up layer, and may have a function of preventing warping of the circuit board (10) during the process or after the process. Therefore, the core layer (110) may be arranged to have a thickness thicker than the insulating layer provided in the upper build-up layer and / or the lower build-up layer.

[0056] The core layer (110) can be called an insulating layer.

[0057] For example, the vertical thickness (t3) of the core layer (110) may be thicker than the vertical thickness (t1) of the first insulating layer (112) or the vertical thickness (t2) of the second insulating layer (114).

[0058] The first insulating layer (112) may be disposed on the core layer (110). The second insulating layer (114) may be disposed on the first insulating layer (114). The third insulating layer (116) may be disposed on the lower surface of the core layer (110). The fourth insulating layer (118) may be disposed on the lower surface of the third insulating layer (116).

[0059] The first to fourth insulating layers (112, 114, 116, 118) may each be any insulator, such as photocurable and / or thermosetting. As the thermosetting insulator, an insulator in which inorganic and / or organic fillers are dispersed in a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., may be used, and a prepreg (PPG) including glass fibers in a resin may be used. In addition, the resin described above may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and the inorganic and / or organic fillers may be provided with a material such as silica or plastic. When an insulating resin is used as a core, a reinforcing material provided with glass fibers or aramid fibers may be included. When the first to fourth insulating layers (112, 114, 116, 118) are photocurable insulators, the first to fourth insulating layers (112, 114, 116, 118) may each be a PID (Photo Imageable Dielectric).

[0060] A circuit board (10) may include a circuit pattern for transmitting electrical signals and / or power to electronic devices such as semiconductor chips. The circuit pattern may include a plurality of wiring portions and a plurality of via portions.

[0061] A plurality of wiring portions may be arranged on the surface of the core layer (110) and the plurality of insulating layers, respectively. Here, the meaning of being arranged on the surface may also include the meaning that at least a portion of the plurality of wiring portions are buried within the core layer (110) and the plurality of insulating layers, respectively, and are exposed to the outside from the surface.

[0062] The plurality of wiring portions may include a first wiring portion (121) disposed on the upper surface of the core layer (110), a second wiring portion (122) disposed on the upper surface of the first insulating layer (112), a third wiring portion (123) disposed on the upper surface of the second insulating layer (114), a fourth wiring portion (124) disposed on the lower surface of the core layer (110), a fifth wiring portion (125) disposed on the lower surface of the third insulating layer (116), and a sixth wiring portion (126) disposed on the lower surface of the fourth insulating layer (118). The third wiring portion (123) disposed on the upper surface of the first build-up layer may be referred to as a first pad portion. The sixth wiring portion (126) disposed on the lower surface of the second build-up layer may be referred to as a second pad portion. In addition, the wiring portion may include a pad portion for connecting to a via portion.

[0063] A via portion may be a metal material arranged in a via hole formed in a core layer (110) or a plurality of insulating layers to connect a plurality of wiring portions facing each other in a vertical direction. Here, the via hole vertically penetrates at least a portion of each of the core layer (110) and / or the plurality of insulating layers, and a via portion may be arranged within the via hole.

[0064] The via portion may include a first via portion (131) penetrating at least a portion of the core layer (110), a second via portion (133) penetrating at least a portion of the first insulating layer (112), a third via portion (134) penetrating at least a portion of the second insulating layer (114), a fourth via portion (135) penetrating at least a portion of the third insulating layer (116), and a fifth via portion (136) penetrating at least a portion of the fourth insulating layer (118).

[0065] The first via portion (131) can electrically connect the first wiring portion (121) and the fourth wiring portion (124). The first via portion (131) has a cavity formed on the inside, and the cavity can be filled with a filling material (132). Therefore, the flatness of the wiring portion arranged on the upper surface of the core layer (110) connected to the first via portion (131) can be controlled, and the via hole of the core layer (110) can be filled without a gap, thereby improving the reliability of the circuit board.

[0066] The second via portion (133) can electrically connect the first wiring portion (121) and the second wiring portion (122). The third via portion (134) can electrically connect the second wiring portion (122) and the third wiring portion (123). The second via portion (133) and the third via portion (134) can have a shape in which the horizontal width becomes narrower as they go downward.

[0067] The fourth via section (135) can electrically connect the fourth wiring section (124) and the fifth wiring section (125). The fifth via section (136) can electrically connect the fifth wiring section (125) and the sixth wiring section (126). The fourth via section (135) and the fifth via section (136) can have a shape in which the horizontal width increases as they go downward.

[0068] The vertical thickness (t1) of the first insulating layer (112) may be thicker than the vertical thickness (t2) of the second insulating layer (114). The vertical length of the third via portion (134) in the second insulating layer (114) may also be shorter than the vertical length of the second via portion (133) in the first insulating layer (112). Accordingly, when the electronic components (220, 230) described later are arranged on the first build-up layer, the signal transmission length can be reduced. In addition, since the thickness of the electronic components (210) arranged in the cavity and the depth of the cavity can be controlled, the flatness of the fifth insulating layer (115) can be improved when the fifth insulating layer (115) is arranged after the electronic components (210) are arranged.

[0069] The cavity may include a first through hole (141) and a second through hole (146).

[0070] And, the first insulating layer (112) may include a first through hole (141). The first through hole (141) may have a shape that penetrates from the upper surface to the lower surface of the first insulating layer (112). For example, the first through hole (141) may be arranged at the horizontal center of the first insulating layer (112). In addition, a part of the upper surface of the core layer (110) may be exposed from the first insulating layer (112) in the vertical direction through the first through hole (141). The first through hole (141) may form a placement area of ​​the first electronic element (210, see FIG. 4) together with the second through hole (146) to be described later. The first through hole (141) may form a cavity together with the second through hole (146). In this case, a part of the upper surface of the core layer (110) may be provided as the bottom surface of the cavity, thereby forming a surface for arranging the first electronic element (210). However, the present invention is not limited thereto, and in the case where another insulating layer is provided between the first insulating layer (112) and the core layer (110), a metal layer may be provided on the upper surface of the other insulating layer to have an etching-preventing function when forming the cavity and may be provided as the bottom surface of the cavity.

[0071] The first through hole (141) may have a shape in which the horizontal width becomes narrower as it goes downward. Accordingly, the inner wall (142) of the first through hole (141) may have an inclined shape. The inner wall (142) of the first through hole (141) may form a predetermined angle with the upper surface of the core layer (110). As illustrated in Fig. 2, the first angle (a) formed by the inner wall (142) of the first through hole (141) and the upper surface of the core layer (110) may be 5 degrees or more and 80 degrees or less. When the first angle (a) is less than 5 degrees, there is a problem in that the horizontal width of the cavity excessively increases, resulting in a decrease in production efficiency due to an increase in the amount of resin to fill the cavity. If the first angle (a) exceeds 80 degrees, the side wall of the first through hole (141) may be concave toward the outside of the cavity during the laser process for forming the cavity, and a gap may be generated due to a problem with the flowability of the resin during the process for forming the insulating layer for filling the cavity, which may lower reliability.

[0072] In addition, the process of forming the first through hole (141) can use a laser process as described above, but it can also be formed using an exposure process or a mechanical drill. In the case of forming the first through hole (141) using an exposure process, if the first angle (a) exceeds 80 degrees, the upper surface of the first insulating layer (112) may collapse, which may cause the flatness to deteriorate in the subsequent process and ultimately cause the height deviation of the bump to increase, which may cause a problem of lowering the connection reliability with the semiconductor chip. In addition, in the case of using a mechanical drill, the side wall of the first through hole (141) may have unevenness due to the shape of the drill, which may cause a gap to be generated due to a problem with the flowability of the resin when placing the insulating layer to fill the cavity, which may lower the reliability. Therefore, by controlling the side wall of the first through hole (141) to be less than 80 degrees and preventing unevenness from occurring even when using a mechanical drill, the reliability of the circuit board can be improved.

[0073] A spacer (165) may be arranged between the inner wall (142) of the first through-hole (141) and the connection pad (160). The spacer (165) may be an area that horizontally separates the inner wall (142) of the first through-hole (141) and the connection pad (160). Accordingly, during the process of bonding the first electronic element (210) to the connection pad (160), damage to the first electronic element (210) caused by the inner wall of the first through-hole (141) can be minimized. In addition, during the process of bonding the first electronic element (210) to the adhesive member (170) described later, a space can be secured through the spacer (165) through which air bubbles between the adhesive member (170) and the first electronic element (210) can be discharged. The above-described embodiment is a case where the bottom surface of the cavity includes at least a portion of the core layer (110), but is not limited thereto. In a case where another insulating layer is arranged between the first insulating layer (112) and the core layer (110), the width of the connection pad (160) may be made larger than the width of the first through hole (141) so that a recess does not occur on the surface of the other insulating layer, thereby manufacturing the cavity so that the separation portion (165) is not provided.

[0074] The second insulating layer (114) may include a second through hole (146). The second through hole (146) may have a shape that penetrates from the upper surface to the lower surface of the second insulating layer (114). For example, the second through hole (146) may be arranged at the horizontal center of the second insulating layer (114). In addition, a portion of the upper surface of the core layer (110) may be exposed from the first insulating layer (112) and the second insulating layer (114) in the vertical direction through the second through hole (146). The second through hole (146) may form a placement area of ​​the first electronic element (210) together with the first through hole (141) described below. However, the present invention is not limited thereto, and when another insulating layer is disposed between the first insulating layer (112) and the core layer (110), a metal layer may be disposed on the upper surface of the other insulating layer to have an etching-preventing function when forming a cavity and may be provided as the bottom surface of the cavity, and at least a portion of the metal layer may be exposed from the first insulating layer (112) and the second insulating layer (114) in the vertical direction through the second through hole (146).

[0075] The second through hole (146) may have a shape in which the horizontal width becomes narrower as it goes downward. Accordingly, the inner wall (147) of the second through hole (146) may have a sloped shape. The inner wall (147) of the second through hole (146) may form a predetermined angle with the upper surface of the core layer (110) or the upper surface of the first insulating layer (112). As illustrated in Fig. 2, the second angle (b) formed by the inner wall (147) of the second through hole (146) and the upper surface of the first insulating layer (112) may be 5 degrees or more and 80 degrees or less. When the second angle (b) is less than 5 degrees, the horizontal width of the cavity may increase excessively, which may lead to a decrease in production efficiency due to an increase in the amount of resin required to fill the cavity. In addition, as the width of the cavity becomes excessively wide, the cavity space may become unnecessarily wide, which may reduce the freedom of wiring design. When the second angle (b) exceeds 80 degrees, when placing the insulating layer to fill the cavity, a gap may occur due to a problem with the flowability of the resin, which may lower reliability.

[0076] The inner wall (142) of the first through hole (141) can be named as the first inner wall, and the inner wall of the second through hole (146) can be named as the second inner wall.

[0077] The first angle (a) may be greater than the second angle (b). Accordingly, the cavity entrance area can be formed wider during the mounting process of the first electronic element (210) within the cavity, thereby facilitating the mounting process. In addition, the flowability of the resin can be improved during the cavity-filling process, thereby preventing the occurrence of voids and improving reliability.

[0078] FIG. 3 is a drawing showing a modified example of the cavity shape according to the first embodiment of the present invention. Referring to FIG. 3, the first angle (a) may be smaller than the second angle (b). Even in this case, the first angle (a) and the second angle (b) may have a size relationship within the aforementioned range. Accordingly, in comparison to the case where the first angle (a) is larger than the second angle (b), the amount of resin for filling the cavity can be reduced, and the second angle (b) can form a more solid bond between the cavity and the protrusion (190) of the fifth insulating layer (115) to be described later.

[0079] Due to the difference in vertical thickness between the first insulating layer (112) and the second insulating layer (114), the vertical length of the first through hole (141) may be different from the vertical length of the second through hole (146). According to an embodiment, the vertical length of the first through hole (141) may be longer than the vertical length of the second through hole (146). Accordingly, the process of forming the inner wall (142) of the first insulating layer (112), which is relatively thicker than the second insulating layer (114), can be performed more easily, thereby providing an advantage in controlling the distance between the first electronic element (210) and the inner wall (142) of the first insulating layer (112).

[0080] A connection pad (160) may be arranged on the bottom surface of the cavity. The connection pad (160) may be arranged on the upper surface of the core layer (110). The connection pad (160) may be electrically connected to the first electronic element (210). The first electronic element (210) may be coupled to the connection pad (160).

[0081] As illustrated in FIG. 4, an adhesive member (170) may be added between the connection pad (160) and the first electronic element (210). The first electronic element (210) may be coupled to the connection pad (160) via the adhesive member (170). A die attach film (DAF) may be used as the adhesive member (170). Although not illustrated, a portion of the adhesive member (170) may be positioned to cover at least a portion of the side surface of the first electronic element (210), thereby improving the fixing force. At this time, the vertical length of the adhesive member (170) arranged on a part of the side surface of the first electronic element (210) is arranged to be smaller than the thickness of the first insulating layer (112), so that the frictional force between the adhesive member (170) and the first electronic element (210) can be controlled, and accordingly, the position of the first electronic element (210) can be prevented from being misaligned when the first electronic element (210) is arranged. In addition, although not shown, another adhesive member (not shown) can be arranged on the upper and / or lower surface of the adhesive member (170) to prevent the position of the first electronic element (210) from being misaligned. In this case, the side surface of the first electronic element (210) can come into contact with the adhesive member (170) and another adhesive member (not shown), and the fixing force between the first electronic element (210) and the circuit board can be more firmly improved.

[0082] Figure 4 is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention.

[0083] Referring to FIG. 4, the semiconductor package according to the present embodiment may additionally include a fifth insulating layer (115), a protective layer (119), a first electronic element (210), a second electronic element (220), and a third electronic element (230) in the circuit board (10) described above.

[0084] The fifth insulating layer (115) may be disposed on the second insulating layer (114). The fifth insulating layer (115) may include a base region disposed on the upper surface of the second insulating layer (114) and a protrusion (190) protruding downward from the upper surface of the second insulating layer (114).

[0085] The protrusion (190) can be coupled to the cavity. The protrusion (190) can protrude from the lower surface of the base region toward the inside of the first through hole (141) and the second through hole (146). A first electronic element (190) disposed in the cavity can be embedded through the protrusion (190). A first side surface (192) coupled with the inner wall (142) of the first through hole (141) and a second side surface (194) coupled with the inner wall (147) of the second through hole (146) can be disposed on the side surface of the protrusion (190). The first side surface (192) and the second side surface (194) can have an inclined surface shape corresponding to the inner wall shape of the first through hole (141) and the second through hole (146), respectively. The first side (192) may be arranged to overlap horizontally with the first insulating layer (112). The second side (194) may be arranged to overlap horizontally with the second insulating layer (114). The first electronic element (210) may be firmly fixed within the cavity through the protrusion (190). In addition, the protrusion (190) may be firmly fixed within the cavity through the plurality of side surfaces (192, 194) having different angles.

[0086] A protective layer (119) may be disposed on the fifth insulating layer (115). The protective layer (119) may prevent short circuits between solders due to low wettability with solder when semiconductor elements are disposed on the surface of the circuit board (10) using a material such as solder, and may protect the circuit board (10) from external moisture or contaminants. Each of the protective layers (119) may be formed using a photocurable insulating material. For example, the protective layer (119) may be formed using a solder resist.

[0087] Although not shown, an additional insulating layer corresponding to the fifth insulating layer (115) of the first build-up layer may be placed on the second build-up layer based on the core layer (110), and a protective layer may also be placed on the lower surface of the additional insulating layer.

[0088] A first electronic element (210) may be placed in the cavity. The first electronic element (210) may be coupled to a connection pad (160) via an adhesive member (170). The first electronic element (210) may be embedded in the cavity via a protrusion (190) of the fifth insulating layer (115). The upper surface of the first electronic element (210) may be placed to overlap the second insulating layer (114) in a horizontal direction. The upper surface of the first electronic element (210) may be placed lower than the upper surface of the second insulating layer (114). However, this is not limited thereto, and the upper surface of the first electronic element (210) may be positioned above the upper surface of the second insulating layer (114), and in this case, a groove may be formed on the lower surface of the fifth insulating layer (115) to which a part of the first electronic element (210) is coupled.

[0089] A second electronic element (220) and a third electronic element (230) may be arranged on the protective layer (119). The second electronic element (220) and the third electronic element (230) may be arranged in a horizontal direction. In the present embodiment, the first electronic element (210) may be a bridge connecting the second electronic element (220) and the third electronic element (230).

[0090] The semiconductor package may include a sixth via portion (137) penetrating the fifth insulating layer (115), a seventh wiring portion (127) disposed on the upper surface of the fifth insulating layer (115), a seventh via portion (138) penetrating the protective layer (119), and a first pad portion (128) disposed on the protective layer (119). The third wiring portion (123) and the seventh wiring portion (127) may be electrically connected through the sixth via portion (137). The seventh wiring portion (127) and the first pad portion (128) may be electrically connected through the seventh via portion (138).

[0091] The second electronic element (220) and the third electronic element (230) can be respectively coupled to some and other of the plurality of first pad portions (128) disposed on the protective layer (119).

[0092] In addition, an eighth via portion (181), an eighth wiring portion (182), a ninth via portion (183), and a second pad portion (184) may be respectively arranged in the region of the fifth insulating layer (115) and the protective layer (119) that overlap vertically with the cavity. Accordingly, the second electronic element (220) and the first electronic element (210), and the third electronic element (230) and the first electronic element (210) may be electrically connected, respectively.

[0093] Below, a circuit board according to a second embodiment of the present invention will be described.

[0094] FIG. 5 is a cross-sectional view of a circuit board according to a second embodiment of the present invention, and FIG. 6 is a drawing photographing the inner wall of a cavity according to the second embodiment of the present invention.

[0095] This embodiment is identical to the first embodiment in all other respects, with the only difference being the shape of the cavity inner wall. Therefore, only the characteristic aspects of this embodiment will be described below, and the descriptions in the previously described embodiment will be used for the remaining aspects.

[0096] Referring to FIGS. 5 and 6, the circuit board (20) according to the present embodiment may include a plurality of inner walls having different inclination angles in the inner wall of the cavity.

[0097] The cavity can be implemented through a first through hole (141) of the first insulating layer (112) and a second through hole (146) of the second insulating layer (114).

[0098] The first through hole (141) may have a shape in which the horizontal width becomes narrower as it goes downward. The inner wall of the first through hole (141) may include a first inner wall (342). The first inner wall (342) may have an inclined shape. The first inner wall (342) may form a predetermined angle with the upper surface of the core layer (110). As illustrated in FIG. 6, the first angle (a) formed by the first inner wall (342) and the upper surface of the core layer (110) may be 5 degrees or more and less than 50 degrees. When the first angle (a) is less than 5 degrees, the horizontal width of the cavity excessively increases, which reduces production efficiency due to an increase in the amount of resin to fill the cavity, and the space of the cavity becomes unnecessarily wide, which limits the freedom of circuit design. If the first angle (a) exceeds 50 degrees, the efficiency of the formation process of the second inner wall (348) and the third inner wall (345) described later is reduced, damage occurs to the connection pad (160) placed on the bottom surface of the cavity during the formation process of the cavity, and there is a problem that it is difficult to secure sufficient space for the placement of electronic components within the cavity.

[0099] Similarly, a spacer (165) may be placed between the first inner wall (342) of the first through hole (141) and the connection pad (160).

[0100] The second through hole (146) may have a shape in which the horizontal width becomes narrower as it goes downward. The inner wall of the second through hole (146) may include a second inner wall (348). The second inner wall (348) may have an inclined shape. The second inner wall (348) may form a predetermined angle with the upper surface of the core layer (110) or the upper surface of the first insulating layer (112). The second angle (c) formed by the second inner wall (348) and the upper surface of the first insulating layer (112) may be 5 degrees or more and 50 degrees or less. When the second angle (c) is less than 5 degrees, there is a problem in that the horizontal width of the cavity excessively increases, resulting in a decrease in production efficiency due to an increase in the amount of resin required to fill the cavity. When the second angle (c) exceeds 50 degrees, the efficiency of the formation process of the first inner wall (342) and the third inner wall (345) described later is reduced, and there is a problem in that it is difficult to secure sufficient space for arranging electronic components within the cavity.

[0101] The inner wall of the cavity may include a third inner wall (345). The third inner wall (345) may be disposed between the first inner wall (342) and the second inner wall (348). The third inner wall (345) may be disposed on the first insulating layer (112). The third inner wall (345) may form a portion of the inner surface of the first through hole (141). The third inner wall (345) may be disposed vertically above the first inner wall (342). The upper end of the third inner wall (345) may form a boundary between the first insulating layer (112) and the second insulating layer (114). Accordingly, a plurality of inner walls having different angles may be disposed vertically on the inner wall of the first through hole (141) based on a single first insulating layer (112). By forming multiple regions with different inclination angles within a single insulating layer by the above structure, the space for arranging electronic components can be secured, and the deviation between different inner walls with different inclination angles can be gradually reduced, thereby improving the bonding properties at the interfaces of the multiple insulating layers. In addition, since the bonding surface with the protrusion that is coupled to the cavity and embeds the electronic components can be formed at various angles, the durability can be improved, and in the cavity-filling process, the flowability of the resin can be improved, thereby preventing the occurrence of voids within the cavity, thereby improving the reliability of the circuit board.

[0102] The third angle (b) formed by the third inner wall (345) and the upper surface of the core layer (110) may be different from the first angle (a) and / or the second angle (b). For example, the third angle (b) may have an angle less than or equal to the first angle (a) and the second angle (c). Accordingly, in order to prevent an excessive amount of resin from being required to fill the cavity and to control the flowability of the resin, the third angle (b) may be provided to have an angle less than the first angle (a) and the second angle (b).

[0103] For example, the third angle (b) may be -20 degrees or more and 90 degrees or less. The meaning that the third angle (b) has a negative angle of 0 degrees or less is that, as illustrated in FIG. 8, the third inner wall (345) protrudes upward and includes a portion that overlaps the second inner wall (348) along the horizontal direction. Since the first to third angles (a, b, c) described above are angles described based on the upper surface of the core layer (110), it should be understood that describing the third angle (b) as having a negative angle is for the convenience of description of the invention.

[0104] When the third angle (b) is less than -20 degrees, the vertical depth of the recess formed by the third inner wall (345) and the second inner wall (348) becomes deeper. In this case, due to the deepened recess, the flowability of the resin may be reduced during the cavity filling process, which may cause a void to be generated and the reliability of the circuit board may be reduced. In addition, when the third angle (b) exceeds 90 degrees, the side wall of the cavity may have a concave surface that is sunken to the outside of the cavity, which may cause a void to be generated during the cavity filling process as described above and the reliability of the circuit board may be reduced.

[0105] Meanwhile, as illustrated in FIG. 9, when the fifth insulating layer (115) is arranged on the second insulating layer (114), a plurality of side surfaces (197, 198, 199) having different inclination angles are formed on the side surface of the protrusion (190) corresponding to the inclined surfaces of the first inner wall (342), the second inner wall (348), and the third inner wall (345), so that the bonding force between the protrusion (190) of the fifth insulating layer (115) and the cavity can be made more solid.

[0106] Meanwhile, in this embodiment, a case where multiple inner walls with different inclination angles are formed within a first insulating layer (112) having a thick vertical thickness and a single inner wall is formed within a second insulating layer (114) having a relatively thin thickness is described as an example, but this is not limited thereto, and it should be understood that a case where a single inner wall is formed within the first insulating layer (112) and multiple inner walls with different inclination angles are formed within the second insulating layer (114) is also included in this embodiment. In addition, a third inner wall (345) disposed between the first inner wall (342) and the second inner wall (348) may be disposed at the interface between the first insulating layer (112) and the second insulating layer (114), and in this case, a part of the third inner wall (345) may be implemented by the first insulating layer (112), and another part may be implemented by the second insulating layer (114). Accordingly, the bonding between multiple insulating layers can be made more solid.

[0107] Referring to Fig. 7, the third inner wall (345) may be arranged parallel to the upper surface of the core layer (110), the upper surface of the first insulating layer (112), or the lower surface of the second insulating layer (114) with an inclination angle of 0 degrees as an example. Accordingly, in the semiconductor package, a plane parallel to the bottom surface of the cavity in the horizontal direction may be formed on the protrusion (190) of the fifth insulating layer (115) corresponding to the third inner wall (345).

[0108] FIG. 8 is a drawing of a second modified example of the inner wall of the cavity according to the second embodiment of the present invention. Referring to FIG. 8, as described above, the angle formed by the third inner wall (345) and the upper surface of the core layer (110) may have a negative angle of 0 degrees or less. Accordingly, the third inner wall (345) may include a portion that protrudes upward and overlaps the second inner wall (348) along the horizontal direction. In this case, as illustrated in FIG. 8, the third angle (b) may be defined as the angle between the upper surface of the third inner wall (345) and the second inner wall (348), and the third angle (b) may be 160 degrees or more and 180 degrees or less. In addition, the third inner wall (345) may be arranged to form an angle of 180 degrees or more with the first inner wall (342). The shape of the third inner wall (345) may be such that the vertical length from the bottom surface of the cavity increases as it goes toward the center of the cavity. Accordingly, by forming an angle of inclination of the third inner wall (345) of 180 degrees or more with respect to the adjacent inner wall between the plurality of inner walls (342, 348), not only is the bonding force with the protrusion (190) of the fifth insulating layer (115) more firmly formed, but also the placement space of the first electronic element in the space within the cavity can be more immediately defined, thereby improving production efficiency.

[0109] Figure 9 is a cross-sectional view of a semiconductor package according to a second embodiment of the present invention.

[0110] Referring to FIG. 9, as described above, a fifth insulating layer (115) may be disposed on the second insulating layer (114). The fifth insulating layer (115) may include a base region and a protrusion (190) that protrudes downward from the lower surface of the base region to fill the cavity. Accordingly, due to the various inclination angles of the cavity inner wall described above, the side surface of the protrusion (190) may be formed with a plurality of regions having different inclination angles. Specifically, the side surface of the protrusion (190) may include a first side surface (199) corresponding to the first inner wall (342), a second side surface (197) corresponding to the second inner wall (348), and a third side surface (198) disposed between the first side surface (199) and the second side surface (197) and corresponding to the third inner wall (345).

[0111] Figure 10 is a table comparing the shapes of cavities according to various process conditions according to an embodiment of the present invention.

[0112] Referring to Fig. 10, the cavity of the circuit board according to the present embodiment can be formed by laser processing. In this case, the laser processing can be performed using CO2 gas.

[0113] The inner wall shape of a circuit board cavity can be controlled by varying process conditions. For example, the inner wall shape of a cavity can be modified by adjusting factors such as the diameter of the irradiating laser, the number of laser pulses per unit time, the number of laser pulses per unit area, and the irradiation pitch.

[0114] In addition, the shape of the inner wall of the cavity of the circuit board can be controlled by controlling the energy of the CO2 being irradiated. In this case, as illustrated in Fig. 10, it can be confirmed that as the CO2 energy increases, the inclination angle formed by the upper surface of the first inner wall (142) or the second inner wall (147) and the first insulating layer (112) increases, and as the CO2 energy decreases, the inclination angle formed by the upper surface of the first inner wall (142) or the second inner wall (147) and the first insulating layer (112) decreases.

[0115] Therefore, according to the present embodiment, the formation of the inner wall of the cavity can be variously controlled according to various changes in process conditions, thereby securing a wider space for arranging electronic components, and the process of bonding electronic components can be performed more easily.

[0116] In addition, since air bubbles in the bonding member can be easily discharged to the outside by securing a gap between the electronic component and the inner wall of the cavity, the bonding strength of the electronic component can be further strengthened.

[0117]

[0118] *99 In addition, due to the multiple inner wall structure with different slope angles within the multiple insulating layers, there is an advantage in that the bonding force between the multiple insulating layers can be maintained more firmly.

[0119] Fig. 11 is a cross-sectional view of a semiconductor package according to a third embodiment of the present invention.

[0120] This embodiment is identical to the first and second embodiments in other respects, with the only difference being the formation of a through-via electrode (139). Therefore, only the through-via electrode, which is a characteristic feature of this embodiment, will be described below, and the description according to the previously described embodiment will be used for the remaining portions.

[0121] Some of the plurality of vias may include a through-via electrode (139). The through-via electrode (139) may be disposed between the seventh wiring portion (127) and the second wiring portion (122). The through-via electrode (139) may be disposed to penetrate a plurality of different insulating layers. The through-via electrode (139) may be disposed to penetrate at least a portion of the fifth insulating layer (115) and the second insulating layer (114). The through-via electrode (139) may be disposed to overlap the fifth insulating layer (115) and the second insulating layer (114) in a horizontal direction. The seventh wiring portion (127) and the second wiring portion (122) may be electrically connected through the through-via electrode (139). The through-via electrode (139) may have a shape in which a horizontal width becomes smaller as it goes downward.

[0122] The signal transmission length can be shortened in the vertical direction within the circuit board through the through via electrode (139). Accordingly, the electrical characteristics of the circuit board, such as insertion loss, resistance, and inductance, can be improved.

[0123] Meanwhile, the second insulating layer (114) includes a via hole through which at least a portion of the through-via electrode (139) passes, and at least a portion of the through-via electrode (139) may be disposed within the via hole. In addition, the fifth insulating layer (115) may include a protrusion (115a) having a shape that protrudes downward from the lower surface, and the protrusion (115a) may be embedded in the via hole within the second insulating layer (114). In this case, at least a portion of the through-via electrode (139) may be disposed within the protrusion (115a).

[0124] When a through-via electrode (139) is placed on a second insulating layer (114) that does not include a protrusion (115a), a side protrusion of the through-via electrode (139) may be formed at the interface between the fifth insulating layer (115) that has undergone the desmear process and the second insulating layer (114). This side protrusion is formed at the interface between the fifth insulating layer (115) and the second insulating layer (114) in the horizontal direction, and may cause problems such as migration of metal ions to the adjacent through-via electrode (139) and / or via portion and / or wiring portion, thereby lowering electrical reliability. Therefore, not only cannot the density of the through-via electrode (139) be improved, but also the reliability of the circuit board is lowered, and further, it becomes a factor that lowers the reliability of electronic products such as servers or high-performance computers to which the circuit board is applied. Accordingly, by arranging the through via electrode (139) within the protrusion (115a) of the fifth insulating layer (115), electrical reliability problems such as migration can be improved, and technical interoperability or functional integrity can be achieved to enable smooth operation of the electronic product.

[0125] Although all components constituting the embodiments of the present invention have been described above as being combined or operating in combination, the present invention is not necessarily limited to these embodiments. That is, within the scope of the purpose of the present invention, all components may be selectively combined and operated one or more times. In addition, terms such as "include," "comprise," or "have" described above, unless specifically stated to the contrary, mean that the corresponding component may be inherent, and therefore should be interpreted as including other components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as generally understood by a person of ordinary skill in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as terms defined in a dictionary, should be interpreted as being consistent with the contextual meaning of the related technology, and shall not be interpreted in an ideal or excessively formal sense, unless explicitly defined in the present invention.

[0126] The above description is merely an illustrative description of the technical idea of ​​the present invention, and those skilled in the art will appreciate that various modifications and variations may be made without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the technical idea of ​​the present invention, and the scope of the technical idea of ​​the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of the rights of the present invention.

[0127] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0128] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

Claims

1. Core layer; A first insulating layer disposed on the core layer and including a first through hole; and A second insulating layer is disposed on the first insulating layer and includes a second through hole that overlaps the first through hole in a vertical direction, The first inner wall of the first through hole forms a first angle with the upper surface of the core layer, The second inner wall of the second through hole and the upper surface of the first insulating layer form a second angle, The above first angle and the above second angle are different, A circuit board in which the vertical thickness of the first insulating layer is different from the vertical thickness of the second insulating layer.

2. In paragraph 1, A circuit board wherein the first angle is smaller than the second angle.

3. In paragraph 1, A circuit board wherein the first angle is greater than the second angle.

4. In paragraph 1, Including a third inner wall disposed between the first inner wall and the second inner wall, A circuit board in which the third inner wall forms a third angle different from the first angle and the second angle with the upper surface of the core layer.

5. In paragraph 4, The circuit board wherein the third angle is smaller than the first angle and the second angle.

6. In paragraph 4, The above third angle is a circuit board having an obtuse angle.

7. In paragraph 4, The third inner wall is a circuit board parallel to the upper surface of the core layer.

8. In paragraph 4, The third inner wall is a circuit board forming the inner wall of the first through hole.

9. In paragraph 1, The above first through hole and the above second through hole form a cavity, including a connection pad arranged on the bottom surface of the cavity; The above connection pad is a circuit board spaced horizontally from the first inner wall.

10. Core layer; A first insulating layer disposed on the core layer and including a first through hole; A second insulating layer disposed on the first insulating layer and including a second through hole vertically overlapping the first through hole; and It includes a first electronic element arranged in a cavity formed by the first through hole and the second through hole, The first inner wall of the first through hole forms a first angle with the upper surface of the core layer, The second inner wall of the second through hole and the upper surface of the first insulating layer form a second angle, The above first angle and the above second angle are different, A semiconductor package wherein the vertical thickness of the first insulating layer is different from the vertical thickness of the second insulating layer.

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