Pixel circuit, pixel driving method and display apparatus

Abstract

Provided in the present disclosure are a pixel circuit, a pixel driving method and a display apparatus. The pixel circuit comprises a light-emitting element, a driving circuit, a compensation control circuit, and a connection / disconnection control circuit, wherein the compensation control circuit controls the connection or disconnection between a third node and a control node under the control of a compensation control signal; and the connection / disconnection control circuit controls the connection or disconnection between a first node and the control node under the control of a first scanning signal. The present disclosure eliminates the impact of gate potential variations of driving transistors caused by the characteristic drift of oxide transistors in reliability processes, thereby ameliorating horizontal stripe mura in the reliability processes.

Description

Pixel circuit, pixel driving method and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a pixel circuit, a pixel driving method and a display device. BACKGROUND

[0002] With the maturity of AMOLED (Active-matrix organic light-emitting diode) technology, more and more terminals use AMOLED as a display panel. In view of diversified application requirements, the market also increasingly urgently requires low frame frequency (90Hz, 120Hz) AMOLED screens. In a related pixel circuit, a transistor included in a compensation control circuit is an oxide transistor. However, because the oxide transistor is very sensitive, during a reliability test process of a product, due to long-time circuit bias and high temperature, the oxide transistor characteristics will shift, especially the threshold voltage shift, which will cause the potential written to the gate of a driving transistor to fluctuate, so that the driving circuit itself is very sensitive to the characteristic change of the transistor included in the compensation control circuit, especially the threshold voltage change, and slight fluctuation of the threshold voltage will cause the change of the light-emitting current, especially at low brightness and low gray scale, the problem is more serious, and horizontal stripe defects are prone to occur during the reliability process.

[0003] SUMMARY

[0004] In one aspect, the embodiments of the present disclosure provide a pixel circuit, comprising a light-emitting element, a driving circuit, a compensation control circuit and a pass-fail control circuit.

[0005] The control end of the driving circuit is electrically connected with a first node, the first end of the driving circuit is electrically connected with a second node, the second end of the driving circuit is electrically connected with a third node, and the driving circuit is used to generate a driving current for driving the light-emitting element under the control of the potential of the first node.

[0006] The compensation control circuit is electrically connected with a compensation control end, a control node and the third node respectively, and is used to control the communication or disconnection between the control node and the third node under the control of a compensation control signal provided by the compensation control end.

[0007] The pass-fail control circuit is electrically connected with a first scanning end, the first node and the control node respectively, and is used to control the communication or disconnection between the first node and the control node under the control of a first scanning signal provided by the first scanning end.

[0008] Optionally, the refresh frame comprises a data writing stage, a voltage control stage and a refresh light emitting stage arranged in sequence.

[0009] The on-off control circuit is configured to, in the voltage control stage, control the first node and the control node to be in communication under the control of the first scan signal.

[0010] Optionally, the holding frame comprises a holding control stage and a holding light emitting stage arranged in sequence.

[0011] The on-off control circuit is configured to, in the holding control stage, control the first node and the control node to be in communication under the control of the first scan signal.

[0012] Optionally, the on-off control circuit comprises a first transistor.

[0013] The gate of the first transistor is electrically connected to the first scan end, the first pole of the first transistor is electrically connected to the first node, and the second pole of the first transistor is electrically connected to the control node.

[0014] The first transistor is a low-temperature polysilicon transistor.

[0015] Optionally, the channel width of the first transistor is greater than 0 and less than or equal to 2.5 μm; and / or, the channel length of the first transistor is greater than 0 and less than or equal to 3 μm.

[0016] Optionally, the pixel circuit further comprises a first energy storage circuit.

[0017] The first end of the first energy storage circuit is electrically connected to the control node, and the second end of the first energy storage circuit is electrically connected to a first voltage end.

[0018] The first voltage end is configured to provide a first voltage signal.

[0019] The first voltage signal is a direct current voltage signal; or,

[0020] In the refresh frame, the voltage value of the first voltage signal in the refresh light emitting stage is not equal to the voltage value of the first voltage signal in the non-light emitting stage; and / or, in at least part of the time of the holding frame, the voltage value of the first voltage signal is not equal to the voltage value of the first voltage signal in at least part of the time of the refresh frame.

[0021] The non-light emitting stage is a time period in the refresh frame except the refresh light emitting stage.

[0022] Optionally, in a refresh frame, a voltage value of the first voltage signal in a refresh light-emitting stage is less than a voltage value of the first voltage signal in a non-light-emitting stage; and / or, in at least part of a holding frame, a voltage value of the first voltage signal is less than a voltage value of the first voltage signal in at least part of a refresh frame.

[0023] Optionally, the pixel circuit further comprises a second energy storage circuit and a third energy storage circuit.

[0024] The first end of the second energy storage circuit is electrically connected with the control node, and the second end of the second energy storage circuit is electrically connected with the compensation control end, and the second energy storage circuit is used for storing electric energy.

[0025] The first end of the third energy storage circuit is electrically connected with the first scanning end, and the second end of the third energy storage circuit is electrically connected with the control node, and the third energy storage circuit is used for storing electric energy.

[0026] Optionally, the pixel circuit comprises a first energy storage circuit; the first energy storage circuit comprises a first capacitor.

[0027] The first end of the first capacitor is electrically connected with the control node, and the second end of the first capacitor is electrically connected with the first voltage end.

[0028] The second energy storage circuit comprises a second capacitor, and the third energy storage circuit comprises a third capacitor.

[0029] The first end of the second capacitor is electrically connected with the control node, and the second end of the second capacitor is electrically connected with the compensation control end.

[0030] The first end of the third capacitor is electrically connected with the first scanning end, and the second end of the third capacitor is electrically connected with the control node.

[0031] The capacitance value of the first capacitor is greater than the capacitance value of the third capacitor, and the capacitance value of the second capacitor is greater than the capacitance value of the third capacitor.

[0032] Optionally, the pixel circuit further comprises a data writing circuit and a fourth energy storage circuit.

[0033] The data writing circuit is electrically connected with a second scanning end, a data line and the second node respectively, and is used for controlling the data line to be in communication or disconnection with the second node under the control of a second scanning signal provided by the second scanning end.

[0034] The fourth energy storage circuit is electrically connected with the first node, and is used for maintaining the electric potential of the first node.

[0035] Optionally, the pixel circuit further comprises a first light-emitting control circuit, a second light-emitting control circuit, a first reset circuit, a second reset circuit and a third reset circuit.

[0036] The first light-emitting control circuit is electrically connected with the light-emitting control end, the power voltage end and the second node respectively, and is configured to control the power voltage end and the second node to be in communication or disconnected under the control of a light-emitting control signal provided by the light-emitting control end.

[0037] The second light-emitting control circuit is electrically connected with the light-emitting control end, the third node and the first pole of the light-emitting element respectively, and is configured to control the third node and the first pole of the light-emitting element to be in communication or disconnected under the control of a light-emitting control signal provided by the light-emitting control end; the second pole of the light-emitting element is electrically connected with the second voltage end.

[0038] The first reset circuit is electrically connected with the first reset control end, the first initial voltage end and the control node respectively, and is configured to write a first initial voltage provided by the first initial voltage end into the control node under the control of a first reset control signal provided by the first reset control end.

[0039] The second reset circuit is electrically connected with the second reset control end, the second initial voltage end and the first pole of the light-emitting element respectively, and is configured to write a second initial voltage provided by the second initial voltage end into the first pole of the light-emitting element under the control of a second reset control signal provided by the second reset control end.

[0040] The third reset circuit is electrically connected with the third reset control end, the third initial voltage end and the second node respectively, and is configured to write a third initial voltage provided by the third initial voltage end into the second node under the control of a third reset control signal provided by the third reset control end.

[0041] Optionally, the compensation control circuit comprises a second transistor, the data writing circuit comprises a third transistor, the driving circuit comprises a driving transistor, and the fourth energy storage circuit comprises a storage capacitor.

[0042] The gate of the second transistor is electrically connected with the compensation control end, the first pole of the second transistor is electrically connected with the control node, and the second pole of the second transistor is electrically connected with the third node.

[0043] The gate of the third transistor is electrically connected with the second scanning end, the first pole of the third transistor is electrically connected with the data line, and the second pole of the third transistor is electrically connected with the second node.

[0044] A gate of the driving transistor is electrically connected with the first node, a first electrode of the driving transistor is electrically connected with the second node, and a second electrode of the driving transistor is electrically connected with the third node.

[0045] A first end of the storage capacitor is electrically connected with the first node, and a second end of the storage capacitor is electrically connected with a direct current voltage terminal.

[0046] Optionally, the second transistor is an oxide transistor.

[0047] In a second aspect, the pixel driving method is applied to the pixel circuit, and a refresh frame includes a set phase and a refresh light-emitting phase arranged in sequence; the set phase includes a first set time period, an interval time period and a second set time period arranged in sequence; and the pixel driving method includes:

[0048] In the first set time period and the second set time period, the on-off control circuit controls the first node and the control node to be connected under the control of the first scan signal.

[0049] In the interval time period, the on-off control circuit controls the first node and the control node to be disconnected under the control of the first scan signal.

[0050] In the refresh light-emitting phase, the driving circuit generates a driving current for driving the light-emitting element under the control of the potential of the first node.

[0051] Optionally, the pixel circuit further includes a data writing circuit; the refresh frame further includes a data writing phase arranged between the set phase and the refresh light-emitting phase; and the pixel driving method further includes:

[0052] In the data writing phase, the data writing circuit writes a data voltage provided by a data line into the second node under the control of a second scan signal, the compensation control circuit controls the control node and the third node to be connected under the control of the compensation control signal, and the on-off control circuit controls the first node and the control node to be connected under the control of the first scan signal.

[0053] Optionally, the refresh frame further includes a voltage control phase arranged between the data writing phase and the refresh light-emitting phase; and the pixel driving method further includes:

[0054] In the voltage control phase, the on-off control circuit controls the first node and the control node to be connected under the control of the first scan signal.

[0055] Optionally, the refresh frame further includes a third reset phase arranged between the data writing phase and the refresh light-emitting phase; and the pixel driving method further includes:

[0056] In the third reset stage, the second reset circuit writes the second initial voltage into the first electrode of the light emitting element under the control of the second reset control signal, and the third reset circuit writes the third initial voltage into the second node under the control of the third reset control signal.

[0057] The voltage control stage is arranged before the third reset stage, or the voltage control stage is arranged after the third reset stage.

[0058] Optionally, the holding frame comprises a holding control stage and a holding light emitting stage arranged in sequence; the pixel driving method further comprises:

[0059] In the holding control stage, the on-off control circuit controls the communication between the first node and the control node under the control of the first scanning signal.

[0060] In the holding light emitting stage, the driving circuit generates the driving current for driving the light emitting element under the control of the potential of the first node.

[0061] Optionally, the holding frame further comprises a holding reset stage; the pixel driving method further comprises:

[0062] In the holding reset stage, the second reset circuit writes the second initial voltage into the first electrode of the light emitting element under the control of the second reset control signal, and the third reset circuit writes the third initial voltage into the second node under the control of the third reset control signal.

[0063] The holding control stage is arranged before the holding reset stage, or the holding control stage is arranged after the holding reset stage.

[0064] In a third aspect, the embodiments of the present disclosure provide a display device comprising the pixel circuit. BRIEF DESCRIPTION OF DRAWINGS

[0065] FIG. 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0066] FIG. 2A is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0067] FIG. 2B is a schematic diagram of the corresponding relationship between the change value of Vth1 and the percentage of the change amount of Id when the pixel circuit is a red pixel circuit;

[0068] FIG. 2C is a schematic diagram of the corresponding relationship between the change value of Vth1 and the percentage of the change amount of Id when the pixel circuit is a green pixel circuit;

[0069] FIG. 2D is a schematic diagram of the corresponding relationship between the change value of Vth1 and the percentage of the change amount of Id when the pixel circuit is a green pixel circuit;

[0070] FIG. 2E is a schematic diagram of the corresponding relationship between the change value of Vth1 and the percentage of the change amount of Id when the channel length L of T1 changes while the channel width W of T1 is fixed;

[0071] FIG. 2F is a schematic diagram of the corresponding relationship between the change value of Vth1 and the percentage of the change amount of Id when the channel width W of T1 changes while the channel length L of T1 is fixed;

[0072] FIG. 2G is a waveform diagram of the voltage value of the first node N1 when the capacitance value of the first capacitor is different;

[0073] FIG. 3A is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0074] FIG. 3B is a waveform diagram of the voltage value of the first node N1 when the capacitance value of the third capacitor is different;

[0075] FIG. 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0076] FIG. 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0077] FIG. 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0078] FIG. 7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0079] FIG. 8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0080] FIG. 9 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0081] FIG. 10A is a timing diagram of at least one embodiment of the pixel circuit shown in FIG. 9;

[0082] FIG. 10B is a timing diagram of at least one embodiment of the pixel circuit shown in FIG. 9;

[0083] FIG. 10C is a timing diagram of at least one embodiment of the pixel circuit shown in FIG. 9;

[0084] FIG. 10D is a timing diagram of at least one embodiment of the pixel circuit shown in FIG. 9;

[0085] FIG. 10E is a timing diagram of at least one embodiment of the pixel circuit shown in FIG. 9;

[0086] FIG. 11 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0087] FIG. 12 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0088] FIG. 13 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0089] FIG. 14 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0090] FIG. 15 is a timing diagram of at least one embodiment of the pixel circuit shown in FIG. 14. DETAILED DESCRIPTION

[0091] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of the present disclosure.

[0092] The transistors used in all the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two poles of the transistor other than the gate, one pole is referred to as the first pole and the other pole is referred to as the second pole.

[0093] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be a drain and the second pole can be a source, or the first pole can be a source and the second pole can be a drain.

[0094] As shown in FIG. 1, the pixel circuit according to the embodiments of the present disclosure includes a light emitting element E1, a driving circuit 10, a compensation control circuit 11, and a on-off control circuit 12.

[0095] The control end of the driving circuit 10 is electrically connected with a first node N1, the first end of the driving circuit 10 is electrically connected with a second node N2, the second end of the driving circuit 10 is electrically connected with a third node N3, and the driving circuit 10 is configured to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1.

[0096] The compensation control circuit 11 is electrically connected with a compensation control end SC, a control node NC, and the third node N3, respectively, and is configured to control the communication or disconnection between the control node NC and the third node N3 under the control of a compensation control signal Ssc provided by the compensation control end SC.

[0097] The on / off control circuit 12 is electrically connected to the first scanning terminal GT1, the first node N1, and the control node NC, respectively, and is used to control the connection or disconnection between the first node N1 and the control node NC under the control of the first scanning signal Sgt1 provided by the first scanning terminal GT1.

[0098] In at least one embodiment of this disclosure, the compensation control circuit 11 includes an oxide transistor. In at least one embodiment of this disclosure, an on / off control circuit 12 is added between the oxide transistor and the gate of the driving transistor in the driving circuit 10. The on / off control circuit 12 includes an LTPS (low-temperature polysilicon) transistor, thereby removing the influence of the gate potential change of the driving transistor caused by the characteristic shift of the oxide transistor during the reliability process, thereby improving the horizontal stripe defects in the reliability process.

[0099] In at least one embodiment of this disclosure, the refresh frame may include a data writing phase, a voltage control phase, and a refresh emission phase that are set sequentially.

[0100] The on / off control circuit is used during the voltage control phase to control the connection between the first node and the control node under the control of the first scan signal.

[0101] In specific implementation, during the refresh frame, before the refresh light emission stage, during the voltage control stage, the on / off control circuit, under the control of the first scan signal, controls the connection between the first node and the control node so that the potential of the first node is the same as the potential of the control node, reducing the leakage current between the first node and the control node, which is beneficial to maintaining the potential of the first node during the refresh light emission stage.

[0102] In at least one embodiment of this disclosure, the holding frame may include a holding control phase and a holding light emission phase that are set sequentially;

[0103] The on / off control circuit is used during the holding control phase to control the connection between the first node and the control node under the control of the first scan signal.

[0104] In specific implementation, during the holding frame, before the holding light emission stage, during the holding control stage, the on / off control circuit, under the control of the first scan signal, controls the connection between the first node and the control node so that the potential of the first node is the same as the potential of the control node, reducing the leakage current between the first node and the control node, which is beneficial to maintaining the potential of the first node during the holding light emission stage.

[0105] Optionally, the on / off control circuit includes a first transistor;

[0106] The gate of the first transistor is electrically connected to the first scan terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the control node.

[0107] The first transistor is a low-temperature polycrystalline silicon transistor.

[0108] As shown in Figure 2A, in at least one embodiment of the pixel circuit shown in Figure 1, the on / off control circuit may include a first transistor T1;

[0109] The gate of T1 is electrically connected to the first scan terminal GT1, the source of T1 is electrically connected to the first node N1, and the drain of T1 is electrically connected to the control node NC.

[0110] T1 is a low-temperature polycrystalline silicon oxide transistor, and T1 is a p-type transistor.

[0111] As shown in Figures 2B, 2C, and 2D, after performing sensitivity simulation on T1, it was found that the driving current Id changes significantly when the threshold voltage Vth1 of T1 changes.

[0112] Figure 2B is a schematic diagram showing the relationship between the change in Vth1 and the percentage change in Id when the pixel circuit is a red pixel circuit.

[0113] Figure 2C is a schematic diagram showing the percentage relationship between the change in Vth1 and the change in Id when the pixel circuit is a green pixel circuit;

[0114] Figure 2D is a schematic diagram showing the percentage relationship between the change in Vth1 and the change in Id when the pixel circuit is a green pixel circuit.

[0115] In Figures 2B, 2C, and 2D, the horizontal axis represents the change in Vth1, and the vertical axis represents the percentage change in Id.

[0116] In at least one embodiment of this disclosure, the channel width of the first transistor is greater than 0 and less than or equal to 2.5 μm; and / or, the channel length of the first transistor is greater than 0 and less than or equal to 3 μm.

[0117] Optionally, the channel width W1 of T1 can be greater than or equal to 1.5 μm and less than or equal to 2.5 μm; for example, W1 can be equal to 1.8 μm.

[0118] The channel length L1 of T1 can be greater than or equal to 2 μm and less than or equal to 3 μm; for example, L1 can be equal to 2.7 μm.

[0119] In a specific implementation, when the channel width W of the first transistor is fixed and the channel length L of the first transistor is changed, the threshold voltage sensitivity of the first transistor is better as the channel length L decreases.

[0120] When the channel length L of the first transistor is fixed and the channel width W of the first transistor is changed, the threshold voltage sensitivity of the first transistor is better as the channel width W decreases.

[0121] In at least one embodiment of this disclosure, the channel width W and channel length L of the first transistor can be made as small as possible while meeting process limits. This results in smaller gate-source parasitic capacitance Cgs and gate-drain parasitic capacitance Cgd of the first transistor. After the threshold voltage shifts, the CV curve (the CV curve is the relationship curve between the parasitic capacitance of the first transistor and the gate-source voltage of the first transistor) will also change. At the instant the first scan terminal is turned off, the potential of the first node and the potential of the control node are pulled up relatively small, resulting in a small final brightness difference, which can effectively improve the flickering problem caused by the first transistor.

[0122] Figure 2E is a schematic diagram showing the relationship between the change in threshold voltage Vth1 of T1 and the percentage change in Id when the channel width W of T1 is fixed and the channel length L of T1 varies.

[0123] Figure 2F is a schematic diagram showing the relationship between the change in threshold voltage Vth1 of T1 and the percentage change in Id when the channel length L of T1 is fixed and the channel width W of T1 varies.

[0124] As shown in Figure 2E, when W is fixed and L decreases, T1 has a better threshold voltage sensitivity; as shown in Figure 2F, when L is fixed and W decreases, T1 has a better threshold voltage sensitivity.

[0125] The pixel circuit described in at least one embodiment of this disclosure further includes a first energy storage circuit;

[0126] The first terminal of the first energy storage circuit is electrically connected to the control node, and the second terminal of the first energy storage circuit is electrically connected to the first voltage terminal. The first energy storage circuit is used to store electrical energy.

[0127] The first voltage terminal is used to provide a first voltage signal;

[0128] The first voltage signal is a DC voltage signal; or,

[0129] During the refresh frame, the voltage value of the first voltage signal during the refresh emission phase is not equal to the voltage value of the first voltage signal during the non-emission phase; and / or, during at least a portion of the hold frame, the voltage value of the first voltage signal is not equal to the voltage value of the first voltage signal during at least a portion of the refresh frame.

[0130] In a specific implementation, the first voltage terminal can be a DC voltage terminal, used to provide a DC voltage signal; for example, the first voltage terminal can be a power supply voltage signal.

[0131] In at least one embodiment of this disclosure, during a refresh frame, the voltage value of the first voltage signal during the refresh emission phase is less than the voltage value of the first voltage signal during the non-emission phase; and / or, during at least a portion of the time of a hold frame, the voltage value of the first voltage signal is less than the voltage value of the first voltage signal during at least a portion of the time of the refresh frame.

[0132] In at least one embodiment of this disclosure, the refresh frame may include a refresh emission phase and a non-emission phase. The non-emission phase may include a time period in the refresh frame other than the refresh emission phase. During the refresh emission phase, the voltage value of the first voltage signal may be lower than the voltage value during the non-emission phase, thereby reducing the potential of the control node during the refresh emission phase, reducing the difference between the potential of the first node and the potential of the control node, reducing leakage current, and facilitating the maintenance of the potential of the first node. For example, the first voltage terminal may be an emission control terminal, and the first voltage signal may be an emission control signal.

[0133] In at least one embodiment of this disclosure, when the display panel is performing a low-frequency display, during at least a portion of the hold frame time, the voltage value of the first voltage signal may be lower than the voltage value of the first voltage signal during at least a portion of the refresh frame time. This lowers the potential of the control node during the hold frame, reducing the difference between the potential of the first node and the potential of the control node, reducing leakage current, facilitating the maintenance of the potential of the first node, and improving flickering. For example, the first voltage terminal may be a second initial voltage terminal or a third initial voltage terminal, and the first voltage signal may be a second initial voltage signal or a third initial voltage signal.

[0134] For example, in a hold frame, the voltage value of the second initial voltage signal can be -4V, and in a refresh frame, the voltage value of the second initial voltage signal can be -3.5V.

[0135] In the hold frame, the voltage value of the third initial voltage signal can be 6.6V, and in the refresh frame, the voltage value of the third initial voltage signal can be 6.8V.

[0136] In a specific implementation, the pixel circuit may further include a first energy storage circuit, which is used to maintain the potential of the control node.

[0137] Optionally, the first energy storage circuit includes a first capacitor;

[0138] The first terminal of the first capacitor is electrically connected to the control node, and the second terminal of the first capacitor is electrically connected to the first voltage terminal.

[0139] In at least one embodiment of this disclosure, the capacitance value of the first capacitor may be greater than or equal to 2.5fF.

[0140] Optionally, the capacitance value of the first capacitor can be greater than or equal to 2.5fF and less than or equal to 4fF. For example, the capacitance value of the first capacitor can be equal to 2.8fF.

[0141] In at least one embodiment of this disclosure, the first transistor is an LTPS transistor. Leakage problems can cause low-frequency drive flickering. Therefore, a first energy storage circuit is used. By setting the capacitance value of the first capacitor included in the first energy storage circuit to a large value, the potential stability of the control node is increased. This makes the potential change of the control node approximately equal to the potential change of the first node at the instant the first scan terminal is turned off, thus making the voltage difference between the control node and the first node smaller and increasing the potential stability of the first node.

[0142] As shown in Figure 2G, when the capacitance value of the first capacitor is large, the voltage value of N1 is more stable.

[0143] In Figure 2G, the horizontal axis represents time, and the vertical axis represents the voltage value of N1;

[0144] The first waveform L1 corresponds to the capacitance value of C1 being the first capacitance value, and the second waveform L2 corresponds to the capacitance value of C1 being the second capacitance value, which is greater than the first capacitance value.

[0145] As shown in FIG3A, based on at least one embodiment of the pixel circuit shown in FIG1, the pixel circuit of at least one embodiment of the present disclosure further includes a first energy storage circuit 31;

[0146] The first terminal of the first energy storage circuit 31 is electrically connected to the control node NC, and the second terminal of the first energy storage circuit 31 is electrically connected to the first voltage terminal V1. The first energy storage circuit 31 is used to store electrical energy.

[0147] The pixel circuit described in at least one embodiment of this disclosure further includes a second energy storage circuit and a third energy storage circuit;

[0148] The first end of the second energy storage circuit is electrically connected to the control node, and the second end of the second energy storage circuit is electrically connected to the compensation control terminal. The second energy storage circuit is used to store electrical energy.

[0149] The first end of the third energy storage circuit is electrically connected to the first scanning end, and the second end of the third energy storage circuit is electrically connected to the control node. The third energy storage circuit is used to store electrical energy.

[0150] In a specific implementation, the pixel circuit may further include a second energy storage circuit and a third energy storage circuit. The second energy storage circuit controls the potential of the control node according to the potential of the compensation control terminal, and the third energy storage circuit controls the potential of the control node according to the potential of the first scanning terminal.

[0151] Optionally, the second energy storage circuit includes a second capacitor, and the third energy storage circuit includes a third capacitor;

[0152] The first terminal of the second capacitor is electrically connected to the control node, and the second terminal of the second capacitor is electrically connected to the compensation control terminal.

[0153] The first terminal of the third capacitor is electrically connected to the first scanning terminal, and the second terminal of the third capacitor is electrically connected to the control node.

[0154] Optionally, the capacitance value of the first capacitor is greater than the capacitance value of the third capacitor, and the capacitance value of the second capacitor is greater than the capacitance value of the third capacitor.

[0155] In at least one embodiment of this disclosure, the capacitance value of the second capacitor is greater than or equal to 1fF. For example, the capacitance value of the second capacitor may be greater than or equal to 1fF and less than or equal to 3fF.

[0156] The capacitance value of the third capacitor is greater than 0 and less than or equal to 3fF.

[0157] As shown in Figure 3B, when the capacitance value of the first capacitor is large, the voltage value of N1 is more stable.

[0158] In Figure 3B, the horizontal axis represents time, and the vertical axis represents the voltage value of N1;

[0159] The third waveform L3 corresponds to the capacitance value of C3, the fourth waveform L4 corresponds to the capacitance value of C3, the fifth waveform L5 corresponds to the capacitance value of C3, and the sixth waveform L6 corresponds to the capacitance value of C3. The third capacitance value is greater than the fourth capacitance value, the fourth capacitance value is greater than the fifth capacitance value, and the fifth capacitance value is greater than the sixth capacitance value.

[0160] In at least one embodiment of this disclosure, the first transistor is an LTPS transistor. Leakage can cause low-frequency drive flickering. Therefore, a second energy storage circuit and a third energy storage circuit are used. By setting the capacitance value of the second capacitor included in the second energy storage circuit to be larger and the capacitance value of the third capacitor included in the third energy storage circuit to be smaller, when the first scanning terminal is turned off, after the potential of the control node is raised by the first scanning signal, the potential of the control node is recoupled and lowered by compensating for the moment the control terminal is turned off, thereby reducing the voltage difference between the control node and the first node, thus reducing leakage and improving the stability of the first node.

[0161] As shown in Figure 4, based on at least one embodiment of the pixel circuit shown in Figure 1, the pixel circuit of at least one embodiment of this disclosure further includes a second energy storage circuit 32 and a third energy storage circuit 33.

[0162] The first end of the second energy storage circuit 32 is electrically connected to the control node NC, and the second end of the second energy storage circuit 32 is electrically connected to the compensation control terminal SC. The second energy storage circuit 32 is used to store electrical energy.

[0163] The first end of the third energy storage circuit 33 is electrically connected to the first scanning end GT1, and the second end of the third energy storage circuit 33 is electrically connected to the control node NC. The third energy storage circuit 33 is used to store electrical energy.

[0164] As shown in Figure 5, based on at least one embodiment of the pixel circuit shown in Figure 1, the pixel circuit of at least one embodiment of this disclosure further includes a first energy storage circuit 31, a second energy storage circuit 32 and a third energy storage circuit 33.

[0165] The first terminal of the first energy storage circuit 31 is electrically connected to the control node NC, and the second terminal of the first energy storage circuit 31 is electrically connected to the first voltage terminal V1. The first energy storage circuit 31 is used to store electrical energy.

[0166] The first end of the second energy storage circuit 32 is electrically connected to the control node NC, and the second end of the second energy storage circuit 32 is electrically connected to the compensation control terminal SC. The second energy storage circuit 32 is used to store electrical energy.

[0167] The first end of the third energy storage circuit 33 is electrically connected to the first scanning end GT1, and the second end of the third energy storage circuit 33 is electrically connected to the control node NC. The third energy storage circuit 33 is used to store electrical energy.

[0168] The pixel circuit described in at least one embodiment of this disclosure further includes a data writing circuit and a fourth energy storage circuit;

[0169] The data writing circuit is electrically connected to the second scanning end, the data line and the second node respectively, and is used to control the connection or disconnection between the data line and the second node under the control of the second scanning signal provided by the second scanning end;

[0170] The fourth energy storage circuit is electrically connected to the first node and is used to maintain the potential of the first node.

[0171] In a specific implementation, the pixel circuit may further include a data writing circuit and a fourth energy storage circuit. Under the control of the second scan signal, the data writing circuit writes the data voltage on the data line into the second node, and the fourth energy storage circuit maintains the potential of the first node.

[0172] In at least one embodiment of this disclosure, the first scanning end and the second scanning end can be the same scanning end, but this is not a limitation. In actual operation, the first scanning end and the second scanning end can be different scanning ends.

[0173] The pixel circuit described in at least one embodiment of this disclosure further includes a first light-emitting control circuit, a second light-emitting control circuit, a first reset circuit, a second reset circuit, and a third reset circuit;

[0174] The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control terminal.

[0175] The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the third node and the first electrode of the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control terminal; the second electrode of the light-emitting element is electrically connected to the second voltage terminal;

[0176] The first reset circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the control node, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the control node under the control of the first reset control signal provided by the first reset control terminal;

[0177] The second reset circuit is electrically connected to the second reset control terminal, the second initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal;

[0178] The third reset circuit is electrically connected to the third reset control terminal, the third initial voltage terminal, and the second node, respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the second node under the control of the third reset control signal provided by the third reset control terminal.

[0179] In a specific implementation, the pixel circuit may further include a first light-emitting control circuit, a second light-emitting control circuit, a first reset circuit, a second reset circuit, and a third reset circuit. The first light-emitting control circuit and the second light-emitting control circuit are used for light-emitting control. Under the control of a first reset control signal, the first reset circuit writes a first initial voltage into the control node to initialize the potential of the control node. Under the control of a second reset control signal, the second reset circuit writes a second initial voltage into the first electrode of the light-emitting element to clear the residual charge on the first electrode of the light-emitting element. Under the control of a third reset control signal, the third reset circuit writes a third initial voltage into the second node to improve the hysteresis phenomenon of the driving transistor in the driving circuit and improve the display quality.

[0180] Optionally, the second voltage terminal can be a low voltage terminal; or, the second voltage terminal can provide a low voltage signal, or other signals, such as an initial voltage signal, a reset voltage signal, a reference voltage signal, etc.

[0181] As shown in Figure 6, based on at least one embodiment of the pixel circuit shown in Figure 3A, the pixel circuit described in at least one embodiment of this disclosure further includes a data writing circuit 40, a fourth energy storage circuit 34, a first light emission control circuit 41, a second light emission control circuit 42, a first reset circuit 51, a second reset circuit 52, and a third reset circuit 53.

[0182] The data writing circuit 40 is electrically connected to the second scanning terminal GT2, the data line DL and the second node N2 respectively, and is used to control the connection or disconnection between the data line DL and the second node N2 under the control of the second scanning signal Sgt2 provided by the second scanning terminal GT2;

[0183] The fourth energy storage circuit 34 is electrically connected to the first node N1 and is used to maintain the potential of the first node N1.

[0184] The first light-emitting control circuit 41 is electrically connected to the light-emitting control terminal EM, the power supply voltage terminal VDD and the second node N2 respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the second node N2 under the control of the light-emitting control signal Sem provided by the light-emitting control terminal EM.

[0185] The second light-emitting control circuit 42 is electrically connected to the light-emitting control terminal EM, the third node N3, and the first pole of the light-emitting element E1, respectively. It is used to control the connection or disconnection between the third node N3 and the first pole of the light-emitting element E1 under the control of the light-emitting control signal Sem provided by the light-emitting control terminal EM; the second pole of the light-emitting element E1 is electrically connected to the second voltage terminal V2.

[0186] The first reset circuit 51 is electrically connected to the first reset control terminal R1, the first initial voltage terminal I1 and the control node NC respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the control node NC under the control of the first reset control signal Sr1 provided by the first reset control terminal R1.

[0187] The second reset circuit 52 is electrically connected to the second reset control terminal R2, the second initial voltage terminal I2, and the first pole of the light-emitting element E1, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first pole of the light-emitting element E1 under the control of the second reset control signal Sr2 provided by the second reset control terminal R2.

[0188] The third reset circuit 53 is electrically connected to the third reset control terminal R3, the third initial voltage terminal I3 and the second node N2 respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the second node N2 under the control of the third reset control signal Sr3 provided by the third reset control terminal R3.

[0189] Optionally, the second reset control terminal and the third reset control terminal can be the same reset control terminal.

[0190] As shown in Figure 7, based on at least one embodiment of the pixel circuit shown in Figure 4, the pixel circuit described in at least one embodiment of this disclosure further includes a data writing circuit 40, a fourth energy storage circuit 34, a first light emission control circuit 41, a second light emission control circuit 42, a first reset circuit 51, a second reset circuit 52, and a third reset circuit 53.

[0191] The data writing circuit 40 is electrically connected to the second scanning terminal GT2, the data line DL and the second node N2 respectively, and is used to control the connection or disconnection between the data line DL and the second node N2 under the control of the second scanning signal Sgt2 provided by the second scanning terminal GT2;

[0192] The fourth energy storage circuit 34 is electrically connected to the first node N1 and is used to maintain the potential of the first node N1.

[0193] The first light-emitting control circuit 41 is electrically connected to the light-emitting control terminal EM, the power supply voltage terminal VDD and the second node N2 respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the second node N2 under the control of the light-emitting control signal Sem provided by the light-emitting control terminal EM.

[0194] The second light-emitting control circuit 42 is electrically connected to the light-emitting control terminal EM, the third node N3, and the first pole of the light-emitting element E1, respectively. It is used to control the connection or disconnection between the third node N3 and the first pole of the light-emitting element E1 under the control of the light-emitting control signal Sem provided by the light-emitting control terminal EM; the second pole of the light-emitting element E1 is electrically connected to the second voltage terminal V2.

[0195] The first reset circuit 51 is electrically connected to the first reset control terminal R1, the first initial voltage terminal I1 and the control node NC respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the control node NC under the control of the first reset control signal Sr1 provided by the first reset control terminal R1.

[0196] The second reset circuit 52 is electrically connected to the second reset control terminal R2, the second initial voltage terminal I2, and the first pole of the light-emitting element E1, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first pole of the light-emitting element E1 under the control of the second reset control signal Sr2 provided by the second reset control terminal R2.

[0197] The third reset circuit 53 is electrically connected to the third reset control terminal R3, the third initial voltage terminal I3 and the second node N2 respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the second node N2 under the control of the third reset control signal Sr3 provided by the third reset control terminal R3.

[0198] As shown in Figure 8, based on at least one embodiment of the pixel circuit shown in Figure 5, the pixel circuit described in at least one embodiment of this disclosure further includes a data writing circuit 40, a fourth energy storage circuit 34, a first light emission control circuit 41, a second light emission control circuit 42, a first reset circuit 51, a second reset circuit 52, and a third reset circuit 53.

[0199] The data writing circuit 40 is electrically connected to the second scanning terminal GT2, the data line DL and the second node N2 respectively, and is used to control the connection or disconnection between the data line DL and the second node N2 under the control of the second scanning signal Sgt2 provided by the second scanning terminal GT2;

[0200] The fourth energy storage circuit 34 is electrically connected to the first node N1 and is used to maintain the potential of the first node N1.

[0201] The first light-emitting control circuit 41 is electrically connected to the light-emitting control terminal EM, the power supply voltage terminal VDD and the second node N2 respectively, and is used to control the connection or disconnection between the power supply voltage terminal VDD and the second node N2 under the control of the light-emitting control signal Sem provided by the light-emitting control terminal EM.

[0202] The second light-emitting control circuit 42 is electrically connected to the light-emitting control terminal EM, the third node N3, and the first pole of the light-emitting element E1, respectively. It is used to control the connection or disconnection between the third node N3 and the first pole of the light-emitting element E1 under the control of the light-emitting control signal Sem provided by the light-emitting control terminal EM; the second pole of the light-emitting element E1 is electrically connected to the second voltage terminal V2.

[0203] The first reset circuit 51 is electrically connected to the first reset control terminal R1, the first initial voltage terminal I1 and the control node NC respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the control node NC under the control of the first reset control signal Sr1 provided by the first reset control terminal R1.

[0204] The second reset circuit 52 is electrically connected to the second reset control terminal R2, the second initial voltage terminal I2, and the first pole of the light-emitting element E1, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first pole of the light-emitting element E1 under the control of the second reset control signal Sr2 provided by the second reset control terminal R2.

[0205] The third reset circuit 53 is electrically connected to the third reset control terminal R3, the third initial voltage terminal I3 and the second node N2 respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the second node N2 under the control of the third reset control signal Sr3 provided by the third reset control terminal R3.

[0206] Optionally, the compensation control circuit includes a second transistor, the data writing circuit includes a third transistor, the driving circuit includes a driving transistor, and the fourth energy storage circuit includes a storage capacitor.

[0207] The gate of the second transistor is electrically connected to the compensation control terminal, the first terminal of the second transistor is electrically connected to the control node, and the second terminal of the second transistor is electrically connected to the third node;

[0208] The gate of the third transistor is electrically connected to the second scan terminal, the first terminal of the third transistor is electrically connected to the data line, and the second terminal of the third transistor is electrically connected to the second node;

[0209] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node.

[0210] The first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the DC voltage terminal.

[0211] Optionally, the DC voltage terminal can be a power supply voltage terminal.

[0212] Optionally, the first light-emitting control circuit includes a fourth transistor, the second light-emitting control circuit includes a fifth transistor, the first reset circuit includes a sixth transistor, the second reset circuit includes a seventh transistor, and the third reset circuit includes an eighth transistor.

[0213] The gate of the fourth transistor is electrically connected to the light-emitting control terminal, the first terminal of the fourth transistor is electrically connected to the power supply voltage terminal, and the second terminal of the fourth transistor is electrically connected to the second node.

[0214] The gate of the fifth transistor is electrically connected to the light-emitting control terminal, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the first electrode of the light-emitting element.

[0215] The gate of the sixth transistor is electrically connected to the first reset control terminal, the first terminal of the sixth transistor is electrically connected to the first initial voltage terminal, and the second terminal of the sixth transistor is electrically connected to the control node.

[0216] The gate of the seventh transistor is electrically connected to the second reset control terminal, the first terminal of the seventh transistor is electrically connected to the second initial voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first terminal of the light-emitting element.

[0217] The gate of the eighth transistor is electrically connected to the third reset control terminal, the first terminal of the eighth transistor is electrically connected to the third initial voltage terminal, and the second terminal of the eighth transistor is electrically connected to the second node.

[0218] In at least one embodiment of this disclosure, the second transistor and the sixth transistor are oxide transistors.

[0219] As shown in Figure 9, based on at least one embodiment of the pixel circuit shown in Figure 6, the on / off control circuit includes a first transistor T1; the light-emitting element is an organic light-emitting diode O1.

[0220] The gate of the first transistor T1 is electrically connected to the scanning terminal GT, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the control node NC.

[0221] The compensation control circuit includes a second transistor T2, the data writing circuit includes a third transistor T3, the driving circuit includes a driving transistor T0, and the fourth energy storage circuit includes a storage capacitor Cst.

[0222] The gate of the second transistor T2 is electrically connected to the compensation control terminal SC, the source of the second transistor T2 is electrically connected to the control node NC, and the drain of the second transistor T2 is electrically connected to the third node N3.

[0223] The gate of the third transistor T3 is electrically connected to the scan terminal GT, the source of the third transistor T3 is electrically connected to the data line DL, and the drain of the third transistor T3 is electrically connected to the second node N2.

[0224] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the second node N2, and the drain of the driving transistor T0 is electrically connected to the third node N3.

[0225] The first end of the storage capacitor Cst is electrically connected to the first node N1, and the second end of the storage capacitor Cst is electrically connected to the power supply voltage terminal VDD.

[0226] The first light-emitting control circuit includes a fourth transistor T4, the second light-emitting control circuit includes a fifth transistor T5, the first reset circuit includes a sixth transistor T6, the second reset circuit includes a seventh transistor T7, and the third reset circuit includes an eighth transistor T8.

[0227] The gate of the fourth transistor T4 is electrically connected to the light-emitting control terminal EM, the source of the fourth transistor T4 is electrically connected to the power supply voltage terminal VDD, and the drain of the fourth transistor T4 is electrically connected to the second node N2.

[0228] The gate of the fifth transistor T5 is electrically connected to the light-emitting control terminal EM, the source of the fifth transistor T5 is electrically connected to the third node N3, and the drain of the fifth transistor T5 is electrically connected to the anode of O1.

[0229] The gate of the sixth transistor T6 is electrically connected to the first reset control terminal R1, the source of the sixth transistor T6 is electrically connected to the first initial voltage terminal I1, and the drain of the sixth transistor T6 is electrically connected to the control node NC; the first initial voltage terminal I1 is used to provide the first initial voltage Vinit1.

[0230] The gate of the seventh transistor T7 is electrically connected to the second reset control terminal R2, the source of the seventh transistor T7 is electrically connected to the second initial voltage terminal I2, and the drain of the seventh transistor T7 is electrically connected to the anode of O1; the second initial voltage terminal I2 is used to provide the second initial voltage Vinit2.

[0231] The gate of the eighth transistor T8 is electrically connected to the second reset control terminal R2, the source of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and the drain of the eighth transistor T8 is electrically connected to the second node N2; the third initial voltage terminal I3 is used to provide the third initial voltage Vinit3.

[0232] The first energy storage circuit includes a first capacitor C1;

[0233] The first terminal of the first capacitor C1 is electrically connected to the control node NC, and the second terminal of the first capacitor C1 is electrically connected to the power supply voltage terminal VDD.

[0234] In at least one embodiment of the pixel circuit shown in Figure 9, the first scanning terminal and the second scanning terminal are the same scanning terminal GT, and the third reset control terminal is the second reset control terminal R2.

[0235] In at least one embodiment of the pixel circuit shown in Figure 9, T1 is an LTPS transistor, and T2 and T6 are oxide transistors.

[0236] T1 is a p-type transistor, while T2 and T6 are n-type transistors;

[0237] T0, T3, T4, T5, T7, and T8 are p-type transistors.

[0238] In at least one embodiment shown in Figure 9, T1 is disposed between the gate of T0 and T2. T1 is an LTPS transistor. T1 isolates the gate of T3 from T2 and T6. Both T1 and T3 are controlled by the scanning terminal GT. Since the backplane process of low temperature polysilicon is relatively mature and has good process stability, the characteristics of T1 are relatively stable. Due to the presence of T1 and the fact that T1 is cut off before T2, the influence of the characteristic difference of T2 on the light emission current is eliminated in the circuit.

[0239] In at least one embodiment shown in Figure 9, the voltage value of the power supply voltage signal provided by VDD can be 4.6V, the voltage value of the third initial voltage Vinit3 provided by I3 can be 6V, the voltage value of the first initial voltage Vinit1 provided by I1 can be -3V, and the voltage value of the second initial voltage Vinit2 provided by I2 can be -3V.

[0240] Optionally, Vinit3 can be greater than 0V and less than 8V, Vinit1 can be greater than or equal to -7V and less than 0V, and Vinit2 can be greater than or equal to -7V and less than 0V.

[0241] As shown in Figure 10A, when at least one embodiment of the pixel circuit shown in Figure 9 of this disclosure is in operation, the refresh frame may include a first reset stage S1, a set stage S2, a second reset stage S3, a data writing stage S4, a third reset stage S5, and a refresh light emission stage S6 set sequentially; the set stage S2 includes a first set time period S21, an interval time period S20, and a second set time period S22 set sequentially.

[0242] In the first reset phase S1, EM provides a high voltage signal, GT provides a high voltage signal, SC provides a low voltage signal, R1 provides a low voltage signal, T7 provides a low voltage signal, T7 and T8 are turned on, the second initial voltage Vinit2 provided by I2 resets the anode of O1 through T7, and the third initial voltage Vinit3 provided by I3 resets N2. Since the voltage value of Vinit3 is higher than the voltage value of the power supply voltage signal provided by VDD, T0 will be in the conducting state in the first reset phase S1, and Vinit3 will also reset N3 through T0, improving the hysteresis phenomenon of T0;

[0243] During the set phase S2, EM provides a high voltage signal, R1 provides a high voltage signal, R2 provides a high voltage signal, SC provides a low voltage signal, T6 is turned on, and I1 provides the first initial voltage Vinit1 to NC; T4, T5, T7, T8 and T2 are turned off.

[0244] During the first set time period S21 and the second set time period S22, GT provides a low voltage signal, T1 and T3 are turned on, and the first initial voltage Vinit1 provided by I1 is written to N1 through T6 and T1.

[0245] Before the first set time period S21, influenced by the potential of node N1 and the gate bias voltage, the gate bias voltage is fixed, but the potential of N1 is related to the data voltage of the previous stage. Therefore, the characteristics of T1 are still affected by the previous stage. During the first set time period S21, the potential of N1 is reset to Vinit1, and the gate voltage of T1 is relatively fixed, whether it is high or low. After the first set time period S21, the first turn-on and turn-off can clear the influence of the previous stage data on the characteristics of T1. During the second set time period S22... When T1 is turned on for the second time, the potential of N1 is reset by Vinit1 again. The two consecutive reset actions can better eliminate the influence of the data voltage of the previous stage on the characteristics of T1, thereby improving image retention and low grayscale image quality. In addition, during the second setting time period S22, the potential of N1 is reset to Vinit1. Since T2 is cut off, the potential of N2 still remains Vinit3 of the previous stage. Therefore, the voltage of T0 is Vinit1-Vinit3. The characteristics of T0 are also reset during the second setting time period S22, thereby improving image retention.

[0246] In the second reset phase S3, EM, R1, R2, GT and SC all provide high voltage signals, T6 and T2 are turned on, and T3, T4, T5, T7, T8 and T1 are all turned off. Since T6 and T2 are turned on at the same time, Vinit1 resets the potential of N3 through T6 and T2, improving the hysteresis phenomenon of T0.

[0247] During the data writing phase, S4, EM and SC provide high voltage signals, T2 is turned on, T4, T5, T7 and T8 are all turned off, R1 provides low voltage signals, T6 is turned off, GT provides low voltage signals, T3 and T1 are turned on, and DL provides data voltage Vdata to N2.

[0248] When the data writing phase S4 begins, T0 is turned on, and Vdata charges Cst through T3, T0, T2 and T1, changing the potential of N1 until T0 is turned off. At this time, the potential of N1 is Vdata + Vth, where Vth is the threshold voltage of T0.

[0249] In the third reset phase S5, EM and GT provide high voltage signals, SC and R1 both provide low voltage signals, T3, T4, T5 and T1 are cut off, T6 and T2 are cut off, R2 provides a low voltage signal, T7 and T8 are turned on, Vinit2 resets through T7 as the anode of O1, clearing the residual charge on the anode of O1; Vinit3 resets through T8 as the potential of N2, improving the hysteresis phenomenon of T0;

[0250] During the refresh emission phase S6, GT provides a high voltage signal, R2 provides a high voltage signal, EM provides a low voltage signal, SC provides a low voltage signal, R1 provides a low voltage signal, T3, T7, T8, T1, T6, and T2 are all cut off, T4 and T5 are turned on, and T0 drives O1 to emit light; Id equals K(Vdd-Vdata). 2 Where K is the current coefficient of T0, Vdd is the voltage value of the power supply voltage signal provided by the power supply voltage terminal VDD, and Id is the driving current generated by T0.

[0251] As shown in Figure 10B, in operation, at least one embodiment of the pixel circuit shown in Figure 9 of this disclosure may include a first reset stage S1, a set stage S2, a second reset stage S3, a data writing stage S4, a third reset stage S5, a voltage control stage S0, and a refresh light emission stage S6, which are set sequentially; the set stage S2 includes a first set time period S21, an interval time period S20, and a second set time period S22, which are set sequentially.

[0252] In the first reset phase S1, EM provides a high voltage signal, GT provides a high voltage signal, SC provides a low voltage signal, R1 provides a low voltage signal, T7 provides a low voltage signal, T7 and T8 are turned on, the second initial voltage Vinit2 provided by I2 resets the anode of O1 through T7, and the third initial voltage Vinit3 provided by I3 resets N2. Since the voltage value of Vinit3 is higher than the voltage value of the power supply voltage signal provided by VDD, T0 will be in the conducting state in the first reset phase S1, and Vinit3 will also reset N3 through T0, improving the hysteresis phenomenon of T0;

[0253] During the set phase S2, EM provides a high voltage signal, R1 provides a high voltage signal, R2 provides a high voltage signal, SC provides a low voltage signal, T6 is turned on, and I1 provides the first initial voltage Vinit1 to NC; T4, T5, T7, T8 and T2 are turned off.

[0254] During the first set time period S21 and the second set time period S22, GT provides a low voltage signal, T1 and T3 are turned on, and the first initial voltage Vinit1 provided by I1 is written to N1 through T6 and T1.

[0255] Before the first set time period S21, influenced by the potential of node N1 and the gate bias voltage, the gate bias voltage is fixed, but the potential of N1 is related to the data voltage of the previous stage. Therefore, the characteristics of T1 are still affected by the previous stage. During the first set time period S21, the potential of N1 is reset to Vinit1, and the gate voltage of T1 is relatively fixed, whether it is high or low. After the first set time period S21, the first turn-on and turn-off can clear the influence of the previous stage data on the characteristics of T1. During the second set time period S22... When T1 is turned on for the second time, the potential of N1 is reset by Vinit1 again. The two consecutive reset actions can better eliminate the influence of the data voltage of the previous stage on the characteristics of T1, thereby improving image retention and low grayscale image quality. In addition, during the second setting time period S22, the potential of N1 is reset to Vinit1. Since T2 is cut off, the potential of N2 still remains Vinit3 of the previous stage. Therefore, the voltage of T0 is Vinit1-Vinit3. The characteristics of T0 are also reset during the second setting time period S22, thereby improving image retention.

[0256] In the second reset phase S3, EM, R1, R2, GT and SC all provide high voltage signals, T6 and T2 are turned on, and T3, T4, T5, T7, T8 and T1 are all turned off. Since T6 and T2 are turned on at the same time, Vinit1 resets the potential of N3 through T6 and T2, improving the hysteresis phenomenon of T0.

[0257] During the data writing phase, S4, EM and SC provide high voltage signals, T2 is turned on, T4, T5, T7 and T8 are all turned off, R1 provides low voltage signals, T6 is turned off, GT provides low voltage signals, T3 and T1 are turned on, and DL provides data voltage Vdata to N2.

[0258] When the data writing phase S4 begins, T0 is turned on, and Vdata charges Cst through T3, T0, T2 and T1, changing the potential of N1 until T0 is turned off. At this time, the potential of N1 is Vdata + Vth, where Vth is the threshold voltage of T0.

[0259] In the third reset phase S5, EM and GT provide high voltage signals, SC and R1 both provide low voltage signals, T3, T4, T5 and T1 are cut off, T6 and T2 are cut off, R2 provides a low voltage signal, T7 and T8 are turned on, Vinit2 resets through T7 as the anode of O1, clearing the residual charge on the anode of O1; Vinit3 resets through T8 as the potential of N2, improving the hysteresis phenomenon of T0;

[0260] During the voltage control phase S0, EM provides a high voltage signal, SC provides a low voltage signal, GT provides a low voltage signal, R1 provides a low voltage signal, R2 provides a high voltage signal, T1 is turned on, and N1 and NC are connected so that the potential of N1 is the same as the potential of NC, reducing the leakage current between N1 and NC, which is beneficial to maintaining the potential of the first node N1 during the refresh light emission phase.

[0261] During the refresh emission stage S6, GT provides a high voltage signal, R2 provides a high voltage signal, EM provides a low voltage signal, SC provides a low voltage signal, R1 provides a low voltage signal, T3, T7, T8, T1, T6, and T2 are all cut off, T4 and T5 are turned on, and T0 drives O1 to emit light; Id is equal to K(Vdd-Vdata)2; where K is the current coefficient of T0, Vdd is the voltage value of the power supply voltage signal provided by the power supply voltage terminal VDD, and Id is the driving current generated by T0.

[0262] As shown in Figure 10C, in at least one embodiment of the pixel circuit shown in Figure 9 of this disclosure, when in operation, the refresh frame may include a first reset stage S1, a set stage S2, a second reset stage S3, a data writing stage S4, a voltage control stage S0, a third reset stage S5, and a refresh light emission stage S6 set sequentially; the set stage S2 includes a first set time period S21, an interval time period S20, and a second set time period S22 set sequentially.

[0263] In the first reset phase S1, EM provides a high voltage signal, GT provides a high voltage signal, SC provides a low voltage signal, R1 provides a low voltage signal, T7 provides a low voltage signal, T7 and T8 are turned on, the second initial voltage Vinit2 provided by I2 resets the anode of O1 through T7, and the third initial voltage Vinit3 provided by I3 resets N2. Since the voltage value of Vinit3 is higher than the voltage value of the power supply voltage signal provided by VDD, T0 will be in the conducting state in the first reset phase S1, and Vinit3 will also reset N3 through T0, improving the hysteresis phenomenon of T0;

[0264] During the set phase S2, EM provides a high voltage signal, R1 provides a high voltage signal, R2 provides a high voltage signal, SC provides a low voltage signal, T6 is turned on, and I1 provides the first initial voltage Vinit1 to NC; T4, T5, T7, T8 and T2 are turned off.

[0265] During the first set time period S21 and the second set time period S22, GT provides a low voltage signal, T1 and T3 are turned on, and the first initial voltage Vinit1 provided by I1 is written to N1 through T6 and T1.

[0266] Before the first set time period S21, influenced by the potential of node N1 and the gate bias voltage, the gate bias voltage is fixed, but the potential of N1 is related to the data voltage of the previous stage. Therefore, the characteristics of T1 are still affected by the previous stage. During the first set time period S21, the potential of N1 is reset to Vinit1, and the gate voltage of T1 is relatively fixed, whether it is high or low. After the first set time period S21, the first turn-on and turn-off can clear the influence of the previous stage data on the characteristics of T1. During the second set time period S22... When T1 is turned on for the second time, the potential of N1 is reset by Vinit1 again. The two consecutive reset actions can better eliminate the influence of the data voltage of the previous stage on the characteristics of T1, thereby improving image retention and low grayscale image quality. In addition, during the second setting time period S22, the potential of N1 is reset to Vinit1. Since T2 is cut off, the potential of N2 still remains Vinit3 of the previous stage. Therefore, the voltage of T0 is Vinit1-Vinit3. The characteristics of T0 are also reset during the second setting time period S22, thereby improving image retention.

[0267] In the second reset phase S3, EM, R1, R2, GT and SC all provide high voltage signals, T6 and T2 are turned on, and T3, T4, T5, T7, T8 and T1 are all turned off. Since T6 and T2 are turned on at the same time, Vinit1 resets the potential of N3 through T6 and T2, improving the hysteresis phenomenon of T0.

[0268] During the data writing phase, S4, EM and SC provide high voltage signals, T2 is turned on, T4, T5, T7 and T8 are all turned off, R1 provides low voltage signals, T6 is turned off, GT provides low voltage signals, T3 and T1 are turned on, and DL provides data voltage Vdata to N2.

[0269] When the data writing phase S4 begins, T0 is turned on, and Vdata charges Cst through T3, T0, T2 and T1, changing the potential of N1 until T0 is turned off. At this time, the potential of N1 is Vdata + Vth, where Vth is the threshold voltage of T0.

[0270] During the voltage control phase S0, EM provides a high voltage signal, SC provides a low voltage signal, GT provides a low voltage signal, R1 provides a low voltage signal, R2 provides a high voltage signal, T1 is turned on, and N1 and NC are connected so that the potential of N1 is the same as the potential of NC, reducing the leakage current between N1 and NC, which is beneficial to maintaining the potential of the first node N1 during the refresh light emission phase.

[0271] In the third reset phase S5, EM and GT provide high voltage signals, SC and R1 both provide low voltage signals, T3, T4, T5 and T1 are cut off, T6 and T2 are cut off, R2 provides a low voltage signal, T7 and T8 are turned on, Vinit2 resets through T7 as the anode of O1, clearing the residual charge on the anode of O1; Vinit3 resets through T8 as the potential of N2, improving the hysteresis phenomenon of T0;

[0272] During the refresh emission stage S6, GT provides a high voltage signal, R2 provides a high voltage signal, EM provides a low voltage signal, SC provides a low voltage signal, R1 provides a low voltage signal, T3, T7, T8, T1, T6, and T2 are all cut off, T4 and T5 are turned on, and T0 drives O1 to emit light; Id is equal to K(Vdd-Vdata)2; where K is the current coefficient of T0, Vdd is the voltage value of the power supply voltage signal provided by the power supply voltage terminal VDD, and Id is the driving current generated by T0.

[0273] As shown in FIG10D, when at least one embodiment of the pixel circuit shown in FIG9 of this disclosure is in operation, the holding frame may include a holding control stage S30, a holding setting stage S31 and a holding light emission stage S32 that are set sequentially.

[0274] During the control phase S30, EM provides a high voltage signal, SC provides a low voltage signal, GT provides a low voltage signal, R1 provides a low voltage signal, R2 provides a high voltage signal, T1 is turned on, and N1 and NC are connected so that the potential of N1 is the same as the potential of NC, reducing the leakage current between N1 and NC, which is beneficial to maintain the potential of the first node N1 during the light-emitting phase.

[0275] During the hold-set phase S31, EM and GT provide high voltage signals, SC and R1 both provide low voltage signals, T3, T4, T5 and T1 are cut off, T6 and T2 are cut off, R2 provides a low voltage signal, T7 and T8 are turned on, Vinit2 resets through T7 as the anode of O1 to clear the residual charge on the anode of O1; Vinit3 resets through T8 as the potential of N2 to improve the hysteresis phenomenon of T0;

[0276] During the light-emitting phase S32, GT provides a high voltage signal, R2 provides a high voltage signal, EM provides a low voltage signal, SC provides a low voltage signal, R1 provides a low voltage signal, T3, T7, T8, T1, T6 and T2 are all cut off, T4 and T5 are turned on, and T0 drives O1 to emit light.

[0277] As shown in FIG10E, when at least one embodiment of the pixel circuit shown in FIG9 of this disclosure is in operation, the holding frame may include a holding setting stage S31, a holding control stage S30 and a holding light emission stage S32 that are set sequentially.

[0278] During the hold-set phase S31, EM and GT provide high voltage signals, SC and R1 both provide low voltage signals, T3, T4, T5 and T1 are cut off, T6 and T2 are cut off, R2 provides a low voltage signal, T7 and T8 are turned on, Vinit2 resets through T7 as the anode of O1 to clear the residual charge on the anode of O1; Vinit3 resets through T8 as the potential of N2 to improve the hysteresis phenomenon of T0;

[0279] During the control phase S30, EM provides a high voltage signal, SC provides a low voltage signal, GT provides a low voltage signal, R1 provides a low voltage signal, R2 provides a high voltage signal, T1 is turned on, and N1 and NC are connected so that the potential of N1 is the same as the potential of NC, reducing the leakage current between N1 and NC, which is beneficial to maintain the potential of the first node N1 during the light-emitting phase.

[0280] During the light-emitting phase S32, GT provides a high voltage signal, R2 provides a high voltage signal, EM provides a low voltage signal, SC provides a low voltage signal, R1 provides a low voltage signal, T3, T7, T8, T1, T6 and T2 are all cut off, T4 and T5 are turned on, and T0 drives O1 to emit light.

[0281] As shown in Figure 11, based on at least one embodiment of the pixel circuit shown in Figure 7, the on / off control circuit includes a first transistor T1; the light-emitting element is an organic light-emitting diode O1.

[0282] The gate of the first transistor T1 is electrically connected to the scanning terminal GT, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the control node NC.

[0283] The compensation control circuit includes a second transistor T2, the data writing circuit includes a third transistor T3, the driving circuit includes a driving transistor T0, and the fourth energy storage circuit includes a storage capacitor Cst.

[0284] The gate of the second transistor T2 is electrically connected to the compensation control terminal SC, the source of the second transistor T2 is electrically connected to the control node NC, and the drain of the second transistor T2 is electrically connected to the third node N3.

[0285] The gate of the third transistor T3 is electrically connected to the scan terminal GT, the source of the third transistor T3 is electrically connected to the data line DL, and the drain of the third transistor T3 is electrically connected to the second node N2.

[0286] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the second node N2, and the drain of the driving transistor T0 is electrically connected to the third node N3.

[0287] The first end of the storage capacitor Cst is electrically connected to the first node N1, and the second end of the storage capacitor Cst is electrically connected to the power supply voltage terminal VDD.

[0288] The first light-emitting control circuit includes a fourth transistor T4, the second light-emitting control circuit includes a fifth transistor T5, the first reset circuit includes a sixth transistor T6, the second reset circuit includes a seventh transistor T7, and the third reset circuit includes an eighth transistor T8.

[0289] The gate of the fourth transistor T4 is electrically connected to the light-emitting control terminal EM, the source of the fourth transistor T4 is electrically connected to the power supply voltage terminal VDD, and the drain of the fourth transistor T4 is electrically connected to the second node N2.

[0290] The gate of the fifth transistor T5 is electrically connected to the light-emitting control terminal EM, the source of the fifth transistor T5 is electrically connected to the third node N3, and the drain of the fifth transistor T5 is electrically connected to the anode of O1.

[0291] The gate of the sixth transistor T6 is electrically connected to the first reset control terminal R1, the source of the sixth transistor T6 is electrically connected to the first initial voltage terminal I1, and the drain of the sixth transistor T6 is electrically connected to the control node NC; the first initial voltage terminal I1 is used to provide the first initial voltage Vinit1.

[0292] The gate of the seventh transistor T7 is electrically connected to the second reset control terminal R2, the source of the seventh transistor T7 is electrically connected to the second initial voltage terminal I2, and the drain of the seventh transistor T7 is electrically connected to the anode of O1; the second initial voltage terminal I2 is used to provide the second initial voltage Vinit2.

[0293] The gate of the eighth transistor T8 is electrically connected to the second reset control terminal R2, the source of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and the drain of the eighth transistor T8 is electrically connected to the second node N2; the third initial voltage terminal I3 is used to provide the third initial voltage Vinit3.

[0294] The second energy storage circuit includes a second capacitor C2, and the third energy storage circuit includes a third capacitor C3;

[0295] The first terminal of the second capacitor C2 is electrically connected to the control node NC, and the second terminal of the second capacitor C2 is electrically connected to the compensation control terminal SC.

[0296] The first end of the third capacitor C3 is electrically connected to the scanning end GT, and the second end of the third capacitor C3 is electrically connected to the control node NC.

[0297] In at least one embodiment of the pixel circuit shown in Figure 11, the first scanning end and the second scanning end are the same scanning end GT.

[0298] In at least one embodiment of the pixel circuit shown in Figure 11, T1 is an LTPS transistor, and T2 and T6 are oxide transistors.

[0299] T1 is a p-type transistor, while T2 and T6 are n-type transistors;

[0300] T0, T3, T4, T5, T7, and T8 are p-type transistors.

[0301] The differences between at least one embodiment of the pixel circuit shown in FIG12 of this disclosure and at least one embodiment of the pixel circuit shown in FIG11 of this disclosure are as follows:

[0302] It also includes a first energy storage circuit, which includes a first capacitor C1;

[0303] The first terminal of the first capacitor C1 is electrically connected to the control node NC, and the second terminal of the first capacitor C1 is electrically connected to the power supply voltage terminal VDD.

[0304] The differences between at least one embodiment of the pixel circuit shown in FIG13 of this disclosure and at least one embodiment of the pixel circuit shown in FIG9 of this disclosure are as follows:

[0305] The second terminal of C1 is electrically connected to the light-emitting control terminal EM, so that during the light-emitting stage, the potential of NC is pulled down by the light-emitting control signal provided by EM, thereby reducing leakage current and improving the display effect.

[0306] The differences between at least one embodiment of the pixel circuit shown in FIG. 14 of this disclosure and at least one embodiment of the pixel circuit shown in FIG. 9 of this disclosure are as follows:

[0307] The second terminal of C1 is electrically connected to the second initial voltage terminal I2.

[0308] As shown in Figure 15, in at least one embodiment of the pixel circuit shown in Figure 14 of this disclosure, when in operation, the refresh frame FS includes a first reset stage S1, a set stage S2, a second reset stage S3, a data writing stage S4, a voltage control stage S0, a third reset stage S5, and a refresh light emission stage S6, which are set sequentially; the set stage S2 includes a first set time period S21, an interval time period S20, and a second set time period S22, which are set sequentially.

[0309] In the first reset phase S1, EM provides a high voltage signal, GT provides a high voltage signal, SC provides a low voltage signal, R1 provides a low voltage signal, T7 provides a low voltage signal, T7 and T8 are turned on, the second initial voltage Vinit2 provided by I2 resets the anode of O1 through T7, and the third initial voltage Vinit3 provided by I3 resets N2. Since the voltage value of Vinit3 is higher than the voltage value of the power supply voltage signal provided by VDD, T0 will be in the conducting state in the first reset phase S1, and Vinit3 will also reset N3 through T0, improving the hysteresis phenomenon of T0;

[0310] During the set phase S2, EM provides a high voltage signal, R1 provides a high voltage signal, R2 provides a high voltage signal, SC provides a low voltage signal, T6 is turned on, and I1 provides the first initial voltage Vinit1 to NC; T4, T5, T7, T8 and T2 are turned off.

[0311] During the first set time period S21 and the second set time period S22, GT provides a low voltage signal, T1 and T3 are turned on, and the first initial voltage Vinit1 provided by I1 is written to N1 through T6 and T1.

[0312] Before the first set time period S21, influenced by the potential of node N1 and the gate bias voltage, the gate bias voltage is fixed, but the potential of N1 is related to the data voltage of the previous stage. Therefore, the characteristics of T1 are still affected by the previous stage. During the first set time period S21, the potential of N1 is reset to Vinit1, and the gate voltage of T1 is relatively fixed, whether it is high or low. After the first set time period S21, the first turn-on and turn-off can clear the influence of the previous stage data on the characteristics of T1. During the second set time period S22... When T1 is turned on for the second time, the potential of N1 is reset by Vinit1 again. The two consecutive reset actions can better eliminate the influence of the data voltage of the previous stage on the characteristics of T1, thereby improving image retention and low grayscale image quality. In addition, during the second setting time period S22, the potential of N1 is reset to Vinit1. Since T2 is cut off, the potential of N2 still remains Vinit3 of the previous stage. Therefore, the voltage of T0 is Vinit1-Vinit3. The characteristics of T0 are also reset during the second setting time period S22, thereby improving image retention.

[0313] In the second reset phase S3, EM, R1, R2, GT and SC all provide high voltage signals, T6 and T2 are turned on, and T3, T4, T5, T7, T8 and T1 are all turned off. Since T6 and T2 are turned on at the same time, Vinit1 resets the potential of N3 through T6 and T2, improving the hysteresis phenomenon of T0.

[0314] During the data writing phase, S4, EM and SC provide high voltage signals, T2 is turned on, T4, T5, T7 and T8 are all turned off, R1 provides low voltage signals, T6 is turned off, GT provides low voltage signals, T3 and T1 are turned on, and DL provides data voltage Vdata to N2.

[0315] When the data writing phase S4 begins, T0 is turned on, and Vdata charges Cst through T3, T0, T2 and T1, changing the potential of N1 until T0 is turned off. At this time, the potential of N1 is Vdata + Vth, where Vth is the threshold voltage of T0.

[0316] During the voltage control phase S0, EM provides a high voltage signal, SC provides a low voltage signal, GT provides a low voltage signal, R1 provides a low voltage signal, R2 provides a high voltage signal, T1 is turned on, and N1 and NC are connected so that the potential of N1 is the same as the potential of NC, reducing the leakage current between N1 and NC, which is beneficial to maintaining the potential of the first node N1 during the refresh light emission phase.

[0317] In the third reset phase S5, EM and GT provide high voltage signals, SC and R1 both provide low voltage signals, T3, T4, T5 and T1 are cut off, T6 and T2 are cut off, R2 provides a low voltage signal, T7 and T8 are turned on, Vinit2 resets through T7 as the anode of O1, clearing the residual charge on the anode of O1; Vinit3 resets through T8 as the potential of N2, improving the hysteresis phenomenon of T0;

[0318] During the refresh emission stage S6, GT provides a high voltage signal, R2 provides a high voltage signal, EM provides a low voltage signal, SC provides a low voltage signal, and R1 provides a low voltage signal. T3, T7, T8, T1, T6, and T2 are all cut off, while T4 and T5 are turned on. T0 drives O1 to emit light. Id is equal to K(Vdd-Vdata)2, where K is the current coefficient of T0, Vdd is the voltage value of the power supply voltage signal provided by the power supply voltage terminal VDD, and Id is the driving current generated by T0.

[0319] The hold frame (FB) includes a hold control phase (S30), a set phase (S31), and a hold emission phase (S32).

[0320] During the control phase S30, EM provides a high voltage signal, SC provides a low voltage signal, GT provides a low voltage signal, R1 provides a low voltage signal, R2 provides a high voltage signal, T1 is turned on, and N1 and NC are connected so that the potential of N1 is the same as the potential of NC, reducing the leakage current between N1 and NC, which is beneficial to maintain the potential of the first node N1 during the light-emitting phase.

[0321] During the hold-set phase S31, EM and GT provide high voltage signals, SC and R1 both provide low voltage signals, T3, T4, T5 and T1 are cut off, T6 and T2 are cut off, R2 provides a low voltage signal, T7 and T8 are turned on, Vinit2 resets through T7 as the anode of O1 to clear the residual charge on the anode of O1; Vinit3 resets through T8 as the potential of N2 to improve the hysteresis phenomenon of T0;

[0322] During the light-emitting phase S32, GT provides a high voltage signal, R2 provides a high voltage signal, EM provides a low voltage signal, SC provides a low voltage signal, R1 provides a low voltage signal, T3, T7, T8, T1, T6 and T2 are all cut off, T4 and T5 are turned on, and T0 drives O1 to emit light.

[0323] As shown in Figure 15, for most of the time included in the refresh frame FS, the voltage value of the second initial voltage signal provided by I2 is greater than the voltage value of the second initial voltage signal provided by I2 in the hold frame FB.

[0324] For example, during the hold frame (FB), the voltage value of the second initial voltage signal can be -4V, and during most of the refresh frame, the voltage value of the second initial voltage signal can be -3.5V.

[0325] In at least one embodiment shown in Figures 14 and 15, the first voltage terminal is the second initial voltage terminal, but is not limited thereto. In actual operation, the first voltage terminal can be the first initial voltage terminal, the second initial voltage terminal, the third initial voltage terminal, or other signal terminals on the display panel, such as power supply voltage terminals. The voltage signal provided by the signal terminal can be adjusted in stages to ensure that the voltage signal provided by the signal terminal during at least a portion of the holding frame is different from the voltage signal provided by the signal terminal during at least a portion of the refresh frame. This allows the potential of the control node to be reduced during the holding frame, thereby reducing the difference between the potential of the first node and the potential of the control node, reducing leakage current, facilitating the maintenance of the potential of the first node, and improving flickering.

[0326] The pixel driving method described in this embodiment is applied to the aforementioned pixel circuit. The refresh frame includes a sequentially set position phase and a refresh emission phase. The set position phase includes a sequentially set first set position time period, an interval time period, and a second set position time period. The pixel driving method includes:

[0327] During the first set time period and the second set time period, the on / off control circuit, under the control of the first scan signal, controls the connection between the first node and the control node;

[0328] During the specified time interval, the on / off control circuit, under the control of the first scan signal, controls the disconnection between the first node and the control node;

[0329] During the refresh light-emitting stage, the driving circuit generates a driving current to drive the light-emitting element under the control of the potential of the first node.

[0330] In at least one embodiment of this disclosure, the pixel circuit further includes a data writing circuit; the refresh frame further includes a data writing phase disposed between the set phase and the refresh emission phase; the pixel driving method further includes:

[0331] During the data writing phase, the data writing circuit, under the control of the second scan signal, writes the data voltage provided by the data line into the second node. The compensation control circuit, under the control of the compensation control signal, controls the connection between the control node and the third node. The on / off control circuit, under the control of the first scan signal, controls the connection between the first node and the control node.

[0332] In at least one embodiment of this disclosure, the refresh frame further includes a voltage control phase disposed between the data writing phase and the refresh emission phase; the pixel driving method further includes:

[0333] During the voltage control phase, the on / off control circuit, under the control of the first scan signal, controls the connection between the first node and the control node so that the potential of the first node is the same as that of the control node, thereby reducing the leakage current between the first node and the control node and facilitating the maintenance of the potential of the first node N1 during the refresh light emission phase.

[0334] In at least one embodiment of this disclosure, the refresh frame further includes a third reset phase disposed between the data writing phase and the refresh emission phase; the pixel driving method further includes:

[0335] In the third reset stage, the second reset circuit, under the control of the second reset control signal, writes the second initial voltage into the first electrode of the light-emitting element to clear the residual charge in the first electrode of the light-emitting element; the third reset circuit, under the control of the third reset control signal, writes the third initial voltage into the second node to improve the hysteresis phenomenon of the driving transistor in the driving circuit.

[0336] The voltage control phase is set before the third reset phase, or the voltage control phase is set after the third reset phase.

[0337] In at least one embodiment of this disclosure, the holding frame includes a holding control phase and a holding illumination phase that are set sequentially; the pixel driving method further includes:

[0338] During the holding control phase, the on / off control circuit, under the control of the first scan signal, controls the connection between the first node and the control node so that the potential of the first node is the same as the potential of the control node, thereby reducing the leakage current between the first node and the control node and facilitating the maintenance of the potential of the first node N1 during the holding light-emitting phase.

[0339] During the light-emitting phase, the driving circuit generates a driving current to drive the light-emitting element under the control of the potential of the first node.

[0340] In at least one embodiment of this disclosure, the holding frame further includes a holding reset phase; the pixel driving method further includes:

[0341] During the reset holding phase, the second reset circuit, under the control of the second reset control signal, writes the second initial voltage into the first electrode of the light-emitting element to clear the residual charge in the first electrode of the light-emitting element; the third reset circuit, under the control of the third reset control signal, writes the third initial voltage into the second node to improve the hysteresis phenomenon of the driving transistor in the driving circuit.

[0342] The holding control phase is set before the holding reset phase, or the holding control phase is set after the holding reset phase.

[0343] The display device described in this disclosure includes the pixel circuit described above.

[0344] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A pixel circuit, comprising a light emitting element, a driving circuit, a compensation control circuit and a pass-through control circuit; a control terminal of the driving circuit is electrically connected with a first node, a first terminal of the driving circuit is electrically connected with a second node, a second terminal of the driving circuit is electrically connected with a third node, and the driving circuit is configured to generate a driving current for driving the light emitting element under the control of a potential of the first node; the compensation control circuit is electrically connected with a compensation control terminal, a control node and the third node respectively, and is configured to control the communication or disconnection between the control node and the third node under the control of a compensation control signal provided by the compensation control terminal; the pass-through control circuit is electrically connected with a first scan terminal, the first node and the control node respectively, and is configured to control the communication or disconnection between the first node and the control node under the control of a first scan signal provided by the first scan terminal.

2. The pixel circuit of claim 1, wherein, A refresh frame comprises a data writing stage, a voltage control stage and a refresh light emitting stage arranged in sequence; the pass-through control circuit is configured to control the communication between the first node and the control node under the control of the first scan signal in the voltage control stage.

3. The pixel circuit of claim 1, wherein, A holding frame comprises a holding control stage and a holding light emitting stage arranged in sequence; the pass-through control circuit is configured to control the communication between the first node and the control node under the control of the first scan signal in the holding control stage.

4. The pixel circuit of claim 1, wherein, the pass-through control circuit comprises a first transistor; a gate of the first transistor is electrically connected with the first scan terminal, a first pole of the first transistor is electrically connected with the first node, and a second pole of the first transistor is electrically connected with the control node; the first transistor is a low temperature poly-silicon transistor.

5. The pixel circuit of claim 4, wherein, a channel width of the first transistor is greater than 0 and less than or equal to 2.5 μm; and / or, a channel length of the first transistor is greater than 0 and less than or equal to 3 μm.

6. The pixel circuit of claim 1, wherein, further comprising a first energy storage circuit; a first terminal of the first energy storage circuit is electrically connected with the control node, a second terminal of the first energy storage circuit is electrically connected with a first voltage terminal, and the first energy storage circuit is configured to store electric energy; the first voltage terminal is configured to provide a first voltage signal; the first voltage signal is a direct current voltage signal; or, in the refresh frame, a voltage value of the first voltage signal in the refresh light emitting stage is not equal to a voltage value of the first voltage signal in a non-light emitting stage; and / or, in at least part of time of the holding frame, a voltage value of the first voltage signal is not equal to a voltage value of the first voltage signal in at least part of time of the refresh frame; the non-light emitting stage is a time period of the refresh frame except the refresh light emitting stage.

7. The pixel circuit of claim 6, wherein, in the refresh frame, the voltage value of the first voltage signal in the refresh light emitting stage is less than the voltage value of the first voltage signal in the non-light emitting stage; and / or, in at least part of time of the holding frame, the voltage value of the first voltage signal is less than the voltage value of the first voltage signal in at least part of time of the refresh frame.

8. The pixel circuit of claim 1 or 6, wherein, further comprising a second energy storage circuit and a third energy storage circuit. A first end of the second energy storage circuit is electrically connected with the control node, and a second end of the second energy storage circuit is electrically connected with the compensation control end, and the second energy storage circuit is used for storing electric energy. A first end of the third energy storage circuit is electrically connected with the first scan end, and a second end of the third energy storage circuit is electrically connected with the control node, and the third energy storage circuit is used for storing electric energy.

9. The pixel circuit of claim 8, wherein, The pixel circuit comprises a first energy storage circuit; the first energy storage circuit comprises a first capacitor; A first end of the first capacitor is electrically connected with the control node, and a second end of the first capacitor is electrically connected with a first voltage end; The second energy storage circuit comprises a second capacitor, and the third energy storage circuit comprises a third capacitor; A first end of the second capacitor is electrically connected with the control node, and a second end of the second capacitor is electrically connected with the compensation control end; A first end of the third capacitor is electrically connected with the first scan end, and a second end of the third capacitor is electrically connected with the control node; The capacitance value of the first capacitor is greater than the capacitance value of the third capacitor, and the capacitance value of the second capacitor is greater than the capacitance value of the third capacitor.

10. The pixel circuit of any one of claims 1 to 7, wherein, Further comprising a data writing circuit and a fourth energy storage circuit; The data writing circuit is electrically connected with a second scan end, a data line and the second node respectively, and is used for controlling the data line to be in communication or disconnected with the second node under the control of a second scan signal provided by the second scan end; The fourth energy storage circuit is electrically connected with the first node, and is used for maintaining the electric potential of the first node.

11. The pixel circuit of claim 10, wherein, Further comprising a first light emitting control circuit, a second light emitting control circuit, a first reset circuit, a second reset circuit and a third reset circuit; The first light emitting control circuit is electrically connected with a light emitting control end, a power voltage end and the second node respectively, and is used for controlling the power voltage end to be in communication or disconnected with the second node under the control of a light emitting control signal provided by the light emitting control end; The second light emitting control circuit is electrically connected with a light emitting control end, a third node and a first pole of the light emitting element respectively, and is used for controlling the third node to be in communication or disconnected with the first pole of the light emitting element under the control of a light emitting control signal provided by the light emitting control end; a second pole of the light emitting element is electrically connected with a second voltage end; The first reset circuit is electrically connected with a first reset control end, a first initial voltage end and the control node respectively, and is used for writing a first initial voltage provided by the first initial voltage end into the control node under the control of a first reset control signal provided by the first reset control end; The second reset circuit is electrically connected with a second reset control end, a second initial voltage end and the first pole of the light emitting element respectively, and is used for writing a second initial voltage provided by the second initial voltage end into the first pole of the light emitting element under the control of a second reset control signal provided by the second reset control end; ​ The third reset circuit is electrically connected with the third reset control end, the third initial voltage end and the second node respectively, and is used for writing the third initial voltage provided by the third initial voltage end into the second node under the control of a third reset control signal provided by the third reset control end.

12. The pixel circuit of claim 11, wherein, The compensation control circuit comprises a second transistor, the data writing circuit comprises a third transistor, the driving circuit comprises a driving transistor, and the fourth energy storage circuit comprises a storage capacitor; The gate of the second transistor is electrically connected with the compensation control end, the first pole of the second transistor is electrically connected with the control node, and the second pole of the second transistor is electrically connected with the third node; The gate of the third transistor is electrically connected with the second scan end, the first pole of the third transistor is electrically connected with the data line, and the second pole of the third transistor is electrically connected with the second node; The gate of the driving transistor is electrically connected with the first node, the first pole of the driving transistor is electrically connected with the second node, and the second pole of the driving transistor is electrically connected with the third node; The first end of the storage capacitor is electrically connected with the first node, and the second end of the storage capacitor is electrically connected with a direct current voltage end.

13. The pixel circuit of claim 12, wherein, The second transistor is an oxide transistor.

14. A pixel driving method applied to the pixel circuit in any one of claims 1 to 13, a refresh frame comprising a set phase and a refresh light-emitting phase arranged in sequence; the set phase comprises a first set time period, an interval time period and a second set time period arranged in sequence; the pixel driving method comprises: In the first set time period and the second set time period, the on-off control circuit controls the communication between the first node and the control node under the control of the first scan signal; In the interval time period, the on-off control circuit controls the disconnection between the first node and the control node under the control of the first scan signal; In the refresh light-emitting phase, the driving circuit generates a driving current for driving the light-emitting element under the control of the potential of the first node.

15. The pixel driving method of claim 14, wherein, The pixel circuit further comprises a data writing circuit; the refresh frame further comprises a data writing phase arranged between the set phase and the refresh light-emitting phase; The pixel driving method further comprises: In the data writing phase, the data writing circuit writes a data voltage provided by the data line into the second node under the control of the second scan signal, the compensation control circuit controls the communication between the control node and the third node under the control of the compensation control signal, and the on-off control circuit controls the communication between the first node and the control node under the control of the first scan signal.

16. The pixel driving method of claim 15, wherein, The refresh frame further comprises a voltage control phase arranged between the data writing phase and the refresh light-emitting phase; The pixel driving method further comprises: In the voltage control phase, the on-off control circuit controls the communication between the first node and the control node under the control of the first scan signal.

17. The pixel driving method of claim 16, wherein, The refresh frame further comprises a third reset phase arranged between the data writing phase and the refresh light-emitting phase; and the pixel driving method further comprises: In the third reset stage, the second reset circuit writes the second initial voltage to the first electrode of the light emitting element under the control of a second reset control signal, and the third reset circuit writes the third initial voltage to the second node under the control of a third reset control signal. The voltage control stage is arranged before the third reset stage, or the voltage control stage is arranged after the third reset stage.

18. The pixel driving method according to any one of claims 14 to 17, wherein, The holding frame comprises a holding control stage and a holding light emitting stage arranged in sequence; the pixel driving method further comprises: In the holding control stage, the on-off control circuit controls the communication between the first node and the control node under the control of a first scanning signal; In the holding light emitting stage, the driving circuit generates a driving current for driving the light emitting element under the control of the potential of the first node.

19. The pixel driving method of claim 18, wherein, The holding frame further comprises a holding reset stage; the pixel driving method further comprises: In the holding reset stage, the second reset circuit writes the second initial voltage to the first electrode of the light emitting element under the control of a second reset control signal, and the third reset circuit writes the third initial voltage to the second node under the control of a third reset control signal. The holding control stage is arranged before the holding reset stage, or the holding control stage is arranged after the holding reset stage.

20. A display device comprising the pixel circuit according to any one of claims 1 to 14.

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