Leakage suppression method and apparatus

Abstract

A leakage suppression method and apparatus, which can be applied to the technical field of nonvolatile memories. The leakage suppression method comprises: inputting into a target neural network data to be stored, and outputting a word-line offset address, wherein the word-line offset address is an address that corresponds to a data state value in the data to be stored and best suppresses leakage between adjacent word lines in a flash memory (S210); determining a word-line base address from among pre-stored word-line addresses in the flash memory (S220); on the basis of the word-line base address and the word-line offset address, determining target word lines from among word lines in the flash memory (S230); and using the target word lines to write the data state value into a memory cell of the flash memory, in order to suppress the leakage (S240).

Description

A method and apparatus for suppressing leakage current Technical Field

[0001] This disclosure relates to the field of non-volatile memory technology, and more specifically, to a leakage current suppression method and apparatus. Background Technology

[0002] Solid-state drives (SSDs) are peripheral devices that assist hosts in managing large-scale data. As the data storage medium for SSDs, 3D NAND flash memory encounters reliability issues such as decreased endurance, inter-cell interference, and data retention errors, leading to increased read errors. Among the factors contributing to increased data errors, lateral leakage caused by charge migration is a significant one.

[0003] In related technologies, lateral leakage current (LCM) poses a significant challenge to memory systems. Lateral leakage current refers to the phenomenon of charge drifting laterally within a memory cell array. Due to various factors such as temperature fluctuations, electrical stress, and material defects, lateral charge movement occurs within the memory cell array over time. When charge moves laterally within the array, it interferes with memory cells connected to adjacent word lines, causing unexpected changes to the data stored in the affected cells. In other words, lateral leakage current causes changes in the threshold voltage of memory cells in flash memory, leading to an increase in data read errors.

[0004] Summary of the Invention

[0005] In view of this, the present disclosure provides a leakage current suppression method and apparatus.

[0006] One aspect of this disclosure provides a leakage current suppression method, comprising: inputting data to be stored into a target neural network and outputting a word line offset address, wherein the word line offset address is the address corresponding to the data state value in the data to be stored that best suppresses leakage current between adjacent word lines in a flash memory; determining a word line base address from pre-stored word line addresses in the flash memory; determining a target word line from the word lines of the flash memory based on the word line base address and the word line offset address; and suppressing leakage current by writing the data state value into a storage cell of the flash memory using the target word line.

[0007] According to embodiments of this disclosure, there are I data state values, where I is an integer greater than 2; inputting the data to be stored into a target neural network and outputting word line offset addresses includes: inputting the I data state values ​​into the target neural network and outputting sorting information, wherein the sorting information includes I sorting positions of the I data state values; and using the I sorting positions as word line offset addresses for the I data state values ​​respectively; determining word line base addresses from pre-stored word line addresses in the flash memory includes: determining I adjacent word line base addresses from the pre-stored word line addresses in the flash memory; determining target word lines from word lines in the flash memory based on the word line base addresses and word line offset addresses includes: generating target word line addresses for the I data state values ​​based on the I word line base addresses and I word line offset addresses; and determining I target word lines from word lines in the flash memory based on the target word line addresses for the I data state values.

[0008] According to an embodiment of this disclosure, inputting I data state values ​​into a target neural network and outputting sorting information includes: inputting I data state values ​​into the target neural network and outputting sorting information and a probability corresponding to the sorting information, wherein the probability is the probability that the sorting position is the optimal position of the data state value. When all I data state values ​​are written to the storage unit in the optimal position, leakage current can be suppressed the most.

[0009] According to an embodiment of this disclosure, there are I data status values ​​and I target word lines, where I is an integer greater than 2; when I data status values ​​are written to the storage unit using I target word lines respectively, the voltage difference between adjacent word lines in the I target word lines is...

[0010] According to an embodiment of this disclosure, there are I data status values ​​and I target word lines, where I is an integer greater than 1; leakage current includes leakage current between adjacent word lines in the I target word lines.

[0011] According to embodiments of this disclosure, the target neural network is trained using the following semi-supervised learning method: acquiring sample data and corresponding label data, wherein the sample data includes M sample data state values, and the label data includes K different sample ranking information corresponding to the M sample data state values, and K sets of scores corresponding to the K sample ranking information, the scores being determined based on the suppression of leakage current by the sample ranking information, where K is a positive integer greater than 1; inputting the M sample data state values ​​into the initial neural network, and outputting K predicted ranking information and K sets of sample probabilities corresponding to the M sample data state values, wherein the K predicted ranking information... The order information is different for each of the K predicted ranking information. The kth predicted ranking information in the K predicted ranking information includes the M predicted ranking positions of the M sample data state values. The kth sample probability in the K groups of sample probabilities is the probability that the predicted ranking position in the kth predicted ranking information is the optimal position of the sample data state value. When all M sample data state values ​​are written to the storage unit with the optimal position of the sample, leakage is best suppressed. M is a positive integer greater than 1. Based on the K sample ranking information, K predicted ranking information, K groups of scores and K groups of sample probabilities, loss information is obtained. Based on the loss information, the network parameters of the initial neural network are adjusted to obtain the target neural network.

[0012] According to embodiments of this disclosure, the score is determined based on a predetermined coefficient, an influence factor, and the data status of the memory cells connected to the N word lines respectively. The influence factor is the influence factor of leakage current caused by the memory cells connected to the N word lines. The predetermined coefficient includes a predetermined comprehensive coefficient and an influence coefficient of leakage current caused by adjacent word lines. The N word lines are adjacent word lines, and N is a positive integer greater than 1.

[0013] According to embodiments of this disclosure, the influencing factors include: an influencing factor on leakage current caused by a memory cell connected to the first word line to a memory cell connected to the second word line, and an influencing factor on leakage current caused by a memory cell connected to the third word line to a memory cell connected to the second word line; wherein, the second word line is a word line adjacent to both the first word line and the third word line; the data state of the memory cells connected to the N word lines respectively includes: the data state of the memory cell connected to the first word line, the data state of the memory cell connected to the second word line, and the data state of the memory cell connected to the third word line.

[0014] According to embodiments of this disclosure, the target neural network is a long short-term memory network.

[0015] Another aspect of this disclosure provides a leakage current suppression device, comprising: a first input module configured to input data to be stored into a target neural network and output a word line offset address, wherein the word line offset address is the address that best suppresses leakage current between adjacent word lines in a flash memory, corresponding to a data state value in the data to be stored; a first determining module configured to determine a word line base address from pre-stored word line addresses in the flash memory; a second determining module configured to determine a target word line from the word lines of the flash memory based on the word line base address and the word line offset address; and a writing module configured to suppress the leakage current by writing the data state value into a storage cell of the flash memory using the target word line.

[0016] According to embodiments of this disclosure, by determining the word line offset address based on the data to be stored, and then determining the target word line from the flash memory based on the word line offset address and the word line base address, the data state value in the data to be stored is written into the storage cell of the flash memory using the target word line. This achieves the adjustment of the threshold voltage distribution of adjacent word lines in the flash memory, thereby suppressing lateral leakage current in the flash memory.

[0017] Furthermore, by using a target neural network to predict the word line offset address corresponding to the data state value in the data to be stored, it is not necessary to exhaustively enumerate all possible lateral leakage currents for all storage locations according to the evaluation rule before selecting the optimal storage location. This significantly shortens the time required to determine the placement location for different data state values ​​and reduces the consumption of computing resources. This feature is more advantageous when there are more word lines. Attached Figure Description

[0018] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0019] Figure 1 schematically illustrates an exemplary system architecture to which the leakage current suppression methods and apparatus of this disclosure can be applied.

[0020] Figure 2 schematically illustrates a flowchart of a leakage current suppression method according to an embodiment of the present disclosure.

[0021] Figure 3 schematically illustrates a lateral leakage current between memory cells connected to adjacent word lines according to an embodiment of the present disclosure.

[0022] Figure 4 schematically illustrates a sorting diagram of data status values ​​according to an embodiment of the present disclosure.

[0023] Figure 5 schematically illustrates the architecture of a neural network according to a first embodiment of the present disclosure.

[0024] Figure 6 schematically illustrates a diagram of a trained neural network according to an embodiment of the present disclosure.

[0025] Figure 7 schematically illustrates a heat map of a three-dimensional combinatorial fraction matrix according to an embodiment of the present disclosure.

[0026] Figure 8 schematically illustrates a neural network architecture according to a second embodiment of the present disclosure.

[0027] Figure 9 schematically illustrates a fraction calculation process according to an embodiment of the present disclosure.

[0028] Figure 10 schematically illustrates a heatmap of the score matrix of sample data according to an embodiment of the present disclosure.

[0029] Figure 11 schematically illustrates a block diagram of a leakage current suppression device according to an embodiment of the present disclosure.

[0030] Figure 12 schematically illustrates a block diagram of an electronic device suitable for implementing a leakage current suppression method according to an embodiment of the present disclosure. Detailed Implementation

[0031] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0033] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0034] When using expressions such as "at least one of A, B, and C", they should generally be interpreted in accordance with the meaning that is commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B, and C, etc.).

[0035] For 3D NAND flash memory built using four-bit cell (QLC) architecture, the greater number of voltage levels compared to cells with fewer threshold states makes QLC more susceptible to lateral leakage current. Therefore, 3D NAND flash memory built using QLC is more vulnerable to lateral leakage current, leading to a higher read error rate.

[0036] A four-bit memory cell has 16 threshold voltage distribution states, namely V th State. Based on the similarities in the principles, programming, and data writing processes of four-bit and three-bit (TLC) memory cell data read / write operations, it can be known that the V of a four-bit memory cell... th The higher the state, the more data is read; therefore, even small perturbations caused by charge migration can affect the data read from a four-bit memory cell. And in the four-bit memory cell, V... th In low-state conditions, charge migration interference can also affect the data read from the four-bit memory cell.

[0037] Based on the characteristics of flash memory arrays, the inventors discovered that the charge migration of a memory cell is closely related to the threshold voltage state of its adjacent cells. These adjacent cells can be memory cells in the array that are connected to the same word lines and adjacent bit lines.

[0038] For example, the data pattern stored in NAND flash memory affects the lateral leakage current in NAND flash memory. When the threshold voltage state of a memory cell is in the erase state, and the cells above and below that memory cell store data, lateral leakage current may occur between that memory cell and its cells above and below.

[0039] Based on this, the inventors discovered that lateral leakage can also affect adjacent memory cells from different directions, and the magnitude of the effect is positively correlated with the difference in threshold voltage between adjacent memory cells.

[0040] Furthermore, the inventors discovered that lateral leakage can be mitigated by employing data mapping or arrangement techniques, thereby reducing data read errors.

[0041] In some embodiments, mitigating lateral leakage can be achieved by adjusting the distribution of threshold voltages within physical pages, an operation that typically requires a large number of identification bits, resulting in excessive storage resource consumption.

[0042] In view of this, embodiments of this disclosure utilize neural networks to optimize data arrangement and mitigate lateral leakage effects in 3D NAND flash memory, based on the relationship between data patterns and charge transfer principles. For example, the neural network may include an LSTM (Long Short-Term Memory) network. LSTM networks can more comprehensively learn the relationship between lateral leakage effects and data arrangement patterns, thereby helping to determine the optimal arrangement.

[0043] Specifically, embodiments of this disclosure provide a leakage current suppression method, comprising: inputting data to be stored into a target neural network and outputting a word line offset address, wherein the word line offset address is the address corresponding to the data state value in the data to be stored that best suppresses leakage current between adjacent word lines in the flash memory; determining a word line base address from pre-stored word line addresses in the flash memory; determining a target word line from the word lines of the flash memory based on the word line base address and the word line offset address; and suppressing leakage current by writing the data state value into the storage cell of the flash memory using the target word line.

[0044] Figure 1 schematically illustrates an exemplary system architecture 100 to which leakage current suppression methods can be applied according to embodiments of the present disclosure. It should be noted that Figure 1 is merely an example of a system architecture to which embodiments of the present disclosure can be applied, to help those skilled in the art understand the technical content of the present disclosure, but does not imply that embodiments of the present disclosure cannot be used in other devices, systems, environments, or scenarios.

[0045] As shown in Figure 1, the system architecture 100 according to this embodiment may include a controller 101 and a memory 102. The controller 101 may be implemented based on a terminal device, a server, or an FPGA (Field Programmable Gate Array). The memory 102 may be a flash memory or similar memory. Specifically, it may be a flash memory built based on QLC. A network is used as a medium to provide a communication link between the controller 101 and the memory 102. The network may include various connection types, such as wired and / or wireless communication links, etc.

[0046] Users can use controller 101 to interact with memory 102 via a network to control memory 102. In some embodiments, controller 101 can automatically perform operations on memory 102 according to predetermined routines to control memory 102.

[0047] It should be noted that the leakage current suppression method provided in this embodiment can generally be executed by the controller 101. Correspondingly, the leakage current suppression device provided in this embodiment can generally be located in the controller 101. The leakage current suppression method provided in this embodiment can also be executed by a server or server cluster that is different from the controller 101 and capable of communicating with the controller 101 and / or the memory 102. Correspondingly, the leakage current suppression device provided in this embodiment can also be located in a server or server cluster that is different from the controller 101 and capable of communicating with the controller 101 and / or the memory 102. Alternatively, the leakage current suppression method provided in this embodiment can also be executed by a terminal device that is different from the controller 101. Correspondingly, the leakage current suppression device provided in this embodiment can also be located in a terminal device that is different from the controller 101.

[0048] For example, the data to be stored may originally be stored in the controller 101, or stored on an external storage device and imported into the controller 101. Then, the controller 101 may execute the leakage current suppression method provided in the embodiments of this disclosure locally, or send the data to be stored to a terminal device, server, or server cluster, and the terminal device, server, or server cluster receiving the data to be stored may execute the leakage current suppression method provided in the embodiments of this disclosure.

[0049] It should be understood that the number of controllers in Figure 1 is merely illustrative. Any number of controllers can be used depending on implementation requirements.

[0050] Figure 2 schematically illustrates a flowchart of a leakage current suppression method according to an embodiment of the present disclosure.

[0051] As shown in Figure 2, the method includes operations S210 to S240.

[0052] In operation S210, the data to be stored is input into the target neural network, and the word line offset address is output. The word line offset address is the address that best suppresses leakage between adjacent word lines in the flash memory, corresponding to the data state value in the data to be stored.

[0053] In operation S220, the word line base address is determined from the pre-stored word line address in the flash memory.

[0054] In operation S230, the target word line is determined from the word lines of the flash memory based on the word line base address and word line offset address.

[0055] In operation S240, leakage current is suppressed by writing data status values ​​to the flash memory's storage cells using the target word line.

[0056] According to embodiments of this disclosure, the data to be stored may include multiple data state values. These multiple data state values ​​may be the same or different. Different data state values ​​correspond to different data states. For example, the lowest data state value is 0, and the highest is 16. The data state corresponding to a data state value of 0 is an erase state, which can be used to erase the data stored in the storage unit. The data state corresponding to data state values ​​ranging from 1 to 15 is a programming state, which can be used to write data into the storage unit.

[0057] Multiple data status values ​​can be written to the memory cells connected to each word line, according to multiple word line addresses. The word line base address can be the initial address used to write multiple data status values. For example, the same number of word line base addresses as the number of data status values ​​can be determined from the pre-stored word lines of the flash memory. After writing the data status values, due to the large difference in voltage thresholds, charge migration will occur between the memory cells connected to adjacent word lines.

[0058] As shown in Figure 3, in different read / write methods, the charge migration within the memory can cause read errors in data with different programming states. This effect spreads between memory cells connected to adjacent word lines. Taking three word lines arranged sequentially as an example, when three different data state values ​​are written to the three word lines in different combinations, the memory cells connected to each of the three word lines will experience varying degrees of lateral leakage due to these different combinations. For example, lateral leakage will occur between the memory cells connected to the first and second word lines. Lateral leakage will occur between the memory cells connected to the second and third word lines. Here, E represents a memory cell with an erased data state. Px represents memory cells with different programming states. For example, P1 represents a memory cell with a data state value of 1, P2 represents a memory cell with a data state value of 2, and so on.

[0059] Based on this, the inventors discovered that the aforementioned leakage current effects can be reduced by rationally placing the addresses of data that are moved in physical pages.

[0060] Word line offset addresses can be used to adjust the base address of the word line used to write data status values, thereby optimizing the voltage threshold difference between memory cells connected to adjacent word lines. Optimization can refer to ensuring that the threshold voltage distribution between memory cells connected to multiple adjacent word lines best suppresses the aforementioned lateral leakage. In this case, the threshold voltage distribution in the memory is minimally affected by the aforementioned lateral leakage, the data retention characteristics in the memory are optimized, and the read error rate of the memory is reduced.

[0061] For example, the base address of the word line corresponding to a certain data status value can be modified based on the word line offset address, and the modified address can be obtained. Then, the data status value can be written to the memory unit connected to the word line through the word line corresponding to the modified address.

[0062] For example, there are I data status values ​​and I target word lines, where I is an integer greater than 2. When writing the I data status values ​​to the memory cell using the I target word lines, the voltage difference between adjacent word lines within the I target word lines is considered. Leakage current includes the leakage current between adjacent word lines within the I target word lines.

[0063] The word line corresponding to the modified address is the target word line. When multiple data state values ​​are written to memory cells connected to the target word lines through multiple target word lines corresponding to the multiple data state values, the probability of lateral leakage between memory cells connected to the multiple target word lines is minimized.

[0064] Figure 4 schematically illustrates a sorting diagram of data status values ​​according to an embodiment of the present disclosure.

[0065] As shown in Figure 4, the process of modifying the word line base address according to the word line offset address is similar to sorting multiple data state values ​​in the data to be stored. For example, the original data sorting can be the data sorting method corresponding to the word line base address, and the optimized data sorting can be the data sorting method after adjusting the word line offset address. As shown in Figure 4, different sortings can correspond to different scores. The score can be used to represent the leakage current suppression effect of the corresponding sorting. The data sorting method after word line offset adjustment has the highest score.

[0066] By placing data located on the same physical page in a reasonable physical location, the memory circuitry is minimized from the effects of lateral leakage current due to the change in data distribution, thereby improving data retention characteristics and reducing read errors.

[0067] Among them, Data X These can represent different data. For example, Data1 can represent the first data state value in the original data sorting; Data2 can represent the second data state value in the original data sorting; Data3 can represent the third data state value in the original data sorting; and Data4 can represent the fourth data state value in the original data sorting. The first, second, third, and fourth data state values ​​mentioned above can be the same value or different values, and this disclosure does not limit this.

[0068] WL XWord lines are designated as follows. For example, WL1 represents the first word line in memory; WL2 represents the second word line in memory; WL3 represents the third word line in memory; and WL4 represents the fourth word line in memory.

[0069] Px represents a storage unit with different programmed data states. For example, P1 represents a storage unit with a data state value of 1, P2 represents a storage unit with a data state value of 2, and so on.

[0070] In this embodiment, a target neural network can be used to predict the word line offset address corresponding to the data to be stored. In some embodiments, the target neural network is a Long Short-Term Memory (LSTM) network. In some sequence generation tasks, LSTM networks were invented as a special variant of RNNs (Recurrent Neural Networks), overcoming the difficulties RNNs face when processing long sequences. Based on this, LSTM networks can more effectively capture long-term sequence dependencies. LSTM networks introduce memory units that can store and retrieve information over a longer period. Furthermore, LSTM networks employ gating mechanisms, including input gates, forget gates, and output gates, to regulate the information flow within the LSTM units, as shown in Figure 5. In Figure 5, W can represent weight coefficients. f W c W i and W o These represent different weight coefficients. In some embodiments, the weight coefficients in the network can be the same or different, which will not be elaborated here. h can represent a latent variable. t-1 This can represent the latent variable at time t-1. t It can represent the latent variable at time t. c can represent the state of the memory cell. For example, c t-1 This could be the state of the memory cells at time t-1. t It can be the state of the memory cell at time t. σ can represent the sigmoid activation function, as exemplified by the following formula (1). tanh can represent the hyperbolic tangent function, as exemplified by the following formula (2).

[0071] For new information input into the LSTM network, the input gate controls the flow of this information into the storage unit, the forget gate determines which information to discard, and the output gate determines which information to output. By integrating storage units and gating mechanisms, the LSTM network can effectively capture long-term dependencies in sequential data, making it suitable for tasks involving sequences of varying lengths. Based on this, the inventors discovered that the LSTM neural network can provide the optimal placement for each data state value in the data to be stored, minimizing the impact of lateral leakage current on the overall data arrangement in the memory, thereby improving the stability of the data stored in the memory.

[0072] According to embodiments of this disclosure, by determining the word line offset address based on the data to be stored, and then determining the target word line from the flash memory based on the word line offset address and the word line base address, the data state value in the data to be stored is written into the storage cell of the flash memory using the target word line. This achieves the adjustment of the threshold voltage distribution of adjacent word lines in the flash memory, thereby suppressing lateral leakage current in the flash memory.

[0073] Furthermore, by using a target neural network to predict the word line offset address corresponding to the data state value in the data to be stored, it is not necessary to exhaustively enumerate all possible lateral leakage currents for all storage locations according to the evaluation rule before selecting the optimal storage location. This significantly shortens the time required to determine the placement location for different data state values ​​and reduces the consumption of computing resources. This feature is more advantageous when there are more word lines.

[0074] According to embodiments of this disclosure, there are I data state values, where I is an integer greater than 2. Inputting the data to be stored into a target neural network and outputting word line offset addresses includes: inputting the I data state values ​​into the target neural network and outputting sorting information, wherein the sorting information includes I sorting positions of the I data state values. And, using the I sorting positions as word line offset addresses for the I data state values ​​respectively. Determining word line base addresses from pre-stored word line addresses in the flash memory includes: determining I adjacent word line base addresses from the pre-stored word line addresses in the flash memory. Determining target word lines from the word lines of the flash memory based on the word line base addresses and word line offset addresses includes: generating target word line addresses for the I data state values ​​based on the I word line base addresses and I word line offset addresses. And, determining I target word lines from the word lines of the flash memory based on the target word line addresses for the I data state values.

[0075] According to embodiments of this disclosure, the sorting information described above is the sorting information of I data state values ​​within a set consisting of I data state values. For example, the sorting position of the i-th data state value is the sorting position of the i-th word line corresponding to the i-th data state value within the I word lines corresponding to the I data state values. i is a positive integer less than or equal to I.

[0076] In some embodiments, inputting I data state values ​​into a target neural network and outputting sorting information includes: inputting I data state values ​​into a target neural network and outputting sorting information and a probability corresponding to the sorting information, wherein the probability is the probability that the sorting position is the optimal position of the data state value. When all I data state values ​​are written to the storage unit in the optimal position, leakage current is best suppressed.

[0077] According to embodiments of this disclosure, the flash memory can be configured with M word lines, where M is an integer greater than or equal to N. Correspondingly, the flash memory can pre-store M word line addresses corresponding to the M word lines. I adjacent word line base addresses can be determined from the M word line addresses. The I adjacent word line base addresses can refer to the I word line addresses that are sequentially adjacent to the corresponding word lines. For example, the nth word line corresponding to the nth word line base address in the I word line base addresses and the (n+1)th word line corresponding to the (n+1)th word line base address in the I word line base addresses are adjacent, where n is a positive integer less than 1.

[0078] In some embodiments, the base address of the i-th word line can be the initial address used to input the i-th data state value. Based on this, the base address of the i-th word line can be modified according to the offset addresses of the i-th word lines to obtain the i-th target word line address corresponding to the i-th data state value. The i-th target word line address is an address among the I-word line base addresses. Based on this, the I word lines used to write the I data state values ​​can be redefined, and the I data state values ​​can be written using the target word lines corresponding to each of the I data state values, thereby suppressing lateral leakage in the memory.

[0079] According to embodiments of this disclosure, by using the word line offset address with the sorting position as the data state value, the target word line address corresponding to the data state value can be re-determined from the word line base address. Thus, by writing the data state value using the target memory cell connected to the target word line address, lateral leakage between adjacent word lines in the flash memory is suppressed, and the efficiency of address adjustment of the data state value is improved.

[0080] According to embodiments of this disclosure, the target neural network is trained using a semi-supervised learning method as follows: Sample data and corresponding label data are acquired. The sample data includes M sample data state values, and the label data includes K different sample ranking information corresponding to the M sample data state values, and K sets of scores corresponding to the K sample ranking information. The scores are determined based on the suppression of leakage current by the sample ranking information, where K is a positive integer greater than 1. The M sample data state values ​​are input into the initial neural network, which outputs K predicted ranking information and K sets of sample probabilities corresponding to the M sample data state values. The K predicted ranking information are all different. The k-th predicted ranking information includes M predicted ranking positions of the M sample data state values. The k-th sample probability in the K sets of sample probabilities is the probability that the predicted ranking position in the k-th predicted ranking information is the optimal ranking position of the sample data state value. When all M sample data state values ​​are written to the storage unit with their optimal ranking positions, leakage current is best suppressed. M is a positive integer greater than 1. Based on the ranking information of K samples, the predicted ranking information of K groups, the scores of K groups, and the probabilities of K groups, loss information is obtained. Based on the loss information, the network parameters of the initial neural network are adjusted to obtain the target neural network.

[0081] Figure 6 schematically illustrates a diagram of a trained neural network according to an embodiment of the present disclosure.

[0082] As shown in Figure 6, sample data 610 and a rating matrix 620 can be obtained. The rating matrix 620 can be constructed based on K sets of ratings and K different sample ranking information. Sample data 610 can be input into neural network 630, which outputs a sample probability matrix 640. The sample probability matrix 640 can be constructed based on K sets of sample probabilities and K predicted ranking information.

[0083] Based on this, loss information 650 can be calculated using K sample ranking information, K predicted ranking information, K sets of scores, and K sets of sample probabilities. For example, the same ranking information can be identified from the K predicted ranking information and the K sample ranking information, and then the loss information 650 can be calculated based on the scores and sample probabilities corresponding to the same ranking information.

[0084] Then, the network parameters of the neural network 630 are adjusted according to the loss information 650 to obtain the target neural network.

[0085] According to embodiments of this disclosure, the score is determined based on a predetermined coefficient, an influence factor, and the data status of the memory cells connected to the N word lines respectively. The influence factor is the influence factor of leakage current caused by the memory cells connected to the N word lines. The predetermined coefficient includes a predetermined comprehensive coefficient and an influence coefficient of leakage current caused by adjacent word lines. The N word lines are adjacent word lines, and N is a positive integer greater than 1.

[0086] For example, the influencing factors include: the influence factor of leakage current caused by the memory cell connected to the first word line to the memory cell connected to the second word line, and the influence factor of leakage current caused by the memory cell connected to the third word line to the memory cell connected to the second word line. Here, the second word line is a word line adjacent to both the first and third word lines. The data states of the memory cells connected to the N word lines respectively include: the data states of the memory cells connected to the first word line, the data states of the memory cells connected to the second word line, and the data states of the memory cells connected to the third word line.

[0087] Based on the above, the above score can be determined by the following evaluation function based on the combination of adjacent data patterns, i.e., the following formula (3). This evaluation function is obtained based on the analysis of the physical mechanism of the circuit. This evaluation function can be used to evaluate the cumulative effect of charge migration on the read performance of the memory cell after long-term storage of data in the memory cell in the 3D NAND flash memory array structure. The lateral leakage current effect can be expressed as a fraction through the following formula (3):

[0088] Where k(x1,x2,x3) represents the score. k1 represents the influence factor of the leakage effect of the first storage cell on the second storage cell, where the word lines connected to the first storage cell and the word lines connected to the second storage cell are adjacent. k2 represents the influence factor of the leakage effect of the second storage cell on the first storage cell. α represents a predetermined comprehensive coefficient used to improve the convergence speed of the neural network during training, and its value can be 9. Ae represents the influence coefficient of the leakage effect caused by adjacent word lines; the smaller the influence, the larger the value of Ae. x1 represents the data state of the storage cell connected to the first word line. x2 represents the data state of the storage cell connected to the second word line. x3 represents the data state of the storage cell connected to the third word line. The second word line is a word line that is adjacent to both the first and third word lines.

[0089] Table 1 below illustrates examples of Ae values.

[0090] Table 1

[0091] In Table 1, P xi This represents the data state of the memory cell connected to the i-th word line. n This indicates the data status of the memory cell connected to the nth word line. n-1 This indicates the data status of the memory cell connected to the (n-1)th word line. n+1 This indicates the data status of the memory cell connected to the (n+1)th word line. In Table 1, n is a positive integer greater than 1, and i is a positive integer less than or equal to n.

[0092] In the above formula, considering the influence of threshold voltage difference on adjacent word lines, the greater the difference in threshold voltage distribution patterns, the higher the score. Therefore, the threshold voltage difference between adjacent word lines is represented by |X n -X n+1 |and|X n -X n-1 |. Among them, X n It refers to the data status of the storage unit connected to a certain word line.

[0093] Furthermore, considering the difference in influence between the upper and lower lines of the lateral leakage current effect, the threshold voltage difference value |X is adjusted according to the influence coefficients k1 and k2. n -X n+1 |and|X n -X n-1 Perform weighted averages.

[0094] Furthermore, considering the influence of the threshold voltage on the transverse electric field, the higher the threshold distribution state of the middle word line, the higher the score. The score coefficient of the threshold voltage is X. n+1 The middle character line can refer to the character line located in the middle position among three character lines arranged in sequence.

[0095] Based on the aforementioned evaluation function, the target word line address that best suppresses leakage current can be determined, thus optimizing the data placement. Furthermore, by using the score calculated through the evaluation function as label data to train an LSTM neural network, the trained target neural network can provide the word line offset address corresponding to the optimal voltage threshold distribution. During training, the highest score is used as the training objective.

[0096] According to embodiments of this disclosure, the aforementioned K sets of sample probabilities can be constructed as a probability matrix. Correspondingly, the aforementioned K sets of scores can be constructed as a score matrix. The score matrix is ​​the design basis for the aforementioned lateral charge loss assessment function, and it is related to three adjacent word lines. Therefore, it can be combined by inputting three data state values ​​into three sequentially adjacent word lines. Each combination reflects a score. Based on this, for N word lines, there should be N·N·N of the aforementioned combinations. However, since the word lines in the combinations cannot be the same according to the non-repetition rule, only N·(N-1)·(N-2) combinations are valid. Invalid combinations have their scores set to 0, while the scores in valid combinations are set as follows.

[0097] S jik Let represent the sequential adjacency combination score of the i, j, k-th data points. i, j, and k represent the state values ​​of the three data points, respectively.

[0098] The three-dimensional combinatorial fraction matrix is ​​visualized as a heatmap, as shown in Figure 7. In Figure 7, WL represents a word line. For example, WL (n-1) This represents the (n-1)th word line. WL (n) This represents the nth word line, where n is a positive integer greater than 1 in this embodiment.

[0099] According to embodiments of this disclosure, the LSTM network described above includes an LSTM embedding layer, a fully connected linear layer, and a softmax network classification layer.

[0100] As shown in Figure 8, the LSTM embedding layer is used to embed data, where C0 and H0 are auxiliary training parameters. An LSTM unit is a single LSTM unit. Input page data can represent the input page data, i.e., the data to be stored. I1……I n These can represent n data status values ​​in the data to be stored, which will not be elaborated here. h1……h n There are n intermediate latent variable features. After embedding the input data into each group, the embedded data are concatenated and sent to the linear layer. h1'……h n Let 'n' represent the embedded latent variable features. A linear layer is used to process the embedded features of the original input; it is a fully connected neural network, and the number of layers affects the final result. Furthermore, the design of the linear layer determines the size of the model, thus determining the computational speed and space usage. The softmax layer is a general-purpose network used for task classification. The output of this layer is the classification probability distribution for each sample. In this embodiment, the output of the softmax layer is the data location probability distribution, i.e., the probability matrix described above. In this embodiment, n is a positive integer.

[0101] In LSTM network design, LSTM cells, linear fully connected layers, and normalized exponential functions are concatenated together to calculate the probability distribution matrix of the location of each data point at different physical addresses.

[0102] According to embodiments of this disclosure, the probability matrix P of the data location distribution in the LSTM output is an important element in the loss calculation. The output of the LSTM network is the order probability distribution of each page. Based on this, and constrained by the non-repeating generation rule, each generated page cannot be the same as any previously generated page.

[0103] For example, in this embodiment, i is a positive integer, N is a positive integer, and n is a positive integer less than or equal to N. Based on this, assuming the physical page of the memory to be generated is page A, the probability of generating page A at the i-th location in the memory is P. i The probability of generating page A in the first n-1 locations of memory is P. 00 P 10 P (n-2)0The prior probability of generating page A at the nth location in memory is 1-P. 00 1-P 10 The product of ... (1-P) (n-2)0 Based on this, let P be the prior probability distribution of the nth data state value at each position. n prior In this sorting sequence generation task, the probability distribution for generating the position of the i-th data state value is P. i gen Based on this, in this sorting sequence generation task, the generation probability of each sorting method for data state values ​​is calculated as follows:

[0104] Based on this, we can obtain the actual sorting generation probability for each page in different lines of text within this non-repeating generation task. Therefore, we can calculate the probability of each sorting combination:

[0105] Among them, P ijk gen P represents the probability of generating three consecutive physical pages in a specific order. i, j, and k represent three consecutive word lines, corresponding to the aforementioned three consecutive physical pages. it loc P is the probability that each data state value output by the LSTM network will be stored in the memory cell connected to the i-th word line. j(t+1) loc P is the probability that each data state value output by the LSTM network will be stored in the memory cell connected to the j-th word line. k(t+2) loc N is the probability that each data state value output by the LSTM network will be stored in the memory cell connected to the k-th word line. N-2 is the number of locations in the memory where the data state value to be written will be.

[0106] Since each word line in the combination is independent, and when there are N word lines, each triplet combination can be set at (N-2) potential positions. It has a combination probability matrix P. combing And the score matrix S for each combination combing The score for each combination is calculated using the following formula:

[0107] As shown in Figure 9, the total score should be the sum of the probability scores of all (N-2) combinations of the sorted positions of three adjacent data state values. Here, Posi(n) represents the coordinate of the nth position, Posi(n-1) represents the coordinate of the (n-1)th position, and Posi(n+1) represents the coordinate of the (n+1)th position. This represents the combination probability matrix. Let S represent the score matrix. a, b, and c represent three word lines arranged sequentially. Based on probability, the final score can be described as the combined score S across all word lines. LCM :

[0108] The higher the score, the greater the probability that the LSTM network will choose that ranking method. However, considering the optimization of a lossy model, model optimization always involves a reduction in loss. Based on this, we can base it on S... LCM The negative value is used to set the loss function. N can represent the number of word lines. t can represent the number of word lines.

[0109] Figure 10 schematically illustrates a score matrix heatmap of a sample dataset. From left to right, it shows the frequency heatmaps for each combination at the start of training, 300 epochs, and the end. In Figure 10, WL represents the word line. For example, WL (n-1) This represents the (n-1)th word line. WL (n) This represents the nth word line, where n is a positive integer greater than 1 in this embodiment.

[0110] As shown in Figure 10, the combination frequency gradually increases as training progresses and the combination frequency increases.

[0111] Based on this, the initial neural network can be trained to obtain the target neural network, which is then used to provide the optimal input position for each page based on the data state values. The training and test sets for training the initial neural network are randomly generated. During training, the neural network should learn the rule of non-repetition and which ordering combination of data state values ​​yields the highest total score. The output probability of the page with the highest total score should be as close to 1 as possible, while the output probabilities of other pages should be as close to 0 as possible.

[0112] Based on the above-described leakage current suppression method, this disclosure also provides a leakage current suppression device. The device will be described in detail below with reference to FIG11.

[0113] Figure 11 schematically illustrates a block diagram of a leakage current suppression device according to an embodiment of the present disclosure.

[0114] As shown in Figure 11, the leakage current suppression device includes a first input module 1110, a first determination module 1120, a second determination module 1130, and a writing module 1140.

[0115] The first input module 1110 is configured to input the data to be stored into the target neural network and output a word line offset address, wherein the word line offset address is the address that best suppresses leakage between adjacent word lines in the flash memory, corresponding to the data state value in the data to be stored. In one embodiment, the first input module 1110 may be configured to perform the operation S210 described above, which will not be repeated here.

[0116] The first determining module 1120 is configured to determine the word line base address from the pre-stored word line addresses of the flash memory. In one embodiment, the first determining module 1120 may be configured to perform the operation S220 described above, which will not be repeated here.

[0117] The second determining module 1130 is configured to determine a target word line from the word lines of the flash memory based on the word line base address and the word line offset address. In one embodiment, the second determining module 1130 may be configured to perform the operation S220 described above, which will not be repeated here.

[0118] The write module 1140 is configured to suppress leakage by writing data status values ​​to the storage cells of the flash memory using a target word line. In one embodiment, the write module 1130 may be configured to perform the operation S230 described above, which will not be repeated here.

[0119] According to embodiments of this disclosure, the first input module 1110 includes an input submodule; the first determination module 1120 includes a first determination submodule and a second determination submodule; and the second determination module 1130 includes a generation submodule and a third determination submodule. The input submodule is configured to input I data state values ​​into the target neural network and output sorting information, wherein the sorting information includes I sorting positions of the I data state values; the first determination submodule is configured to use the I sorting positions as word line offset addresses for the I data state values; the second determination submodule is configured to determine I adjacent word line base addresses from pre-stored word line addresses in the flash memory; the generation submodule is configured to generate target word line addresses for the I data state values ​​based on the I word line base addresses and the I word line offset addresses; and the third determination submodule is configured to determine I target word lines from the word lines of the flash memory based on the target word line addresses of the I data state values.

[0120] According to embodiments of this disclosure, the input submodule includes an input unit. The input unit is configured to input I data state values ​​into a target neural network and output sorting information and a probability corresponding to the sorting information. The probability is the probability that the sorting position is the optimal position of the data state value. When all I data state values ​​are written to the storage unit in their optimal positions, leakage current is best suppressed.

[0121] According to embodiments of this disclosure, the leakage current suppression device further includes an acquisition module, a second input module, an acquisition module, and an adjustment module. The acquisition module is configured to acquire sample data and corresponding label data. The sample data includes M sample data state values, and the label data includes K different sample ranking information corresponding to the M sample data state values, and K sets of scores corresponding to the K sample ranking information. The scores are determined based on the leakage current suppression status of the sample ranking information, where K is a positive integer greater than 1. The second input module is configured to input the M sample data state values ​​into an initial neural network and output K predicted ranking information and K sets of sample probabilities corresponding to the M sample data state values. The K predicted ranking information are all different, and the K predicted ranking information... The k-th predicted ranking information in the information includes M predicted ranking positions of M sample data state values. The k-th sample probability in the K-group sample probability is the probability that the predicted ranking position in the k-th predicted ranking information is the optimal position of the sample data state value. When all M sample data state values ​​are written to the storage unit with the optimal position, leakage is best suppressed. M is a positive integer greater than 1. The acquisition module is configured to obtain loss information based on the K sample ranking information, K predicted ranking information, K groups of scores and K groups of sample probabilities. The adjustment module is configured to adjust the network parameters of the initial neural network based on the loss information to obtain the target neural network.

[0122] According to embodiments of this disclosure, any plurality of modules among the first input module 1110, the first determining module 1120, the second determining module 1130, and the writing module 1140 may be combined into one module, or any one of these modules may be split into multiple modules. Alternatively, at least a portion of the functionality of one or more of these modules may be combined with at least a portion of the functionality of other modules and implemented in one module. According to embodiments of this disclosure, at least one of the first input module 1110, the first determining module 1120, the second determining module 1130, and the writing module 1140 may be at least partially implemented as hardware circuitry, such as a field-programmable gate array (FPGA), a programmable logic array (PLA), a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit (ASIC), or implemented in hardware or firmware by any other reasonable means of integrating or packaging the circuitry, or implemented in any one of software, hardware, and firmware methods, or in a suitable combination of any of these methods. Alternatively, at least one of the first input module 1110, the first determining module 1120, the second determining module 1130, and the writing module 1140 may be implemented at least partially as a computer program module, which can perform corresponding functions when the computer program module is run.

[0123] Figure 12 schematically illustrates a block diagram of an electronic device suitable for implementing a leakage current suppression method according to an embodiment of the present disclosure.

[0124] As shown in FIG12, an electronic device 1200 according to an embodiment of the present disclosure includes a processor 1201, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1202 or a program loaded from a storage portion 1208 into a random access memory (RAM) 1203. The processor 1201 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 1201 may also include onboard memory configured for caching purposes. The processor 1201 may include a single processing unit or multiple processing units configured to perform different actions of the method flow according to an embodiment of the present disclosure.

[0125] RAM 1203 stores various programs and data required for the operation of electronic device 1200. Processor 1201, ROM 1202, and RAM 1203 are interconnected via bus 1204. Processor 1201 performs various operations of the method flow according to embodiments of the present disclosure by executing programs in ROM 1202 and / or RAM 1203. It should be noted that the programs may also be stored in one or more memories other than ROM 1202 and RAM 1203. Processor 1201 may also perform various operations of the method flow according to embodiments of the present disclosure by executing programs stored in said one or more memories.

[0126] According to embodiments of this disclosure, the electronic device 1200 may further include an input / output (I / O) interface 1205, which is also connected to the bus 1204. The electronic device 1200 may also include one or more of the following components connected to the input / output (I / O) interface 1205: an input section 1206 including a keyboard, mouse, etc.; an output section 1207 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 1208 including a hard disk, etc.; and a communication section 1209 including a network interface card such as a LAN card, modem, etc. The communication section 1209 performs communication processing via a network such as the Internet. A drive 1210 is also connected to the input / output (I / O) interface 1205 as needed. A removable medium 1211, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 1210 as needed so that computer programs read from it can be installed into the storage section 1208 as needed.

[0127] This disclosure also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs that, when executed, implement the method according to the embodiments of this disclosure.

[0128] According to embodiments of this disclosure, the computer-readable storage medium may be a non-volatile computer-readable storage medium, such as including, but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this disclosure, the computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of this disclosure, the computer-readable storage medium may include ROM 1202 and / or RAM 1203 and / or one or more memories other than ROM 1202 and RAM 1203 described above.

[0129] Embodiments of this disclosure also include a computer program product comprising a computer program containing program code for performing the methods shown in the flowchart. When the computer program product is run on a computer system, the program code is used to enable the computer system to implement the leakage current suppression method provided in the embodiments of this disclosure.

[0130] When the computer program is executed by the processor 1201, it performs the functions defined in the system / apparatus of this disclosure embodiments. According to embodiments of this disclosure, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0131] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and may be downloaded and installed via the communication section 1209, and / or installed from the removable medium 1211. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0132] In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 1209, and / or installed from the removable medium 1211. When the computer program is executed by the processor 1201, it performs the functions defined in the system of this disclosure embodiment. According to embodiments of this disclosure, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0133] According to embodiments of this disclosure, program code for executing the computer programs provided in embodiments of this disclosure can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can execute entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0134] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0135] Those skilled in the art will understand that the features described in the various embodiments of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0136] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for suppressing leakage, comprising: inputting data to be stored into a target neural network, and outputting a word line offset address corresponding to a data state value in the data to be stored, wherein the word line offset address is an address that can most effectively suppress leakage between adjacent word lines in a flash memory; determining a word line base address from pre-stored word line addresses of the flash memory; determining a target word line from word lines of the flash memory based on the word line base address and the word line offset address; and suppressing the leakage by writing the data state value into a storage unit of the flash memory using the target word line.

2. The method of claim 1, wherein, The data state value is I, and I is an integer greater than 2. The inputting of the data to be stored into the target neural network and the outputting of the word line offset address comprises: inputting I data state values into the target neural network and outputting ranking information, wherein the ranking information comprises I ranking bits of the I data state values; and taking the I ranking bits as word line offset addresses of the I data state values, respectively. The determining of the word line base address from the pre-stored word line addresses of the flash memory comprises: determining I adjacent word line base addresses from the pre-stored word line addresses of the flash memory. The determining of the target word line from the word lines of the flash memory based on the word line base address and the word line offset address comprises: generating target word line addresses of the I data state values based on the I word line base addresses and the I word line offset addresses; and determining I target word lines from the word lines of the flash memory according to the target word line addresses of the I data state values.

3. The method of claim 2, wherein, The inputting of the I data state values into the target neural network and the outputting of the ranking information comprises: inputting I data state values into the target neural network and outputting ranking information and a probability corresponding to the ranking information, wherein the probability is a probability that the ranking bits are optimal bits of the data state value, and in a case that the I data state values are written into the storage unit at the optimal bits, the leakage can be most effectively suppressed.

4. The method according to any one of claims 1 to 3, wherein, The data state value is I, and the target word line is I, and I is an integer greater than 2. In a case that the I data state values are written into the storage unit using the I target word lines, respectively, a voltage difference between adjacent word lines in the I target word lines.

5. The method according to any one of claims 1 to 3, wherein, The data state value is I, and the target word line is I, and I is an integer greater than 1. The leakage comprises leakage between adjacent word lines in the I target word lines.

6. The method of any one of claims 1-3, wherein, The target neural network is trained by a semi-supervised learning method as follows: obtaining sample data and label data corresponding to the sample data, wherein the sample data comprises M sample data state values, the label data comprises K different sample ranking information corresponding to the M sample data state values, and K groups of scores corresponding to the K sample ranking information, and the scores are determined based on suppression conditions of the leakage by the sample ranking information, and K is a positive integer greater than 1. inputting the M sample data state values into an initial neural network, outputting K pieces of prediction ranking information corresponding to the M sample data state values and K groups of sample probabilities, wherein the K pieces of prediction ranking information are different from each other, the kth piece of prediction ranking information in the K pieces of prediction ranking information comprises M prediction ranking bits of the M sample data state values, and the kth group of sample probabilities in the K groups of sample probabilities is a probability that a prediction ranking bit in the kth piece of prediction ranking information is an optimal bit of the sample data state value, wherein, in a case where the M sample data state values are all written into the storage unit in the optimal bit, the M sample data state values can most inhibit the leakage, and M is a positive integer greater than 1; obtaining loss information based on the K pieces of sample ranking information, the K pieces of prediction ranking information, the K groups of scores, and the K groups of sample probabilities; adjusting network parameters of the initial neural network based on the loss information to obtain the target neural network.

7. The method of claim 6, wherein, The score is determined based on a predetermined coefficient, an influence factor, and data states of storage units respectively connected to N word lines, wherein the influence factor is an influence factor of mutual leakage influence of the storage units respectively connected to the N word lines, the predetermined coefficient includes a predetermined comprehensive coefficient and an influence coefficient of mutual leakage influence of the adjacent word lines, and the N word lines are adjacent word lines, and N is a positive integer greater than 1.

8. The method of claim 7, wherein, The influence factor includes an influence factor of leakage influence of the storage unit connected to the first word line on the storage unit connected to the second word line, and an influence factor of leakage influence of the storage unit connected to the third word line on the storage unit connected to the second word line, wherein the second word line is adjacent to the first word line and the third word line. The data states of the storage units respectively connected to the N word lines include data states of the storage units connected to the first word line, the second word line, and the third word line.

9. The method of any one of claims 1-3, wherein, The target neural network is a long short-term memory network.

10. A leakage suppression device, comprising: a first input module configured to input to-be-stored data into a target neural network and output a word line offset address corresponding to a data state value in the to-be-stored data, wherein the word line offset address is an address that can most inhibit leakage between adjacent word lines in a flash memory; a first determination module configured to determine a word line base address from pre-stored word line addresses of the flash memory; a second determination module configured to determine a target word line from word lines of the flash memory based on the word line base address and the word line offset address; a writing module configured to write the data state value into a storage unit of the flash memory by using the target word line to suppress the leakage.

Images