Display panel and display device

Abstract

A display panel and a display device, the display panel comprising multi-stage cascaded gate driving units. The Nth-stage gate driving unit comprises: a scan signal output end (OUT); a cascading signal output end (Carry); a first control signal input end (SW); a first transistor (NT15) connected to the cascading signal output end (Carry) and a first clock signal input end (CKN); a second transistor (NT9) connected to the scan signal output end (OUT) and the first clock signal input end (CKN); and a third transistor (NT18) connected to gates of the first and second transistors (NT15, NT9) and the first control signal input end (SW), wherein N is a positive integer. Thus, differentiated scan control of different display areas can be realized.

Description

Display panel and display device TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] In the prior art, a display panel usually adopts a gate driving circuit to control the scanning signals of each row of pixels.

[0003] The conventional gate driving circuit usually adopts a fixed frequency for scanning. This method is simple, but in some application scenarios, it will cause unnecessary power consumption. Moreover, the gate driving scheme with fixed scanning frequency is difficult to meet complex display requirements. For example, high refresh rate dynamic content and low refresh rate static content may need to be displayed on the same display panel at the same time, and the prior art is difficult to realize such differentiated scanning control on the same panel.

[0004] Therefore, there is an urgent need for a new display panel which can realize differentiated scanning control of different regions, thereby effectively reducing power consumption while ensuring display quality. SUMMARY

[0005] Embodiments of the present application provide a display panel and a display device, aiming to realize differentiated scanning control of different display regions in the display panel.

[0006] An embodiment of the present application provides a display panel, which comprises a plurality of cascaded gate driving units, an Nth gate driving unit in the plurality of cascaded gate driving units comprising: a scanning signal output end; a stage transmission signal output end; a first control signal input end; a first transistor, one of a source and a drain of the first transistor being electrically connected to the stage transmission signal output end, the other of the source and the drain of the first transistor being electrically connected to a first clock signal input end of the gate driving unit; a second transistor, one of a source and a drain of the second transistor being electrically connected to the scanning signal output end, the other of the source and the drain of the second transistor being electrically connected to the first clock signal input end; and a third transistor, one of a source and a drain of the third transistor being electrically connected to a gate of the first transistor, the other of the source and the drain of the third transistor being electrically connected to a gate of the second transistor, a gate of the third transistor being electrically connected to the first control signal input end; wherein N is a positive integer.

[0007] Embodiments of the present application also provide a display device, comprising a display panel, a timing controller and a source driving circuit, the display panel comprising a plurality of pixels, a plurality of scan lines, a plurality of data lines and a gate driving circuit, the gate driving circuit being electrically connected to the plurality of scan lines, the source driving circuit being electrically connected to the plurality of data lines, the scan lines and the data lines being electrically connected to the pixels, and the timing controller being electrically connected to the gate driving circuit and the source driving circuit; the gate driving circuit comprising a plurality of cascaded gate driving units, an Nth gate driving unit of the plurality of gate driving units comprising: a scan signal output end; a stage transmission signal output end; a first control signal input end; a first transistor, one of a source and a drain of the first transistor being electrically connected to the stage transmission signal output end, and the other of the source and the drain of the first transistor being electrically connected to a first clock signal input end of the gate driving unit; a second transistor, one of a source and a drain of the second transistor being electrically connected to the scan signal output end, and the other of the source and the drain of the second transistor being electrically connected to the first clock signal input end; and a third transistor, one of a source and a drain of the third transistor being electrically connected to a gate of the first transistor, the other of the source and the drain of the third transistor being electrically connected to a gate of the second transistor, and a gate of the third transistor being electrically connected to the first control signal input end; wherein N is a positive integer. Advantages

[0008] The present application introduces a first transistor, a second transistor and a third transistor in the gate driving unit, and connects the gate of the third transistor to the first control signal input end, thereby achieving independent control of the scan signal output end and the stage transmission signal output end, and separating the output of the stage transmission signal from the output of the scan signal. This design enables the gate driving unit to selectively output or not output the scan signal according to the level state of the first control signal, thereby realizing differentiated scanning control. Even in the case of not outputting the scan signal, the stage transmission signal can still be normally output, ensuring the continuity and stability of the gate driving circuit. In addition, by selectively controlling the gate driving unit to output or not output the scan signal, some areas of the display panel can be kept at a high refresh rate, while other areas are maintained at a low refresh rate, thereby enabling differentiated refresh rate control of different areas on the same display panel. This differentiated refresh rate control not only enables high refresh rate in areas displaying dynamic content to ensure display quality, but also enables low refresh rate in areas displaying static content to save power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0009] FIG. 1 is a schematic diagram of a display device according to an embodiment of the present application.

[0010] FIG. 2 is a schematic diagram of a gate driving unit of a display device according to an embodiment of the present application.

[0011] FIG. 3 is a timing diagram of a gate driving unit of a display device according to an embodiment of the present application.

[0012] FIG. 4 is a schematic diagram of display modes of images of a display device according to an embodiment of the present application at different refresh frequencies. Embodiments of the present application

[0013] The specific embodiments of the present application will be described below in detail with reference to the accompanying drawings.

[0014] The terms "first", "second", and similar terms do not denote any order, quantity, or importance, but are used to distinguish different technical features. The term "plurality" and similar terms mean two or more, unless otherwise explicitly limited.

[0015] The display device according to an embodiment of the present application includes an LCD display device, an OLED display device, etc. As shown in FIG. 1, the display device includes a display panel, a timing controller TCON, a source driving circuit DataDriver, a power management chip (not shown in the figure), and the power management chip can be integrated into the same chip as the timing controller TCON. The display panel includes a plurality of pixels P, a plurality of scan lines (GL1-GLn), a plurality of data lines (DL1-DLm), a gate driving circuit GOA, etc. The plurality of pixels P are arranged in rows and columns. The gate driving circuit GOA is electrically connected to the plurality of scan lines (GL1-GLn). The source driving circuit DataDriver is electrically connected to the plurality of data lines (DL1-DLm). The scan lines (GL1-GLn) and the data lines (DL1-DLm) are electrically connected to the pixels P. The timing controller TCON is electrically connected to the gate driving circuit GOA and the source driving circuit DataDriver.

[0016] In the case where the display panel is an LCD display panel, the display panel includes a thin film transistor array substrate, a counter substrate, and a liquid crystal material disposed between the thin film transistor array substrate and the counter substrate. The thin film transistor array substrate includes a substrate, a gate driving circuit GOA, a pixel P, a scan line (GL1-GLn), a data line (DL1-DLm), a color resist, etc. The pixel P includes a thin film transistor, a pixel electrode, etc. The thin film transistor is electrically connected to the pixel electrode, the scan line (GL1-GLn), and the data line (DL1-DLm).

[0017] In a case where the display panel is an OLED display panel, the display panel comprises a substrate, a pixel P, a gate drive circuit GOA, an organic light emitting device, an encapsulation layer, a polarizer, a color filter, etc., the substrate may be, for example, a glass substrate, a flexible substrate (e.g., a polyimide substrate), etc., the pixel P comprises an organic light emitting device (OLED) and a drive circuit, the drive circuit comprises a plurality of thin film transistors, the organic light emitting device is electrically connected to the drive circuit, the organic light emitting device comprises a light emitting layer, an electron transport layer, a hole transport layer, a cathode, an anode, etc., and the encapsulation layer comprises a multilayer structure of organic / inorganic alternation.

[0018] The gate drive circuit GOA comprises a plurality of cascaded gate drive units, each of which is electrically connected to a row of pixels P, and each of the gate drive units is configured to provide a scan signal to the pixels P.

[0019] The source drive circuit DataDriver is configured to provide a data signal to the pixels P.

[0020] The timing controller TCON is configured to receive externally input image data, and control the gate drive circuit GOA to output the scan signal, and control the source drive circuit DataDriver to output the data signal.

[0021] The power management chip is configured to provide required operating voltages for various parts of the display device.

[0022] As shown in FIG. 2, the display panel in the display device provided by the embodiments of the present application comprises a plurality of cascaded gate drive units, and an Nth gate drive unit in the plurality of cascaded gate drive units comprises:

[0023] a scan signal output terminal OUT configured to output a scan signal;

[0024] a carry signal output terminal Carry configured to output a carry signal;

[0025] a first control signal input terminal SW0 configured to receive a first control signal;

[0026] a first clock signal input terminal CK[N] configured to receive a first clock signal;

[0027] a first transistor NT15 having one of a source or a drain electrically connected to the carry signal output terminal Carry, and the other electrically connected to the first clock signal input terminal CK[N];

[0028] a second transistor NT9 having one of a source or a drain electrically connected to the scan signal output terminal OUT, and the other electrically connected to the first clock signal input terminal CK[N];

[0029] A third transistor NT18 has one of its source or drain electrically connected to the gate of the first transistor NT15 and the other electrically connected to the gate of the second transistor NT9, and its gate electrically connected to the first control signal input terminal SW0. In other words, one of the source or drain of the third transistor NT18 is electrically connected to the first node Q of the gate drive unit.

[0030] wherein N is a positive integer.

[0031] The first transistor NT15 and the second transistor NT9 are respectively used to control the output of the stage transmission signal and the scanning signal. The third transistor NT18 is used as a control switch to control the on-off state of the second transistor NT9 through the control signal received by the first control signal input terminal SW0.

[0032] For example, when the first control signal is at a high level, the third transistor NT18 is turned on, so that the gate potential of the second transistor NT9 is raised, thereby allowing the output of the scanning signal. Conversely, when the first control signal is at a low level, the third transistor NT18 is turned off, so that the gate potential of the second transistor NT9 is lowered, thereby inhibiting the output of the scanning signal.

[0033] It should be noted that whether the stage transmission signal is outputted or not is not controlled by the first control signal, and the output of the stage transmission signal is controlled by the potential of the Q point of the gate drive unit.

[0034] Through the above technical solution, the gate drive unit of each stage can flexibly control the output of the scanning signal according to the state of the first control signal, thereby realizing the differential scanning control of different regions or different contents of the display panel.

[0035] The gate drive unit in the display device provided by the embodiment of the present application presents two different working modes according to the level state of the first control signal:

[0036] When the first control signal is a high level signal, the third transistor NT18 is turned on. Since the source and the drain of the third transistor NT18 are respectively connected to the gates of the first transistor NT15 and the second transistor NT9, the first transistor NT15 and the second transistor NT9 are simultaneously turned on in the case that the potential of the Q point of the gate drive unit is at a high level. At this time, the stage transmission signal output terminal Carry outputs the stage transmission signal, and the scanning signal output terminal OUT outputs the scanning signal. The stage transmission signal is transmitted from the first clock signal input terminal CK[N] to the stage transmission signal output terminal Carry through the turned-on first transistor NT15. The scanning signal is transmitted from the first clock signal input terminal CK[N] to the scanning signal output terminal OUT through the turned-on second transistor NT9.

[0037] When the first control signal is a low-level signal, the third transistor NT18 is turned off. Since the third transistor NT18 is turned off, the potential of the gate of the second transistor NT9 is no longer consistent (approximately equal) with the potential of the Q point of the gate drive unit, causing the second transistor NT9 to be turned off. At this time, the carry signal output terminal Carry can still output the carry signal, because the output of the carry signal is controlled by the potential of the Q point of the gate drive unit, and the scan signal output terminal OUT does not output the scan signal. Since the second transistor NT9 is turned off, the first clock signal cannot be transmitted to the scan signal output terminal OUT, so the scan signal is inhibited from being output.

[0038] Through the above technical solution, the display panel of the present application can flexibly control the output of the scan signal according to the state of the first control signal, without affecting the normal transmission of the carry signal, which is conducive to realizing differentiated scanning control and low-power operation of the display panel. For example, in areas or time periods where there is no need to update the display content, the output of the scan signal can be suspended by setting the first control signal to a low level, thereby reducing unnecessary power consumption.

[0039] As shown in FIG. 3, the multiple frames of pictures displayed by the display panel include one frame of first picture and one frame of second picture that are continuous in time.

[0040] During the driving period of the first picture, the first control signal remains a high-level signal. At this time, the carry signal output terminal Carry outputs the carry signal, and the scan signal output terminal OUT outputs the scan signal. This means that during the entire display process of the first picture, the display panel maintains normal scanning and driving to ensure complete display of the picture.

[0041] The driving period of the second picture includes a first stage and a second stage located after the first stage, in the first stage, the first control signal is a high-level signal, and in the second stage, the first control signal is a low-level signal. Alternatively, in the first stage, the first control signal is a low-level signal, and in the second stage, the first control signal is a high-level signal.

[0042] For example, the driving period of the second picture is divided into two stages:

[0043] First stage: the first control signal is a high-level signal, and the working state of this stage is the same as that of the driving period of the first picture, both the carry signal and the scan signal are normally output, and this stage is used to update the part of the second picture that changes.

[0044] The second stage: the first control signal turns into a low level signal. At this time, the carry signal output end Carry still outputs the carry signal, but the scan signal output end OUT does not output the scan signal. This stage is used to maintain the part of the second picture that does not change, and there is no need to continue the scan driving.

[0045] The above technical solution can dynamically adjust the driving strategy based on the actual display content requirements. In the case of similar two frames of picture content or no change in part of the area, the scan of the unchanged area in the second picture can be stopped in the second stage, so as to achieve the purpose of reducing power consumption.

[0046] For example, if only part of the second picture changes, after the update of the changed area is completed in the first stage, the remaining second stage can stop the output of the scan signal by reducing the level of the first control signal, which ensures the timeliness of picture update and avoids unnecessary refreshing of static content, thereby realizing low-power operation of the display panel.

[0047] The time length of the first stage and the second stage in the second picture driving period can be flexibly adjusted according to the degree of change of the actual display content. Specifically, the time length can be adjusted by a control signal generation circuit to further optimize the power consumption.

[0048] Embodiments of the present application further optimize the switching timing of the first control signal, so that it is accurately synchronized with the first clock signal CK, thereby realizing more precise driving control. Specifically:

[0049] The falling edge start time of the first control signal is consistent with the falling edge start time of the Kth first clock signal CK in the second picture driving period. Here, K is a positive integer, representing the number of first clock signals counted from the beginning of the second picture driving period.

[0050] Through the above synchronization design, it can be ensured that the state switching of the first control signal occurs at the falling edge of the first clock signal CK, which is usually the most stable time in digital circuits, which can effectively avoid glitches or abnormalities caused by asynchronous signal switching. In addition, by selecting an appropriate K value, the time length of the first stage and the second stage in the second picture driving period can be accurately controlled, thereby realizing fine adjustment of scan control (refresh frequency control) and power consumption control.

[0051] In specific implementation, the K value can be set according to the actual requirements of the display panel:

[0052] If the K value is small, it means that the first control signal switches to the low level early, which will result in a shorter first stage in the second picture driving period, which is suitable for the case where only a small amount of content update is required in the picture.

[0053] If the K value is large, the first control signal switches to low level later, making the first stage of the second picture driving period longer, which is suitable for the case where the picture needs more content update.

[0054] For example, assuming that the driving period of a display panel contains 100 clock periods, if K = 30 is set, it means that during the first 30 clock periods of the second picture driving period, the first control signal maintains high level, and the gate driving unit normally outputs the scanning signal. From the falling edge of the 30th clock signal, the first control signal SW0 switches to low level, and the gate driving unit stops outputting the scanning signal and enters the low-power mode.

[0055] By dynamically adjusting the K value, the display panel can find the best balance point between display quality and power consumption according to the needs of different scenes.

[0056] In practical applications, the optimal K value can be dynamically calculated by an image analysis algorithm, thereby realizing adaptive scanning control.

[0057] The display panel in the display device provided by the embodiment of the present application includes a plurality of display areas, which at least include a first display area and a second display area. The first display area and the second display area are arranged in sequence along the arrangement direction of the gate driving units. Among them, the first display area adopts high-frequency refresh, and the second display area adopts low-frequency refresh. The frequency of the high-frequency refresh is higher than that of the low-frequency refresh, and vice versa. The first display area is used to display content requiring high refresh rate, and the second display area is used to display content allowing low refresh rate, thereby achieving the purpose of reducing overall power consumption.

[0058] The first display area is used to display dynamic content (such as video, animation, etc.), so a higher refresh frequency is required to ensure smooth picture; while the second display area is used to display static content (such as text, icon, etc.), only a lower refresh frequency is needed to meet the display requirements. This design enables the display panel to realize differentiated driving of different areas, thereby meeting the needs of different application scenarios.

[0059] Each display area has a corresponding group of gate driving units. These gate driving units each include a scanning signal output end OUT, a carry signal output end Carry, etc.

[0060] The first control signal is used to realize differentiated scanning control of different display areas of the display panel:

[0061] For the first display area, the first control signal controls the gate drive unit electrically connected to the pixels in the first display area, so that the scan signal output end OUT outputs the scan signal at the first frequency f1. For the second display area, the first control signal controls the gate drive unit electrically connected to the pixels in the second display area, so that the scan signal output end OUT outputs the scan signal at the second frequency f2. The first frequency f1 is greater than the second frequency f2. The specific values of the first frequency f1 and the second frequency f2 can be optimized according to the actual application scenario of the display panel. For example, as shown in FIG. 4, in some applications, f1 can be set to 60 Hz, and f2 can be set to 30 Hz, or f1 can be set to 120 Hz, and f2 can be set to 60 Hz.

[0062] Through the above technical solution, the most suitable refresh frequency can be implemented in the area of different content types, thereby improving the overall display effect, and for the area that does not need high-frequency refresh, a lower refresh frequency can be used, thereby significantly reducing power consumption.

[0063] The gate drive unit of the embodiment further includes a second control signal input end SW1 and a fourth transistor NT19, and the second control signal input end SW1 is used to input a second control signal.

[0064] One of the source or drain of the fourth transistor NT19 is electrically connected to the gate of the second transistor NT9, the other of the source or drain of the fourth transistor NT19 is electrically connected to the low potential signal input end VGL of the gate drive unit, and the gate of the fourth transistor NT19 is electrically connected to the second control signal input end SW1.

[0065] The second control signal is used to pull down the voltage of the gate of the second transistor through the fourth transistor in the case that the third transistor NT18 is closed, so that the second transistor remains closed, avoiding the gate of the second transistor being pulled up by the coupling effect of the first clock signal input end, and further avoiding the scan signal output end outputting the scan signal at the time when it should not output the scan signal.

[0066] That is, the second control signal is used to control the on-off state of the fourth transistor NT19 to prevent the scan signal output end OUT from appearing in a suspended state.

[0067] The gate potential of the second transistor NT9 is controlled through the on-off state of the fourth transistor NT19, thereby realizing accurate control of the scan signal output.

[0068] In the embodiment, when the first control signal is at a high level, the second control signal is at a low level; and when the first control signal is at a low level, the second control signal is at a high level.

[0069] Specifically, when the scan signal needs to be output, the first control signal is high, the second control signal is low, the third transistor NT18 is turned on, and the fourth transistor NT19 is turned off, the gate of the second transistor NT9 is pulled high, allowing the scan signal to be output.

[0070] When the scan signal does not need to be output, the first control signal is low, the second control signal is high, the third transistor NT18 is turned off, and the fourth transistor NT19 is turned on, the gate of the second transistor NT9 is pulled low to the VGL potential, ensuring that the scan signal will not be output.

[0071] In the above technical solution, through the double control mechanism, the misoperation caused by the abnormality of a single control signal is effectively prevented. The anti-interference ability of the circuit is enhanced. Even if the gate of the second transistor NT9 is coupled by the first clock signal input from the first clock signal input terminal, the potential of the gate of the second transistor NT9 is low when the scan signal does not need to be output, further reducing the leakage current and reducing the static power consumption.

[0072] The display device of the embodiment further includes a control signal generation circuit. The control signal generation circuit is provided with a control signal output terminal, and the control signal output terminal is electrically connected with the first control signal input terminal of each stage of gate driving units in the display panel.

[0073] The control signal generation circuit is used to generate and output the first control signal, and the first control signal is used to uniformly control whether all the gate driving units output the scan signal. Specifically, the control signal generation circuit is used to transmit the first control signal to the first control signal input terminal of each stage of gate driving units through the control signal output terminal. After each stage of gate driving units receives the first control signal, the high or low level state of the first control signal is used to control whether the scan signal output terminal outputs or does not output the scan signal.

[0074] Since all the gate driving units receive the same control signal, the working state of each gate driving unit can be highly synchronized, and potential timing deviation is reduced.

[0075] The control signal generation circuit can be, for example, a digital logic circuit, a microcontroller, or an application-specific integrated circuit (ASIC), etc. The control signal generation circuit can be, for example, a timing control circuit, and the control signal generation circuit can also be integrated in the timing control circuit.

[0076] The gate driving unit of the embodiment further includes an inverter. The inverter is electrically connected to the first control signal input terminal and the second control signal input terminal SW1. The inverter is used to generate the second control signal which is opposite to the first control signal transmitted by the first control signal input terminal according to the first control signal.

[0077] When the first control signal is at high level, the inverter outputs the second control signal at low level. When the first control signal is at low level, the inverter outputs the second control signal at high level.

[0078] With the built-in inverter, the gate drive unit can generate the required complementary control signals without external circuits, reducing the complexity of the overall circuit. In addition, since the second control signal is directly generated from the first control signal, the timing relationship between the two is more accurate, reducing the possibility of signal delay or synchronization problems. The inverter can ensure that the first control signal and the second control signal always remain in complementary states, helping to accurately control the working state of the gate drive unit and further optimize power consumption.

[0079] The inverter of the embodiment includes a fifth transistor NT22 and a sixth transistor NT23.

[0080] One of the source or drain of the fifth transistor NT22 is electrically connected to the high potential signal input end VGH of the gate drive unit, the other of the source or drain of the fifth transistor NT22 is electrically connected to the gate of the fifth transistor NT22, and the other of the source or drain of the fifth transistor NT22 is electrically connected to the second control signal input end SW1 for outputting the second control signal SW1.

[0081] One of the source or drain of the sixth transistor NT23 is electrically connected to the other of the source or drain of the fifth transistor NT22 (i.e. the second control signal input end SW1), the other of the source or drain of the sixth transistor NT23 is electrically connected to the low potential signal input end VGL, and the gate of the sixth transistor NT23 is electrically connected to the first control signal input end for receiving the first control signal.

[0082] The working principle of the inverter is as follows:

[0083] When the first control signal is at high level, the sixth transistor NT23 is turned on, pulling the second control signal input end SW1 to the VGL level, at this time, the second control signal is at low level. When the first control signal is at low level, the sixth transistor NT23 is closed, and the fifth transistor NT22 is turned on under the action of the high potential signal at the high potential signal input end VGH, the second control signal input end SW1 is pulled to high level, at this time, the second control signal SW1 is at high level.

[0084] Through the combination of two transistors, a fast and reliable signal inversion function is realized.

[0085] The gate drive unit of the embodiment further includes a seventh transistor NT16 and an eighth transistor NT10.

[0086] One of the source or drain of the seventh transistor NT16 is electrically connected to the carry signal output end Carry, and the other of the source or drain of the seventh transistor NT16 is electrically connected to the low potential signal input end VGL. The seventh transistor NT16 is used for controlling the output of the carry signal. When the seventh transistor NT16 is turned on, the carry signal output end Carry can be pulled low to the low level, effectively inhibiting the unwanted carry signal output.

[0087] One of the source or drain of the eighth transistor NT10 is electrically connected to the scan signal output end OUT, and the other of the source or drain of the eighth transistor NT10 is electrically connected to the low potential signal input end VGL. The eighth transistor NT10 is used for controlling the output of the scan signal. When the eighth transistor NT10 is turned on, the scan signal output end OUT can be pulled low to the low level, ensuring that the scan signal remains in the low level state during the non-scanning period.

[0088] Through the actions of the seventh transistor NT16 and the eighth transistor NT10, the floating state of the carry signal and the scan signal during the non-working period can be effectively prevented.

[0089] The gate driving unit in the display panel of the embodiment further includes a ninth transistor NT11, a tenth transistor NT12, an eleventh transistor NT17, a twelfth transistor NT20, a thirteenth transistor NT13, a fourteenth transistor NT1, a fifteenth transistor NT7, a sixteenth transistor NT3, a seventeenth transistor NT4, an eighteenth transistor NT14, a nineteenth transistor NT8, a twentieth transistor NT2, a twenty-first transistor NT6, a twenty-second transistor NT21, a twenty-third transistor NT5, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0090] The gate of the ninth transistor NT11 is electrically connected to one of the source or drain of the ninth transistor NT11, and the other of the source or drain of the ninth transistor NT11 is electrically connected to the carry signal output end Carry. The gate of the ninth transistor NT11 is electrically connected to the first all row switching signal (Gate All Switch) input end GAS1.

[0091] The gate of the tenth transistor NT12 is electrically connected to the gate of the ninth transistor NT11, one of the source or drain of the tenth transistor NT12 is electrically connected to the low potential signal input end VGL, and the other of the source or drain of the tenth transistor NT12 is electrically connected to the gate of the seventh transistor NT16.

[0092] The gate of the eleventh transistor NT17 is electrically connected to one of the source or drain of the eleventh transistor NT17, and the other of the source or drain of the eleventh transistor NT17 is electrically connected to the scan signal output end OUT.

[0093] One of the source and the drain of the twelfth transistor NT20 is electrically connected to the low potential signal input terminal VGL, one of the source and the drain of the twelfth transistor NT20 is electrically connected to the gate of the eighth transistor NT10, and one of the source and the drain of the twelfth transistor NT20 is electrically connected to the gate of the seventh transistor NT16.

[0094] One of the source and the drain of the thirteenth transistor NT13 is electrically connected to the low potential signal input terminal VGL, the other of the source and the drain of the thirteenth transistor NT13 is electrically connected to the scan signal output terminal OUT, and the gate of the thirteenth transistor NT13 is electrically connected to the second Gate All Switch input terminal GAS2.

[0095] The gate of the fourteenth transistor NT1 is electrically connected to the start signal input terminal STV of the gate drive unit, one of the source and the drain of the fourteenth transistor NT1 is electrically connected to the forward scan control signal input terminal U2D, and the other of the source and the drain of the fourteenth transistor NT1 is electrically connected to the first node Q of the gate drive unit.

[0096] The gate of the fifteenth transistor NT7 is electrically connected to the high level signal input terminal VGH of the gate drive unit, one of the source and the drain of the fifteenth transistor NT7 is electrically connected to the first node Q, and the other of the source and the drain of the fifteenth transistor NT7 is electrically connected to the gate of the first transistor NT15. The fifteenth transistor NT7 is used to ensure that each first clock signal can be given to the stage transmission signal output terminal Carry when the first node Q is at a high potential.

[0097] The gate of the sixteenth transistor NT3 is electrically connected to the forward scan control signal input terminal U2D, and one of the source and the drain of the sixteenth transistor NT3 is electrically connected to the second clock signal input terminal CK[N+2].

[0098] The gate of the seventeenth transistor NT4 is electrically connected to the reverse scan control signal input terminal D2U, one of the source and the drain of the seventeenth transistor NT4 is electrically connected to the third clock signal input terminal CK[N-2], and the other of the source and the drain of the seventeenth transistor NT4 is electrically connected to the other of the source and the drain of the sixteenth transistor NT3.

[0099] The gate of the eighteenth transistor NT14 is electrically connected to the first Gate All Switch input terminal GAS1, and one of the source and the drain of the eighteenth transistor NT14 is electrically connected to the other of the source and the drain of the sixteenth transistor NT3.

[0100] The first plate of the first capacitor C1 is electrically connected to the first node Q, and the second plate of the first capacitor is electrically connected to the other one of the source and the drain of the eighteenth transistor NT14.

[0101] The gate of the nineteenth transistor NT8 is electrically connected to the other one of the source and the drain of the sixteenth transistor NT3, one of the source and the drain of the nineteenth transistor NT8 is electrically connected to the high potential signal input terminal VGH, and the other one of the source and the drain of the nineteenth transistor NT8 is electrically connected to the gate of the seventh transistor NT16.

[0102] The gate of the twentieth transistor NT2 is electrically connected to the scanning signal output terminal G[N+2] of the N+2th stage gate driving unit, and one of the source and the drain of the twentieth transistor NT2 is electrically connected to the reverse scanning control signal input terminal D2U.

[0103] The gate of the twenty-first transistor NT6 is electrically connected to the other one of the source and the drain of the twentieth transistor NT2, one of the source and the drain of the twenty-first transistor NT6 is electrically connected to the low potential signal input terminal VGL, and the other one of the source and the drain of the twenty-first transistor NT6 is electrically connected to the gate of the seventh transistor NT16.

[0104] The gate of the twenty-second transistor NT21 is electrically connected to the reset signal input terminal Reset of the gate driving unit, one of the source and the drain of the twenty-second transistor NT21 is electrically connected to the gate of the twenty-second transistor NT21, and the other one of the source and the drain of the twenty-second transistor NT21 is electrically connected to the gate of the seventh transistor NT16.

[0105] The gate of the twenty-third transistor NT5 is electrically connected to the gate of the seventh transistor NT16, one of the source and the drain of the twenty-third transistor NT5 is electrically connected to the low potential signal input terminal VGL, and the other one of the source and the drain of the twenty-third transistor NT5 is electrically connected to the first node Q.

[0106] The first plate of the second capacitor C2 is electrically connected to the low potential signal input terminal VGL, and the second plate of the second capacitor C2 is electrically connected to the gate of the seventh transistor NT16.

[0107] The first plate of the third capacitor C3 is electrically connected to the gate of the first transistor NT15, and the second plate of the third capacitor C3 is electrically connected to the stage transmission signal output terminal Carry.

[0108] The transistors in the embodiment are N-type thin film transistors (TFT). Of course, the transistors can also be P-type thin film transistors.

[0109] The application introduces the first transistor, the second transistor and the third transistor in the gate driving unit, and connects the gate of the third transistor to the first control signal input end, thereby realizing independent control of the scan signal output end and the stage transmission signal output end, and separating the output of the stage transmission signal from the output of the scan signal. This design enables the gate driving unit to selectively output or not output the scan signal according to the level state of the first control signal, thereby realizing differentiated scan control. Even in the case of not outputting the scan signal, the stage transmission signal can be normally output, ensuring the continuity and stability of the gate driving circuit. In addition, by selectively controlling the gate driving unit to output or not output the scan signal, some areas of the display panel can be kept at a high refresh rate, while other areas are maintained at a low refresh rate, thereby enabling differentiated refresh rate control of different areas on the same display panel. This differentiated refresh rate control not only enables high refresh rate in areas displaying dynamic content to ensure display quality, but also enables low refresh rate in areas displaying static content to save power consumption.

[0110] The embodiment of the application provides a technical scheme for realizing partition frequency display of a display panel. The gate driving unit of the display panel adopts a design of separating a scan signal output end from a stage transmission signal output end, and realizes output of the stage transmission signal and control of output or non-output of the scan signal by a switch. The transistors NT15 and NT16 of the application added in the gate driving unit serve as replica tubes of the transistors NT9 and NT10, and can generate the stage transmission signal with the same potential as the scan signal, thereby realizing separation of the scan signal and the stage transmission signal. Whether the scan signal is output or not is controlled by controlling the transistors NT18 and NT19 of the application, thereby achieving the purpose of outputting a multi-frequency signal and effectively reducing the power consumption of the display panel as a whole.

[0111] The gate driving unit of the display panel of the application generates an inverted second control signal from a first control signal by using an inverter. As shown in FIG. 2, the gate driving unit controls whether the transistor NT9 outputs the scan signal by the first control signal. When the first control signal is a low potential signal, the potential at the N point is easily affected by the first clock signal CK and the like. At this time, the gate potential of the transistor NT19 is a high potential, and the potential at the N point can be pulled down to VGL, thereby eliminating the influence of the N point on the output of the scan signal by the transistor NT9. Since the inverted signal, that is, the second control signal, generated according to the first control signal has high time accuracy and small reverse delay, it can accurately control whether a specified line in each frame outputs, thereby not only preventing the transistor NT9 from misoutputting the scan signal, but also accurately controlling multi-frequency driving output, while reducing an external signal input port.

[0112] As shown in FIG. 3, in the first frame, the first control signal keeps high potential, ensuring that each row can be normally output. In the second frame, the first control signal keeps consistent with the falling edge of the first clock signal CK1, thereby controlling all rows after the G[2] row not to output. This design realizes the feature that the refresh frequency of the first two rows is higher than that of the following rows within two frames, and has high time accuracy while realizing multi-frequency driving, thereby reducing the error of the output scanning signal.

[0113] The above has introduced the embodiments of the present application in detail, and the content of the specification should not be understood as limiting the protection scope of the present application.

Claims

1. A display panel, wherein, The display panel includes cascaded multi-stage gate driving units, wherein the Nth stage of the multi-stage gate driving units includes: Scan signal output terminal; cascade signal output terminal; First control signal input terminal; A first transistor, wherein one of the source and drain of the first transistor is electrically connected to the stage signal output terminal, and the other of the source and drain of the first transistor is electrically connected to the first clock signal input terminal of the gate driving unit. A second transistor, wherein one of its source and drain is electrically connected to the scan signal output terminal, and the other of its source and drain is electrically connected to the first clock signal input terminal; and The third transistor has one of its source and drain electrically connected to the gate of the first transistor, and the other of its source and drain electrically connected to the gate of the second transistor. The gate of the third transistor is electrically connected to the first control signal input terminal. Where N is a positive integer.

2. The display panel according to claim 1, wherein, When the first control signal is a high-level signal, the stage transmission signal output terminal is used to output the stage transmission signal, and the scan signal output terminal is used to output the scan signal. When the first control signal is a low-level signal, the stage transmission signal output terminal is used to output the stage transmission signal, and the scan signal output terminal is used not to output the scan signal.

3. The display panel according to claim 2, wherein, The display panel displays multiple frames, including a first frame and a second frame that are consecutive in time. During the driving cycle of the first frame, the first control signal is a high-level signal; The driving cycle of the second screen includes a first stage and a second stage following the first stage. In the first stage, the first control signal is either a high-level signal or a low-level signal. In the second stage, the first control signal is either a high-level signal or a low-level signal.

4. The display panel according to claim 3, wherein, The start time of the falling edge of the first control signal is the same as the start time of the falling edge of the Kth first clock signal in the driving cycle of the second screen. Where K is a positive integer.

5. The display panel according to claim 1, wherein, The display panel includes multiple display areas, including a first display area and a second display area, wherein the first display area and the second display area are arranged in the same direction as the arrangement direction of the multiple gate driving units; The first control signal is used to control the scan signal output terminals of the plurality of gate driving units of the pixels electrically connected to the first display area to output the scan signal at a first frequency, and to control the scan signal output terminals of the plurality of gate driving units of the pixels electrically connected to the second display area to output the scan signal at a second frequency, wherein the first frequency is greater than the second frequency.

6. The display panel according to claim 1, wherein, The gate driving unit further includes: The second control signal input terminal; and The fourth transistor has one of its source and drain electrically connected to the gate of the second transistor, the other of its source and drain electrically connected to the low-potential signal input terminal of the gate driving unit, and the gate of the fourth transistor electrically connected to the second control signal input terminal. Specifically, when the first control signal input at the first control signal input terminal is a high-level signal, the second control signal input at the second control signal input terminal is a low-level signal; when the first control signal is a low-level signal, the second control signal is a high-level signal.

7. The display panel according to claim 6, wherein, The display panel further includes a control signal generation circuit, the control signal output terminal of which is electrically connected to the first control signal input terminal of each stage of the gate driving unit.

8. The display panel according to claim 7, wherein, The gate driving unit further includes: An inverter is electrically connected to the first control signal input terminal and the second control signal input terminal. The inverter is used to generate the second control signal based on the first control signal transmitted from the first control signal input terminal.

9. The display panel according to claim 8, wherein, The inverter includes a fifth transistor and a sixth transistor. The gate of the fifth transistor is electrically connected to the high-potential signal input terminal of the gate driving unit. One of the source and drain of the fifth transistor is electrically connected to the gate of the fifth transistor. The other of the source and drain of the fifth transistor is electrically connected to the second control signal input terminal. One of the source and drain of the sixth transistor is electrically connected to the other of the source and drain of the fifth transistor. The other of the source and drain of the sixth transistor is electrically connected to the low-potential signal input terminal. The gate of the sixth transistor is electrically connected to the first control signal input terminal.

10. The display panel according to claim 1, wherein, The gate driving unit further includes: A seventh transistor, wherein one of its source and drain is electrically connected to the stage signal output terminal, and the other of its source and drain is electrically connected to the low-potential signal input terminal; and The eighth transistor has one of its source and drain electrically connected to the scan signal output terminal, and the other of its source and drain electrically connected to the low potential signal input terminal.

11. A display device, wherein, The display device includes a display panel, a timing controller, and a source driving circuit. The display panel includes multiple pixels, multiple scan lines, multiple data lines, and a gate driving circuit. The gate driving circuit is electrically connected to the multiple scan lines, and the source driving circuit is electrically connected to the multiple data lines. The scan lines and the data lines are electrically connected to the pixels. The timing controller is electrically connected to the gate driving circuit and the source driving circuit. The gate driving circuit includes cascaded multi-stage gate driving units, wherein the Nth stage of the multi-stage gate driving units includes: Scan signal output terminal; cascade signal output terminal; First control signal input terminal; A first transistor, wherein one of the source and drain of the first transistor is electrically connected to the stage signal output terminal, and the other of the source and drain of the first transistor is electrically connected to the first clock signal input terminal of the gate driving unit. A second transistor, wherein one of its source and drain is electrically connected to the scan signal output terminal, and the other of its source and drain is electrically connected to the first clock signal input terminal; and The third transistor has one of its source and drain electrically connected to the gate of the first transistor, and the other of its source and drain electrically connected to the gate of the second transistor. The gate of the third transistor is electrically connected to the first control signal input terminal. Where N is a positive integer.

12. The display device according to claim 11, wherein, When the first control signal is a high-level signal, the stage transmission signal output terminal is used to output the stage transmission signal, and the scan signal output terminal is used to output the scan signal. When the first control signal is a low-level signal, the stage transmission signal output terminal is used to output the stage transmission signal, and the scan signal output terminal is used not to output the scan signal.

13. The display device according to claim 12, wherein, The display panel displays multiple frames, including a first frame and a second frame that are consecutive in time. During the driving cycle of the first frame, the first control signal is a high-level signal; The driving cycle of the second screen includes a first stage and a second stage following the first stage. In the first stage, the first control signal is either a high-level signal or a low-level signal. In the second stage, the first control signal is either a high-level signal or a low-level signal.

14. The display device according to claim 13, wherein, The start time of the falling edge of the first control signal is the same as the start time of the falling edge of the Kth first clock signal in the driving cycle of the second screen. Where K is a positive integer.

15. The display device according to claim 11, wherein, The display panel includes multiple display areas, including a first display area and a second display area, wherein the first display area and the second display area are arranged in the same direction as the arrangement direction of the multiple gate driving units; The first control signal is used to control the scan signal output terminals of the plurality of gate driving units of the pixels electrically connected to the first display area to output the scan signal at a first frequency, and to control the scan signal output terminals of the plurality of gate driving units of the pixels electrically connected to the second display area to output the scan signal at a second frequency, wherein the first frequency is greater than the second frequency.

16. The display device according to claim 11, wherein, The gate driving unit further includes: The second control signal input terminal; and The fourth transistor has one of its source and drain electrically connected to the gate of the second transistor, the other of its source and drain electrically connected to the low-potential signal input terminal of the gate driving unit, and the gate of the fourth transistor electrically connected to the second control signal input terminal. Specifically, when the first control signal input at the first control signal input terminal is a high-level signal, the second control signal input at the second control signal input terminal is a low-level signal; when the first control signal is a low-level signal, the second control signal is a high-level signal.

17. The display device according to claim 16, wherein, The display panel further includes a control signal generation circuit, the control signal output terminal of which is electrically connected to the first control signal input terminal of each stage of the gate driving unit.

18. The display device according to claim 17, wherein, The gate driving unit further includes: An inverter is electrically connected to the first control signal input terminal and the second control signal input terminal. The inverter is used to generate the second control signal based on the first control signal transmitted from the first control signal input terminal.

19. The display device according to claim 18, wherein, The inverter includes a fifth transistor and a sixth transistor. The gate of the fifth transistor is electrically connected to the high-potential signal input terminal of the gate driving unit. One of the source and drain of the fifth transistor is electrically connected to the gate of the fifth transistor. The other of the source and drain of the fifth transistor is electrically connected to the second control signal input terminal. One of the source and drain of the sixth transistor is electrically connected to the other of the source and drain of the fifth transistor. The other of the source and drain of the sixth transistor is electrically connected to the low-potential signal input terminal. The gate of the sixth transistor is electrically connected to the first control signal input terminal.

20. The display device according to claim 11, wherein, The gate driving unit further includes: A seventh transistor, wherein one of its source and drain is electrically connected to the stage signal output terminal, and the other of its source and drain is electrically connected to the low-potential signal input terminal; and The eighth transistor has one of its source and drain electrically connected to the scan signal output terminal, and the other of its source and drain electrically connected to the low potential signal input terminal.

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