Flip light-emitting diode chip and manufacturing method therefor

Abstract

Provided in the present invention are a flip light-emitting diode chip and a manufacturing method therefor. The flip light-emitting diode chip comprises: a substrate, and an N-type semiconductor layer, an active light-emitting layer, a P-type semiconductor layer, a current spreading layer, a first insulating layer, a Bragg reflective layer, a metal reflective layer, a second insulating layer, a connection metal layer, a third insulating layer and a bonding pad layer, which are sequentially deposited on the substrate. The connection metal layer comprises a reflective layer and a protective layer that are sequentially arranged from bottom to top; the protective layer comprises a first protective parent layer, a second protective parent layer, and a third protective parent layer that are sequentially arranged from bottom to top, the second protective parent layer comprising n first protective sublayers and second protective sublayers that are periodically stacked, the thicknesses of the first protective sublayers gradually increasing linearly toward the third insulating layer, and the thicknesses of the second protective sublayers gradually decreasing linearly toward the third insulating layer.

Description

A flip-chip light-emitting diode and its fabrication method Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a flip-chip light-emitting diode and its fabrication method. Background Technology

[0002] In recent years, LED chip technology has developed rapidly due to competition among major manufacturers, and it has been widely used in various fields such as general lighting, special lighting, direct display screens, backlight displays, and automotive lights.

[0003] Flip-chip LEDs offer higher color contrast, brightness, and color gamut, longer lifespan, and thinner profile. They are also widely used due to their advantages such as resistance to high current surges, high reliability, high luminous efficiency, back-emitting light, strong heat dissipation, good solderability, and high reliability.

[0004] In the existing technology, the method for fabricating the third insulating layer opening in the current flip-chip manufacturing process is a dry etching process, which cannot be used for wet etching. This is because wet etching will cause corrosion of the Al metal at the bottom of the connecting electrode, resulting in Al voids and bubbles, which will ultimately affect the photoelectric performance and reliability of the flip-chip. Furthermore, using the dry etching method for the third insulating layer opening requires photolithography to be performed separately on the area of ​​the third insulating layer where the opening is required.

[0005] Summary of the Invention

[0006] Therefore, the purpose of this invention is to provide a flip-chip light-emitting diode and its fabrication method, which can preferentially solve the shortcomings of the prior art.

[0007] A flip-chip light-emitting diode (LED) chip, comprising:

[0008] The substrate and the N-type semiconductor layer, active light-emitting layer, P-type semiconductor layer, current spreading layer, first insulating layer, Bragg reflector layer, metal reflector layer, second insulating layer, connecting metal layer, third insulating layer and pad layer are sequentially deposited on the substrate.

[0009] The connecting metal layer includes a reflective layer and a protective layer arranged sequentially from bottom to top. The protective layer includes a first protective parent layer, a second protective parent layer and a third protective parent layer arranged sequentially from bottom to top. The second protective parent layer includes n periodically stacked first protective sub-layers and second protective sub-layers.

[0010] The thickness of the first protective sublayer gradually increases linearly toward the third insulating layer, and the thickness of the second protective sublayer gradually decreases linearly toward the third insulating layer.

[0011] Furthermore, the reflective layer is made of metallic Al, and its thickness is greater than [missing information].

[0012] Furthermore, the first protective matrix is ​​made of metallic Cr, and its thickness is greater than [missing information].

[0013] Furthermore, the period n of the second protective parent layer is ≥3.

[0014] Furthermore, the first protective sub-layer is made of metallic Ni, and its thickness increases linearly toward the third insulating layer.

[0015] Furthermore, the second protective sub-layer is made of metallic Cr, and its thickness decreases linearly toward the third insulating layer.

[0016] Furthermore, the material of the third protective matrix is ​​metallic Ni, and the thickness of the third protective matrix is ​​between [missing information]. between.

[0017] On the other hand, the present invention also proposes a method for fabricating a flip-chip light-emitting diode, the method comprising the following steps:

[0018] S1. A substrate is provided, and an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer are sequentially deposited on the substrate;

[0019] S2. An N-type semiconductor conductive step is prepared on the P-type semiconductor layer;

[0020] S3. A current spreading layer is prepared on the P-type semiconductor layer and the N-type semiconductor conductive step;

[0021] S4. Prepare a first insulating layer on the current spreading layer;

[0022] S5. A Bragg reflector layer and a via in the Bragg reflector layer are prepared on the first insulating layer;

[0023] S6. A first insulating layer through-hole is formed on the Bragg reflector layer, the Bragg reflector layer through-hole, and the first insulating layer;

[0024] S7. A metal reflective layer is prepared on the Bragg reflective layer, the through-hole of the Bragg reflective layer, and the through-hole of the first insulating layer;

[0025] S8. A second insulating layer and a second insulating layer through-hole are prepared in the metal reflective layer and the area not covered by the metal reflective layer.

[0026] S9. A connecting metal layer is prepared on the second insulating layer and the through-hole of the second insulating layer;

[0027] S10. A third insulating layer and a through-hole in the third insulating layer are prepared on the connecting metal layer and the second insulating layer not covered by the connecting metal layer.

[0028] S11. Prepare a pad layer on the through-hole of the third insulating layer;

[0029] The connecting metal layer includes a reflective layer and a protective layer arranged sequentially from bottom to top. The protective layer includes a first protective parent layer, a second protective parent layer and a third protective parent layer arranged sequentially from bottom to top. The second protective parent layer includes n periodically stacked first protective sub-layers and second protective sub-layers.

[0030] The thickness of the first protective sublayer gradually increases linearly toward the third insulating layer, and the thickness of the second protective sublayer gradually decreases linearly toward the third insulating layer.

[0031] Furthermore, in step S10, the steps of preparing the third insulating layer and the through-hole in the third insulating layer include:

[0032] SiO2 is deposited as a third insulating layer using PECVD process on the connecting metal layer and the second insulating layer not covered by the connecting metal layer. Then, photoresist is coated on the third insulating layer, and then exposed and developed to remove part of the photoresist, exposing part of the third insulating layer. Then, the exposed part of the third insulating layer is removed using BOE etching solution to form a via in the third insulating layer.

[0033] Furthermore, in S11, the step of preparing the pad layer includes:

[0034] On the via of the third insulating layer, Al metal, Ti metal, Al metal, Ti metal, Ni metal, Ti metal, Ni metal, Ti metal, Ni metal, Ni metal and AuSn metal are sequentially deposited as pad layers using an electron beam evaporation process. Then, the metal on top of the photoresist is removed using a blue film stripping process, and finally the photoresist is removed.

[0035] Compared with the prior art, the beneficial effects of the present invention are as follows: by setting the connecting metal layer as a reflective layer and a protective layer from bottom to top, and by setting the protective layer as a first protective mother layer, a second protective mother layer and a third protective mother layer from bottom to top, the reflective layer of the connecting electrode can be protected by the protective layer, effectively preventing the etchant from corroding the reflective layer of the connecting electrode when the third insulating layer is prepared by wet etching process. Moreover, this setting allows the pad layer to be prepared with the third insulating layer via in one photolithography process, without the need for a separate photolithography process on the opening area of ​​the third insulating layer, thus reducing the manufacturing cost of the flip-chip. Attached Figure Description

[0036] Figure 1 is a cross-sectional schematic diagram of the flip-chip light-emitting diode in Embodiment 1 of the present invention;

[0037] Figure 2 is a cross-sectional schematic diagram of the connecting metal layer in Embodiment 1 of the present invention;

[0038] Figure 3 is a flowchart of the fabrication method of the flip-chip light-emitting diode in Embodiment 2 of the present invention;

[0039] Explanation of key component symbols:

[0040] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0041] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0042] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0044] Example 1

[0045] Please refer to Figures 1 and 2. In this embodiment of the invention, the flip-chip light-emitting diode includes a substrate 10 and N-type semiconductor layer 111, active light-emitting layer 112, P-type semiconductor layer 113, current spreading layer 12, first insulating layer 13, Bragg reflector layer 14, metal reflector layer 15, second insulating layer 16, connecting metal layer 17, third insulating layer 18 and pad layer 19, which are sequentially deposited on the substrate.

[0046] The connecting metal layer 17 includes a reflective layer 171 and a protective layer 172 arranged sequentially from bottom to top. The protective layer 172 includes a first protective parent layer 1721, a second protective parent layer 1722 and a third protective parent layer 1723 arranged sequentially from bottom to top. The second protective parent layer 1722 includes n periodically stacked first protective sub-layers and second protective sub-layers.

[0047] Furthermore, the reflective layer 171 is made of metal Al, and the thickness of the reflective layer 171 is greater than [missing information].

[0048] Furthermore, the first protective base layer 1721 is made of metallic Cr, and the thickness of the first protective base layer 1721 is greater than [missing information].

[0049] Furthermore, the period n of the second protective parent layer 1722 is ≥3.

[0050] Furthermore, the third protective layer 1723 is made of metallic Ni, and its thickness is between [missing information]. between.

[0051] The thickness of the first protective sublayer gradually increases linearly toward the third insulating layer 18, and the thickness of the second protective sublayer gradually decreases linearly toward the third insulating layer 18.

[0052] Furthermore, the first protective sub-layer is made of metallic Ni, and its thickness increases linearly toward the third insulating layer.

[0053] Furthermore, the second protective sub-layer is made of metallic Cr, and its thickness decreases linearly toward the third insulating layer.

[0054] Understandably, by setting the connecting metal layer 17 as the reflective layer 171 and the protective layer 172 from bottom to top, and by setting the protective layer 172 as the first protective mother layer 1721, the second protective mother layer 1722, and the third protective mother layer 1723 from bottom to top, the reflective layer 171 of the connecting electrode can be protected by the protective layer 172, effectively preventing the etchant from corroding the reflective layer 171 of the connecting electrode when the third insulating layer via is prepared using a wet etching process. Moreover, this setting allows the pad layer 19 to be prepared together with the third insulating layer via in one photolithography process, eliminating the need for a separate photolithography process on the opening area of ​​the third insulating layer 18, thus reducing the manufacturing cost of the flip-chip.

[0055] Example 2

[0056] Please refer to Figure 3. This embodiment 2 provides a method for fabricating a flip-chip light-emitting diode (LED) chip, used to fabricate the flip-chip light-emitting diode chip described in embodiment 1. The fabrication method includes the following steps:

[0057] S1. Provide a substrate 10, and sequentially deposit an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113 on the substrate 10;

[0058] In this embodiment, the specific process for depositing the N-type semiconductor layer 111, the active light-emitting layer 112, and the P-type semiconductor layer 113 is as follows:

[0059] A substrate 10 is provided, and then the N-type semiconductor layer 111, the active light-emitting layer 112 and the P-type semiconductor layer 113 are sequentially deposited on the substrate 10 using an MOCVD process. The substrate 10 can be a GaN substrate, an Al2O3 substrate or a Si substrate.

[0060] S2. An N-type semiconductor conductive step 114 is prepared on the P-type semiconductor layer 113;

[0061] In this embodiment, the specific process for preparing the N-type semiconductor conductive step 114 is as follows:

[0062] Photoresist is coated on the surface of the P-type semiconductor layer 113. Then, a portion of the photoresist is removed using an exposure and development process to expose a portion of the P-type semiconductor layer. Then, an inductively coupled plasma etching process is used to remove the exposed portion of the P-type semiconductor layer and the active light-emitting layer below this portion of the P-type semiconductor layer to form the N-type semiconductor conductive step 114. Finally, the photoresist is removed.

[0063] S3. A current spreading layer 12 is prepared on the P-type semiconductor layer 113 and the N-type semiconductor conductive step 114.

[0064] In this embodiment, the specific process for preparing the current spreading layer 12 is as follows:

[0065] Indium tin oxide (ITO) is deposited on the surfaces of the P-type semiconductor layer 113 and the N-type semiconductor conductive step 114 using a magnetron sputtering process. Then, photoresist is coated on the ITO surface. After exposure and development, some of the photoresist is removed, exposing some of the ITO. Then, the exposed ITO is removed using an ITO etchant, the temperature of which is controlled at 45±5℃. Finally, the photoresist is removed to form the current spreading layer 12.

[0066] S4. A first insulating layer 13 is prepared on the current spreading layer 12;

[0067] In this embodiment, the specific process for preparing the first insulating layer 13 is as follows:

[0068] SiO2 is deposited as the first insulating layer 13 on the surfaces of the current spreading layer 12, the P-type semiconductor layer 113, and the N-type semiconductor conductive step 114 using a PECVD process, wherein the thickness of the first insulating layer 13 is greater than... The temperature is controlled at 270±10℃ during the PECVD process.

[0069] S5. A Bragg reflector layer 14 and a Bragg reflector through-hole are formed on the first insulating layer 13.

[0070] In this embodiment, the specific process for preparing the Bragg reflector layer 14 and the through-hole of the Bragg reflector layer is as follows:

[0071] Using electron beam evaporation, 2-10 stacks of TiO2 and SiO2 are sequentially deposited on the surface of the first insulating layer 13 to form the Bragg reflector layer 14. Then, photoresist is coated on the surface of the Bragg reflector layer 14. Then, exposure and development are used to remove part of the photoresist on the Bragg reflector layer. Then, inductively coupled plasma etching is used to remove part of the exposed Bragg reflector layer to form the via of the Bragg reflector layer, exposing the first insulating layer under the via of the Bragg reflector layer. Then, the photoresist is removed.

[0072] S6. A first insulating layer through-hole is formed on the Bragg reflector layer 14, the Bragg reflector layer through-hole and the first insulating layer 13;

[0073] In this embodiment, the specific process for preparing the through-hole in the first insulating layer is as follows:

[0074] Photoresist is applied to the surfaces of the Bragg reflector layer 14, the via of the Bragg reflector layer, and the first insulating layer 13. Then, exposure and development are used to remove part of the photoresist inside the via of the Bragg reflector layer, exposing the first insulating layer below the via of the Bragg reflector layer. Then, BOE etching solution is used to remove the exposed first insulating layer to form the via of the first insulating layer. Finally, the photoresist is removed.

[0075] S7. A metal reflective layer 15 is prepared on the Bragg reflective layer, the through-hole of the Bragg reflective layer and the through-hole of the first insulating layer;

[0076] In this embodiment, the specific process for preparing the metal reflective layer 15 is as follows:

[0077] Photoresist is applied to the Bragg reflective layer 14, the vias of the Bragg reflective layer, the vias of the first insulating layer, and the exposed areas of the vias of the first insulating layer. Then, exposure and development are used to remove part of the photoresist. Then, Ag metal, Ni metal, Ti metal, Ni metal, Ti metal, Ni metal, Ti metal, Ni metal, and Ti metal are sequentially deposited using an electron beam evaporation process to form the metal reflective layer 15. Then, the metal on top of the photoresist is removed using a blue film stripping process, and then the photoresist is removed.

[0078] S8. A second insulating layer 16 and a second insulating layer through-hole are prepared in the metal reflective layer 15 and the area not covered by the metal reflective layer 15.

[0079] In this embodiment, the specific process for preparing the second insulating layer 16 and the through-hole in the second insulating layer is as follows:

[0080] Al2O3 is deposited on the surface of the metal reflective layer 15 and the area not covered by the metal reflective layer 15 using atomic layer deposition technology. The temperature of the atomic layer deposition process is controlled at 200±10℃. Then, SiO2 is deposited on the Al2O3 surface using plasma chemical vapor deposition technology. The temperature of the plasma chemical vapor deposition process is controlled at 270±10℃. The stack of Al2O3 and SiO2 serves as the second insulating layer 16. Then, photoresist is coated on the surface of the second insulating layer 16. Then, exposure and development are performed to remove part of the photoresist, exposing part of the second insulating layer. Then, inductively coupled plasma etching is used to remove the exposed part of the second insulating layer, forming a via in the second insulating layer. Finally, the photoresist is removed.

[0081] S9. A connecting metal layer 17 is prepared on the second insulating layer 16 and the through-hole of the second insulating layer;

[0082] In this embodiment, the specific process for preparing the connecting metal layer 17 is as follows:

[0083] Photoresist is coated onto the second insulating layer 16 and the surface of the through-holes in the second insulating layer. Then, exposure and development are performed to remove some of the photoresist. Finally, an electron beam evaporation process is used to deposit a layer with a thickness greater than [missing information]. Metal Al is used as the reflective layer 171. Then, the protective layer 172 is deposited on the reflective layer 171 using an electron beam evaporation process. The stack of the reflective layer 171 and the protective layer 172 serves as the connecting metal layer 17. Then, the metal located on the photoresist is removed using a blue film stripping process, and then the photoresist is removed.

[0084] In this embodiment, the specific process for vapor-depositing the protective layer 172 is as follows:

[0085] Electron beam evaporation is used to deposit a thickness greater than [missing information] on the reflective layer 171. Metallic Cr is used as the first protective master layer 1721. Metallic Ni is deposited on the first protective master layer 1721 using electron beam evaporation as the first protective sublayer. Metallic Cr is then deposited on the first protective sublayer using electron beam evaporation as the second protective sublayer. This process of preparing the first and second protective sublayers N times is repeated to form the second protective master layer 1722. Finally, a layer with a thickness between [missing information] is deposited on the second protective master layer 1722 using electron beam evaporation. The metal Ni between them serves as the third protective parent layer 1723, and the stack of the first protective parent layer 1721, the second protective parent layer 1722, and the third protective parent layer 1723 serves as the protective layer 172.

[0086] Furthermore, the thickness of the first protective sub-layer increases linearly toward the third insulating layer. The thickness of the second protective sublayer decreases linearly toward the third insulating layer.

[0087] Specifically, in this embodiment, the first protective mother layer 1721 has a thickness of The metal Cr, in the second protective parent layer 1722, has a period n of 3 for both the first and second protective sublayers, and the thickness of the first protective sublayer increases linearly toward the third insulating layer. The thickness of the second protective sublayer decreases linearly toward the third insulating layer. The thickness of the first protective sublayer from bottom to top is as follows: as well as The thickness of the second protective sublayer from bottom to top is as follows: as well as The third protective layer 1723 has a thickness of Ni metal.

[0088] S10. A third insulating layer and a through-hole in the third insulating layer are formed on the connecting metal layer 17 and the second insulating layer 16 not covered by the connecting metal layer 17.

[0089] Furthermore, in step S10, the steps of preparing the third insulating layer and the through-hole in the third insulating layer include:

[0090] SiO2 is deposited as a third insulating layer 18 on the connecting metal layer 17 and the second insulating layer 16 not covered by the connecting metal layer 17 using a PECVD process. The temperature is controlled at 270±10℃ during the PECVD process. Then, photoresist is coated on the third insulating layer 18, and then exposed and developed to remove part of the photoresist, exposing part of the third insulating layer. Then, the exposed part of the third insulating layer is removed using BOE etching solution to form a via in the third insulating layer.

[0091] S11. Prepare a pad layer 19 on the through-hole of the third insulating layer;

[0092] Furthermore, in S11, the step of preparing the pad layer 19 includes:

[0093] Al metal, Ti metal, Al metal, Ti metal, Ni metal, Ti metal, Ni metal, Ti metal, Ni metal, Ti metal, Ni metal and AuSn metal are sequentially deposited on the through-hole of the third insulating layer as pad layer 19 using electron beam evaporation process. Then, the metal on the photoresist is removed using blue film stripping process, and finally the photoresist is removed.

[0094] The connecting metal layer 17 includes a reflective layer 171 and a protective layer 172 arranged sequentially from bottom to top. The protective layer 172 includes a first protective parent layer 1721, a second protective parent layer 1722 and a third protective parent layer 1723 arranged sequentially from bottom to top. The second protective parent layer 1722 includes n periodically stacked first protective sub-layers and second protective sub-layers.

[0095] The thickness of the first protective sublayer gradually increases linearly toward the third insulating layer, and the thickness of the second protective sublayer gradually decreases linearly toward the third insulating layer.

[0096] Comparative Example 1

[0097] A flip-chip light-emitting diode (LED) differs from the flip-chip light-emitting diode prepared in Example 2 in that:

[0098] The thickness of the first protective sublayer increases linearly toward the third insulating layer. The thickness of the second protective sublayer decreases linearly toward the third insulating layer. The thickness of the first protective sublayer from bottom to top is as follows: as well as The thickness of the second protective sublayer from bottom to top is as follows: as well as

[0099] Comparative Example 2

[0100] A flip-chip light-emitting diode (LED) differs from the flip-chip light-emitting diode prepared in Example 2 in that:

[0101] The first protective layer has a thickness of [missing information]. The metal Cr, the third protective matrix is ​​of thickness Ni metal.

[0102] Comparative Example 3

[0103] A flip-chip light-emitting diode (LED) differs from the flip-chip light-emitting diode prepared in Example 2 in that:

[0104] The first protective layer has a thickness of [missing information]. The thickness of the first protective sublayer of the metallic Cr increases linearly towards the third insulating layer. The thickness of the second protective sublayer decreases linearly toward the third insulating layer. The thickness of the first protective sublayer from bottom to top is as follows: as well as The thickness of the second protective sublayer from bottom to top is as follows: as well as The third protective layer has a thickness of [missing information]. Ni metal.

[0105] Comparative Example 4

[0106] A flip-chip light-emitting diode (LED) differs from the flip-chip light-emitting diode prepared in Example 2 in that:

[0107] The protective layer does not contain a second protective parent layer; the first protective parent layer has a thickness of [missing information]. The metallic Ti, with a third protective matrix layer of thickness Metal Pt.

[0108] Comparative Example 5

[0109] A flip-chip light-emitting diode (LED) differs from the flip-chip light-emitting diode prepared in Example 2 in that:

[0110] The protective layer does not include the second and third protective layers; the first protective layer has a thickness of [missing information]. Metal Pt.

[0111] Based on the flip-chip LED prepared in Example 2 and the flip-chip LEDs in Comparative Examples 1 to 5, the ESD yield of the flip-chip LED prepared in Example 2 and the flip-chip LEDs in Comparative Examples 1 to 5 were compared. The corresponding test results are shown in the table below:

[0112] It should be noted that, in order to ensure the reliability of the verification results, when comparing the ESD yield of the flip-chip LED prepared in Example 2 of the present invention and the flip-chip LED chips in Comparative Examples 1 to 5, all other processes and parameters should be kept consistent except for the parameters mentioned above.

[0113] As can be seen from the table above, the flip-chip LED prepared in Example 2 of the present invention and the flip-chip LED provided by Comparative Examples 1 to 3 have significantly improved ESD yield compared with the flip-chip LED provided by Comparative Examples 4 and 5.

[0114] In summary, the flip-chip LED and its fabrication method in the above embodiments of the present invention, by setting the connecting metal layer as a reflective layer and a protective layer from bottom to top, and by setting the protective layer as a first protective mother layer, a second protective mother layer and a third protective mother layer from bottom to top, can protect the reflective layer of the connecting electrode through the protective layer, effectively preventing the etchant from corroding the reflective layer of the connecting electrode when the third insulating layer is fabricated using a wet etching process. Moreover, this setting allows the pad layer to be fabricated with the third insulating layer through the through-hole in one photolithography process, eliminating the need for a separate photolithography process on the opening area of ​​the third insulating layer, thus reducing the fabrication cost of the flip-chip LED.

[0115] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0116] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A flip-chip light-emitting diode, characterized in that, include: The substrate and the N-type semiconductor layer, active light-emitting layer, P-type semiconductor layer, current spreading layer, first insulating layer, Bragg reflector layer, metal reflector layer, second insulating layer, connecting metal layer, third insulating layer and pad layer are sequentially deposited on the substrate. The connecting metal layer includes a reflective layer and a protective layer arranged sequentially from bottom to top. The protective layer includes a first protective parent layer, a second protective parent layer and a third protective parent layer arranged sequentially from bottom to top. The second protective parent layer includes n periodically stacked first protective sub-layers and second protective sub-layers. The thickness of the first protective sublayer gradually increases linearly toward the third insulating layer, and the thickness of the second protective sublayer gradually decreases linearly toward the third insulating layer.

2. The flip-chip LED according to claim 1, characterized in that, The reflective layer is made of metal Al, and its thickness is greater than [missing information].

3. The flip-chip LED according to claim 1, characterized in that, The first protective matrix is ​​made of metallic Cr, and its thickness is greater than [missing information].

4. The flip-chip LED according to claim 1, characterized in that, The period n of the second protective parent layer is ≥3.

5. The flip-chip LED according to claim 1, characterized in that, The first protective sublayer is made of metallic Ni, and its thickness increases linearly toward the third insulating layer.

6. The flip-chip LED according to claim 1, characterized in that, The second protective sublayer is made of metallic Cr, and its thickness decreases linearly toward the third insulating layer.

7. The flip-chip LED according to claim 1, characterized in that, The third protective matrix is ​​made of metallic Ni, and its thickness is between [missing information]. between.

8. A method for fabricating a flip-chip light-emitting diode, characterized in that, The preparation method includes the following steps: S1. A substrate is provided, and an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer are sequentially deposited on the substrate; S2. An N-type semiconductor conductive step is prepared on the P-type semiconductor layer; S3. A current spreading layer is prepared on the P-type semiconductor layer and the N-type semiconductor conductive step; S4. Prepare a first insulating layer on the current spreading layer; S5. A Bragg reflector layer and a via in the Bragg reflector layer are prepared on the first insulating layer; S6. A first insulating layer through-hole is formed on the Bragg reflector layer, the Bragg reflector layer through-hole, and the first insulating layer; S7. A metal reflective layer is prepared on the Bragg reflective layer, the through-hole of the Bragg reflective layer, and the through-hole of the first insulating layer; S8. A second insulating layer and a second insulating layer through-hole are prepared in the metal reflective layer and the area not covered by the metal reflective layer. S9. A connecting metal layer is prepared on the second insulating layer and the through-hole of the second insulating layer; S10. A third insulating layer and a through-hole in the third insulating layer are prepared on the connecting metal layer and the second insulating layer not covered by the connecting metal layer. S11. Prepare a pad layer on the through-hole of the third insulating layer; The connecting metal layer includes a reflective layer and a protective layer arranged sequentially from bottom to top. The protective layer includes a first protective parent layer, a second protective parent layer and a third protective parent layer arranged sequentially from bottom to top. The second protective parent layer includes n periodically stacked first protective sub-layers and second protective sub-layers. The thickness of the first protective sub-layer gradually increases linearly toward the third insulating layer. The thickness of the second protective sublayer gradually decreases linearly toward the third insulating layer.

9. The method for fabricating a flip-chip light-emitting diode according to claim 8, characterized in that, In step S10, the steps of preparing the third insulating layer and the through-hole in the third insulating layer include: SiO2 is deposited as a third insulating layer using PECVD process on the connecting metal layer and the second insulating layer not covered by the connecting metal layer. Then, photoresist is coated on the third insulating layer, and then exposed and developed to remove part of the photoresist, exposing part of the third insulating layer. Then, the exposed part of the third insulating layer is removed using BOE etching solution to form a via in the third insulating layer.

10. The method for fabricating a flip-chip light-emitting diode according to claim 8, characterized in that, In step S11, the step of preparing the pad layer includes: On the via of the third insulating layer, Al metal, Ti metal, Al metal, Ti metal, Ni metal, Ti metal, Ni metal, Ti metal, Ni metal, Ni metal and AuSn metal are sequentially deposited as pad layers using an electron beam evaporation process. Then, the metal on top of the photoresist is removed using a blue film stripping process, and finally the photoresist is removed.

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