Drive circuit, display device, and driving method

Abstract

Embodiments of the present application relate to the technical field of display, and provide a drive circuit, a display device, and a driving method, used for mitigating the problem of internal voltage changes in gate driver on array (GOA) circuits, and improving the display effect of a display. The specific solution comprises: the drive circuit comprises a plurality of GOA circuits, and each GOA circuit comprises a register circuit, an output circuit, a frequency control circuit, and a reset circuit. The output circuit is coupled to the register circuit, and is configured to generate a gate scanning signal in response to a voltage of a pull-up node and a voltage of a pull-down node of the register circuit, and output the gate scanning signal to a pixel circuit corresponding to the GOA circuit. The frequency control circuit is coupled to the output circuit at a first node, and is configured to receive a first frequency control signal to control the frequency of the gate scanning signal. The reset circuit is coupled to the output circuit at the first node, and is configured to control a voltage of the first node on the basis of a reset signal. The embodiments of the present application are used for the process in which the drive circuit sends gate scanning signals to pixel circuits.

Description

Drive circuit, display device and driving method

[0001] This application claims priority to Chinese Patent Application No. 202411046493.2, filed with the State Intellectual Property Office of China on July 31, 2024, entitled "Driving Circuit, Display Device and Driving Method", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and in particular to a driving circuit, display device, and driving method. Background Technology

[0003] Currently, to enhance the user's video or gaming experience, organic light-emitting diode (OLED) displays require very high refresh rates (e.g., 120 Hz). High refresh rates lead to high power consumption and reduced battery life. To reduce power consumption and improve battery life, existing OLED displays utilize low-temperature polycrystalline oxide (LTPO) technology. This involves using a higher refresh rate in video or gaming scenarios and a lower refresh rate (e.g., 1 Hz) for static images, effectively saving power.

[0004] The gate-driven on array (GOA) circuit controls the refresh rate of the display. By adding a frequency control circuit to the GOA circuit, the refresh rate of a local display area can be reduced. When the GOA circuit enables the local refresh rate reduction function, the voltage changes inside the GOA circuit will affect the display effect. Summary of the Invention

[0005] This application provides a driving circuit, a display device, and a driving method, which improves the problem of voltage variation inside the GOA circuit and enhances the display effect of the display.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions.

[0007] In a first aspect, embodiments of this application provide a driving circuit including multiple array driving scan (GOA) circuits. Each GOA circuit includes a register circuit, an output circuit, a frequency control circuit, and a reset circuit. The output circuit and the register circuit are coupled and configured to generate a gate scan signal in response to the voltages of the pull-up and pull-down nodes of the register circuit, and output the gate scan signal to the corresponding pixel circuit of the GOA circuit. The frequency control circuit and the output circuit are coupled to a first node and configured to receive a first frequency control signal to control the frequency of the gate scan signal. The reset circuit and the output circuit are coupled to the first node and configured to control the voltage of the first node based on a reset signal.

[0008] Therefore, in the driving circuit provided in this application embodiment, when the GOA circuit enables the local refresh rate reduction function, the first node and the first frequency control signal are turned on. At this time, the voltage of the first node is different, that is, it may be positive or negative. The driving circuit can control the voltage of the first node through the reset circuit to maintain the voltage of the first node at the same value, which can avoid the impact of voltage changes of the first node on the display effect of the display, improve the stability of the GOA circuit, and improve the display effect of the display.

[0009] In one possible design, the reset circuit includes a first transistor, with a first terminal coupled to a first node and a second terminal coupled to a first voltage source. The gate of the first transistor is used to receive a reset signal. Specifically, the reset circuit is configured to control the voltage of the first node by means of the voltage output from the first voltage source when the reset signal controls the first transistor to turn on. Thus, the reset circuit can control the voltage of the first node by means of the voltage output from the first voltage source, maintaining the voltage of the first node at a constant value. This avoids the impact of voltage fluctuations at the first node on the display's performance, improving the stability of the GOA circuit and enhancing the display's overall performance.

[0010] In one possible design, the reset circuit further includes a second transistor. The first terminal of the second transistor is coupled to the first terminal of the first transistor, the second terminal of the second transistor is coupled to the first node, and the gate of the second transistor is coupled to the gate of the first transistor. Therefore, adding a second transistor between the first node and the first transistor reduces the voltage across the first and second terminals of the first transistor, improving the reliability of the GOA circuit. Furthermore, employing a common-gate structure for both the first and second transistors further enhances transistor reliability.

[0011] In one possible design, the frequency control circuit includes a third transistor, with a first terminal coupled to a register circuit and a second terminal coupled to an output circuit. The gate of the third transistor is used to receive a second frequency control signal. The frequency control circuit is also configured to receive both the first and second frequency control signals to control the frequency of the gate scan signal. Thus, by jointly controlling the frequency of the gate scan signal with the first and second frequency control signals, the GOA circuit can reduce the frequency of the clock signal during low-frequency drive, further reducing the power consumption of the drive circuit.

[0012] In one possible design, the output circuit further includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a first capacitor. The gate and register circuitry of the fourth transistor are coupled to a pull-up node; the first terminal of the fourth transistor is coupled to a high-voltage gate source; the second terminal of the fourth transistor is coupled to the first terminal of the fifth transistor; the second terminal of the fifth transistor is coupled to a low-voltage gate source; and the gate and register circuitry of the fifth transistor are coupled to a pull-down node. The pull-up node is also coupled to the first terminal of the sixth transistor; the gate of the sixth transistor is coupled to the first node; the second terminal of the sixth transistor is coupled to the gate of the seventh transistor; the first terminal of the seventh transistor is coupled to a high-voltage gate source; the second terminal of the seventh transistor is coupled to the first terminal of the eighth transistor; the second terminal of the eighth transistor is coupled to a low-voltage gate source; and the gate of the eighth transistor is coupled to the pull-down node. The first terminal of the first capacitor is coupled to the gate of the sixth transistor; and the second terminal of the first capacitor is coupled to the second terminal of the sixth transistor.

[0013] In one possible design, the output circuit also includes a ninth transistor. The first and second terminals of the ninth transistor are both coupled to the first terminal of the fifth transistor, and the gate of the ninth transistor is coupled to a pull-down node. Thus, the output circuit can reduce the rising edge step of the cascaded signal through the capacitive coupling effect of the ninth transistor, optimizing the quality of the cascaded signal.

[0014] In one possible design, the output circuit also includes a tenth transistor. The first terminal of the tenth transistor is coupled to the pull-down node, the second terminal of the tenth transistor is coupled to the gate of the eighth transistor, and the gate of the tenth transistor is coupled to the first node. Thus, the tenth transistor can prevent the eighth transistor from accidentally turning on, improving the stability of the GOA circuit.

[0015] In one possible design, the output circuit also includes an eleventh transistor. The first terminal of the eleventh transistor is coupled to a high-voltage gate source, the second terminal of the eleventh transistor is coupled to the second terminal of the sixth transistor, and the gate of the eleventh transistor is coupled to the gate of the eighth transistor. Thus, the voltage drop of the gate scan signal can be accelerated through the eleventh transistor.

[0016] Secondly, embodiments of this application provide a display device, which includes a pixel array, a peripheral driving circuit, and a plurality of cascaded driving circuits. The peripheral driving circuit includes at least one gate high-voltage source, and the at least one gate high-voltage source is coupled to a plurality of gate high-voltage signal lines. Adjacent driving circuits in the plurality of cascaded driving circuits are respectively coupled to different gate high-voltage signal lines.

[0017] Therefore, in the display device provided in this application embodiment, coupling the gate high voltage source with multiple gate high voltage signal lines can further reduce the resistance of the gate high voltage signal lines and optimize signal quality. Furthermore, by coupling adjacent driving circuits with different gate high voltage signal lines respectively, voltage disturbances between adjacent rows of the gate high voltage can be reduced.

[0018] In one possible design, the peripheral driving circuit further includes a level conversion circuit, and at least one gate high voltage source includes a first gate high voltage source and a second gate high voltage source. The output circuits of multiple cascaded driving circuits are coupled to the first gate high voltage source, and the register circuits and level conversion circuits of the multiple cascaded driving circuits are coupled to the second gate high voltage source. Therefore, by providing a gate high voltage only to the output circuits of the driving circuits through the first gate high voltage source, and by boosting the gate high voltage source to other circuits through the second gate high voltage source, the stability of the gate scan signal output by the output circuit can be improved, and signal disturbances can be reduced.

[0019] In one possible design, the drive current of the first gate high-voltage source is greater than that of the second gate high-voltage source. Therefore, the first gate high-voltage source can provide a larger drive current to the output circuit, ensuring the stability of the gate scan signal output by the output circuit and reducing signal disturbances.

[0020] In one possible design, at least one gate high voltage source includes a first gate high voltage source and a second gate high voltage source. The first transistor in the output circuit of an adjacent driving circuit is coupled to the gate high voltage signal line of the first gate high voltage source, and other transistors in the output circuit of an adjacent driving circuit are coupled to the gate high voltage signal line of the second gate high voltage source. This improves the stability of the gate scan signal output by the output circuit and reduces signal disturbances.

[0021] In one possible design, the output of the first gate high-voltage source is coupled to multiple parallel-connected voltage-regulating capacitors.

[0022] In one possible design, the first signal line of each output circuit is coupled to the corresponding gate high-voltage signal line, and the length of the first signal line is such that each first signal line overlaps with multiple gate high-voltage signal lines. Thus, the impedances of the multiple first signal lines are the same, eliminating differences in gate high voltage.

[0023] In one possible design, the gate high voltage signal line of the first gate high voltage source includes at least two metal layers connected through at least one via. This reduces the impedance on the gate high voltage signal line of the first gate high voltage source.

[0024] Thirdly, embodiments of this application provide a driving method applied to a driving circuit. The driving circuit includes multiple Gate Object Array (GOA) circuits. Each GOA circuit includes a register circuit, an output circuit, a frequency control circuit, and a reset circuit. The frequency control circuit, output circuit, and reset circuit are coupled to a first node. The driving method includes: the output circuit generating a gate scan signal in response to the voltages of the pull-up and pull-down nodes of the register circuit, and outputting the gate scan signal to the pixel circuit corresponding to the GOA circuit; the frequency control circuit receiving a first frequency control signal to control the frequency of the gate scan signal; and the reset circuit controlling the voltage of the first node based on a reset signal.

[0025] In one possible design, the frequency control circuit receives a first frequency control signal to control the frequency of the gate scan signal, including: the frequency control circuit receives a first frequency control signal and a second frequency control signal to control the frequency of the gate scan signal.

[0026] Fourthly, embodiments of this application provide a display device, which includes a processor and a driving circuit as described in the first aspect, wherein the driving circuit and the processor are coupled.

[0027] Fifthly, embodiments of this application provide a computer-readable storage medium including computer instructions that, when executed on an electronic device, cause the electronic device to perform the driving method in any possible implementation of the third aspect described above.

[0028] Sixthly, embodiments of this application provide a computer program product that, when run on a computer or processor, causes the computer or processor to execute the display driving method in any possible implementation of the third aspect described above.

[0029] It is understood that any of the driving circuits, display devices, display equipment, computer-readable storage media or computer program products provided above can be applied to the corresponding methods provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding methods, and will not be repeated here.

[0030] These or other aspects of this application will become more readily apparent in the following description. Attached Figure Description

[0031] Figure 1 is a structural diagram of a display device provided in an embodiment of this application;

[0032] Figure 2 is a structural diagram of a pixel circuit provided in an embodiment of this application;

[0033] Figure 3 is a timing diagram of a pixel circuit provided in an embodiment of this application;

[0034] Figure 4 is a structural diagram of a gate driving circuit provided in an embodiment of this application;

[0035] Figure 5 is a timing diagram of the gate scan signal of a gate driving circuit provided in an embodiment of this application;

[0036] Figure 6 is a structural diagram of a peripheral driving circuit provided in an embodiment of this application;

[0037] Figure 7 is a structural diagram of a multi-level GOA circuit provided in an embodiment of this application;

[0038] Figure 8 is a timing diagram of a multi-stage GOA circuit provided in an embodiment of this application;

[0039] Figure 9 is a timing diagram of another multi-stage GOA circuit provided in an embodiment of this application;

[0040] Figure 10 is a schematic diagram of the partitioning of a display panel provided in an embodiment of this application;

[0041] Figure 11 is a timing diagram of a driving circuit provided in an embodiment of this application at different refresh cycles;

[0042] Figure 12 is a voltage variation diagram of an N1 node provided in an embodiment of this application;

[0043] Figure 13 is a waveform diagram of a signal provided in an embodiment of this application;

[0044] Figure 14 is a structural diagram of a driving circuit provided in an embodiment of this application;

[0045] Figure 15 is a timing diagram of a driving circuit provided in an embodiment of this application;

[0046] Figure 16 is a structural diagram of another driving circuit provided in an embodiment of this application;

[0047] Figure 17 is a structural diagram of another driving circuit provided in an embodiment of this application;

[0048] Figure 18 is a structural diagram of another driving circuit provided in an embodiment of this application;

[0049] Figure 19 is a structural diagram of another driving circuit provided in an embodiment of this application;

[0050] Figure 20 is a structural diagram of another driving circuit provided in an embodiment of this application;

[0051] Figure 21 is a timing diagram of another driving circuit provided in an embodiment of this application;

[0052] Figure 22 is a waveform diagram of a gate scan signal provided in an embodiment of this application;

[0053] Figure 23 is a structural diagram of another display device provided in an embodiment of this application;

[0054] Figure 24 is a structural diagram of another display device provided in an embodiment of this application;

[0055] Figure 25 is a structural diagram of another display device provided in an embodiment of this application;

[0056] Figure 26 is a structural diagram of another display device provided in an embodiment of this application;

[0057] Figure 27 is a schematic diagram of a gate high voltage signal line provided in an embodiment of this application;

[0058] Figure 28 is a flowchart of a driving method provided in an embodiment of this application;

[0059] Figure 29 is a timing diagram of another driving circuit provided in an embodiment of this application;

[0060] Figure 30 is a timing diagram of another driving circuit provided in an embodiment of this application;

[0061] Figure 31 is a timing diagram of another driving circuit provided in an embodiment of this application;

[0062] Figure 32 is a timing diagram of another driving circuit provided in an embodiment of this application. Detailed Implementation

[0063] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B; "and / or" in this text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the description of the embodiments of this application, "multiple" refers to two or more than two.

[0064] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this embodiment, unless otherwise stated, "a plurality of" means two or more.

[0065] The embodiments of this application use terms such as "first" and "second" to distinguish objects with similar names, functions, or effects. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or order of execution. The term "coupling" is used to indicate an electrical connection, including direct connection via wires or terminals or indirect connection via other devices. Therefore, "coupling" should be considered as a broad type of electronic communication connection.

[0066] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0067] In the circuits provided in the embodiments of this disclosure, the first node, the second node, and the third node do not represent actual existing components, but rather represent the junctions of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junctions of related electrical connections in the circuit diagram.

[0068] In the embodiments of this application, the transistor can be a thin-film transistor (TFT), such as hydrogenated amorphous silicon (a-Si:H) TFT, low-temperature polysilicon (LTPS) TFT, and amorphous oxide semiconductor (AOS) TFT. Transistors are classified into two types: N-type (negative) transistors and P-type (positive) transistors. A transistor includes a source, a drain, and a gate. The transistor's conduction or cutoff can be controlled by controlling the voltage input to the gate. When the transistor is on, the source and drain conduct, generating a conduction current. Furthermore, the magnitude of the conduction current generated between the source and drain varies depending on the gate voltage. When the transistor is off, the source and drain do not conduct, generating only a very small off-state current. In the embodiments of this application, the source of the transistor is referred to as the first terminal, and the drain as the second terminal; or, the drain is referred to as the first terminal, and the source as the second terminal. Furthermore, an N-type transistor conducts when its gate is at a high level, with both its first and second terminals conducting, generating a current between them. When its gate is at a low level, the N-type transistor is cut off, with neither its first nor second terminals conducting, generating only a very small off-state current. A P-type transistor conducts when its gate is at a low level, with both its first and second terminals conducting, generating a current. When its gate is at a high level, the P-type transistor is cut off, with neither its first nor second terminals conducting, generating only a very small off-state current.

[0069] The technical solutions provided in this application can be applied to various electronic devices including display devices. These electronic devices include, for example, consumer electronics, home electronics, automotive electronics, and financial electronic devices with display functions. Consumer electronics include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, and drones. Home electronics include smart door locks, televisions, remote controls, refrigerators, and rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners). Automotive electronic devices include car navigation systems and in-vehicle high-density digital video discs (DVDs). Financial electronic devices include automated teller machines (ATMs) and self-service electronic devices. This application does not impose any special limitations on the specific form of the aforementioned electronic devices.

[0070] To facilitate understanding, the specific structure of the display device will be introduced below.

[0071] As shown in Figure 1, Figure 1 is a structural diagram of a display device provided in an embodiment of this application. The display device 10 may include an active display area (AA) 100, a non-active display area (NA) 200, a data control circuit 300, and a peripheral driving circuit 400. The active display area 100 and the non-active display area 200 together form a display panel 11. The active display area 100 is the pixel light-emitting area, and the non-active display area 200 is the area within the display panel 11 that does not emit light. The data control circuit 300 receives external image information and provides data signals (DS) to the display panel 11. The data signals are digital signals that determine the pixel light-emitting current in the pixel circuit programming. The peripheral driving circuit 400 provides multiple sets of control signals (CS) and multiple pixel voltages (PV) required by the display panel.

[0072] Specifically, the effective display area 100 may include multiple pixels arranged in an array (i.e., a pixel array), multiple data lines, and multiple gate scan lines. Each data line is coupled to multiple pixels along the Y direction, each gate scan line is coupled to multiple pixels along the X direction, and each pixel is coupled to the data lines, gate scan lines, power supply voltage lines (positive power supply voltage (ELVDD) and negative power supply voltage (ELVSS)) and initialization voltage (VINI) lines. A pixel can be understood as a pixel circuit, which may include light-emitting diodes (LEDs) and circuit units for controlling the LEDs. The LEDs may be OLEDs, quantum dot light-emitting diodes (QLEDs), mini LEDs, or micro LEDs. The circuit units, by executing specific pixel circuit timing, can control the current value from the positive power supply voltage (ELVDD) to the negative power supply voltage (ELVSS), allowing the LEDs to emit light of a specific brightness at a specific current value.

[0073] The inactive display area 200 is located on one or both sides of the active display area 100 and may include multiple gate driving circuits. Since the inactive display area 200 uses GOA (Gate of Area) technology, the gate driving circuit is also called a GOA circuit. After receiving the control signal, the GOA circuit can generate multiple shift pulse signals output line by line, i.e., multiple gate scan signals. Each gate signal line (GL) is coupled to one or more rows of pixel circuits. The gate scan signals are output line by line, controlling the thin-film transistors (TFTs) in the pixel circuits to turn on or off line by line. Referring again to Figure 1, the inactive display area 200 may include k gate driving circuits, namely the first gate driving circuit, the second gate driving circuit, the third gate driving circuit, ..., the kth gate driving circuit. Each gate driving circuit outputs a gate scan signal that controls multiple rows of pixel circuits. The gate scan signals that control the first row of pixel circuits are, for example, S1_1, S2_1, S3_1, ..., Sk_1, and the gate scan signals that control the nth row of pixel circuits are, for example, S1_n, S2_n, S3_n, ..., Sk_n.

[0074] The data control circuit 300 provides multiple sets of data signals. The data control circuit 300 transmits these data signals to the pixel circuits within the display panel 11 via multiple data lines, enabling the pixel circuits to function properly. The number of data lines can be the same as the total number of columns in the pixel array formed by the pixel circuits.

[0075] The peripheral driving circuit 400 provides multiple sets of control signals, which may include a start voltage signal (STV), a clock signal (CLK), a gate high-level voltage (VGH), and a gate low-level voltage (VGL). Upon receiving the control signals, the gate driving circuit generates corresponding high and low level gate scan signals. Additionally, the peripheral driving circuit 400 also provides multiple sets of pixel voltages, which may include power supply voltages (VDD and VSS) and initialization voltages. The peripheral driving circuit 400 transmits the pixel voltage values ​​to the pixel circuits in the display panel 11 via multiple signal lines, enabling the pixel circuits to function properly.

[0076] After loading the drive timing and voltage settings, the display panel can configure the brightness and refresh rate of the pixel circuits. The drive timing is a set of gate control signals, including multiple signal waveforms whose voltage changes over time. The refresh rate is the number of times the display panel can refresh per second. Each time the display panel refreshes, data voltage needs to be written from the first row of pixel circuits to the last row. Limited by the data voltage writing speed, the display panel has a maximum refresh rate N, meaning it only refreshes N frames per second, with one frame taking 1 / N seconds. At the maximum refresh rate, the pixel circuits always operate within the data refresh cycle, containing N refresh frames per second. A refresh frame is the time for a data voltage update, and within each refresh frame, the display panel's pixel circuits execute the refresh frame drive timing. Taking a maximum refresh rate of 120Hz as an example, the display panel refreshes 120 times per second. Assuming the period time for one refresh is T, then T = 1 / 120s, approximately 8.333ms. At low refresh rates, such as 1Hz, the display panel refreshes once per second, including one refresh frame and 119 hold frames, with each frame lasting 8.333ms. Assuming the effective display area of ​​the display panel has M rows of pixels, the charging time or refresh time H of one row of pixels satisfies the following relationship: H = T / M. Assuming M = 2844 and T = 8.333ms, then H = 8.333 / 2844ms, approximately 2.93µs. The 1H time can be flexibly set according to the number of display rows, refresh rate, and vertical blanking time, etc. This embodiment does not limit the specific length of the 1H time.

[0077] Based on the display device shown in Figure 1, the pixel circuit, gate driving circuit, and peripheral driving circuit will be further described below.

[0078] The pixel circuit can employ LTPO technology, as shown in Figure 2(a). The pixel circuit may include a first transistor T1, a second transistor T2, a driving transistor Td, a capacitor C1, a light-emitting diode D1, a first driving circuit module, a second driving circuit module, and a third driving circuit module. The first transistor T1 is an N-type transistor and can be indium gallium zinc oxide (IGZO). The second transistor T2 is a P-type transistor and can be low-temperature polysilicon (LTPS). The gate scan signal for the first transistor T1 is S1, and the gate scan signal for the second transistor T2 is S2.

[0079] In one possible example, as shown in Figure 2(b), the first driving circuit module may include a fifth transistor T5 and a sixth transistor T6, the second driving circuit module includes a third transistor T3 and a seventh transistor T7, and the third driving circuit module includes a fourth transistor T4. This pixel circuit can also be referred to as an 8T1C circuit, wherein the gate scan signal of the third transistor T3 is S3, the gate scan signal of the fourth transistor T4 is S4, the gate scan signal of the fifth transistor T5 is S5, and the gate scan signals of the sixth transistor T6 and the seventh transistor T7 are emission signals (EM). One end of the third transistor T3 is used to input a first initialization voltage (VINI1), one end of the fourth transistor T4 is used to input a second initialization voltage (VINI2), one end of the fifth transistor T5 is used to input a third initialization voltage (VINI3), and one end of the second transistor T2 is used to input a data signal (DATA). It is understood that the pixel circuit structure can also be in other forms, such as 6T1C, 7T1C, 9T2C, and 9T3C, etc. This application embodiment does not limit the specific structure of the pixel circuit.

[0080] The switching of transistors within the pixel circuit is determined by the gate scan signal. Figure 3 shows the timing diagrams of S1 and S2 in the j-th and j+1-th refresh cycles. S1 is a positive waveform of a certain length during the non-light-emitting period, with a duration of any value such as 2H or 6H. S2 is a negative waveform of a certain length during the non-light-emitting period, with a duration of any value such as 1H, 2H, or 0.7H. To ensure sufficient data signal is written to the gate of the driving transistor, the pulse width of S1 is longer than that of S2. That is, the first transistor T1 turns on earlier and turns off later than the second transistor T2.

[0081] The gate driving circuit may include multiple levels of circuit units, as shown in Figure 4, which is a structural diagram of a gate driving circuit provided in an embodiment of this application. Figure 4 shows n levels of circuit units, namely circuit unit 1, circuit unit 2, circuit unit 3, ..., circuit unit n. Circuit unit 1 outputs a gate scan signal out_1, circuit unit 2 outputs a gate scan signal out_2, circuit unit 3 outputs a gate scan signal out_3, and circuit unit n outputs a gate scan signal out_n. out_1 to out_n correspond to the first row of pixel circuits to the nth row of pixel circuits, respectively. That is, one row of gate scan signals can control one row of pixel circuits. Furthermore, one row of gate scan signals can also control two rows of pixel circuits. For example, gate scan signal out_1 can correspond to the first row of pixel circuits and the second row of pixel circuits, gate scan signal out_2 can correspond to the third row of pixel circuits and the fourth row of pixel circuits, and so on. Gate scan signal out_n can correspond to the (2n-1)th row of pixel circuits and the 2nth row of pixel circuits.

[0082] Referring again to Figure 4, after receiving the start frame signal (STV), first clock signal (CLK_1), second clock signal (CLK_2), gate high voltage (VGH), and gate low voltage (VGL) generated by the peripheral driving circuit, circuit unit 1 generates gate scan signals out_1 to out_n, which are output line by line. Circuit unit 1 is coupled to the start frame signal line, and other circuit units are coupled to the output of the preceding stage circuit unit. The gate scan signal output by the preceding stage circuit unit serves as the start signal for the next stage circuit unit. For example, the input of circuit unit 2 is coupled to the output of circuit unit 1, and the gate scan signal out_1 output by circuit unit 1 serves as the input signal of circuit unit 2. Alternatively, the input of circuit unit 3 is coupled to the output of circuit unit 2, and the gate scan signal out_2 output by circuit unit 2 serves as the input signal of circuit unit 3. In addition, each level of circuit unit is connected to CLK_1 and CLK_2 in a fixed order. For example, circuit unit 1 is connected to CLK_1 and CLK_2; circuit unit 2 is connected to CLK_2 and CLK_1; circuit unit 3 is connected to CLK_1 and CLK_2, etc.

[0083] As shown in Figure 5, which is a timing diagram of the gate scan signal of the gate driving circuit in Figure 4, Figure 5 specifically shows the timing diagram of the start frame signal (STV), the first clock signal (CLK_1), the second clock signal (CLK_2), and the gate scan signals out_1 to out_n. The gate scan signal is a square wave signal switching between high and low voltages. The high voltage value of the gate scan signal is equal to the high voltage value of the gate signal (VGH1), and the low voltage value is equal to the low voltage value of the gate signal (VGL1). The interval between each row of gate scan signals can be 1H, 2H, 4H, or any equal time. The gate driving circuit can output positive voltage pulse waveforms row by row to realize the row-by-row scanning and voltage writing of the AA area pixel circuit.

[0084] The structure of the peripheral driving circuit is shown in Figure 6. The peripheral driving circuit can generate control signals and pixel voltage signals. Specifically, the peripheral driving circuit can include various voltage regulators, such as gate high voltage regulators, gate low voltage regulators, ELVSS voltage regulators, ELVDD voltage regulators, and VINI voltage regulators. The gate high voltage regulator can generate VGH1 and VGH2, the gate low voltage regulator can generate VGL1 and VGL2, and the VINI voltage regulator can generate VINI1, VINI2, ..., VININ. The voltage regulator can be a low-dropout regulator (LDO), a buck-boost converter, or a charge pump, etc. The gate high voltage regulator and the gate low voltage regulator can also be integrated in the same module, such as a power management integrated circuit (PMIC). This embodiment of the application does not limit this.

[0085] In addition, referring to Figure 6, the peripheral driving circuit may also include a digital voltage signal source, which can generate a digital start frame signal (data STV, DSTV) and a digital clock signal (data CLK, DCLK). The peripheral driving circuit may also include a level conversion circuit, which can convert DSTV to STV_1 to STV_N, and DCLK to CLK_1, CLK_2, ..., CLK_N, based on the voltage values ​​of VGH1, VGH2, VGL1, and VGL2. The high voltage value of the converted start frame signal and clock signal can be VGH1 or VGH2, and the low voltage value can be VGL1 or VGL2. When the voltage values ​​of VGH1, VGH2, VGL1, or VGL2 change, the voltage values ​​of STV_1 to STV_N and CLK_1 to CLK_N also change dynamically. Furthermore, the peripheral driving circuit also outputs a control signal to the gate driving circuit, enabling the gate driving circuit to output gate control signals with different high and low voltage values.

[0086] To reduce the driving power consumption of display devices, a zoned frequency control method is proposed. The GOA circuit in this method comprises multiple circuit units, each including a register circuit and an output circuit. Specifically, the output circuit includes a frequency control circuit and a first frequency control signal PS1. When PS1 is low, the GOA circuit outputs a valid pulse signal; when PS1 is high, the GOA circuit does not output a valid pulse signal. By switching the high and low levels of the PS1 waveform at specific times, it is possible to control whether the GOA circuits of certain rows output valid pulse signals within a frame. For example, depending on the user scenario, the refresh rate of the pixel circuits in some rows of the AA area can be selectively lower than the refresh rate of the pixel circuits in other rows, thereby reducing the driving power consumption of the display device.

[0087] Taking the gate scan signal output by the GOA circuit as a positive voltage waveform of a certain length as an example, as shown in Figure 7, Figure 7 shows the (m-1)th level GOA circuit, the mth level GOA circuit, and the (m+1)th level GOA circuit. Each GOA circuit includes a register circuit, an output circuit, and a frequency control circuit. The output circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5. Among them, the gate of the first transistor T1, the first terminal of the third transistor T3, and the register circuit are coupled to the pull-up (PU) node; the gate of the second transistor T2, the first terminal of the fifth transistor T5, and the register circuit are coupled to the pull-down (PD) node; the second terminal of the third transistor and the gate of the fourth transistor T4 are coupled to the buffer pull-up (BPU) node; and the partition control circuit and the gate of the third transistor T3 are coupled to the N1 node.

[0088] Understandably, the first transistor of the (m-1)th stage GOA circuit is denoted as T1_m-1, the first transistor of the m-th stage GOA circuit is denoted as T1_m, and the first transistor of the (m+1)th stage GOA circuit is denoted as T1_m+1. The notation used later is similar and will not be repeated here.

[0089] Taking the m-th stage GOA circuit as an example, register circuit m receives the cascaded signal SR_m-1 output from the previous stage GOA circuit and outputs the cascaded signal SR_m of this stage GOA circuit to register circuit m+1 of the next stage GOA circuit. Register circuit m also outputs pull-up signal PU_m and pull-down signal PD_m. When the partial refresh rate reduction function is disabled, the third transistor T3_m receives PU_m, and the fifth transistor T5_m receives PD_m. The next stage GOA circuit continues to receive SR_m and continues to transmit signals to the next stage GOA circuit, and so on. When the partial refresh rate reduction function is enabled, the gate of the third transistor T3 is used as the input PS1. PS1 controls the third transistor T3 to be turned on or off. For example, if PS1 is high, the third transistor T3 is turned off, and the fourth transistor T4 is also turned off. At this time, the GOA circuit does not output a valid gate scan signal.

[0090] Figure 8 shows a timing diagram of the GOA circuit in Figure 7. Figure 8 illustrates the timing of the nodes and gate scan signals when the m-th stage GOA circuit outputs a valid pulse signal and the (m+1)-th stage GOA circuit does not output a valid pulse signal. That is, S1_m outputs a valid pulse signal, and S1_m+1 does not output a valid pulse signal. Specifically, PS1 switches from low to high when the m-th stage GOA circuit outputs SR_m.

[0091] When the register circuit in the m-th stage GOA circuit generates PU_m, PS1 is low, so the gate of the fourth transistor T4_m (i.e., the BPU node) is written low, and the gate scan signal S1_m is output normally. When the register circuit in the (m+1)-th stage GOA circuit generates PU_m+1, PS1 is switched to high, so the gate of the first transistor T1_m+1 remains high, and the gate scan signal out_m+1 is not output. There can be 120 refresh frames within 1 second. PS1 can control S1_m to output 120 times, while S1_m+1 outputs once, thus enabling different rows of pixels on the display panel to simultaneously have 120Hz and 1Hz.

[0092] Another timing diagram of the GOA circuit in Figure 7 is shown in Figure 9. Figure 9 only shows the timing diagram of the gate scan signals of the (m-1)th, mth, m+1th, and m+2th stage GOA circuits. S1_m+1 can be silent in the first frame but can be output in the second frame. That is, as long as the output frequency of S1_m+1 is lower than the output frequency of S1_m, a lower driving frequency display can be achieved. For example, the upper half of the display panel could be 120Hz, and the lower half could be 60Hz.

[0093] As shown in Figure 10, this figure illustrates the display panel's partitioning function. The partitioning precision can be determined by the actual display requirements. The partitioning precision of the display screen can be one line, two lines, or multiple lines. Figure 10(a) shows the partitioning of a display screen with a partitioning precision of two lines. The number of partitions is greater than or equal to two, and the frequency of each partition can be 240Hz, 144Hz, 120Hz, 60Hz, 30Hz, 10Hz, 1Hz, and 0.1Hz, etc. The display device can have any number of display areas with the same or different display frequencies, such as two, three, or four.

[0094] Figure 10 shows an 8-level GOA circuit, namely GOA1, GOA2, ..., GOA8. In Figure 10(b), two partitions are included: the partition consisting of GOA1 and GOA2 uses a 120Hz refresh rate, and the partitions consisting of GOA3 to GOA8 use a 10Hz refresh rate. Figure 10(c) also includes two partitions: the partition consisting of GOA1 to GOA4 uses a 120Hz refresh rate, and the partitions consisting of GOA5 to GOA8 use a 10Hz refresh rate. Figure 10(d) also includes two partitions: the partition consisting of GOA1 to GOA6 uses a 120Hz refresh rate, and the partitions consisting of GOA7 to GOA8 use a 10Hz refresh rate. Figure 10(e) includes three partitions: partitions GOA1 to GOA2 use a 120Hz refresh rate, partitions GOA3 to GOA4 use a 60Hz refresh rate, and partitions GOA5 to GOA8 use a 30Hz refresh rate. Figure 10(f) also includes three partitions: partitions GOA1 to GOA2 use a 120Hz refresh rate, partitions GOA3 to GOA6 use a 60Hz refresh rate, and partitions GOA7 to GOA8 use a 30Hz refresh rate. Figure 10(g) also includes three partitions: partitions GOA1 to GOA4 use a 120Hz refresh rate, partitions GOA5 to GOA6 use a 60Hz refresh rate, and partitions GOA7 to GOA8 use a 30Hz refresh rate. In Figure 10, (h) includes four partitions: partitions GOA1 to GOA2 use a refresh rate of 120Hz, partitions GOA3 to GOA4 use a refresh rate of 60Hz, partitions GOA5 to GOA6 use a refresh rate of 30Hz, and partitions GOA7 to GOA8 use a refresh rate of 10Hz.

[0095] However, due to the voltage difference of PS1, the input of the frequency control circuit in the GOA circuit, in the high and low frequency regions, the voltage of node N1 also differs when the refresh rate output is high and the refresh rate output is low. That is, node N1 is at a high level when the GOA circuit does not output a valid pulse signal, and at a low level when the GOA circuit outputs a valid pulse signal.

[0096] Figure 11 shows the timing diagrams for the j-th refresh cycle and the (j+1)-th refresh cycle. Figure 11 also shows the timing diagrams for each node of CLK1, CLK2, the first frequency control signal PS1, STV, the m-th stage GOA circuit of the driver circuit, and the (m+1)-th stage GOA circuit. The nodes of the m-th stage GOA circuit include: N1_m, PU_m, PD_m, BPU_m, S1_m, and SR_m. The nodes of the (m+1)-th stage GOA circuit include: N1_m+1, PU_m+1, PD_m+1, BPU_m+1, S1_m+1, and SR_m+1.

[0097] Wherein, S1_m is the high-frequency output, and S1_m+1 is the low-frequency output. From the output interface of SR_m in the j-th refresh cycle to the start of the output of SR_m in the (j+1)-th refresh cycle, N1_m remains at a low level. From the end of the output of SR_m+1 in the j-th refresh cycle to the start of the output of SR_m+1 in the (j+1)-th refresh cycle, N1_m+1 remains at a high level.

[0098] Specifically, in the j-th refresh cycle, S1_m is the effective pulse signal, and its working principle is as follows:

[0099] (1) t1 time period: SR_m-1 signal voltage changes from VGL to VGH, the m-th level GOA circuit is activated, at this time the first frequency control signal PS1 is VGL, the potential of N1_m node is also VGL, T3_m is turned on, the potential of PD_m node changes from VGL to VGH, and T2_m and T5_m are turned off.

[0100] (2) During time period t2: As T3_m turns on, the potential of node PU_m changes from VGH to VGL, and the potential of node BPU_m also changes from VGH to VGL. The potential of node N1_m is pulled down to VGL* due to capacitive coupling, where the amplitude of VGL* is close to 2*VGL-VGH. When T1_m turns on, SR_m starts outputting, and when T4_m turns on, S1_m starts outputting.

[0101] (3) t4 period: The SR_m-1 signal voltage changes from VGH to VGL, and the GOA circuit will end the output of SR and S1 in the t5 period.

[0102] (4) During time period t5: The potential of node PU_m changes from VGL to VGH, the potential of node PD_m changes from VGH to VGL, the potential of node N1_m is coupled from VGL* to VGL, and the potential of node BPU_m changes from VGL to VGH. T1_m is turned off, T2_m is turned on, and SR_m output ends. T4_m is turned off, T5_m is turned on, and S1_m output ends.

[0103] In the j-th refresh cycle, S1_m+1 is an invalid pulse signal, and its working principle is as follows:

[0104] (1) During the t2 period: the SR_m signal voltage changes from VGL to VGH, the m+1 level GOA circuit is activated, the PS1 signal is VGH, the potential of the N1_m+1 node changes from VGL to VGH, the T3_m+1 transistor is turned off, the potential of the PD_m+1 node changes from VGL to VGH, and T2_m+1 and T5_m+1 are turned off.

[0105] (2) During time period t3: The potential of node PU_m+1 changes from VGH to VGL, but since T3_m+1 is off, the potentials of nodes PD_m+1 and BPU_m+1 remain at VGH. The potential of node N1_m+1 remains at VGH, T1_m+1 is on, SR_m+1 starts outputting, T4_m+1 is off, and S1_m+1 has no signal output.

[0106] (3) t5 period: The SR_m signal voltage changes from VGH to VGL, and the GOA_m+1 circuit will output at the end of the t6 period.

[0107] (4) During time period t6: The potential of node PU_m+1 changes from VGL to VGH, the potential of node PD_m+1 changes from VGH to VGL, T1_m is turned off, T2_m is turned on, and the output of SR_m+1 ends. The potentials of nodes N1_m+1 and BPU_m+1 remain at VGH, T4_m+1 is turned off, T5_m+1 is turned on, and the output of S1_m+1 ends.

[0108] During the (j+1)th refresh cycle, the PS1 signal always maintains VGL, and both S1_m and S1_m+1 are output. The working principle and the type of S1_m in the jth refresh cycle will not be elaborated here.

[0109] In one possible example, as shown in Figure 12(a), when the PS1 signal is low, the voltage difference between the gate and drain of the third transistor T3 is Vgd = 3.9V, and the voltage difference between the drain and source of the third transistor T3 is Vds = 0V. As shown in Figure 12(b), when the PS1 signal is low, the voltage difference between the gate and drain of the third transistor T3 is Vgd = -14.7V, and the voltage difference between the drain and source of the third transistor T3 is Vds = 14.1V. Therefore, if the partitioning function of the GOA circuit is continuously enabled in a fixed position, TFT device characteristic drift will occur, resulting in uneven display between high refresh rate and low refresh rate areas.

[0110] Additionally, as shown in Figure 13, which illustrates the waveforms of the PU node, PD node, and gate scan signal, the PU node's waveform changes earlier than the PD node. Step noise appears in the cascaded signal when the PU node voltage rises. Since the cascaded signal is used to implement the shift output of the GOA circuit, the presence of step noise on the rising edge of the cascaded signal will cause the gate scan signal waveform to become unsmooth, potentially leading to gate scan signal distortion and affecting its accuracy.

[0111] Therefore, this application provides a driving circuit with an added reset circuit. The driving circuit can control the voltage of node N1 through the reset circuit to maintain the voltage of node N1 at the same value. This avoids the impact of voltage changes of node N1 on the display effect of the display, improves the stability of the GOA circuit, and improves the display effect of the display.

[0112] The driving circuit provided in the embodiments of this application will be further described below with reference to the accompanying drawings.

[0113] This application provides a driving circuit, as shown in Figure 14. The driving circuit includes multiple GOA circuits, each of which includes a register circuit, an output circuit, a frequency control circuit, and a reset circuit. Figure 14 shows a schematic diagram of the structure of n GOA circuits, namely GOA circuit_1, GOA circuit_2, ..., GOA circuit_n.

[0114] The output circuit and the register circuit are coupled. The output circuit is configured to generate a gate scan signal in response to the voltage of the pull-up node and the voltage of the pull-down node of the register circuit, and output the gate scan signal to the pixel circuit corresponding to the GOA circuit.

[0115] For example, the register circuit can receive a carry signal, which can be a start frame signal or a cascaded signal output from the previous stage GOA circuit. The register circuit and the output circuit are coupled to pull-up nodes and pull-down nodes, where the signal of the pull-up node is the PU signal and the signal of the pull-down node is the PD signal. When the PU signal is low and the PD signal is high, the output circuit outputs a high-level gate scan signal; when the PU signal is high and the PD signal is low, the output circuit outputs a low-level gate scan signal.

[0116] It is understood that the gate scan signal provided in the embodiments of this application is often used to turn on or off the first transistor T1 in the pixel circuit, that is, the gate scan signal is S1.

[0117] The frequency control circuit and the output circuit are coupled to the first node. The frequency control circuit is configured to receive a first frequency control signal to control the frequency of the gate scan signal.

[0118] For example, when the first frequency control signal is low, the gate scan signal output by the output circuit is a valid pulse signal; when the first frequency control signal is high, the gate scan signal output by the output circuit is an invalid pulse signal. Thus, the frequency control circuit can realize the partitioning function of the display screen.

[0119] The reset circuit and the output circuit are coupled to the first node, and the reset circuit is configured to control the voltage of the first node based on the reset signal.

[0120] For example, the driving circuit can control the voltage of the first node through the reset circuit to eliminate the difference in voltage between the first nodes of different GOA circuits over a long period of time. This can avoid the impact of voltage changes of the first node on the display effect of the monitor, improve the stability of the GOA circuit, and improve the display effect of the monitor.

[0121] For example, as shown in Figure 15, which, based on Figure 11, also illustrates the timing diagrams of the frequency control circuit _m, the reset circuit _m, the frequency control circuit _m+1, and the reset circuit _m+1. The reset circuit _m is turned off when the frequency control circuit is on (at time t1) and turns on again after S1 output is complete (at time t6). As can be seen from Figure 15, the voltages of N1_m and N1_m+1 remain at a low level for a period between the two refresh cycles. This avoids voltage fluctuations at node N1, improves the stability of the GOA circuit, and enhances the display effect.

[0122] Optionally, as shown in Figure 16, which illustrates the structural diagrams of the (m-1)th stage GOA circuit, the mth stage GOA circuit, and the m+1th stage GOA circuit, the reset circuit includes a first transistor (represented by T1 in Figure 16). The first terminal of the first transistor T1 is coupled to the first node (represented by N1 in Figure 16), and the second terminal of the first transistor T1 is coupled to the first voltage source (represented by V1 in Figure 16). The gate of the first transistor T1 is used to receive the reset signal (represented by Vrs in Figure 16).

[0123] Specifically, the reset circuit is configured to control the voltage of the first node by means of the voltage output from the first voltage source when the reset signal controls the first transistor to turn on.

[0124] For example, the register circuit may include a register sub-circuit and a second node. The reset signal may originate from a second node in the register circuit (denoted as N2 in Figure 16), which may also be referred to as a bootstrap node. The second node N2 is coupled to the first terminal of a twelfth transistor (denoted as T12 in Figure 16), and the second terminal of the twelfth transistor T12 is coupled to either a first clock signal CLK_1 or a second clock signal CLK_2. The second node N2 is also coupled to the first terminal of a fourth capacitor (denoted as C4 in Figure 16), and the second terminal of the fourth capacitor C4 is coupled to a third node (denoted as N3 in Figure 16).

[0125] For example, the voltage output by the first voltage source can be a low level. In one possible example, the voltage output by the first voltage source can be VGL. The voltage output by the first voltage source can also be any voltage signal lower than VGH. When the first transistor T1 is turned on, due to the presence of the first transistor T1, the voltage of the first node is less than the voltage output by the first voltage source.

[0126] Optionally, as shown in Figure 17, which is based on Figure 16, the structural schematic diagrams of the (m-1)th level GOA circuit, the m-th level GOA circuit, and the (m+1)th level GOA circuit are presented. The reset transistor also includes a second transistor (represented as T2 in Figure 17). The first terminal of the second transistor T2 is coupled to the first terminal of the first transistor T1, the second terminal of the second transistor T2 is coupled to the first node N1, and the gate of the second transistor T2 is coupled to the gate of the first transistor T1.

[0127] For example, adding a second transistor T2 between the first node N1 and the first transistor T1 can reduce the voltage across the first and second terminals of the first transistor T1, thus improving the reliability of the GOA circuit. Furthermore, the common-gate structure of the first transistor T1 and the second transistor T2 can further enhance transistor reliability.

[0128] Optionally, as shown in Figure 18, the frequency control circuit includes a third transistor (represented by T3 in Figure 18). The first terminal of the third transistor T3 is coupled to the register circuit, the second terminal of the third transistor T3 is coupled to the output circuit, and the gate of the third transistor T3 is used to receive the second frequency control signal.

[0129] The frequency control circuit is also configured to receive a first frequency control signal and a second frequency control signal to control the frequency of the gate scan signal.

[0130] For example, by using a first frequency control signal and a second frequency control signal to jointly control the frequency of the gate scan signal, the GOA circuit can reduce the frequency of the clock signal during low-frequency driving, thereby further reducing the power consumption of the driving circuit.

[0131] Optionally, referring to Figures 16, 17, or 18, the output circuit includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a first capacitor C1. Specifically, the gate and register circuit of the fourth transistor T4 are coupled to a pull-up node; the first terminal of the fourth transistor T4 is coupled to a high-voltage gate source (represented as VGH in Figures 16, 17, or 18); the second terminal of the fourth transistor T4 is coupled to the first terminal of the fifth transistor T5; the second terminal of the fifth transistor T5 is coupled to a low-voltage gate source (represented as VGL in Figures 16, 17, or 18); and the gate and register circuit of the fifth transistor T5 are coupled to a pull-down node. The pull-up node is also coupled to the first terminal of the sixth transistor T6. The gate of the sixth transistor T6 is coupled to the first node N1. The second terminal of the sixth transistor T6 is coupled to the gate of the seventh transistor T7. The first terminal of the seventh transistor T7 is coupled to the gate high voltage source VGH. The second terminal of the seventh transistor T7 is coupled to the first terminal of the eighth transistor T8. The second terminal of the eighth transistor T8 is coupled to the gate low voltage source VGL. The gate of the eighth transistor T8 is coupled to the pull-down node. The first terminal of the first capacitor C1 is coupled to the gate of the sixth transistor T6, and the second terminal of the first capacitor C2 is coupled to the second terminal of the sixth transistor T6.

[0132] Optionally, as shown in Figure 19, the output circuit also includes a ninth transistor (represented by T9 in Figure 19), the first and second terminals of the ninth transistor T9 are both coupled to the first terminal of the fifth transistor T5, and the gate of the ninth transistor T9 is coupled to the pull-down node.

[0133] For example, the output circuit can reduce the rising edge step of the cascaded signal and optimize the quality of the cascaded signal by using the capacitive coupling effect of the ninth transistor.

[0134] Optionally, referring to Figure 19, the output circuit also includes a tenth transistor (represented by T10 in Figure 19). The first terminal of the tenth transistor T10 is coupled to the pull-down node, the second terminal of the tenth transistor T10 is coupled to the gate of the eighth transistor T8, and the gate of the tenth transistor T10 is coupled to the first node N1.

[0135] For example, the tenth transistor T10 can prevent the eighth transistor T8 from turning on accidentally, which can improve the stability of the GOA circuit.

[0136] Optionally, referring to Figure 19, the output circuit also includes an eleventh transistor (represented by T11 in Figure 19). The first terminal of the eleventh transistor T11 is coupled to the gate high voltage source VGH, the second terminal of the eleventh transistor T11 is coupled to the second terminal of the sixth transistor T6, and the gate of the eleventh transistor T11 is coupled to the gate of the eighth transistor T8.

[0137] For example, the voltage drop of the gate scan signal can be accelerated by the eleventh transistor T11.

[0138] In addition, referring to Figure 19, the output circuit also includes a second capacitor (represented by C2 in Figure 19) and a third capacitor (represented by C3 in Figure 19). The first terminal of the second capacitor C2 is coupled to the first terminal of the seventh transistor T7, and the second terminal of the second capacitor C2 is coupled to the gate of the seventh transistor T7. The first terminal of the third capacitor C3 is coupled to the first terminal of the eighth transistor T8, and the second terminal of the third capacitor C3 is coupled to the gate of the eighth transistor T8.

[0139] For example, the drive circuit may also include more capacitors, which can stabilize the node voltage to compensate for voltage drops caused by power supply voltage fluctuations or other factors.

[0140] As shown in Figure 20, the specific circuit of the frequency control circuit can include a thirteenth transistor (represented as T13 in Figure 20) and a fourteenth transistor (represented as T14 in Figure 20). The first terminal of the thirteenth transistor T13 is used to input the first frequency control signal PS1. The gate of the thirteenth transistor T13 is coupled to the fourth node of the previous stage GOA circuit (represented as N4_m-1 in Figure 20). The second terminal of the thirteenth transistor T13 is coupled to the first terminal of the fourteenth transistor T14. The gate of the fourteenth transistor T14 is used to input the cascaded signal. The second terminal of the fourteenth transistor T14 is coupled to the first node N1.

[0141] For example, the gate signal of the transistor in the frequency control circuit can also be coupled to the nodes of other GOA circuits. The gate of T13_m in the driving circuit can also be coupled to the fourth node (such as N4_m-2, N4_m-3…N4_m-k, k≥2) of the GOA circuit two or more levels above. The gate of the driving circuit T14_m can also be coupled to the SR signal (such as SR_m-1, SR_m-2…SR_m-k, k≥1) of the GOA circuit one level above. This is used to adjust the synchronization state between signals and reduce signal delay.

[0142] Figure 20 also shows the specific circuitry of the register circuit, which may include a third node (denoted as N3 in Figure 20), a fourth node (denoted as N4 in Figure 20), multiple transistors (e.g., T15 to T26), and multiple capacitors (e.g., C5 and C6). The capacitors can stabilize the node voltage to compensate for voltage drops caused by power supply voltage fluctuations or other factors.

[0143] Figure 21 shows the timing diagram of the internal nodes and external signals in Figure 20. Specifically, Figure 21 shows the timing of N4_m-1, N2_m, N4_m, and N2_m+1 based on Figure 15. As can be seen from Figure 21, the driving circuit can achieve a partial refresh rate reduction function through the frequency control circuit. Furthermore, the voltages of N1_m and N1_m+1 remain at a low level for a period of time between two refresh cycles. This avoids voltage differences at node N1, improves the stability of the GOA circuit, and enhances the display effect.

[0144] The following description, in conjunction with the accompanying drawings, provides a further description of a display device provided in an embodiment of this application.

[0145] In this circuit, the driving circuit typically uses the same gate high voltage source for power supply, meaning that multiple GOA circuits in the driving circuit are coupled to the gate high voltage signal line of this gate high voltage source. When the output gate scan signal of the previous row changes from VGH to VGL, there is a transient load reduction in the gate high voltage source and its signal line. The potential of the gate high voltage source is pulled down, which will generate noise ripple.

[0146] Specifically, as shown in Figure 22, the gate scan signals (S1_m and S1_m+1) will have multiple ripples with fixed time intervals (e.g., 2H) when in the high-level state. Since the opening degree of the first transistor T1 in the pixel circuit depends on the high-level potential of S1, after the first transistor T1 is turned on via S1, the second transistor T2 is then turned on via S2. The data voltage DATA is written to the gate of the driving transistor Td at the time point of S1. At this time, the high-voltage source of the driving circuit that generates S1 should maintain a stable potential. Therefore, if the ripple signal is too dense, it will disturb the data voltage writing, resulting in uneven brightness in the display.

[0147] To address the aforementioned ripple problem, this application provides a display device, as shown in FIG23. The display device includes a pixel array, a peripheral driving circuit, and multiple cascaded driving circuits. Each driving circuit includes multiple GOA circuits, each GOA circuit comprising a register circuit and an output circuit. The driving circuit may include n GOA circuits; FIG23 shows register circuits 1 to n and output circuits 1 to n. Furthermore, the driving circuit may include redundant GOA circuits, which include virtual register circuits and virtual output circuits. It is understood that the GOA circuits may also include more components, such as the frequency control circuit and reset circuit mentioned above; this application does not limit this.

[0148] In addition, the peripheral driving circuit includes at least one gate high voltage source, which is coupled to multiple gate high voltage signal lines. Adjacent driving circuits in the multiple cascaded driving circuits are coupled to different gate high voltage signal lines.

[0149] For example, suppose the peripheral driving circuit can provide j gate high voltage signal lines, where j is an integer greater than or equal to 1, i.e., VGH1, VGH2, ..., VGHj. Taking the output circuit in the driving circuit as an example, the output circuit can be connected to the j gate high voltage signal lines through k first signal lines, where k is an integer greater than or equal to 1. The connection relationship can also be that adjacent first signal lines are connected to different gate high voltage signal lines.

[0150] In one possible implementation, continuing to refer to FIG23, FIG23 shows a first gate high voltage source VGH1, which is coupled to a first gate high voltage signal line VGH1_1 and a second gate high voltage signal line VGH1_2. The first signal lines and gate high voltage signal lines of the output circuits are connected alternately in a row; for example, the first signal line of output circuit 1 is connected to VGH1_1, the first signal line of output circuit 2 is connected to VGH1_2, the first signal line of output circuit 3 is connected to VGH1_1, and the first signal line of output circuit 4 is connected to VGH1_2.

[0151] In another possible implementation, as shown in FIG24, a first gate high voltage source VGH1 and a second gate high voltage source VGH2 are illustrated. The first gate high voltage source VGH1 is coupled to a first gate high voltage signal line VGH1_1 and a second gate high voltage signal line VGH1_2, respectively. The second gate high voltage source VGH2 is coupled to a third gate high voltage signal line VGH2_1 and a fourth gate high voltage signal line VGH2_2, respectively. The first signal lines and gate high voltage signal lines of the output circuits are connected alternately. For example, the first signal line of output circuit 1 is connected to VGH1_1, the first signal line of output circuit 2 is connected to VGH2_1, the first signal line of output circuit 3 is connected to VGH1_2, and the first signal line of output circuit 4 is connected to VGH2_2. Similarly, every four GOA circuits can be connected to the gate high voltage signal lines in the same connection manner as output circuits 1 to 4.

[0152] Optionally, as shown in Figure 25, the peripheral driving circuit further includes a level conversion circuit, and at least one gate high voltage source includes a first gate high voltage source VGH1 and a second gate high voltage source VGH2. The output circuits of the multiple cascaded driving circuits are coupled to the first gate high voltage source, and the register circuits and level conversion circuits of the multiple cascaded driving circuits are coupled to the second gate high voltage source.

[0153] For example, the first gate high voltage source VGH1 is coupled to the first gate high voltage signal line VGH1_1 and the second gate high voltage signal line VGH1_2, respectively. The second gate high voltage source VGH2 is coupled to the third gate high voltage signal line VGH2_1 and the fourth gate high voltage signal line VGH2_2, respectively. The register circuit is connected to STV, CLK1, CLK2, VGH2_1, and VGH2_2. STV, CLK1, and CLK2 are generated based on the level conversion of VGH2, and the gate high voltage required for the operation of the register circuit is provided by VGH2. In addition, the output circuit is connected separately to VGH1, and the gate high voltage required for the output circuit is provided by VGH1. Therefore, the independent power supply drive capability of VGH1 can be flexibly adjusted, which helps to improve the stability of the gate scan signal output by the output circuit and reduce signal disturbance.

[0154] Optionally, the drive current of the first gate high voltage source is greater than the drive current of the second gate high voltage source.

[0155] For example, the drive current of VGH1 is greater than the drive current of VGH2. VGH1 can output a more stable high gate voltage to the output circuit, which helps to improve the stability of the gate scan signal output by the output circuit and reduce signal disturbance.

[0156] Optionally, at least one gate high voltage source includes a first gate high voltage source and a second gate high voltage source. The first transistor in the output circuit of an adjacent driving circuit is coupled to the gate high voltage signal line of the first gate high voltage source, and other transistors in the output circuit of an adjacent driving circuit are coupled to the gate high voltage signal line of the second gate high voltage source.

[0157] For example, the first transistor can be the seventh transistor of the output circuit of the driving circuit described above, and the other transistors can be the eleventh transistor of the output circuit of the driving circuit described above. Therefore, using a single first gate high-voltage source to provide a gate high voltage to the first terminal of the first transistor helps improve the stability of the gate scan signal output by the output circuit and reduces signal disturbances.

[0158] For example, the length of the signal line between the gate high voltage signal line of the first gate high voltage source and the output circuit can be within a preset range. In one possible example, the gate high voltage signal line of the first gate high voltage source can be positioned close to the output circuit to reduce the length of the signal line between the gate high voltage signal line and the output circuit, thereby improving signal transmission quality.

[0159] Optionally, the output of the first gate high voltage source is coupled to multiple parallel voltage-regulating capacitors.

[0160] For example, connecting multiple voltage-regulating capacitors in parallel at the output terminal of the first gate high voltage source can improve the stability of the gate high voltage output by the first gate high voltage source, which helps to improve the stability of the gate scan signal output by the output circuit and reduce signal disturbance.

[0161] Understandably, multiple voltage-regulating capacitors can be connected in parallel at the output of other gate high voltage sources in the peripheral driving circuit to improve the stability of the gate high voltage output by the gate high voltage source.

[0162] Optionally, the first signal line of each output circuit is coupled to the corresponding gate high voltage signal line, and the length of the first signal line is such that each first signal line overlaps with multiple gate high voltage signal lines.

[0163] For example, as shown in Figure 26, the gate high-voltage signal line can be distributed on the first conductive layer, and the first signal line can be distributed on the second conductive layer. The first and second conductive layers are disposed opposite to each other, and the first signal line and the corresponding gate high-voltage signal line are connected through a connection hole. Taking the first signal line of the output circuit 2 as an example, the first signal line is connected to VGH1_1 through a connection hole, and the first signal line forms an overlapping capacitance with other signal lines (e.g., STV, VGH2_2, and VGH2_2). In addition, the first signal line also has an extension portion, such as the dashed line portion in Figure 26, which forms an overlapping capacitance with VGH1_2. It is understood that there is no electrical connection between the extension portion of the first signal line and other signal lines. Furthermore, the first signal line can extend beyond VGH1_2, and this embodiment does not limit the length of the line extending beyond VGH1_2.

[0164] Therefore, the impedance of the first signal line between the output circuit and the gate high voltage signal line is the same, which can reduce the difference in the gate scan signal output by the output circuit.

[0165] Optionally, the gate high voltage signal line of the first gate high voltage source includes at least two metal layers, and the at least two metal layers are connected through at least one connection hole.

[0166] For example, the gate high voltage signal line of the first gate high voltage source can be formed by overlapping multiple metal layers, with inorganic layers between adjacent metal layers. The multiple metal layers can be connected by vias at appropriate locations to achieve electrical conduction. This reduces the impedance of the gate high voltage signal line of the first gate high voltage source.

[0167] For example, as shown in Figure 27, three metal layers and two inorganic layers are arranged sequentially: a first metal layer, a first inorganic layer, a second metal layer, a second inorganic layer, and a third metal layer. The first and second metal layers can be connected via a first connecting hole, and the second and third metal layers can be connected via a second connecting hole.

[0168] In one possible example, the metal layer could be three layers of titanium-aluminum-titanium metal or one layer of molybdenum metal, and the inorganic layer could be silicon nitride or silicon oxide.

[0169] The driving method provided in the embodiments of this application will be further described below with reference to the accompanying drawings.

[0170] Applying to the above-mentioned driving circuit, this application provides a driving method, as shown in FIG28, which includes the following process.

[0171] S2801, the output circuit generates a gate scan signal in response to the voltage of the pull-up node and the pull-down node of the register circuit, and outputs the gate scan signal to the pixel circuit corresponding to the GOA circuit.

[0172] S2802, the frequency control circuit receives the first frequency control signal to control the frequency of the gate scan signal.

[0173] S2803, the reset circuit controls the voltage of the first node based on the reset signal.

[0174] For example, when the driver circuit does not enable the local refresh rate reduction function, as shown in Figure 29, Figure 29 shows the timing diagram of STV, CLK1, CLK2, each node of the eight GOA circuits (PU_1~PU_8, PD_1~PD_8, BPU_1~BPU_8), the first frequency control signal PS1, and the gate scan signals (S1_1~S1_8) output by each GOA circuit. When the first frequency control signal PS1 is set to a low level (VGL), the eight GOA circuits normally output gate scan signals, and the pulse width of each gate scan signal is 6H.

[0175] For example, when the driver circuit enables the partial refresh rate reduction function, as shown in Figure 30, Figure 30 shows the timing diagram of the first frequency control signal PS1 for each node (PU_1~PU_8, PD_1~PD_8, BPU_1~BPU_8) of STV, CLK1, CLK2, and the gate scan signals (S1_1~S1_8) output by each GOA circuit. Specifically, when the first frequency control signal PS1 switches from low level (VGL) to high level (VGH) when S1_4 is enabled, the signals from BPU_5 to BPU_8 are shielded. The first four GOA circuits output gate scan signals in a certain frame, while the latter four GOA circuits do not output gate scan signals.

[0176] Optionally, S2802 may include: a frequency control circuit receiving a first frequency control signal and a second frequency control signal to control the frequency of the gate scan signal.

[0177] For example, when the driver circuit does not enable the local refresh rate reduction function, as shown in Figure 31, Figure 31 shows the timing diagram of the first frequency control signal PS1, the second frequency control signal PS2, and the gate scan signal (S1_1~S1_8) output by each node (PU_1~PU_8, PD_1~PD_8, BPU_1~BPU_8) of STV, CLK1, CLK2, and the eight GOA circuits. When both the first frequency control signal PS1 and the second frequency control signal PS2 are set to low level (VGL), the eight GOA circuits normally output gate scan signals, and the pulse width of each gate scan signal is 6H.

[0178] For example, when the driver circuit enables the partial refresh rate reduction function, as shown in Figure 32, Figure 32 illustrates the timing diagram of the first frequency control signal PS1, the second frequency control signal PS2, and the gate scan signals (S1_1 to S1_8) output by each node (PU_1~PU_8, PD_1~PD_8, BPU_1~BPU_8) of STV, CLK1, CLK2, and the eight GOA circuits. Specifically, the first frequency control signal PS1 switches from low level (VGL) to high level (VGH) when S1_4 is enabled. At this time, the signals of BPU_5 to BPU_8 are shielded, and the first four GOA circuits output gate scan signals in a certain frame, while the latter four GOA circuits do not output gate scan signals. Since S1_5 does not output gate scan signals, after the output of S1_4, CLK1 and CLK2 can be converted to fixed voltage signals (such as high level), and PS2 changes from low level to high level to maintain the PU node potential. This further reduces power consumption.

[0179] This application also provides a display device, which may include a processor and the driving circuit described above, wherein the driving circuit and the processor are coupled.

[0180] For example, the processor can be a display driver integrated circuit (DDIC) chip, a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0181] Embodiments of this application also provide a computer storage medium storing computer instructions. When the computer instructions are executed on an electronic device, the electronic device performs the aforementioned method steps to implement the driving method in the above embodiments.

[0182] Embodiments of this application also provide a computer program product that, when run on a computer, causes the computer to perform the aforementioned related steps to implement the driving method executed by the electronic device in the above embodiments.

[0183] In addition, embodiments of this application also provide an apparatus, which may specifically be a chip, component, or module. The apparatus may include a connected processor and a memory. The memory is used to store computer execution instructions. When the apparatus is running, the processor can execute the computer execution instructions stored in the memory to cause the chip to execute the driving method executed by the electronic device in the above-described method embodiments.

[0184] In this embodiment, the driving circuit, display device, display equipment, computer storage medium, computer program product or chip are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects in the corresponding methods provided above, and will not be repeated here.

[0185] Through the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0186] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0187] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0188] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0189] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, essentially or in other words, the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0190] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A drive circuit characterized by comprising: The array driving scanning GOA circuit comprises a register circuit, an output circuit, a frequency control circuit and a reset circuit; The output circuit and the register circuit are coupled and configured to generate a gate scanning signal in response to the voltage of a pull-up node and the voltage of a pull-down node of the register circuit, and output the gate scanning signal to a corresponding pixel circuit of the GOA circuit; The frequency control circuit and the output circuit are coupled at a first node and configured to receive a first frequency control signal to control the frequency of the gate scanning signal; The reset circuit and the output circuit are coupled at the first node and configured to control the voltage of the first node based on a reset signal.

2. The drive circuit according to claim 1, characterized by The reset circuit comprises a first transistor; The first end of the first transistor is coupled with the first node, the second end of the first transistor is coupled with a first voltage source, and the gate of the first transistor is configured to receive the reset signal; The reset circuit is specifically configured to control the voltage of the first node by the voltage output by the first voltage source when the reset signal controls the first transistor to be turned on.

3. The drive circuit according to claim 2, characterized in that, The reset circuit further comprises a second transistor; The first end of the second transistor is coupled with the first end of the first transistor, the second end of the second transistor is coupled with the first node, and the gate of the second transistor is coupled with the gate of the first transistor.

4. The drive circuit according to any one of claims 1 to 3, characterized in that, The frequency control circuit comprises a third transistor; The first end of the third transistor is coupled with the register circuit, the second end of the third transistor is coupled with the output circuit, and the gate of the third transistor is configured to receive a second frequency control signal; The frequency control circuit is further configured to receive the first frequency control signal and the second frequency control signal to control the frequency of the gate scanning signal.

5. The drive circuit according to any one of claims 1 to 4, characterized in that, The output circuit comprises a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a first capacitor; The gate of the fourth transistor is coupled with the register circuit at the pull-up node, the first end of the fourth transistor is coupled with a high gate voltage source, the second end of the fourth transistor is coupled with the first end of the fifth transistor, the second end of the fifth transistor is coupled with a low gate voltage source, and the gate of the fifth transistor is coupled with the register circuit at the pull-down node; The pull-up node is further coupled with the first end of the sixth transistor, the gate of the sixth transistor is coupled with the first node, the second end of the sixth transistor is coupled with the gate of the seventh transistor, the first end of the seventh transistor is coupled with the high gate voltage source, the second end of the seventh transistor is coupled with the first end of the eighth transistor, the second end of the eighth transistor is coupled with the low gate voltage source, and the gate of the eighth transistor is coupled with the pull-down node; The first end of the first capacitor is coupled with the gate of the sixth transistor, and the second end of the first capacitor is coupled with the second end of the sixth transistor.

6. The drive circuit according to claim 5, characterized in that, The output circuit further comprises a ninth transistor; The first end and the second end of the ninth transistor are coupled with the first end of the fifth transistor, and the gate of the ninth transistor is coupled with the pull-down node.

7. The drive circuit according to claim 5 or 6, characterized in that, The output circuit further comprises a tenth transistor; The first end of the tenth transistor is coupled with the pull-down node, the second end of the tenth transistor is coupled with the gate of the eighth transistor, and the gate of the tenth transistor is coupled with the first node.

8. The drive circuit according to any one of claims 5 to 7, characterized in that The output circuit further comprises an eleventh transistor; The first end of the eleventh transistor is coupled with the gate high voltage source, the second end of the eleventh transistor is coupled with the second end of the sixth transistor, and the gate of the eleventh transistor is coupled with the gate of the eighth transistor.

9. A display device, characterized by comprising: Comprise: a pixel array, a peripheral driving circuit and a plurality of driving circuits in series; The peripheral driving circuit comprises at least one gate high voltage source, and the at least one gate high voltage source is coupled with a plurality of gate high voltage signal lines; The adjacent driving circuits in the plurality of driving circuits in series are respectively coupled with different gate high voltage signal lines.

10. The display device according to claim 9, wherein The peripheral driving circuit further comprises a level conversion circuit, and the at least one gate high voltage source comprises a first gate high voltage source and a second gate high voltage source; The output circuit of the plurality of driving circuits in series is coupled with the first gate high voltage source; The register circuit of the plurality of driving circuits in series is coupled with the second gate high voltage source and the level conversion circuit.

11. The display device according to claim 10, wherein The driving current of the first gate high voltage source is greater than the driving current of the second gate high voltage source.

12. The display device of claim 9, wherein, The at least one gate high voltage source comprises a first gate high voltage source and a second gate high voltage source; The first transistor in the output circuit of the adjacent driving circuits is coupled with the gate high voltage signal line of the first gate high voltage source; The other transistors in the output circuit of the adjacent driving circuits are coupled with the gate high voltage signal line of the second gate high voltage source.

13. A display device according to any of claims 10-12, characterized in that The output end of the first gate high voltage source is coupled with a plurality of parallel voltage stabilizing capacitors.

14. A display device according to any one of claims 10 to 13, wherein The first signal line of each output circuit is coupled with the corresponding gate high voltage signal line, and the length of the first signal line is such that each first signal line overlaps with the plurality of gate high voltage signal lines.

15. A display device according to any one of claims 10-14, characterized in that The gate high voltage signal line of the first gate high voltage source comprises at least two metal layers connected through at least one connection hole.

16. A driving method, comprising: The method is applied to a driving circuit, and the driving circuit comprises a plurality of GOA circuits, each GOA circuit comprising: a register circuit, an output circuit, a frequency control circuit and a reset circuit, the frequency control circuit, the output circuit and the reset circuit being coupled to a first node, and the method comprising: The output circuit generates a gate scanning signal in response to the voltage of a pull-up node and the voltage of a pull-down node of the register circuit, and outputs the gate scanning signal to a corresponding pixel circuit of the GOA circuit; The frequency control circuit receives a first frequency control signal to control the frequency of the gate scanning signal; The reset circuit controls the voltage of the first node based on a reset signal.

17. The driving method according to claim 16, wherein The frequency control circuit receives a first frequency control signal to control the frequency of the gate scan signal, comprising: The frequency control circuit receives the first frequency control signal and a second frequency control signal to control the frequency of the gate scan signal.

18. A display device, characterized by A drive circuit comprising a processor and the drive circuit of any of claims 1-8, the drive circuit and the processor coupled.

19. A computer-readable storage medium, characterized in that, A computer program product comprising computer instructions to cause a display device to perform the method of any of claims 16-17 when the computer instructions are run on the display device.

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