Data display method and apparatus, and electronic device

Abstract

A data display method and apparatus, and an electronic device. In the data display method, the frame rate of a display apparatus (304) and the frame rate of a processor (302) in an electronic device are always kept synchronized. The data display method comprises: the display apparatus (304) sending a pulse signal to the processor (302), wherein the pulse signal comprises an N-th level (HN) maintained for a certain duration within an N-th time period (TN), the N-th time period (TN) is a time period corresponding to an N-th frame rate, and N is a positive integer (S401); the processor (302) receiving the pulse signal from the display apparatus (304) (S402); the display apparatus (304) receiving display data sent by the processor (302) at an (N+1)-th frame rate (S404), wherein the display data is sent by the processor (302) in response to the received N-th level (HN), and a sending start moment of the display data is earlier than an end moment of the N-th time period (TN); and on the basis of the (N+1)-th frame rate, starting to display the display data at a start moment of an (N+1)-th time period (S405), wherein the (N+1)-th time period is a time period following the N-th time period (TN) and corresponding to the (N+1)-th frame rate.

Description

A data display method, apparatus and electronic device

[0001] This application claims priority to Chinese Patent Application No. 202411028607.0, filed on July 29, 2024, entitled “A Data Display Method, Apparatus and Electronic Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to a data display method, apparatus and electronic device. Background Technology

[0003] OLED screens in electronic devices support adaptive multi-level frame rate dynamic switching technology to improve display smoothness and reduce power consumption. Specifically, when the user's usage scenario is a low frame rate scenario, such as an idle desktop scenario or reading scenario, the frame rate of the application process (AP) and the OLED screen is reduced. When the user's usage scenario is a high frame rate scenario, such as a gaming scenario or video scenario, the frame rate of the AP and the OLED screen is increased. The AP's frame rate refers to the speed at which the AP processes image data, that is, the number of image frames the AP can process per second.

[0004] Currently, the AP transmits display data to the display device through the embedded display port (eDP) interface. Since the interaction between the AP and the display device is one-way, the AP cannot know the status of the display device. This may result in the frame rate on the AP side and the frame rate on the display device side being out of sync, causing OLED screen flicker and affecting display smoothness. Summary of the Invention

[0005] This application provides a data display method, apparatus, and electronic device. The data display method enables the frame rate of the display device and the frame rate of the processor in the electronic device to remain synchronized at all times.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] A first aspect provides a data display method, the method comprising: a display device sending a pulse signal to a processor, the pulse signal including an Nth level lasting for a certain duration within an Nth time period, the Nth time period being the time period corresponding to an Nth frame rate, where N is a positive integer; receiving display data sent by the processor to the display device at an N+1th frame rate, the display data being sent by the processor in response to the received Nth level, the start time of the transmission of the display data being earlier than the end time of the Nth time period; and a display screen in the display device starting to display the display data based on a second frame rate at the start time of the N+1th time period, the N+1th time period being the next time period after the Nth time period, the N+1th time period being the time period corresponding to the N+1th frame rate.

[0008] In the above technical solution, the display device sends a pulse signal to the processor. The pulse signal includes a level N that lasts for a certain duration within the Nth time period. The processor responds to the received level N and sends display data to the display device at the (N+1)th frame rate. The start time of sending the display data is earlier than the end time of the Nth time period, ensuring that the display device can start displaying the display data based on the second frame rate at the start time of the (N+1)th time period (i.e., the next time period after the Nth time period). This ensures that the frame rate of the display device and the frame rate of the processor are always synchronized. Through the bidirectional synchronization mechanism between the display device and the processor, the influence of external interference on the processor's frame rate is avoided, solving the problem of screen flickering caused by frame rate asynchrony and improving the display smoothness.

[0009] In one possible implementation of the first aspect, the method is applied to a display device in which the reset frequency of the display screen is an integer multiple of the frame rate, and the reset frequency is an integer multiple of the frequency of the pulse signal. The above-described possible implementations improve operational convenience.

[0010] In one possible implementation of the first aspect, the duration between the start time of the Nth level and the start time of the display data transmission is the target duration. In the above possible implementation, the transmission delay of the pulse signal and the transmission delay of the display data are considered. The pulse signal is sent in advance before the end time of the Nth time period, allowing the processor to send the display data to the display device before the end time of the Nth time period. This ensures that the display device can display the display data before the start time of the next time period (i.e., the N+1th time period), guaranteeing the synchronization of the processor's frame rate and the display device's frame rate.

[0011] In one possible implementation of the first aspect, the target duration is preset; or, the target duration is sent by the processor. The above possible implementations increase the selectivity of the solution.

[0012] In a second aspect, a data display method is provided, the method comprising: a processor receiving a pulse signal from a display device, the pulse signal including an Nth level lasting for a certain duration within an Nth time period, the Nth time period being a time period corresponding to an Nth frame rate; the processor responding to the Nth level of the pulse signal by sending display data to the display device at an N+1th frame rate before the end of the Nth time period, the display data being display data for the N+1th time period, the N+1th time period being the next time period after the Nth time period, the N+1th time period being a time period corresponding to the N+1th frame rate.

[0013] In the above technical solution, after the processor receives a pulse signal of level N, which lasts for a certain duration, during the Nth time period, the processor responds to the received level N and sends display data to the display device at the (N+1)th frame rate. The start time of sending the display data is earlier than the end time of the Nth time period, ensuring that the display device can start displaying the display data based on the second frame rate at the start time of the (N+1)th time period (i.e., the next time period after the Nth time period). This ensures that the frame rate of the display device and the frame rate of the processor are always synchronized. Through the bidirectional synchronization mechanism between the display device and the processor, the influence of external interference on the processor's frame rate is avoided, solving the problem of screen flickering caused by frame rate asynchrony and improving the display smoothness.

[0014] In one possible implementation of the second aspect, the reset frequency of the display screen in the display device is an integer multiple of the frame rate, and the reset frequency is an integer multiple of the frequency of the pulse signal. The above-described possible implementations improve operational convenience.

[0015] In one possible implementation of the second aspect, the duration between the start time of the Nth level and the start time of the display data transmission is the target duration. In the above possible implementation, the transmission delay of the pulse signal and the transmission delay of the display data are considered. The pulse signal is sent in advance before the end of the Nth time period, allowing the processor to send the display data to the display device before the end of the Nth time period. This ensures that the display device can display the display data before the start of the next time period (i.e., the N+1th time period), guaranteeing the synchronization of the processor's frame rate and the display device's frame rate.

[0016] In one possible implementation of the second aspect, the method is applied to the processor, and the target duration is preset; or, the target duration is sent by the processor. The above possible implementations increase the selectivity of the solution.

[0017] In one possible implementation of the second aspect, the method further includes: within the Nth time period, if the processor receives at least two Nth level signals, and before receiving the last Nth level of the at least two Nth level signals, sending display data to the display device at the Nth frame rate; if the processor receives the last Nth level of the at least two Nth level signals, the processor sends display data to the display device at the (N+1)th frame rate. In the above possible implementation, when at least two level signals are received within a certain time period, only the last level signal within that time period is responded to, ensuring synchronization between the processor's frame rate and the display device's frame rate.

[0018] Thirdly, a data display device is provided, comprising: a transmitting unit for transmitting a pulse signal to a processor, the pulse signal including an Nth level lasting for a certain duration within an Nth time period, the Nth time period being the time period corresponding to the Nth frame rate, and N being a positive integer; a receiving unit for receiving display data transmitted by the processor at the N+1th frame rate, the display data being transmitted by the processor in response to the received Nth level, the start time of transmission of the display data being earlier than the end time of the Nth time period; and a display unit for displaying the display data starting at the start time of the N+1th time period based on a second frame rate, the N+1th time period being the next time period after the Nth time period, and the N+1th time period being the time period corresponding to the N+1th frame rate.

[0019] In one possible implementation of the third aspect, the reset frequency of the display screen in the display device is an integer multiple of the frame rate, and the reset frequency is an integer multiple of the frequency of the pulse signal.

[0020] In one possible implementation of the third aspect, the duration between the start time of the Nth level and the start time of the transmission of the display data is the target duration.

[0021] In one possible implementation of the third aspect, the target duration is preset; or, the target duration is sent by the processor.

[0022] Fourthly, a data display device is provided, comprising: a receiving unit for receiving a pulse signal from a display device, the pulse signal including an Nth level lasting for a certain duration within an Nth time period, the Nth time period being a time period corresponding to an Nth frame rate; and a transmitting unit for transmitting display data at an N+1th frame rate before the end of the Nth time period in response to the Nth level of the pulse signal, the display data being display data for the N+1th time period, the N+1th time period being the next time period after the Nth time period, and the N+1th time period being a time period corresponding to the N+1th frame rate.

[0023] In one possible implementation of the fourth aspect, the reset frequency of the display screen in the display device is an integer multiple of the frame rate, and the reset frequency is an integer multiple of the frequency of the pulse signal.

[0024] In one possible implementation of the fourth aspect, the duration between the start time of the Nth level and the start time of the display data transmission is the target duration.

[0025] In one possible implementation of the fourth aspect, the data display device includes a processor, and the target duration is preset; or, the target duration is sent by the processor.

[0026] In one possible implementation of the fourth aspect, the transmitting unit is further configured to transmit display data to the display device at a frame rate of N before the receiving unit receives at least two Nth levels and before receiving the last Nth level among the at least two Nth levels; the transmitting unit is further configured to transmit display data to the display device at a frame rate of N+1 when the receiving unit receives the last Nth level among the at least two Nth levels.

[0027] Fifthly, an electronic device is provided, comprising a display device and a processor, wherein the display device is configured to perform a data display method provided by the first aspect or any possible implementation thereof, and the processor is configured to perform a data display method provided by the second aspect or any possible implementation thereof.

[0028] In another aspect of this application, a computer-readable storage medium is provided that stores computer instructions, which, when executed by a display chip in a display device, cause the display chip to perform a data display method as provided in the first aspect or any possible implementation thereof.

[0029] In another aspect of this application, a computer-readable storage medium is provided that stores computer instructions that, when executed by a processor, cause the processor to perform a data display method as provided in the second aspect or any possible implementation thereof.

[0030] In another aspect of this application, a computer program product is provided, comprising: a computer program that, when run by a display device, causes the display device to perform a data display method as provided in the first aspect or any possible implementation thereof.

[0031] In another aspect of this application, a computer program product is provided, comprising: a computer program that, when executed by a processor, causes the processor to perform a data display method as provided in the second aspect or any possible implementation thereof.

[0032] Understandably, the beneficial effects achieved by any of the above-mentioned data display devices, electronic devices, computer-readable storage media, and computer program products can be referred to in relation to the beneficial effects of the data display methods provided above, and will not be repeated here. Attached Figure Description

[0033] Figure 1 is a schematic diagram of a one-way synchronous expected frame rate provided in an embodiment of this application;

[0034] Figure 2 is a schematic diagram of a one-way synchronous actual frame rate provided in an embodiment of this application;

[0035] Figure 3 is a schematic diagram of the structure of the electronic device provided in an embodiment of this application;

[0036] Figure 4 is a flowchart of a data display method provided in an embodiment of this application;

[0037] Figure 5 is a schematic diagram of the frequency of a pulse signal and the reset frequency provided in an embodiment of this application;

[0038] Figure 6 is a schematic diagram of a bidirectional synchronous frame rate provided in an embodiment of this application;

[0039] Figure 7 is a schematic diagram of another bidirectional synchronous frame rate provided in an embodiment of this application;

[0040] Figure 8 is a flowchart of another data display method provided in an embodiment of this application;

[0041] Figure 9 is a schematic diagram of another bidirectional synchronous frame rate provided in an embodiment of this application;

[0042] Figure 10 is a schematic diagram of another bidirectional synchronous frame rate provided in an embodiment of this application;

[0043] Figure 11 is a schematic diagram of a data display device provided in an embodiment of this application;

[0044] Figure 12 is a schematic diagram of another data display device provided in an embodiment of this application. Detailed Implementation

[0045] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple. Furthermore, embodiments of this application utilize terms such as "first" and "second" to distinguish identical or similar items with essentially the same function and effect. For example, a first threshold and a second threshold are merely for distinguishing different thresholds and do not limit their order. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or execution order.

[0046] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0047] Before introducing the embodiments of this application, we will first explain the relevant knowledge of organic light-emitting diode (OLED) screens.

[0048] OLED screens in electronic devices support adaptive multi-level frame rate dynamic switching technology to improve display smoothness and reduce power consumption. Specifically, when the user's usage scenario is a low frame rate scenario, such as an idle desktop or reading scenario, the frame rate of the application process (AP) and the OLED screen is reduced. When the user's usage scenario is a high frame rate scenario, such as a gaming or video scenario, the frame rate of the AP and the OLED screen is increased. The AP's frame rate refers to the speed at which the AP processes image data, that is, the number of image frames the AP can process per second. The OLED screen's frame rate can also be called the display frame rate, or refresh rate.

[0049] Because switching directly from a high frame rate (e.g., 102Hz) to a low frame rate (e.g., 1Hz) on an OLED screen can cause flickering, a frame transition technique is needed to gradually reduce the OLED screen's frame rate. For example, first switch from 120Hz to 80Hz, then from 80Hz to 60Hz, then from 60Hz to 30Hz, and finally from 30Hz to 1Hz.

[0050] In electronic devices, the AP can transmit display data to the display device through the embedded display port (eDP) interface. The AP and the display device use one-way interaction, which means that the AP cannot know the status of the display device. During frame transition, the frame rate on the AP side and the frame rate on the display device side may not be synchronized, causing the OLED screen to flicker and affecting the smoothness of the display.

[0051] For example, Figure 1 is a schematic diagram of a one-way synchronous expected frame rate. The display screen has a reset frequency, which can also be called the display screen's anode reset frequency. The reset frequency of the display screen is an integer multiple of the display screen's frame rate; for example, the reset frequency is 240Hz. The display screen's frame rate can include 120Hz, 80Hz, 60Hz, 30Hz, or 1Hz, etc. When transmitting display data, the AP is the transmitting device, and the display device is the receiving device. Figure 1 uses a reset frequency of 240Hz as an example for illustration.

[0052] Specifically, the sending device sends display data to the receiving device via the eDP interface at different frame rates. For example, considering transmission delay, before the end of the first time period T1, the processor sends display data D1 to the display device at a frame rate of 120Hz (the frame rate corresponding to the second time period T2). The display device begins displaying display data D1 at the start of the second time period T2 at a frame rate of 120Hz (the frame rate corresponding to the second time period T2). The second time period T2 is the next time period after the first time period T1. Similarly, before the end of the second time period T2, the processor sends display data D2 to the display device via the eDP interface at a frame rate of 80Hz (the frame rate corresponding to the third time period T3). The display device begins displaying display data D2 at the start of the third time period T3 at a frame rate of 80Hz (the frame rate corresponding to the third time period T3). The third time period T3 is the next time period after the second time period T2. Similarly, before the end of the third time period T3, the processor sends display data D3 to the display device at a frame rate of 60Hz (the frame rate corresponding to the fourth time period T4). The display device begins displaying display data D3 at a frame rate of 60Hz (the frame rate corresponding to the fourth time period T4) at the beginning of the fourth time period T4. The fourth time period T4 is the next time period after the third time period T3. Similarly, before the end of the fourth time period T4, the processor sends display data D4 to the display device at a frame rate of 60Hz (the frame rate corresponding to the fifth time period T5). The display device begins displaying display data D4 at a frame rate of 60Hz (the frame rate corresponding to the fifth time period T5) at the beginning of the fifth time period T5. The fifth time period T5 is the next time period after the fourth time period T4. As shown in Figure 1, the processor's expected frame rate changes are 120Hz, 80Hz, and 60Hz, and the display device's frame rate changes are also 120Hz, 80Hz, and 60Hz, maintaining expected synchronization between the display device's frame rate and the processor's frame rate. Figure 1 illustrates the interaction process between the processor and the display device, but does not show the eDP interface.

[0053] However, in practical applications, external interference can cause slight deviations in the processor's frame rate. Furthermore, since the interaction between the display device and the processor is one-way, the processor cannot know the status of the display device, resulting in the processor's frame rate being out of sync with the display device's frame rate. In other words, there is a level difference between the processor's frame rate and the display device's frame rate, which may cause screen flickering and affect the smoothness of the display.

[0054] For example, Figure 2 is a schematic diagram of a one-way synchronous actual frame rate provided in an embodiment of this application. As shown in Figure 2, during the third time period T3, external interference causes the processor to send display data D3 to the display device at a frame rate of 60Hz (the frame rate corresponding to the fourth time period T4) at the beginning of the fourth time period T4 (i.e., the first reset time of the display screen in the fourth time period T4). After receiving the display data D3, the display device displays the display data D3 at a frame rate of 80Hz after a delay of 240Hz (i.e., the second reset time of the display screen in the fourth time period T4). The processor expects the frame rate to change to 120Hz, 80Hz, and 60Hz, while the actual frame rate change of the display device is 120Hz, 60Hz, 80Hz, and 60Hz. The frame rate of the processor and the frame rate of the display device are not synchronized during the third time period T3 and the fourth time period T4, and there is a level deviation between the frame rate of the processor and the frame rate of the display device.

[0055] Based on this, embodiments of this application provide a data display method, apparatus, and electronic device. The data display method can keep the frame rate of the processor consistent with the frame rate of the display device, avoid the influence of external interference on the processor frame rate, solve the problem of screen flickering in the display device due to frame rate asynchrony, and improve the display smoothness.

[0056] The data display method provided in this application can be applied to electronic devices including displays, which may include, but are not limited to, personal computers, server computers, mobile devices (such as mobile phones, tablets, media players, etc.), wearable devices, in-vehicle devices, consumer electronic devices, mobile robots, and drones. The specific structure of the electronic device is described below.

[0057] Figure 3 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device is illustrated using a laptop computer as an example. As shown in Figure 3, the electronic device may include: a memory 301, a processor 302, a sensor assembly 303, a display device 304, a power supply 305, and an input / output interface 306.

[0058] The memory 301 can be used to store data, software programs, and software modules; it mainly includes a program storage area and a data storage area. The program storage area can store the operating system and application programs required for at least one function, such as sound playback or image playback. The data storage area can store data created according to the use of the electronic device, such as audio data, image data, or spreadsheet data. Furthermore, the electronic device may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0059] The processor 302 is the control center of the electronic device. It connects various parts of the device via various interfaces and lines. By running or executing software programs and / or software modules stored in the memory 301, and by calling data stored in the memory 301, it performs various functions and processes data, thereby providing overall monitoring of the electronic device. Optionally, the processor 302 may include one or more processing units. For example, the processor 302 may include a central processing unit (CPU), an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU). Different processing units can be independent devices or integrated into one or more processors. The processor 302 can communicate with the display device 304 via an eDP interface, which features high bandwidth and low power consumption.

[0060] Sensor assembly 303 includes one or more sensors for providing status assessments of various aspects of the electronic device. Sensor assembly 303 may include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor. Sensor assembly 303 can detect acceleration / deceleration, orientation, on / off state, relative positioning of components, or temperature changes of the electronic device. Furthermore, sensor assembly 303 may also include a light sensor for detecting ambient light.

[0061] Display device 304 may include a display chip and a display screen. The display chip can communicate bidirectionally with processor 302 via an eDP interface. For example, the display chip can receive display data sent by the processor 302 via the eDP interface. The display chip can also send pulse signals to the processor 302 via the eDP interface. The pulse signals are used to indicate that the display chip can receive display data. The display chip is also used to send display data to the display screen, which is used to display the display data. The display screen can be an OLED display, or a high-resolution, high-frame-rate display. The display screen can be a touch panel, and when the screen is a touch panel, it can be implemented as a touchscreen to receive input signals from the user.

[0062] Power supply 305 is used to provide power to various components of the electronic device. Power supply 305 may include a power management system, one or more power supplies, or other components associated with the generation, management, and distribution of power by the electronic device. In embodiments of this application, power supply 305 may include the charging and discharging circuit provided herein, and power supply 305 may also include a battery pack. The charging and discharging circuit can be used to power the aforementioned components and to charge the battery pack, which can also be used to power the aforementioned components.

[0063] Input / output interface 306 provides an interface between processor 302 and peripheral interface modules, such as keyboards, mice, or universal serial bus (USB) devices.

[0064] Although not shown, the electronic device may also include audio components and communication components, such as a microphone for audio components and a wireless fidelity (WiFi) module or a Bluetooth module for communication components, which will not be described in detail in the embodiments of this application. Those skilled in the art will understand that the electronic device structure shown in FIG3 does not constitute a limitation on the electronic device, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0065] The data display method provided in this application embodiment will be described below. This data display method can be applied to an electronic device including a processor and a display device, which can be the processor and display device shown in FIG3 above. For example, the processor can be an AP, and the display device can include a display chip. In the following embodiments, the steps on the display device side are all performed by the display chip. For example, as shown in FIG4, the data display method includes the following steps.

[0066] S401: The display device sends a pulse signal to the processor. The pulse signal includes a level HN that lasts for a certain duration within the Nth time period TN. The Nth time period TN is the time period corresponding to the Nth frame rate, and N is a positive integer.

[0067] The display device may include a display screen, which may be an OLED screen. The display screen includes a finite number of frame rate levels, meaning it includes a finite number of refresh rates. Each frame rate level within the finite frame rate range is the reset frequency of the display screen. X is a positive integer greater than 1. For example, X can be equal to 2, 3, or 4. For example, the reset frequency of the display is 240Hz. The frame rate of the limited range of the display can include 5 frame rates such as 120Hz, 80Hz, 60Hz, 30Hz and 1Hz. In practical applications, the specific values ​​can be set according to user needs or the experience of relevant personnel. This application does not make any specific limitations.

[0068] Secondly, the sustained level of a pulse signal can indicate the state of the display device. For example, a sustained level in a pulse signal can indicate that the display device is ready to receive and display data. The duration of the level is shorter than the duration of the time period corresponding to that level.

[0069] Furthermore, the Nth frame rate is any one of the frame rates included in the limited frame rate range of the display screen; for example, the Nth frame rate can be any one of 120Hz, 80Hz, or 60Hz. Each frame rate within the limited frame rate range corresponds to a time period, and the time period corresponding to the Nth frame rate is the Nth time period TN.

[0070] Furthermore, the reset frequency of the display screen in the display device is an integer multiple of the frequency of the pulse signal. For example, the reset frequency of the display screen is 1, 2, 3, or 4 times the frequency of the pulse signal, etc. Optionally, it is assumed that the reset frequency of the display screen in the display device can be 240Hz, and the frequency of the pulse signal can be 240Hz, 120Hz, 80Hz, or 60Hz, etc. The embodiments in this application are not specifically limited.

[0071] The following explanation, with reference to Figure 5, illustrates different scenarios regarding the frequency of the pulse signal and the reset frequency of the display screen. The correspondence between the rising edge of the pulse signal and the transition edge of the reset frequency in Figure 5 is only used to represent the relationship between the pulse signal frequency and the reset frequency, and does not constitute a specific limitation on the transmission time of the pulse signal. Optionally, the correspondence between the falling edge of the pulse signal and the transition edge of the reset frequency can also be used to represent the relationship between the pulse signal frequency and the reset frequency; this application does not specifically limit this approach. This application uses the rising edge of the pulse signal as an example for explanation.

[0072] In one possible embodiment, the reset frequency of the display screen in the display device is twice the frequency of the pulse signal; that is, the reset frequency of the display screen in the display device is the same as the frequency of the pulse signal. In this embodiment, the display device sends pulse signals to the processor at a fixed frequency, with each time period corresponding to at least two levels. For example, when the reset frequency of the display screen is 360Hz, the frequency of the pulse signal is 360Hz, or when the reset frequency of the display screen is 240Hz, the frequency of the pulse signal is 240Hz.

[0073] For example, as shown in Figure 5(a), where the reset frequency of the display screen is 240Hz, the rising edge of each of the multiple levels in the pulse signal is consistent with the rising edge of the reset frequency. The reset frequency and the frequency of the pulse signal are the same, both being 240Hz. Each time period corresponds to at least two levels. For example, the zeroth time period T0 corresponds to two zeroth levels H0, the first time period T1 corresponds to two first levels H1, the second time period T2 corresponds to three second levels H2, the third time period T3 corresponds to four third levels H3, and the fourth time period T4 corresponds to four fourth levels H4.

[0074] The time period is the time period corresponding to the frame rate at which the processor sends display data. For example, the zero time period T0 is the time period corresponding to the zero frame rate of 120Hz, the first time period T1 is the time period corresponding to the first frame rate of 120Hz, the second time period T2 is the time period corresponding to the second frame rate of 80Hz, the third time period T3 is the time period corresponding to the third frame rate of 60Hz, and the fourth time period T4 is the time period corresponding to the fourth frame rate of 60Hz.

[0075] Optionally, the pulse signals corresponding to the multiple time periods in the embodiments of this application can be sent at once or sent multiple times, and the embodiments of this application do not specifically limit this.

[0076] In another possible embodiment, the reset frequency of the display screen in the display device is M times the frequency of the pulse signal, where M is a positive integer greater than 1. For example, when the reset frequency of the display screen is 240Hz, the frequency of the pulse signal can be 120Hz, 80Hz, 60Hz, 30Hz, or 1Hz. In this embodiment, the display device sends pulse signals to the processor at varying frequencies, and the frame rate corresponding to each time period is the same as the frequency of the pulse signal within that time period.

[0077] For example, as shown in Figure 5(b), which uses a display screen reset frequency of 240Hz as an example, any two adjacent levels in the pulse signal include Q reset frequency transition edges. The reset frequency is Q+1 times the pulse signal frequency, where Q is a positive integer greater than or equal to 1. For instance, when there is one reset frequency transition edge between any two adjacent levels, the reset frequency is twice the pulse signal frequency, and the pulse signal frequency is 120Hz, so the frame rate during this time period is also 120Hz; when there are two reset frequency transition edges between any two adjacent levels, the reset frequency is three times the pulse signal frequency, and the pulse signal frequency is 80Hz, so the frame rate during this time period is also 80Hz; when there are three reset frequency transition edges between any two adjacent levels, the reset frequency is four times the pulse signal frequency, and the pulse signal frequency is 60Hz, so the frame rate during this time period is also 60Hz, and so on. Further details are omitted here.

[0078] In this example, each time period corresponds to a level. For example, the zeroth time period T0 corresponds to a zeroth level H0 with a frame rate of 120Hz, the first time period T1 corresponds to a first level H1 with a frame rate of 120Hz, the second time period T2 corresponds to a second level H2 with a frame rate of 80Hz, the third time period T3 corresponds to a third level H3 with a frame rate of 60Hz, and the fourth time period T4 corresponds to a fourth level H4 with a frame rate of 60Hz.

[0079] Furthermore, within the time period corresponding to each finite frame rate level, the pulse signal includes a level that lasts for a certain duration. In the following embodiment, the finite frame rates of the display screen can include 120Hz, 80Hz, and 60Hz as examples. Within the first time period T1 corresponding to the 120Hz frame rate, the pulse signal includes a first level H1 that lasts for a certain duration; within the second time period T2 corresponding to the 80Hz frame rate, the pulse signal includes a second level H2 that lasts for a certain duration; and within the third time period T3 corresponding to the 60Hz frame rate, the pulse signal includes a third level H3 that lasts for a certain duration. The duration of the level within each time period is less than the duration of the time period in which the level exists.

[0080] S402: The processor receives a pulse signal from the display device.

[0081] Since the display device can send pulse signals to the processor at a fixed frequency or at a varying frequency, the different situations will be explained below with reference to Figures 6 to 10.

[0082] In one possible embodiment, the display device sends pulse signals to the processor at a varying frequency, the frequency of which is the same as the frame rate corresponding to that time period, with each time period corresponding to a different level. The method provided in this application also includes:

[0083] S403a: The processor responds to the Nth level HN of the pulse signal and sends display data at the N+1th frame rate before the end of the Nth time period TN. The display data is the display data of the N+1th time period TN+1. The N+1th time period TN+1 is the next time period of the Nth time period TN, and the N+1th time period TN+1 is the time period corresponding to the N+1th frame rate.

[0084] The N+1th frame rate is any one of the frame rates in the limited range of the display screen. For example, the N+1th frame rate can be any one of 120Hz, 80Hz, or 60Hz.

[0085] In practical applications, the processor can determine the frame rate at which it sends display data based on the user's usage scenario and the frame rate requirements. For example, when the user's usage scenario is a high frame rate scenario, which includes, but is not limited to, video scenarios (including video and audio, video calls) and gaming scenarios, the processor sends display data at a higher frame rate, such as 120Hz or 80Hz. When the user's usage scenario is a low frame rate scenario, which includes, but is not limited to, reading scenarios or idle desktop scenarios, the processor sends display data to the display device at a lower frame rate, such as 30Hz or 1Hz.

[0086] Furthermore, the duration between the start time of the Nth level and the start time of the display data transmission is the target duration t0. The target duration t0 can be preset, for example, it can be determined during the processor design phase; the preset duration t0 can also be sent by the processor, for example, the display device sends an acquisition instruction to the processor, the acquisition instruction is used to indicate the acquisition of the processor's preset duration t0, the processor receives the acquisition instruction, and in response to the acquisition instruction sends the preset duration to the display device. This application does not specifically limit this aspect.

[0087] S404: The display device receives display data sent by the processor at the N+1th frame rate.

[0088] S405: Display this data starting at the beginning of the N+1 time period TN+1 based on the N+1 frame rate.

[0089] Specifically, the display chip in the display device receives display data and sends the display data and reset instruction information to the display screen. The display screen resets based on the reset instruction information and displays the display data at the N+1 frame rate during the N+1th time period TN+1. The start time of the N+1th time period TN+1 is the reset time when the display screen receives the reset instruction information.

[0090] For example, as shown in Figure 6, assume the processor sends display data to the display device at a first frame rate, a second frame rate, a third frame rate, and a fourth frame rate, respectively. Taking a first frame rate of 120Hz, a second frame rate of 80Hz, and third and fourth frame rates of 60Hz as an example, the time period corresponding to the first frame rate is the first time period T1, the time period corresponding to the second frame rate is the second time period T2, the time period corresponding to the third frame rate is the third time period T3, and the time period corresponding to the fourth frame rate is the fourth time period T4. The display device sends pulse signals to the processor at varying frequencies, the frequency of which is the same as the frame rate corresponding to that time period, with each time period corresponding to a different level. During the first time period T1, the display device sends pulse signals to the processor at a frequency of 120Hz; during the second time period T2, the display device sends pulse signals to the processor at a frequency of 80Hz; during the third time period T3, the display device sends pulse signals to the processor at a frequency of 60Hz; during the fourth time period T4, the display device sends pulse signals to the processor at a frequency of 60Hz. Assume that the time period preceding the first time period T1 is the zeroth time period T0.

[0091] In practical applications, considering the transmission delay of the display device sending pulse signals to the processor, and the transmission delay of the processor sending display data to the display device, the display device needs to send pulse signals to the processor before the display screen resets, that is, before the reset frequency. This allows the display device to receive display data before the next reset and start displaying that data upon the next reset. Therefore, the pulse signal is sent to the processor in the preceding time period. For example, the pulse signal is sent to the processor in the zeroth time period T0 preceding the first time period T1, and the sending process for other time periods is similar.

[0092] Specifically, please refer to Figure 6. Before the end of the zero time period T0, that is, before the first reset of the display screen (for ease of understanding, let's assume this is the first reset of the display screen), the display device sends a zero level H0 for a certain duration to the processor. After receiving the zero level H0, the processor sends display data D1 to the display device at a frame rate of 120Hz (the first frame rate) corresponding to the first time period T1. The time of sending display data D1 is earlier than the end of the zero time period T0. The display device receives display data D1 and starts displaying display data D1 at a frame rate of 120Hz (the first frame rate) at the beginning of the first time period T1 (that is, the time when the display screen is reset for the first time). Before the end of the first time period T1 (i.e. before the third reset of the display screen), the display device sends a first level H1 for a certain duration to the processor. After receiving the first level H1, the processor sends display data D2 to the display device at a frame rate of 80Hz (second frame rate) corresponding to the second time period T2. The time of sending display data D2 is earlier than the end of the first time period T1. The display device receives display data D2 and displays display data D2 at a frame rate of 80Hz (second frame rate) at the beginning of the second time period T2 (i.e. the third reset time). Before the end of the second time period T2 (i.e. before the sixth reset of the display screen), the display device sends a second level H2 for a certain duration to the processor. After receiving the second level H2, the processor sends display data D3 to the display device at a frame rate of 60Hz (third frame rate) corresponding to the third time period T3. The time of sending display data D3 is earlier than the end of the second time period T2. The display device receives display data D3 and displays display data D3 at a frame rate of 60Hz (third frame rate) at the beginning of the third time period T3 (i.e. the sixth reset time). Similarly, before the end of the third time period T3 (i.e. before the tenth reset of the display), the display device sends a third level H3 for a certain duration to the processor. After receiving the third level H3, the processor sends display data D4 to the display device at a frame rate of 60Hz (fourth frame rate) corresponding to the fourth time period T4. The time of sending display data D4 is earlier than the end of the third time period T3. The display device receives display data D4 and displays display data D4 at a frame rate of 60Hz (fourth frame rate) at the beginning of the fourth time period T4 (i.e. the tenth reset time).

[0093] Among them, display data 1 to display data 4 can be display data corresponding to the same scene, or display data corresponding to different scenes.

[0094] In addition, the duration of different voltage levels can be the same or different, and this application does not make specific limitations.

[0095] In one possible embodiment, exemplarily as shown in FIG7, the processor can send display data N times to the display device, wherein the transmission frame rate of the Nth display data DN is the Nth frame rate, the time period corresponding to the Nth frame rate is the Nth time period TN, and the level corresponding to the Nth time period TN is HN. The specific interaction process between the processor and the display device shown in FIG7 is similar to the interaction process between the processor and the display device shown in FIG6 above, and will not be described again here.

[0096] In one possible embodiment, the display device sends pulse signals to the processor at a fixed frequency. In this case, within each time period, the pulse signal sent by the display device to the processor includes at least two levels. The frequency of the pulse signal is the same as the reset frequency of the display screen. In this embodiment, the frequency of the pulse signal is an integer multiple of the frame rate. Exemplarily, as shown in FIG8, the method provided in this application embodiment further includes:

[0097] S403b: In response to the Nth level HN of the pulse signal, the processor sends display data at the (N+1)th frame rate before the end of the Nth time period. The display data is the display data for the (N+1)th time period TN+1, which is the next time period after the Nth time period TN. The (N+1)th time period TN+1 corresponds to the time period of the (N+1)th frame rate. The Nth level HN is the last Nth level HN received by the processor during the Nth time period TN.

[0098] Specifically, within the Nth time period TN, if the processor receives at least two Nth level HNs, and before receiving the last Nth level HN among the at least two Nth level HNs, the processor sends display data to the display device at the Nth frame rate; if the processor receives the last Nth level HN among the at least two Nth level HNs, the processor sends display data to the display device at the N+1th frame rate.

[0099] For example, referring to Figure 6 and as shown in Figure 9, the display device sends pulse signals to the processor at a fixed frequency. For instance, the display device sends pulse signals to the processor at a frequency of 240Hz, meaning the frequency of the pulse signal is 240Hz. Specifically, during the zero time period T0, the display device sends two zero-level signals H0 to the processor for a certain duration. During the first zero-level signal H0 in the zero time period T0, the processor does not respond to the first zero-level signal H0. After receiving the second zero-level signal H0 (i.e., the last zero-level signal H0) in the zero time period T0, the processor sends display data D1 to the display device at a frame rate of 120Hz (the first frame rate) corresponding to the first time period T1. The transmission time of display data D1 is earlier than the end time of the zero time period T0. The display device receives display data D1 and begins displaying display data D1 at a frame rate of 120Hz (the first frame rate) at the beginning time of the first time period T1 (i.e., when the display screen is reset for the first time). When the processor receives the first first level H1 in the first time period T1, it still sends the display data D1 at the first frame rate of 120Hz (i.e., it does not respond to the first first level H1). After receiving the second first level H1 (i.e., the last first level H1) in the first time period T1, it sends the display data D2 to the display device at the frame rate of 80Hz corresponding to the second time period T2. The time of sending the display data D2 is earlier than the time of ending the first time period T1. The display device receives the display data D2 and displays the display data D2 at the frame rate of 80Hz (the second frame rate) at the start time of the second time period T2 (i.e., the third reset time). When the processor receives the first and second second level H2 in the second time period T2, it does not respond to the first and second second level H2. After receiving the third (last) second level H2 in the second time period T2, it sends display data D3 to the display device at the frame rate of 60Hz (third frame rate) corresponding to the third time period. The transmission time of display data D3 is earlier than the end time of the second time period T2. The display device receives display data D3 and starts displaying display data D3 at the frame rate of 60Hz (third frame rate) at the start time of the third time period T3 (i.e., the third reset time). Similarly, the process of the fourth time period is similar to that of the third time period, and will not be described again here.

[0100] In one possible embodiment, for example as shown in FIG10, the processor can send display data N times to the display device, wherein the transmission frame rate of the Nth display data DN is the Nth frame rate, the time period corresponding to the Nth frame rate is the Nth time period TN, and the level of the pulse signal corresponding to the Nth time period is the Nth level HN. The specific interaction process between the processor and the display device shown in FIG10 is similar to the specific interaction process between the processor and the display device shown in FIG9 above, and will not be described again here.

[0101] Furthermore, after receiving the display data sent by the processor, the display device executes steps S404 and S405 in sequence.

[0102] This application provides a data display method applied to an electronic device including a display device and a processor. The data display method includes: the display device sending a pulse signal to the processor, the pulse signal including a level of duration N for a certain duration within an Nth time period, the Nth time period being the time period corresponding to the Nth frame rate, and N being a positive integer; the processor receiving the pulse signal from the display device and, in response to the Nth level of the pulse signal, sending display data at a frame rate of N+1 before the end of the Nth time period, the display data being the display data for the N+1th time period, the N+1th time period being the next time period after the Nth time period, and the N+1th time period being the time period corresponding to the N+1th frame rate; the display device receiving the display data and starting to display the display data at the beginning of the N+1th time period based on the N+1th frame rate, the N+1th time period being the next time period after the Nth time period, and the N+1th time period being the time period corresponding to the N+1th frame rate. In this process, the processor and display device employ a bidirectional synchronous frame rate mechanism to avoid the influence of external interference on the processor's frame rate, solving the problem of screen flickering caused by frame rate asynchrony and improving the display smoothness.

[0103] This application embodiment also provides a data display device, as shown in FIG11. The data display device includes a transmitting unit 111, a receiving unit 112, and a display unit 113. In this application embodiment, the transmitting unit 111 can be used to perform step S401 in the above method embodiment, and / or other steps described herein; the receiving unit 112 can be used to perform step S404 in the above method embodiment, and / or other steps described herein; the display unit 113 can be used to perform step S405 in the above method embodiment, and / or other steps described herein.

[0104] This application embodiment also provides another data display device, as shown in FIG12. The data display device includes a receiving unit 120 and a transmitting unit 121. In this application embodiment, the receiving unit 120 can be used to perform step S402 in the above method embodiment, and / or other steps described herein; the transmitting unit 120 can be used to perform steps S403a and S403b in the above method embodiment, and / or other steps described herein.

[0105] On another aspect of this application, an electronic device is also provided, comprising a processor and a display device. The display device includes a display chip and a display screen. The display device is used to execute steps S401, S404, and S405 in the above embodiments, and / or other steps described herein. The processor can be used to execute steps S402, S403a, and S403b in the above embodiments, and / or other steps described herein. This electronic device can be the electronic device shown in FIG3 above.

[0106] It is understood that all relevant content of each step involved in the above method embodiments can be referenced in the embodiments of the data display device and electronic device, and will not be repeated here.

[0107] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules or units is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another apparatus, or some features may be ignored or not executed.

[0108] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0109] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. This readable storage medium may include various media capable of storing program code, such as a USB flash drive, external hard drive, read-only memory, random access memory, magnetic disk, or optical disk. Based on this understanding, the technical solution of the embodiments of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product.

[0110] In another embodiment of this application, a readable storage medium is also provided, which stores computer instructions that, when executed by a computer, cause the display chip in the display device to perform the steps described in the above method embodiments.

[0111] In another embodiment of this application, a readable storage medium is also provided, which stores computer instructions that, when executed by a processor, cause the processor to perform the steps described in the above method embodiments.

[0112] In another embodiment of this application, a computer program product is also provided, which includes a computer program that, when run by a display device, causes the display device to perform the steps described in the method embodiments above.

[0113] In another embodiment of this application, a computer program product is also provided, which includes a computer program that, when run by a processor, causes the processor to perform the steps in the above method embodiments.

[0114] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data display method, characterized in that, The method includes: A pulse signal is sent to the processor. The pulse signal includes an Nth level that lasts for a certain duration within the Nth time period. The Nth time period is the time period corresponding to the Nth frame rate, and N is a positive integer. The processor receives display data sent at the (N+1)th frame rate, the display data being sent by the processor in response to the received Nth level, and the start time of the transmission of the display data being earlier than the end time of the Nth time period; The display data is started at the beginning of the N+1 time period based on the N+1 frame rate, where the N+1 time period is the next time period after the Nth time period and the N+1 time period is the time period corresponding to the N+1 frame rate.

2. The method according to claim 1, characterized in that, When applied in a display device, the reset frequency of the display screen in the display device is an integer multiple of the frame rate, and the reset frequency is an integer multiple of the frequency of the pulse signal.

3. The method according to claim 1 or 2, characterized in that, The duration between the start time of the Nth level and the start time of the transmission of the display data is the target duration.

4. The method according to claim 3, characterized in that, The target duration is preset; or the target duration is sent by the processor.

5. A data display method, characterized in that, The method includes: Receive a pulse signal from the display device, the pulse signal including an Nth level lasting for a certain duration within the Nth time period, the Nth time period being the time period corresponding to the Nth frame rate, and N being a positive integer; In response to the Nth level of the pulse signal, display data is transmitted at the (N+1)th frame rate before the end of the Nth time period. The display data is the display data for the (N+1)th time period, which is the next time period after the Nth time period and the time period corresponding to the (N+1)th frame rate.

6. The method according to claim 5, characterized in that, The reset frequency of the display screen in the display device is an integer multiple of the frame rate, and the reset frequency is an integer multiple of the frequency of the pulse signal.

7. The method according to claim 5 or 6, characterized in that, The duration between the start time of the Nth level and the start time of the transmission of the display data is the target duration.

8. The method according to claim 7, characterized in that, When applied to a processor, the target duration is preset; or, the target duration is sent by the processor.

9. The method according to any one of claims 5-8, characterized in that, The method further includes: During the Nth time period, if the processor receives at least two Nth levels, and before receiving the last Nth level of the at least two Nth levels, it sends the display data to the display device at the Nth frame rate; If the processor receives the last of the at least two Nth levels, the processor sends the display data to the display device at the (N+1)th frame rate.

10. A data display device, characterized in that, The device includes: A transmitting unit is used to send a pulse signal to the processor. The pulse signal includes an Nth level that lasts for a certain duration within the Nth time period. The Nth time period is the time period corresponding to the Nth frame rate, and N is a positive integer. A receiving unit is configured to receive display data sent by the processor at the (N+1)th frame rate, wherein the display data is sent by the processor in response to the received Nth level, and the start time of the transmission of the display data is earlier than the end time of the Nth time period; The display unit is configured to display the display data starting at the beginning of the N+1 time period based on the N+1 frame rate, wherein the N+1 time period is the next time period after the Nth time period and the N+1 time period is the time period corresponding to the N+1 frame rate.

11. The apparatus according to claim 10, characterized in that, The reset frequency of the display screen in the display device is an integer multiple of the frame rate, and the reset frequency is an integer multiple of the frequency of the pulse signal.

12. The apparatus according to claim 10 or 11, characterized in that, The duration between the start time of the Nth level and the start time of the transmission of the display data is the target duration.

13. The apparatus according to claim 12, characterized in that, The target duration is preset; or the target duration is sent by the processor.

14. A data display device, characterized in that, The device includes: A receiving unit is configured to receive a pulse signal from a display device, wherein the pulse signal includes an Nth level lasting for a certain duration within an Nth time period, and the Nth time period is the time period corresponding to the Nth frame rate. The transmitting unit is configured to respond to the Nth level of the pulse signal and transmit display data at a frame rate of N+1 before the end of the Nth time period. The display data is the display data for the N+1 time period, the N+1 time period is the next time period after the Nth time period, and the N+1 time period is the time period corresponding to the N+1 frame rate.

15. The apparatus according to claim 14, characterized in that, The reset frequency of the display screen in the display device is an integer multiple of the frame rate, and the reset frequency is an integer multiple of the frequency of the pulse signal.

16. The apparatus according to claim 14 or 15, characterized in that, The duration between the start time of the Nth level and the start time of the transmission of the display data is the target duration.

17. The apparatus according to claim 16, characterized in that, The data display device includes a processor, and the target duration is preset; or, the target duration is sent by the processor.

18. The apparatus according to any one of claims 14-17, characterized in that, The transmitting unit is further configured to transmit the display data to the display device at an Nth frame rate before the receiving unit receives at least two Nth levels and before receiving the last Nth level of the at least two Nth levels; The transmitting unit is further configured to, when the receiving unit receives the last of the at least two Nth levels, send the display data to the display device at a frame rate of N+1.

19. An electronic device, characterized in that, The electronic device includes a display device and a processor, the display device being configured to perform the data display method as described in any one of claims 1-4, and the processor being configured to perform the data display method as described in any one of claims 5-9.

20. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by the device, cause the device to perform the data display method as described in any one of claims 1-9.

21. A computer program product, characterized in that, The computer program product includes: a computer program that, when run by a device, causes the device to perform the data display method as described in any one of claims 1-9.

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