Display panel and display apparatus

Abstract

The present disclosure relates to the technical field of display. Provided are a display panel and a display apparatus. The display panel comprises a pixel driving circuit, wherein the pixel driving circuit comprises a P-type transistor, an N-type transistor and a capacitor. The display panel comprises a base substrate, a first gate layer, a second active layer and a third gate layer that are sequentially stacked, wherein at least part of the structure of the first gate layer is used for forming a gate electrode of the P-type transistor; at least part of the structure of the second active layer is used for forming a channel region of the N-type transistor; at least part of the structure of the third gate layer is used for forming a gate electrode of the N-type transistor; the orthographic projections of a first electrode and a second electrode of the capacitor on the base substrate at least partially overlap; the first electrode comprises part of the structure of at least one of the first gate layer, the second active layer and the third gate layer; and the second electrode comprises part of the structure of at least one of the first gate layer, the second active layer and the third gate layer. The display panel involves a simple process and has a better display effect.

Description

Display panel and display device

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Chinese Patent Application No. 202411045966.7, filed on July 31, 2024, entitled “Display panel and display device”, the disclosure of which is incorporated herein in its entirety as part of the present application. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0004] In the related art, a pixel driving circuit in a display panel can be formed using a low temperature polycrystalline oxide (LTPO) technology. The display panel can include a first gate layer, a second gate layer, and a third gate layer. Two electrodes of a capacitor in the pixel driving circuit can be formed by the first gate layer and the second gate layer, respectively. However, there is a partial overlap between the traces in the second gate layer and the third gate layer, which can cause potential problems such as low brightness horizontal lines and low brightness unevenness.

[0005] It should be noted that the information disclosed in the above BACKGROUND section is only intended to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0006] According to an aspect of the present disclosure, a display panel is provided, wherein the display panel includes a pixel driving circuit, the pixel driving circuit includes a P-type transistor, an N-type transistor, and a capacitor, and the display panel includes:

[0007] a substrate substrate;

[0008] a first gate layer located on one side of the substrate substrate, at least part of the structure of the first gate layer being used to form a gate of the P-type transistor;

[0009] a second active layer located on a side of the first gate layer away from the substrate substrate, at least part of the structure of the second active layer being used to form a channel region of the N-type transistor;

[0010] a third gate layer located on a side of the second active layer away from the substrate substrate, at least part of the structure of the third gate layer being used to form a gate of the N-type transistor;

[0011] The capacitor includes a first electrode and a second electrode located at different conductive layers, and a projection of the first electrode on the substrate and a projection of the second electrode on the substrate at least partially overlap.

[0012] The first electrode includes a partial structure of at least one of the first gate layer, the second active layer, and the third gate layer, and the second electrode includes a partial structure of at least one of the first gate layer, the second active layer, and the third gate layer.

[0013] In an example embodiment of the present disclosure, the first electrode includes:

[0014] The first conductive part is located at the first gate layer.

[0015] The second electrode includes:

[0016] The third conductive part is located at the second active layer.

[0017] The projection of the first conductive part on the substrate and the projection of the third conductive part on the substrate at least partially overlap.

[0018] Or, the first electrode includes:

[0019] The first conductive part is located at the first gate layer.

[0020] The second electrode includes:

[0021] The second conductive part is located at the third gate layer.

[0022] The projection of the first conductive part on the substrate and the projection of the second conductive part on the substrate at least partially overlap.

[0023] Or, the first electrode includes:

[0024] The third conductive part is located at the second active layer.

[0025] The second electrode includes:

[0026] The second conductive part is located at the third gate layer.

[0027] The projection of the third conductive part on the substrate and the projection of the second conductive part on the substrate at least partially overlap.

[0028] In an example embodiment of the present disclosure, the first electrode includes:

[0029] A first conductive part is located at the first gate layer;

[0030] A second conductive part is located at the third gate layer;

[0031] The second electrode comprises:

[0032] A third conductive part is located at the second active layer;

[0033] The first conductive part and the third conductive part at least partially overlap on the substrate, and the second conductive part and the third conductive part at least partially overlap on the substrate.

[0034] In an example embodiment of the present disclosure, the second electrode further comprises:

[0035] A fourth conductive part is at least partially attached to the side of the third conductive part away from the substrate, and the fourth conductive part and the third conductive part are electrically connected through the attached surface.

[0036] In an example embodiment of the present disclosure, the display panel further comprises:

[0037] A first source-drain layer is located at the side of the third gate layer away from the substrate, and part of the structure of the first source-drain layer is used to bridge different transistors in the pixel driving circuit.

[0038] The fourth conductive part is located at the first source-drain layer.

[0039] In an example embodiment of the present disclosure, the fourth conductive part and the second conductive part do not overlap on the substrate;

[0040] The fourth conductive part and the first conductive part do not overlap on the substrate, or the fourth conductive part and the first conductive part overlap on the substrate.

[0041] In an example embodiment of the present disclosure, the pixel driving circuit further comprises a driving transistor and a fifth transistor, and the display panel further comprises a light emitting unit, wherein the driving transistor is used to provide a driving current to the light emitting unit according to the gate-source voltage difference thereof, and the first electrode of the fifth transistor is connected to a power supply line, and the second electrode of the fifth transistor is connected to the first electrode of the driving transistor.

[0042] The display panel further comprises:

[0043] a first active layer between the substrate and the first gate layer, the first active layer comprising a third active part, a fifth active part, and a tenth active part, the third active part configured to form a channel region of the driving transistor, the fifth active part configured to form a channel region of the fifth transistor, the tenth active part connected between the fifth active part and the third active part, and a projection of the tenth active part on the substrate extending along a second direction;

[0044] the first gate layer comprising:

[0045] an enable signal line, a projection of the enable signal line on the substrate extending along a first direction, and a part of the enable signal line configured to form a gate of the fifth transistor, the first direction intersecting the second direction;

[0046] wherein a projection of the fourth conductive part on the substrate and a projection of the tenth active part on the substrate at least partially overlap.

[0047] In an example embodiment of the present disclosure, a projection of the first conductive part on the substrate and a projection of the second conductive part on the substrate at least partially overlap.

[0048] In an example embodiment of the present disclosure, the display panel further comprises:

[0049] a first source-drain layer on a side of the third gate layer away from the substrate, and a part of the first source-drain layer configured to bridge different transistors in the pixel driving circuit;

[0050] wherein the first source-drain layer further comprises a first bridging part, and the first bridging part is connected to the first conductive part and the second conductive part through vias, respectively.

[0051] In an example embodiment of the present disclosure, the pixel driving circuit further comprises a driving transistor and a fifth transistor, and the display panel further comprises a light emitting unit, the driving transistor configured to provide a driving current to the light emitting unit according to a gate-source voltage difference of the driving transistor, and a first electrode of the fifth transistor connected to a power supply line, and a second electrode of the fifth transistor connected to a first electrode of the driving transistor.

[0052] the display panel further comprising:

[0053] a first active layer between the substrate and the first gate layer, the first active layer comprising a third active part, the third active part configured to form a channel region of the driving transistor;

[0054] the first gate layer comprising:

[0055] An enable signal line, wherein the orthographic projection of the enable signal line on the substrate extends along a first direction, and a portion of the structure of the enable signal line is used to form the gate of the fifth transistor;

[0056] The first conductive portion includes a first body portion and a first protrusion portion. The orthographic projection of the first protrusion portion on the substrate is located on the side of the orthographic projection of the first body portion on the substrate that is away from the orthographic projection of the enable signal line on the substrate. The orthographic projection of the first body portion on the substrate covers the orthographic projection of the third active portion on the substrate.

[0057] The first bridging portion connects the first protrusion and the second conductive portion through vias.

[0058] In one exemplary embodiment of this disclosure, the first electrode includes:

[0059] A first conductive portion, wherein the first conductive portion is located in the first gate layer;

[0060] The second electrode includes:

[0061] The second conductive portion is located in the third gate layer;

[0062] A third conductive portion, wherein the third conductive portion is located in the second active layer;

[0063] Wherein, the orthographic projections of the first conductive portion and the second conductive portion on the substrate at least partially overlap, the orthographic projections of the first conductive portion and the third conductive portion on the substrate at least partially overlap, and the orthographic projections of the second conductive portion and the third conductive portion on the substrate at least partially do not overlap.

[0064] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a driving transistor and a fifth transistor, the display panel further includes a light-emitting unit, the driving transistor is used to provide driving current to the light-emitting unit according to its gate-source voltage difference, the first terminal of the fifth transistor is connected to a power supply line, and the second terminal of the fifth transistor is connected to the first terminal of the driving transistor;

[0065] The display panel also includes:

[0066] a first active layer between the first gate layer and the substrate, the first active layer comprising a third active part, a fifth active part, and a tenth active part, the third active part configured to form a channel region of the driving transistor, the fifth active part configured to form a channel region of the fifth transistor, the tenth active part connected between the fifth active part and the third active part, and a projection of the tenth active part on the substrate extending along a second direction;

[0067] the first gate layer comprises:

[0068] an enable signal line, a projection of the enable signal line on the substrate extending along a first direction, and a part of the enable signal line configured to form a gate of the fifth transistor, the first direction intersecting the second direction;

[0069] wherein a projection of the second conductive part on the substrate and a projection of the third active part on the substrate at least partially overlap, and / or a projection of the third conductive part on the substrate and a projection of the tenth active part on the substrate at least partially overlap.

[0070] In an example embodiment of the present disclosure, the display panel further comprises:

[0071] a first source-drain layer on a side of the third gate layer away from the substrate, and a part of the first source-drain layer configured to bridge different transistors in the pixel driving circuit;

[0072] wherein the first source-drain layer further comprises a first bridging part, and the first bridging part is connected to the second conductive part and the third conductive part through vias, respectively.

[0073] In an example embodiment of the present disclosure, the display panel further comprises:

[0074] a first source-drain layer on a side of the third gate layer away from the substrate, and a part of the first source-drain layer configured to bridge different transistors in the pixel driving circuit;

[0075] wherein the first electrode further comprises a second bridging part, the second bridging part is on the first source-drain layer, and the second bridging part is connected to the first conductive part through a via.

[0076] a projection of the second bridging part on the substrate and a projection of the second conductive part on the substrate at least partially overlap, and / or a projection of the second bridging part on the substrate and a projection of the third conductive part on the substrate at least partially overlap.

[0077] In an example embodiment of the present disclosure, the display panel further comprises a light emitting unit, and the pixel driving circuit further comprises a driving transistor, a second transistor and a fifth transistor, the driving transistor is configured to provide a driving current to the light emitting unit according to a gate-source voltage difference thereof, a first electrode of the second transistor is connected to a gate electrode of the driving transistor, a second electrode of the second transistor is connected to a second electrode of the driving transistor, and a first electrode of the fifth transistor is connected to a power supply line, and a second electrode of the fifth transistor is connected to a first electrode of the driving transistor.

[0078] The display panel further comprises:

[0079] a first gate line, a projection of the first gate line on the substrate substrate extends along a first direction, and a partial structure of the first gate line is configured to form a gate electrode of the second transistor;

[0080] an enable signal line, a projection of the enable signal line on the substrate substrate extends along the first direction, and a partial structure of the enable signal line is configured to form a gate electrode of the fifth transistor;

[0081] the first electrode and the second electrode of the capacitor are located between the projection of the first gate line on the substrate substrate and the projection of the enable signal line on the substrate substrate.

[0082] In an example embodiment of the present disclosure, the pixel driving circuit further comprises a driving transistor, and the display panel further comprises a light emitting unit, the driving transistor is configured to provide a driving current to the light emitting unit according to a gate-source voltage difference thereof, a first electrode of the capacitor is connected to a gate electrode of the driving transistor, and the first conductive part is multiplexed as the gate electrode of the driving transistor.

[0083] In an example embodiment of the present disclosure, no conductive layer is arranged between the first gate electrode layer and the second active layer.

[0084] According to an aspect of the present disclosure, a display device is provided, wherein the display device comprises the display panel described above.

[0085] It should be understood that the general description above and the detailed description below are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0086] The drawings herein are incorporated into the description and form part of the description, show embodiments consistent with the present disclosure, and together with the description, serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0087] FIG. 1 is a schematic diagram of a circuit structure of a pixel driving circuit in the related art;

[0088] FIG. 2 is a timing diagram of nodes in a driving method of the pixel driving circuit in FIG. 1;

[0089] FIG. 3 is a structure layout in an exemplary embodiment of a display panel in the related art;

[0090] FIG. 4 is a structure layout of a light shielding layer in FIG. 3;

[0091] FIG. 5 is a structure layout of a first active layer in FIG. 3;

[0092] FIG. 6 is a structure layout of a first gate layer in FIG. 3;

[0093] FIG. 7 is a structure layout of a second gate layer in FIG. 3;

[0094] FIG. 8 is a structure layout of a second active layer in FIG. 3;

[0095] FIG. 9 is a structure layout of a third gate layer in FIG. 3;

[0096] FIG. 10 is a structure layout of a first source-drain layer in FIG. 3;

[0097] FIG. 11 is a structure layout of a second source-drain layer in FIG. 3;

[0098] FIG. 12 is a structure layout of the light shielding layer, the first active layer in FIG. 3;

[0099] FIG. 13 is a structure layout of the light shielding layer, the first active layer, the first gate layer in FIG. 3;

[0100] FIG. 14 is a structure layout of the light shielding layer, the first active layer, the first gate layer, the second gate layer in FIG. 3;

[0101] FIG. 15 is a structure layout of the light shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer in FIG. 3;

[0102] FIG. 16 is a structure layout of the light shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer in FIG. 3;

[0103] FIG. 17 is a structure layout of the light shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source-drain layer in FIG. 3;

[0104] FIG. 18 is a partial cross-sectional view along the dashed line AA of the display panel shown in FIG. 3;

[0105] FIG. 19 is a partial cross-sectional view in another exemplary embodiment of a display panel of the present disclosure;

[0106] FIG. 20 is a structural schematic diagram of one exemplary embodiment of a display panel of the present disclosure;

[0107] FIG. 21 is a structural schematic diagram of another exemplary embodiment of a display panel of the present disclosure;

[0108] FIG. 22 is a structural schematic diagram of one exemplary embodiment of a display panel of the present disclosure;

[0109] FIG. 23 is a partial structural layout of another exemplary embodiment of a display panel of the present disclosure;

[0110] FIG. 24 is a structural layout of a first active layer in the display panel of FIG. 23;

[0111] FIG. 25 is a structural layout of a first gate layer in the display panel of FIG. 23;

[0112] FIG. 26 is a structural layout of the first active layer and the first gate layer in the display panel of FIG. 23;

[0113] FIG. 27 is a structural layout of the first active layer, the first gate layer, and a second active layer in the display panel of FIG. 23;

[0114] FIG. 28 is a structural layout of the first active layer, the first gate layer, the second active layer, and a third gate layer in the display panel of FIG. 23;

[0115] FIG. 29 is a partial cross-sectional view of the display panel of FIG. 23 along the dotted line BB;

[0116] FIG. 30 is a partial structural layout of another exemplary embodiment of a display panel of the present disclosure;

[0117] FIG. 31 is a structural layout of a third gate layer in FIG. 30;

[0118] FIG. 32 is a structural schematic diagram of another exemplary embodiment of a display panel of the present disclosure;

[0119] FIG. 33 is a partial structural layout of another exemplary embodiment of a display panel of the present disclosure;

[0120] FIG. 34 is a structural layout of a first active layer in the display panel of FIG. 33;

[0121] FIG. 35 is a structural layout of the first active layer and a first gate layer in the display panel of FIG. 33;

[0122] FIG. 36 is a structural layout of the first active layer, the first gate layer, and a second active layer in the display panel of FIG. 33;

[0123] FIG. 37 is a structural layout of the first active layer, the first gate layer, the second active layer, and a third gate layer in the display panel of FIG. 33;

[0124] FIG. 38 is a partial cross-sectional view of the display panel shown in FIG. 33 along the dotted line CC;

[0125] FIG. 39 is a partial structure layout of another exemplary embodiment of the display panel of the present disclosure;

[0126] FIG. 40 is a cross-sectional view of the display panel shown in FIG. 39 along the dotted line DD. DETAILED DESCRIPTION

[0127] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings; however, these embodiments can be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the several views of the drawings, and description of the same elements will be omitted from the detailed description.

[0128] The terms "one", "a", "said" are used to indicate one or more of something; the terms "comprising", "having" and "including" are used to mean "including but not limited to"; the term "consisting essentially of" means "including normal, inherent variations of the materials, components and / or elements similar or equivalent to the listed materials, components and / or elements that serve substantially the same function in substantially the same way".

[0129] In the description of the present disclosure, unless otherwise clearly specified and limited, the terms "first", "second" are used only for the purpose of description, and cannot be understood as indicating or implying relative importance; the term "multiple" means two or more; the term "and / or" includes any combination and all combinations of the associated listed items. In particular, referring to "the" or "one" object is also intended to mean one of possibly multiple such objects.

[0130] Unless otherwise specified or explained, the terms "connection", "fixing", and the like should be interpreted broadly, for example, "connection" can be fixed connection, or detachable connection, or integrally connected, or electrically connected, or signal connected; "connection" can be directly connected, or indirectly connected through an intermediate medium. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0131] Further, in the description of the present disclosure, it needs to be understood that the orientation words such as "upper", "lower", "inner", "outer" and the like described in the example embodiments of the present disclosure are described in the angle shown in the drawings, and should not be understood as the limitation of the example embodiments of the present disclosure. It also needs to be understood that in the context, when referring to one element or feature connected to another element or one or more elements "on", "under", or "inner", "outer", it can not only be directly connected to another element or one or more elements "on", "under", or "inner", "outer", but also indirectly connected to another element or one or more elements "on", "under", or "inner", "outer" through an intermediate element.

[0132] As shown in FIG. 1 and FIG. 2, FIG. 1 is a schematic diagram of the circuit structure of a pixel driving circuit in the related art, and FIG. 2 is a timing diagram of each node in a driving method of the pixel driving circuit in FIG. 1.

[0133] As shown in FIG. 1, the pixel driving circuit can include a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. The first electrode of the fourth transistor T4 is connected to a data signal terminal Da, the second electrode is connected to the first electrode of the driving transistor T3, and the gate electrode is connected to a second gate driving signal terminal G2. The first electrode of the fifth transistor T5 is connected to a first power supply terminal VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate electrode is connected to an enable signal terminal EM. The gate electrode of the driving transistor T3 is connected to a node N. The first electrode of the second transistor T2 is connected to the node N, the second electrode is connected to the second electrode of the driving transistor T3, and the gate electrode is connected to a first gate driving signal terminal G1. The first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode is connected to the second electrode of the seventh transistor T7, and the gate electrode is connected to the enable signal terminal EM. The first electrode of the seventh transistor T7 is connected to a second initial signal terminal Vinit2, and the gate electrode is connected to a second reset signal terminal Re2. The second electrode of the first transistor T1 is connected to the node N, the first electrode is connected to a first initial signal terminal Vinit1, and the gate electrode is connected to a first reset signal terminal Re1. The first electrode of the capacitor C is connected to the node N, and the second electrode is connected to the first power supply terminal VDD. The pixel driving circuit can be connected to a light emitting unit OLED. The pixel driving circuit can be used to drive the light emitting unit OLED to emit light. The light emitting unit OLED can be connected between the second electrode of the sixth transistor T6 and a second power supply terminal VSS. The first transistor T1 and the second transistor T2 can be N-type transistors, and the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type transistors.

[0134] As shown in FIG. 2, G1 represents the timing of the first gate drive signal end G1, G2 represents the timing of the second gate drive signal end G2, Re1 represents the timing of the first reset signal end Re1, Re2 represents the timing of the second reset signal end Re2, EM represents the timing of the enable signal end EM, and Da represents the timing of the data signal end Da. The driving method of the pixel driving circuit can include a first reset stage t1, a compensation stage t2, a second reset stage t3, and a light-emitting stage t4. In the first reset stage t1, the first reset signal end Re1 outputs a high-level signal, the first transistor T1 is turned on, and the first initial signal end Vinit1 inputs an initial signal to the node N. In the compensation stage t2, the first gate drive signal end G1 outputs a high-level signal, the second gate drive signal end G2 outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal end Da outputs a driving signal to write a voltage Vdata+Vth to the node N, where Vdata is the voltage of the driving signal, and Vth is the threshold voltage of the driving transistor T3. In the second reset stage t3, the second reset signal end Re2 outputs a low-level signal, the seventh transistor T7 is turned on, and the second initial signal end Vinit2 inputs an initial signal to the second electrode of the sixth transistor T6. In the light-emitting stage t4, the enable signal end EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the voltage Vdata+Vth stored in the capacitor C. According to the driving transistor output current formula I=(μWCox / 2L)(Vgs-Vth) 2 , where μ is the carrier mobility, Cox is the unit area gate capacitance, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the driving transistor gate-source voltage difference, and Vth is the driving transistor threshold voltage. The output current I=(μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 of the driving transistor in the pixel driving circuit of the present disclosure. The pixel driving circuit can avoid the influence of the threshold voltage of the driving transistor on its output current.

[0135] As shown in FIG. 3-17, FIG. 3 is a structural layout of an exemplary embodiment of a display panel in the related art, which can include a substrate, a light shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source-drain layer, and a second source-drain layer, which are sequentially stacked, and an insulating layer between the conductive layers. FIG. 4 is a structural layout of the light shielding layer in FIG. 3, FIG. 5 is a structural layout of the first active layer in FIG. 3, FIG. 6 is a structural layout of the first gate layer in FIG. 3, FIG. 7 is a structural layout of the second gate layer in FIG. 3, FIG. 8 is a structural layout of the second active layer in FIG. 3, FIG. 9 is a structural layout of the third gate layer in FIG. 3, FIG. 10 is a structural layout of the first source-drain layer in FIG. 3, FIG. 11 is a structural layout of the second source-drain layer in FIG. 3, FIG. 12 is a structural layout of the light shielding layer and the first active layer in FIG. 3, FIG. 13 is a structural layout of the light shielding layer, the first active layer, and the first gate layer in FIG. 3, FIG. 14 is a structural layout of the light shielding layer, the first active layer, the first gate layer, and the second gate layer in FIG. 3, FIG. 15 is a structural layout of the light shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in FIG. 3, FIG. 16 is a structural layout of the light shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in FIG. 3, and FIG. 17 is a structural layout of the light shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source-drain layer in FIG. 3.

[0136] The display panel can include a plurality of pixel driving circuits as shown in FIG. 1. As shown in FIG. 3, the plurality of pixel driving circuits can be arrayed along a first direction X and a second direction Y, wherein the first direction X and the second direction Y can intersect, for example, the first direction can be a row direction and the second direction can be a column direction.

[0137] As shown in FIG. 3, 4, and 12, the light shielding layer can include a plurality of light shielding portions 61 arrayed along the first direction X and the second direction. The light shielding layer can be a conductive structure, for example, the light shielding layer can be a light shielding metal layer.

[0138] As shown in FIG. 3, 5 and 13, the first active layer can include a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77 and an eighth active portion 78. The third active portion 73 can be used to form a channel region of the driving transistor T3; the fourth active portion 74 can be used to form a channel region of the fourth transistor T4; the fifth active portion 75 can be used to form a channel region of the fifth transistor T5; the sixth active portion 76 can be used to form a channel region of the sixth transistor T6; the seventh active portion 77 can be used to form a channel region of the seventh transistor T7; and the eighth active portion 78 is connected to a side of the fifth active portion 75 away from the third active portion 73. As shown in FIG. 12, the normal projection of the light shielding portion 61 on the substrate can cover the normal projection of the third active portion 73 on the substrate, and the light shielding portion 61 can reduce the influence of light on the characteristics of the driving transistor. In addition, the light shielding layer can be connected to a stable voltage terminal, so that the light shielding portion 61 can shield the signal of the driving transistor. The first active layer can be formed of polysilicon material, and accordingly, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 can be P-type low-temperature polysilicon thin film transistors.

[0139] As shown in FIG. 3, 6, 13, the first gate layer can include: the first conductive part 11, the second gate line G2, the enable signal line EM, the second reset signal line Re2. The second gate line G2 can be used to provide the second gate driving signal end in FIG. 1; the enable signal line EM can be used to provide the enable signal end in FIG. 1; the second reset signal line Re2 can be used to provide the second reset signal end in FIG. 1. The orthogonal projection of the second gate line G2 on the substrate substrate, the orthogonal projection of the enable signal line EM on the substrate substrate, the orthogonal projection of the second reset signal line Re2 on the substrate substrate can extend along the first direction X. Among them, the orthogonal projection of the second gate line G2 on the substrate substrate covers the orthogonal projection of the fourth active part 74 on the substrate substrate, and part of the structure of the second gate line G2 is used to form the gate of the fourth transistor. The orthogonal projection of the enable signal line EM on the substrate substrate covers the orthogonal projection of the fifth active part 75 on the substrate substrate and the orthogonal projection of the sixth active part 76 on the substrate substrate, and part of the structure of the enable signal line EM can be used to form the gate of the fifth transistor T5 and the sixth transistor T6 respectively. The orthogonal projection of the second reset signal line Re2 on the substrate substrate can cover the orthogonal projection of the seventh active part 77 on the substrate substrate, and part of the structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7. The orthogonal projection of the first conductive part 11 on the substrate substrate covers the orthogonal projection of the third active part 73 on the substrate substrate, and the first conductive part 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor. In addition, the display panel can use the first gate layer as a mask to perform conductorization processing on the first active layer, that is, the region of the first active layer covered by the first gate layer can form the channel region of the transistor, and the region not covered by the first gate layer forms the conductor structure.

[0140] As shown in FIG. 3, 7, 14, the second gate layer can include: the first initial signal line Vinit1, the third reset signal line 2Re1, the third gate line 2G1, and a plurality of second conductive parts 22. Among them, the first initial signal line Vinit1 is used to provide the first initial signal end in FIG. 1, the third reset signal line 2Re1 can be used to provide the first reset signal end in FIG. 1, and the third gate line 2G1 can be used to provide the first gate driving signal end in FIG. 1. The orthogonal projection of the first initial signal line Vinit1 on the substrate substrate, the orthogonal projection of the third reset signal line 2Re1 on the substrate substrate, and the orthogonal projection of the third gate line 2G1 on the substrate substrate can extend along the first direction X.

[0141] As shown in Figures 3, 8, and 15, the second active layer may include an active portion 81, which may include a first active portion 811 and a second active portion 812. The first active portion 811 can be used to form the channel region of the first transistor; the second active portion 812 can be used to form the channel region of the second transistor T2. The second active layer may be formed of indium gallium zinc oxide (IGaZn), and correspondingly, the first transistor T1 and the second transistor T2 may be N-type metal-oxide thin-film transistors. The orthogonal projection of the third gate line 2G1 onto the substrate may cover the orthogonal projection of the second active portion 812 onto the substrate, and a portion of the structure of the third gate line 2G1 may be used to form the bottom gate of the second transistor. The orthogonal projection of the third reset signal line 2Re1 onto the substrate may cover the orthogonal projection of the first active portion 811 onto the substrate, and a portion of the structure of the third reset signal line 2Re1 may be used to form the bottom gate of the first transistor T1.

[0142] As shown in Figures 3, 9, and 16, the third gate layer may include a first reset signal line 3Re1 and a first gate line 3G1. The orthographic projections of the first reset signal line 3Re1 and the first gate line 3G1 on the substrate can both extend along the first direction X. The first reset signal line 3Re1 can be used to provide the first reset signal terminal in Figure 1. The orthographic projection of the first reset signal line 3Re1 on the substrate can cover the orthographic projection of the first active portion 811 on the substrate. A portion of the structure of the first reset signal line 3Re1 can be used to form the top gate of the first transistor T1. Simultaneously, the first reset signal line 3Re1 can be connected to the third reset signal terminal 2Re1 through a via located in the edge routing area of ​​the display panel. The first gate line 3G1 can be used to provide the first gate drive signal terminal in FIG1. ​​The orthogonal projection of the first gate line 3G1 on the substrate can cover the orthogonal projection of the second active part 812 on the substrate. Part of the structure of the first gate line 3G1 can be used to form the top gate of the second transistor T2. At the same time, the first gate line 3G1 can be connected to the third gate line 2G1 through a via located in the edge routing area of ​​the display panel. In addition, the display panel can use the third gate layer as a mask to perform conductor processing on the second active layer. That is, the area of ​​the second active layer covered by the third gate layer can form the channel region of the transistor, and the area not covered by the third gate layer forms a conductor structure.

[0143] As shown in Figures 3, 10, and 17, the first source / drain layer may include a second bridging portion 42, a third bridging portion 43, a fourth bridging portion 44, a fifth bridging portion 45, a sixth bridging portion 46, an eighth bridging portion 48, and a second initial signal line Vinit2. The eighth bridging portion 48 can be connected to two adjacent second conductive portions 22 in the first direction via two vias, and also to two adjacent eighth active portions 78 in the first direction via vias, thereby connecting the first electrode of the fifth transistor and the second electrode of the capacitor C. The fourth bridging portion 44 can be connected to the first active layer between the sixth active portion 76 and the seventh active portion 77 via vias, thereby connecting the second electrode of the sixth transistor T6 and the first electrode of the seventh transistor T7. The fourth bridging portion 44 can be used to connect the first electrode of the light-emitting unit in the display panel. The third bridging portion 43 can be connected via vias to the first active layer between the sixth active portion 76 and the third active portion 73, and the second active layer of the second active portion 812 on the side away from the first active portion 811, to connect the second terminal of the second transistor T2, the first terminal of the sixth transistor T6, and the second terminal of the driving transistor T3. The second bridging portion 42 can be connected via vias to the second active layer between the first active portion 811 and the second active portion 812, and the first conductive portion 11, to connect the first terminal of the second transistor T2 and the gate of the driving transistor. As shown in FIG10, an opening 221 is formed on the second conductive portion 22, and a via connecting the first conductive portion 11 and the second bridging portion 42 is disposed through the opening 221. The fifth bridging portion 45 can be connected via vias to the second active layer of the first active portion 811 on the side away from the second active portion 812, and the first initial signal line Vinit1, to connect the second terminal of the first transistor and the first initial signal terminal. The sixth bridging portion 46 can be connected via a via to the first active layer of the fourth active portion 74 on the side away from the third active portion 73, thereby connecting the first electrode of the fourth transistor. The second initial signal line Vinit2 can be used to provide the second initial signal terminal in FIG1. ​​The second initial signal line Vinit2 can be connected via a via to the first active layer of the seventh active portion 77 on the side away from the sixth active portion 76, thereby connecting the second electrode of the seventh transistor and the second initial signal terminal.

[0144] As shown in Figures 3 and 11, the second source / drain layer may include multiple power lines VDD, multiple data lines Da, and a seventh bridge portion 57. The orthographic projections of power lines VDD and data lines Da onto the substrate can both extend along the second direction Y. Power lines VDD can provide the first power supply terminal in Figure 1, and data lines Da can provide the data signal terminal in Figure 1. Power lines VDD can be connected to the eighth bridge portion 48 via vias to connect the first electrode of the fifth transistor and the first power supply terminal. Data lines Da can be connected to the sixth bridge portion 46 via vias to connect the first electrode of the fourth transistor and the data signal terminal. The seventh bridge portion 57 can be connected to the fourth bridge portion 44 via vias to connect the first electrode of the seventh transistor, and the seventh bridge portion 57 can be used to connect the first electrode of the light-emitting unit.

[0145] Figure 18 shows a partial cross-sectional view along the dashed line AA of the display panel shown in Figure 3. This display panel may further include a first insulating layer 91, a second insulating layer 92, a third insulating layer 93, a fourth insulating layer 94, a fifth insulating layer 95, a first dielectric layer 96, a second dielectric layer 97, a passivation layer 98, and a planarization layer 99, wherein the substrate 90, the light-shielding layer, the first insulating layer 91, the first active layer, the second insulating layer 92, the first gate layer, the third insulating layer 93, the second gate layer, the fourth insulating layer 94, the second active layer, the fifth insulating layer 95, the third gate layer, the first dielectric layer 96, the second dielectric layer 97, the first source / drain layer, the passivation layer 98, the planarization layer 99, and the second source / drain layer are stacked sequentially. It should be understood that in other exemplary embodiments, the insulating layer between the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source / drain layer, and the second source / drain layer may have other configurations. For example, as shown in FIG19, which is a partial cross-sectional view of another exemplary embodiment of the display panel of the present disclosure, the display panel may include a substrate (including a first polyimide layer PI1, a first barrier layer Ba1, and a second polyimide layer PI2), a second barrier layer Ba2-1, a third barrier layer Ba2-2, a shielding layer BSM, a first buffer layer Bf1 (including a silicon nitride layer and a silicon oxide layer), a first active layer Poly, a first insulating layer GI1, a first gate layer Gate1, a second insulating layer GI2, a second gate layer Gate2, a first dielectric layer ILD1, a second buffer layer Bf2, a second active layer IGZO, a third insulating layer GI3, a third gate layer Gate3, a second dielectric layer ILD2, a first source / drain layer SD1, a first planarization layer PLN1, a second source / drain layer SD2, a second planarization layer PLN2, an electrode layer Ad, and a pixel defining layer PDL, which are stacked sequentially.

[0146] In related technologies, as shown in Figures 18 and 19, the two electrodes of capacitor C in the pixel driving circuit are formed by partial structures of the first gate layer and the second gate layer, respectively. However, the orthogonal projections of the traces in the second gate layer and the third gate layer onto the substrate overlap, which can lead to potential problems such as low-brightness horizontal stripes and uneven image quality in low brightness.

[0147] Based on this, an exemplary embodiment provides a display panel, the display panel including a pixel driving circuit, the pixel driving circuit including a P-type transistor, an N-type transistor, and a capacitor, the display panel including: a substrate, a first gate layer, a second active layer, and a third gate layer, the first gate layer being located on one side of the substrate, at least a portion of the structure of the first gate layer being used to form the gate of the P-type transistor; the second active layer being located on the side of the first gate layer away from the substrate, at least a portion of the structure of the second active layer being used to form the channel region of the N-type transistor; the third gate layer being located on the side of the second active layer away from the substrate, at least a portion of the structure of the third gate layer being used to form the gate of the N-type transistor; wherein, the capacitor includes a first electrode and a second electrode located in different conductive layers, the orthographic projection of the first electrode on the substrate and the orthographic projection of the second electrode on the substrate at least partially overlapping; the first electrode includes a portion of at least one of the first gate layer, the second active layer, and the third gate layer, the second electrode includes a portion of at least one of the first gate layer, the second active layer, and the third gate layer.

[0148] The display panel provided in this exemplary embodiment omits the second gate layer found in related technologies. On the one hand, this arrangement can improve potential problems such as low-brightness horizontal stripes and uneven low-brightness image quality caused by overlapping traces in the second and third gate layers; on the other hand, this arrangement can simplify the manufacturing process of the display panel. Accordingly, the first and second electrodes of the capacitor in the display panel may include a partial structure of at least one of the first gate layer, the second active layer, and the third gate layer.

[0149] Figure 20 shows a schematic diagram of an exemplary embodiment of the display panel of this disclosure. In this exemplary embodiment, the first electrode of capacitor C includes a first conductive portion 11, which is located in the first gate layer; the second electrode of capacitor C includes a third conductive portion 83, which is located in the second active layer; wherein the orthographic projection of the first conductive portion 11 on the substrate and the orthographic projection of the third conductive portion 83 on the substrate at least partially overlap.

[0150] As shown in FIG20, the display panel may further include a substrate 10, a first buffer layer 103, a first active layer Poly, a first insulating layer 104, and a second buffer layer 105. The substrate 10 may include a flexible layer 101 and a barrier layer 102. In this exemplary embodiment, the substrate 10, the first buffer layer 103, the first active layer, the first insulating layer 104, the first gate layer, the second buffer layer 105, and the second active layer are sequentially stacked.

[0151] Figure 21 shows a schematic diagram of another exemplary embodiment of the display panel of this disclosure. In this exemplary embodiment, the first electrode of the capacitor includes a first conductive portion 11, which is located in the first gate layer; the second electrode of the capacitor includes a second conductive portion 32, which is located in the third gate layer; wherein the orthographic projection of the first conductive portion 11 on the substrate and the orthographic projection of the second conductive portion 32 on the substrate at least partially overlap.

[0152] As shown in Figure 21, the display panel may further include a substrate 10, a first buffer layer 103, a first active layer (Poly), a first insulating layer 104, a second buffer layer 105, and a second insulating layer 106. The substrate 10 may include a flexible layer 101 and a barrier layer 102. In this exemplary embodiment, the substrate 10, the first buffer layer 103, the first active layer, the first insulating layer 104, the first gate layer, the second buffer layer 105, the second active layer, the second insulating layer 106, and the third gate layer are sequentially stacked.

[0153] Figure 22 shows a schematic diagram of an exemplary embodiment of the display panel of this disclosure. In this exemplary embodiment, the first electrode of the capacitor includes a third conductive portion 83, which is located in the second active layer; the second electrode of the capacitor includes a second conductive portion 32, which is located in the third gate layer; wherein the orthographic projection of the third conductive portion 83 on the substrate and the orthographic projection of the second conductive portion 32 on the substrate at least partially overlap.

[0154] As shown in Figure 22, the display panel may further include a substrate 10, a first buffer layer 103, a first active layer (Poly), a first insulating layer 104, a second buffer layer 105, and a second insulating layer 106. The substrate 10 may include a flexible layer 101 and a barrier layer 102. In this exemplary embodiment, the substrate 10, the first buffer layer 103, the first active layer, the first insulating layer 104, the first gate layer, the second buffer layer 105, the second active layer, the second insulating layer 106, and the third gate layer are sequentially stacked.

[0155] As shown in Figures 23-28, Figure 23 is a partial structural layout diagram of another exemplary embodiment of the display panel of this disclosure. The display panel includes a substrate, a first active layer, a first gate layer, a third gate layer, and a first source / drain layer stacked sequentially. An insulating layer is disposed between the conductive layers. Figure 24 is a structural layout diagram of the first active layer in the display panel shown in Figure 23; Figure 25 is a structural layout diagram of the first gate layer in the display panel shown in Figure 23; Figure 26 is a structural layout diagram of the first active layer and the first gate layer in the display panel shown in Figure 23; Figure 27 is a structural layout diagram of the first active layer, the first gate layer, and the second active layer in the display panel shown in Figure 23; and Figure 28 is a structural layout diagram of the first active layer, the first gate layer, the second active layer, and the third gate layer in the display panel shown in Figure 23. The pixel driving circuit in the display panel shown in Figure 23 can be as shown in Figure 1.

[0156] As shown in Figures 23-28, the first electrode of the capacitor may include a first conductive portion 11 and a second conductive portion 32, wherein the first conductive portion 11 is located in the first gate layer, and the second conductive portion 32 is located in the third gate layer. The second electrode of the capacitor includes a third conductive portion 83, which is located in the second active layer; wherein the orthographic projections of the first conductive portion 11 and the third conductive portion 83 on the substrate at least partially overlap, and the orthographic projections of the second conductive portion 32 and the third conductive portion 83 on the substrate at least partially overlap.

[0157] Figure 29 shows a partial cross-sectional view of the display panel shown in Figure 23 along the dashed line BB. The display panel may further include a first buffer layer 103, a first insulating layer 104, a second buffer layer 105, a second insulating layer 106, and a first dielectric layer 107, wherein the substrate 10, the first buffer layer 103, the first active layer, the first insulating layer 104, the first gate layer, the second buffer layer 105, the second active layer, the second insulating layer 106, the third gate layer, the first dielectric layer 107, and the first source / drain layer are sequentially stacked. In this exemplary embodiment, a first sub-capacitor C1 can be formed between the first conductive portion 11 and the third conductive portion 83, and a second sub-capacitor C2 can be formed between the second conductive portion 32 and the third conductive portion 83. The first sub-capacitor C1 and the second sub-capacitor C2 are connected in parallel to form capacitor C.

[0158] In this exemplary embodiment, as shown in Figures 23-29, the second electrode of the capacitor further includes a fourth conductive portion 404. The fourth conductive portion 404 is at least partially attached to the side of the third conductive portion 83 facing away from the substrate, and the fourth conductive portion 404 and the third conductive portion 83 are electrically connected through their attachment surfaces. The fourth conductive portion 404 can improve the conductivity efficiency of the third conductive portion 83, thereby increasing the power density of the capacitor and reducing power consumption during charging and discharging. Furthermore, the fourth conductive portion 404 can also improve the conductor efficiency of the third conductive portion 83. The third conductive portion 83 can be automatically doped, meaning that when the conductive layer containing the fourth conductive portion 404 is deposited on the side of the second active layer facing away from the substrate, plasma or metal atoms can be bombarded on the surface of the second active layer using a sputtering deposition process to partially conductorize the second active layer. In other words, this structure allows the second active layer to achieve conductor formation without using a doping process or adding other processes.

[0159] In this exemplary embodiment, as shown in FIG23-29, a portion of the structure of the first source / drain layer is used to bridge different transistors in the pixel driving circuit. The fourth conductive portion 404 may be located in the first source / drain layer. It should be understood that in other exemplary embodiments, the fourth conductive portion 404 may also be located in any conductive layer on the side of the second active layer away from the substrate. For example, the fourth conductive portion 404 may be located in any one or more of the third gate layer, the first source / drain layer, and the second source / drain layer.

[0160] In this exemplary embodiment, as shown in Figures 23-29, the first terminal of the fifth transistor T5 is connected to a power supply line, and the second terminal of the fifth transistor T5 is connected to the first terminal of the driving transistor T3. The first power supply line is used to provide the first power supply terminal in Figure 1. The first active layer includes a third active portion 73, a fifth active portion 75, and a tenth active portion 710. The third active portion 73 is used to form the channel region of the driving transistor T3, the fifth active portion 75 is used to form the channel region of the fifth transistor T5, and the tenth active portion 710 is connected between the fifth active portion 75 and the third active portion 73. The orthographic projection of the tenth active portion 710 on the substrate extends along the second direction Y. The first gate layer includes an enable signal line EM. The orthographic projection of the enable signal line EM on the substrate 10 extends along the first direction X. A portion of the structure of the enable signal line EM is used to form the gate of the fifth transistor T5. The first direction X and the second direction Y intersect. The orthographic projections of the fourth conductive portion 404 and the tenth active portion 710 on the substrate at least partially overlap.

[0161] In this exemplary embodiment, as shown in FIG23-29, the orthographic projection of the fourth conductive portion 404 on the substrate 10 and the orthographic projection of the second conductive portion 32 on the substrate do not overlap; and the orthographic projection of the fourth conductive portion 404 on the substrate 10 and the orthographic projection of the first conductive portion 11 on the substrate do not overlap. The orthographic projection of the first conductive portion 11 on the substrate may only cover the orthographic projection of the third active portion 73 in the first active layer on the substrate. In this exemplary embodiment, the first active layer can be conductiveized using the first gate layer as a mask.

[0162] In this exemplary embodiment, as shown in Figures 23-29, the orthographic projections of the first conductive portion 11 and the second conductive portion 32 on the substrate at least partially overlap. This arrangement reduces the area of ​​the orthographic projection of the capacitor C on the substrate, thereby facilitating the design of the pixel driving circuit.

[0163] In this exemplary embodiment, as shown in Figures 23-29, the first source / drain layer further includes a first bridging portion 41, which connects the first conductive portion 11 and the second conductive portion 32 via vias. The connected first conductive portion 11 and second conductive portion 32 form the first electrode of a capacitor.

[0164] In this exemplary embodiment, as shown in FIG23-29, the first conductive portion 11 includes a first body portion 111 and a first protrusion portion 112. The orthographic projection of the first protrusion portion 112 on the substrate is located on the side of the orthographic projection of the first body portion 111 on the substrate away from the orthographic projection of the enable signal line EM on the substrate. The orthographic projection of the first body portion 111 on the substrate covers the orthographic projection of the third active portion 73 on the substrate. The first bridging portion 41 connects the first protrusion portion 112 and the second conductive portion 32 through vias. This arrangement can bridge the first conductive portion 11 and the second conductive portion 32 through the first bridging portion 41, while also preventing the first protrusion portion 112 and the enable signal line EM from being short-circuited.

[0165] As shown in Figures 27 and 28, a first opening 831 is formed on the third conductive part 83, and a second opening 323 is formed on the second conductive part 32. The orthographic projection of the first opening 831 on the substrate and the orthographic projection of the second opening 323 on the substrate overlap. The bridging part used to bridge the gate of the driving transistor T3 and the first electrode of the second transistor T2 can be connected to the first conductive part 11 through the vias passing through the first opening 831 and the second opening 323.

[0166] It should be understood that in other exemplary embodiments, the first bridging portion 41 may also be located in other positions. For example, as shown in Figures 30 and 31, Figure 30 is a partial structural layout diagram of another exemplary embodiment of the display panel of this disclosure, and Figure 31 is a structural layout diagram of the third gate layer in Figure 30. The second conductive portion 32 includes a second body portion 321 and a second protrusion 322. The orthographic projection of the second protrusion 322 on the substrate is located on the side of the orthographic projection of the second body portion 321 on the substrate away from the orthographic projection of the enable signal line EM on the substrate. The orthographic projection of the second body portion 321 on the substrate overlaps with the orthographic projection of the first body portion 111 on the substrate. The first bridging portion 41 can connect the second protrusion 322 and the first protrusion 112 respectively through vias to connect the second conductive portion 32 and the first conductive portion 11.

[0167] The other structures of the display panel shown in Figure 30 can be the same as those of the display panel shown in Figure 23.

[0168] Figure 32 shows a schematic diagram of another exemplary embodiment of the display panel of this disclosure. Compared with the display panel shown in Figure 23, in this exemplary embodiment, the orthographic projection of the fourth conductive part 404 on the substrate can overlap with the orthographic projection of the first conductive part 11 on the substrate. This arrangement can increase the capacitance C.

[0169] This exemplary embodiment also provides another display panel, as shown in Figures 33-37. Figure 33 is a partial structural layout diagram of another exemplary embodiment of the display panel of this disclosure. The display panel includes a substrate, a first active layer, a first gate layer, a third gate layer, and a first source / drain layer stacked sequentially. An insulating layer is disposed between the conductive layers. Figure 34 is a structural layout diagram of the first active layer in the display panel shown in Figure 33; Figure 35 is a structural layout diagram of the first active layer and the first gate layer in the display panel shown in Figure 33; Figure 36 is a structural layout diagram of the first active layer, the first gate layer, and the second active layer in the display panel shown in Figure 33; and Figure 37 is a structural layout diagram of the first active layer, the first gate layer, the second active layer, and the third gate layer in the display panel shown in Figure 33. The pixel driving circuit in the display panel shown in Figure 33 can be as shown in Figure 1.

[0170] As shown in Figures 33-37, the first electrode of the capacitor includes a first conductive portion 11 located in the first gate layer; the second electrode of the capacitor includes a second conductive portion 32 and a third conductive portion 83 located in the third gate layer; the third conductive portion 83 located in the second active layer; wherein, the orthographic projections of the first conductive portion 11 and the second conductive portion 32 on the substrate at least partially overlap, the orthographic projections of the first conductive portion 11 and the third conductive portion 83 on the substrate at least partially overlap, and the orthographic projections of the second conductive portion 32 and the third conductive portion 83 on the substrate at least partially do not overlap.

[0171] Figure 38 shows a partial cross-sectional view of the display panel shown in Figure 33 along the dashed line CC. The display panel may further include a first buffer layer 103, a first insulating layer 104, a second buffer layer 105, a second insulating layer 106, and a first dielectric layer 107. In this exemplary embodiment, the substrate 10, the first buffer layer 103, the first active layer, the first insulating layer 104, the first gate layer, the second buffer layer 105, the second active layer, the second insulating layer 106, the third gate layer, the first dielectric layer 107, and the first source / drain layer are sequentially stacked. In this exemplary embodiment, a first sub-capacitor C1 can be formed between the first conductive portion 11 and the third conductive portion 83, and a second sub-capacitor C2 can be formed between the first conductive portion 11 and the second conductive portion 32. The first sub-capacitor C1 and the second sub-capacitor C2 are connected in parallel to form capacitor C.

[0172] In this exemplary embodiment, as shown in FIG33-38, the first active layer includes a third active portion 73, a fifth active portion 75, and a tenth active portion 710. The third active portion 73 is used to form the channel region of the driving transistor T3, the fifth active portion 75 is used to form the channel region of the fifth transistor T5, and the tenth active portion 710 is connected between the fifth active portion 75 and the third active portion 73, and the orthographic projection of the tenth active portion 710 on the substrate extends along the second direction Y. The first gate layer includes an enable signal line EM, the orthographic projection of the enable signal line EM on the substrate extends along the first direction X, and a portion of the structure of the enable signal line EM is used to form the gate of the fifth transistor T5. The first direction X and the second direction Y intersect. The orthographic projections of the second conductive portion 32 on the substrate and the third active portion 73 on the substrate at least partially overlap, and the orthographic projections of the third conductive portion 83 on the substrate and the tenth active portion 710 on the substrate at least partially overlap.

[0173] In this exemplary embodiment, as shown in Figures 33-38, a portion of the structure of the first source / drain layer is used to bridge different transistors in the pixel driving circuit. The first source / drain layer further includes a first bridging portion 41, which connects the second conductive portion 32 and the third conductive portion 83 via vias. The second conductive portion 32 and the third conductive portion 83 are bridged by the first bridging portion 41 to form the second electrode of a capacitor. It should be understood that in other exemplary embodiments, the first bridging portion 41 may be located at other positions.

[0174] As shown in Figures 39 and 40, Figure 39 is a partial structural layout diagram of another exemplary embodiment of the display panel of this disclosure, and Figure 40 is a cross-sectional view of the display panel shown in Figure 39 along the dashed line DD. The first electrode further includes a second bridging portion 42, which is located in the first source / drain layer and is connected to the first conductive portion 11 through a via. The orthographic projection of the second bridging portion 42 on the substrate and the orthographic projection of the second conductive portion 32 on the substrate at least partially overlap, and the orthographic projection of the second bridging portion 42 on the substrate and the orthographic projection of the third conductive portion 83 on the substrate at least partially overlap. The second bridging portion 42 and the third conductive portion 83 can form a third sub-capacitor C3, and the second bridging portion 42 and the second conductive portion 32 can form a fourth sub-capacitor C4. The first sub-capacitor C1, the second sub-capacitor C2, the third sub-capacitor C3, and the fourth sub-capacitor C4 are connected in parallel to form capacitor C.

[0175] In this exemplary embodiment, as shown in FIG33-40, the first conductive portion 11 covers the first active layer that has been conductord except for the third active portion 73. Accordingly, this exemplary embodiment cannot perform conductor processing on the first active layer using the first gate layer as a mask. This exemplary embodiment can perform conductor processing on the first active layer using photoresist as a mask. After the first active layer portion structure has been conductor processed, the photoresist can be removed.

[0176] In this exemplary embodiment, as shown in Figures 23-40, the display panel further includes: a first gate line 3G1, the orthographic projection of the first gate line 3G1 on the substrate extending along a first direction X, a portion of the structure of the first gate line 3G1 being used to form the gate of the second transistor, and the first gate line 3G1 may be located in a third gate layer. As shown in Figures 23-40, the orthographic projections of the first electrode and the second electrode of the capacitor on the substrate are located between the orthographic projection of the first gate line 3G1 on the substrate and the orthographic projection of the enable signal line EM on the substrate.

[0177] In this exemplary embodiment, as shown in Figures 23-40, the first conductive portion 11 can be reused as the gate of the driving transistor T3. The second bridging portion 42 can also be used to connect the first terminal of the second transistor and the second terminal of the first transistor.

[0178] In this exemplary embodiment, in the display panel shown in Figures 23-40, the first initial signal line for providing the first initial signal terminal can be located in other conductive layers such as the third gate layer and the first source / drain layer. Other structures of the display panel shown in Figures 23-40 can be the same as those of the display panel shown in Figure 3. Furthermore, the display panel shown in Figures 23-40 may omit the eighth bridging portion found in the display panel shown in Figure 3. Correspondingly, the fourth conductive portion 404 in the display panels shown in Figures 23 and 32 is connected to the power line via a via, and the first bridging portion in the display panels shown in Figures 33 and 39 can be connected to the power line via a via.

[0179] In the above exemplary embodiments, the insulating layers, such as the first insulating layer, second insulating layer, third insulating layer, fourth insulating layer, and fifth insulating layer, can be silicon oxide layers; the dielectric layer and passivation layer can be silicon nitride layers; the planarization layer can be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The barrier layer can be an inorganic material. The materials of the first gate layer, second gate layer, and third gate layer can be one or an alloy of molybdenum, aluminum, copper, titanium, and niobium, or a molybdenum / titanium alloy or a stack, etc. The materials of the first source / drain layer and the second source / drain layer can include metallic materials, such as one or an alloy of molybdenum, aluminum, copper, titanium, and niobium, or a molybdenum / titanium alloy or a stack, etc., or a titanium / aluminum / titanium stack.

[0180] It should be understood that in other exemplary embodiments, the pixel driving circuit in the display panel shown in FIG23-40 may also have other structures, and the other structures of the display panel shown in FIG23-40 may also be different from those of the display panel shown in FIG3.

[0181] It should be noted that the black squares drawn on the side of the first source / drain layer facing away from the substrate represent vias connecting the first source / drain layer to other layers facing the substrate.

[0182] Furthermore, the scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channels, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display panel and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The accompanying drawings described in this disclosure are merely schematic diagrams of the structure. In addition, the terms "first," "second," etc., are only used to define different structural names and do not have a specific order meaning. The same structural layer can be formed by the same patterning process. In this exemplary embodiment, the orthographic projection of a certain structure on the substrate extends along a certain direction, which can be understood as the orthographic projection of the structure on the substrate extending in a straight line or bending along that direction.

[0183] This exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, tablet computer, television, or other display device.

[0184] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0185] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0186] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A display panel, wherein, The display panel comprises a pixel driving circuit, the pixel driving circuit comprises a P-type transistor, an N-type transistor, and a capacitor, and the display panel comprises: a substrate substrate; a first gate layer located on one side of the substrate substrate, at least part of the structure of the first gate layer being used to form a gate of the P-type transistor; a second active layer located on a side of the first gate layer away from the substrate substrate, at least part of the structure of the second active layer being used to form a channel region of the N-type transistor; a third gate layer located on a side of the second active layer away from the substrate substrate, at least part of the structure of the third gate layer being used to form a gate of the N-type transistor; wherein the capacitor comprises a first electrode and a second electrode located on different conductive layers, and the orthographic projection of the first electrode on the substrate substrate and the orthographic projection of the second electrode on the substrate substrate at least partially overlap; The first electrode comprises part of the structure of at least one of the first gate layer, the second active layer, and the third gate layer, and the second electrode comprises part of the structure of at least one of the first gate layer, the second active layer, and the third gate layer.

2. The display panel of claim 1, wherein, The first electrode comprises: a first conductive part, the first conductive part being located on the first gate layer; The second electrode comprises: a third conductive part, the third conductive part being located on the second active layer; wherein the orthographic projection of the first conductive part on the substrate substrate and the orthographic projection of the third conductive part on the substrate substrate at least partially overlap; Or, the first electrode comprises: a first conductive part, the first conductive part being located on the first gate layer; The second electrode comprises: a second conductive part, the second conductive part being located on the third gate layer; wherein the orthographic projection of the first conductive part on the substrate substrate and the orthographic projection of the second conductive part on the substrate substrate at least partially overlap; Or, the first electrode comprises: a third conductive part, the third conductive part being located on the second active layer; The second electrode comprises: a second conductive part, the second conductive part being located on the third gate layer; wherein the orthographic projection of the third conductive part on the substrate substrate and the orthographic projection of the second conductive part on the substrate substrate at least partially overlap.

3. The display panel of claim 1, wherein, The first electrode comprises: a first conductive part, the first conductive part being located on the first gate layer; a second conductive part, the second conductive part being located on the third gate layer; The second electrode comprises: a third conductive part, the third conductive part being located on the second active layer; wherein the orthographic projection of the first conductive part on the substrate substrate and the orthographic projection of the third conductive part on the substrate substrate at least partially overlap, and the orthographic projection of the second conductive part on the substrate substrate and the orthographic projection of the third conductive part on the substrate substrate at least partially overlap.

4. The display panel of claim 3, wherein, The second electrode further comprises: a fourth conductive part, the fourth conductive part being at least partially attached to a side of the third conductive part away from the substrate substrate, and the fourth conductive part and the third conductive part being electrically connected through the attachment surface thereof.

5. The display panel of claim 4, wherein, The display panel further comprises: A first source-drain layer is located on a side of the third gate layer away from the substrate, and a part of the structure of the first source-drain layer is used to bridge different transistors in the pixel driving circuit. The fourth conductive part is located on the first source-drain layer.

6. The display panel of claim 4, wherein, The orthogonal projection of the fourth conductive part on the substrate and the orthogonal projection of the second conductive part on the substrate do not overlap. The orthogonal projection of the fourth conductive part on the substrate and the orthogonal projection of the first conductive part on the substrate do not overlap, or the orthogonal projection of the fourth conductive part on the substrate and the orthogonal projection of the first conductive part on the substrate overlap.

7. The display panel of claim 4, wherein, The pixel driving circuit further comprises a driving transistor and a fifth transistor, and the display panel further comprises a light emitting unit, the driving transistor is used to provide a driving current to the light emitting unit according to a gate-source voltage difference thereof, the first electrode of the fifth transistor is connected to a power supply line, and the second electrode of the fifth transistor is connected to the first electrode of the driving transistor. The display panel further comprises: A first active layer is located between the substrate and the first gate layer, and the first active layer comprises a third active part, a fifth active part and a tenth active part, the third active part is used to form a channel region of the driving transistor, the fifth active part is used to form a channel region of the fifth transistor, and the tenth active part is connected between the fifth active part and the third active part, and the orthogonal projection of the tenth active part on the substrate extends along a second direction. The first gate layer comprises: An enable signal line, the orthogonal projection of the enable signal line on the substrate extends along a first direction, and a part of the structure of the enable signal line is used to form a gate of the fifth transistor, the first direction and the second direction intersect; The orthogonal projection of the fourth conductive part on the substrate and the orthogonal projection of the tenth active part on the substrate at least partially overlap.

8. The display panel of claim 3, wherein, The orthogonal projection of the first conductive part on the substrate and the orthogonal projection of the second conductive part on the substrate at least partially overlap.

9. The display panel of claim 3, wherein, The display panel further comprises: A first source-drain layer is located on a side of the third gate layer away from the substrate, and a part of the structure of the first source-drain layer is used to bridge different transistors in the pixel driving circuit. The first source-drain layer further comprises a first bridging part, and the first bridging part is connected to the first conductive part and the second conductive part through a via hole respectively.

10. The display panel of claim 9, wherein, The pixel driving circuit further comprises a driving transistor and a fifth transistor, and the display panel further comprises a light emitting unit, the driving transistor is used to provide a driving current to the light emitting unit according to a gate-source voltage difference thereof, the first electrode of the fifth transistor is connected to a power supply line, and the second electrode of the fifth transistor is connected to the first electrode of the driving transistor. The display panel further comprises: A first active layer is located between the substrate and the first gate layer, and the first active layer comprises a third active part, a fifth active part and a tenth active part, the third active part is used to form a channel region of the driving transistor, the fifth active part is used to form a channel region of the fifth transistor, and the tenth active part is connected between the fifth active part and the third active part, and the orthogonal projection of the tenth active part on the substrate extends along a second direction. The first gate layer comprises: An enable signal line, the orthogonal projection of the enable signal line on the substrate extends along a first direction, and a part of the structure of the enable signal line is used to form a gate of the fifth transistor, the first direction and the second direction intersect; The orthogonal projection of the fourth conductive part on the substrate and the orthogonal projection of the tenth active part on the substrate at least partially overlap. An enable signal line, a part of structure of the enable signal line is used for forming a gate of the fifth transistor, a projection of the enable signal line on the substrate substrate extends along a first direction; The first conductive part includes a first body part and a first protruding part, a projection of the first protruding part on the substrate substrate is located on a side of a projection of the first body part on the substrate substrate away from a projection of the enable signal line on the substrate substrate, and a projection of the first body part on the substrate substrate covers a projection of the third active part on the substrate substrate. The first bridge part is connected to the first protruding part and the second conductive part through a via hole.

11. The display panel of claim 1, wherein, The first electrode includes: A first conductive part located in the first gate layer; The second electrode includes: A second conductive part located in the third gate layer; A third conductive part located in the second active layer; The projection of the first conductive part on the substrate substrate and the projection of the second conductive part on the substrate substrate at least partially overlap, the projection of the first conductive part on the substrate substrate and the projection of the third conductive part on the substrate substrate at least partially overlap, and the projection of the second conductive part on the substrate substrate and the projection of the third conductive part on the substrate substrate at least partially do not overlap.

12. The display panel of claim 11, wherein, The pixel driving circuit further includes a driving transistor and a fifth transistor, and the display panel further includes a light emitting unit, the driving transistor is used to provide a driving current to the light emitting unit according to a gate-source voltage difference thereof, a first electrode of the fifth transistor is connected to a power supply line, and a second electrode of the fifth transistor is connected to a first electrode of the driving transistor. The display panel further includes: A first active layer located between the first gate layer and the substrate substrate, the first active layer includes a third active part, a fifth active part and a tenth active part, the third active part is used to form a channel region of the driving transistor, the fifth active part is used to form a channel region of the fifth transistor, and the tenth active part is connected between the fifth active part and the third active part and a projection of the tenth active part on the substrate substrate extends along a second direction; The first gate layer includes: An enable signal line, a projection of the enable signal line on the substrate substrate extends along a first direction, a part of structure of the enable signal line is used for forming a gate of the fifth transistor, and the first direction and the second direction intersect; The projection of the second conductive part on the substrate substrate and the projection of the third active part on the substrate substrate at least partially overlap, and / or the projection of the third conductive part on the substrate substrate and the projection of the tenth active part on the substrate substrate at least partially overlap.

13. The display panel of claim 1, wherein, The display panel further comprises a light emitting unit, and the pixel driving circuit further comprises a driving transistor, a second transistor and a fifth transistor, the driving transistor is configured to provide a driving current to the light emitting unit according to a gate-source voltage difference thereof, a first electrode of the second transistor is connected to a gate electrode of the driving transistor, a second electrode of the second transistor is connected to a second electrode of the driving transistor, a first electrode of the fifth transistor is connected to a power supply line, and a second electrode of the fifth transistor is connected to a first electrode of the driving transistor. The display panel further comprises: a first gate line, a projection of the first gate line on the substrate substrate extends along a first direction, and a part of a structure of the first gate line is configured to form a gate electrode of the second transistor; an enable signal line, a projection of the enable signal line on the substrate substrate extends along the first direction, and a part of a structure of the enable signal line is configured to form a gate electrode of the fifth transistor; a first electrode and a second electrode of the capacitor are located between a projection of the first gate line on the substrate substrate and a projection of the enable signal line on the substrate substrate.

14. The display panel of any of claims 1-13, wherein, No conductive layer is arranged between the first gate electrode layer and the second active layer.

15. A display device, wherein, The display device comprises the display panel of any one of claims 1-14.

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