Array substrate and display device

Abstract

The present disclosure provides an array substrate and a display device. The array substrate comprises: a plurality of first metal lines; a plurality of first active patterns; a first insulating sub-layer and a second insulating sub-layer, a first insulating layer being provided with a plurality of first via holes located in a display area, the first via holes passing through the second insulating sub-layer, exposing part of the first metal lines and exposing part of the first insulating sub-layer on at least one side of the first metal lines, and the first active patterns passing through the first via holes, partially covering the first metal lines, and partially covering the first insulating layer on a side of the first metal lines; and a second metal layer located on the side of a first active layer facing away from the first insulating layer, wherein the second metal layer comprises a plurality of second metal lines located in the display area and extending in a first direction, and the orthographic projections of the second metal lines on a substrate cover the orthographic projections of the first via holes on the substrate.

Description

Array substrate and display device

[0001] Cross-reference to Related Applications

[0002] This application claims priority to the Chinese Patent Application No. 202411044794.1, filed on July 31, 2024, and entitled "Array substrate and display device", the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the technical field of semiconductor technology, and in particular to an array substrate and a display device. BACKGROUND

[0004] With the rise of the concept of the meta universe, Virtual Reality (VR) head-mounted products as port devices have attracted much attention. At present, the display products with good effects in the market are usually Micro OLED products with 3000+ PPI, but the Micro OLED products are difficult to popularize due to high cost and great process difficulty. SUMMARY

[0005] The present disclosure provides an array substrate and a display device. The array substrate has a display area and a peripheral area located at the periphery of the display area; the array substrate comprises:

[0006] a substrate;

[0007] a first metal layer located on one side of the substrate, the first metal layer comprising a plurality of first metal lines located in the display area;

[0008] a first active layer located on a side of the first metal layer away from the substrate, the first active layer comprising a plurality of first active patterns located in the display area;

[0009] a first insulating layer located on a side of the first active layer facing the substrate; the first insulating layer comprises a first sub-insulating layer located between the first metal layer and the substrate, and a second sub-insulating layer located between the first metal layer and the first active layer; the first insulating layer has a plurality of first vias located in the display area, the first vias penetrating through the second sub-insulating layer, exposing part of the first metal lines, and exposing part of the first sub-insulating layer on at least one side of the first metal lines; the first active patterns partially cover the first metal lines and the first insulating layer on the side edges of the first metal lines through the first vias;

[0010] A second metal layer is located on a side of the first active layer facing away from the first insulating layer, and the second metal layer includes: a plurality of second metal lines located in the display area and extending along a first direction; the second metal lines cover the first via in the orthographic projection of the substrate.

[0011] In a possible implementation, the first sub-insulating layer has a first surface facing away from the substrate, and the first via exposes part of the first surface; and the first active pattern covers part of the first surface.

[0012] In a possible implementation, the first sub-insulating layer has a first surface facing away from the substrate; and the first via passes through the first surface and extends to the inside of the first sub-insulating layer via the first surface.

[0013] In a possible implementation, the array substrate further includes a light-blocking layer located on a side of the first insulating layer facing the substrate.

[0014] The light-blocking layer has a hollow part; and the hollow part covers the first active pattern in the orthographic projection of the substrate.

[0015] In a possible implementation, the array substrate further includes: a plurality of pixel electrodes located in the display area; and the pixel electrode includes: a first sub-electrode; and the first active pattern further covers part of the first sub-electrode.

[0016] In a possible implementation, the first sub-electrode includes: a first sub-part, and a second sub-part connected to the first sub-part.

[0017] The first sub-part is located in the area between the orthographic projections of two adjacent first metal lines on the substrate; and the second sub-part overlaps the orthographic projections of the first metal lines on the substrate.

[0018] In a possible implementation, the second metal line includes a first outer edge and a second outer edge; and the orthographic projection of the first outer edge on the substrate is located on a side of the orthographic projection of the second outer edge on the substrate facing the first sub-electrode.

[0019] The side of the second sub-part away from the first sub-part has a third outer edge, and the third outer edge extends along the first direction; and the orthographic projection of the third outer edge on the substrate coincides with the orthographic projection of the first outer edge on the substrate.

[0020] In a possible implementation, a projection of the first sub-electrode on the substrate does not overlap with a projection of the first via on the substrate.

[0021] In a possible implementation, the first sub-electrode is located between the first active layer and the second sub-insulating layer.

[0022] In a possible implementation, the first active pattern includes a first pattern portion and a second pattern portion; a projection of the first pattern portion on the substrate overlaps with a projection of the second metal line on the substrate; a projection of the second pattern portion on the substrate does not overlap with a projection of the second metal line on the substrate.

[0023] The first sub-electrode is multiplexed with the second pattern portion, and the second pattern portion has a higher conductive performance than the first pattern portion.

[0024] In a possible implementation, the pixel electrode further includes a second sub-electrode located on a side of the second metal layer away from the substrate, and a third sub-electrode located on a side of the second sub-electrode away from the substrate and stacked with part of the second sub-electrode.

[0025] The array substrate further includes a second insulating layer located between the second metal layer and the second sub-electrode; the second insulating layer has a second via that exposes part of the first sub-portion, and the second sub-electrode is overlapped with the first sub-portion of the first sub-electrode through the second via.

[0026] In a possible implementation, the second metal line includes a second metal line main portion and a second metal line protruding portion; the second metal line main portion extends along the first direction; and the second metal line protruding portion protrudes from the second metal line main portion along a direction perpendicular to the first direction.

[0027] A projection of the second metal line protruding portion on the substrate overlaps with a projection of part of the first metal line on the substrate.

[0028] In a possible implementation, the first active pattern extends along a second direction, and a projection of the first active pattern on the substrate overlaps with a projection of the first metal line on the substrate and overlaps with a projection of the second metal line on the substrate.

[0029] In a possible implementation, a maximum width of the first active pattern in the first direction is greater than a maximum width of the first metal line in the first direction.

[0030] In a possible implementation, a maximum width of the first via in the first direction is greater than a maximum width of the first metal line in the first direction.

[0031] In a possible implementation, the first metal line comprises a first sub-data portion, a second sub-data portion, and a third sub-data portion.

[0032] The first sub-data portion and the second sub-data portion each extend along a second direction, and an outer edge extension line of the first sub-data portion extending along the second direction does not overlap the second sub-data portion; the third sub-data portion extends along the first direction, and one end of the third sub-data portion is connected to the first sub-data portion and the other end of the third sub-data portion is connected to the second sub-data portion.

[0033] In a possible implementation, a projection of the second via on the substrate overlaps a projection of the third sub-data portion on the substrate; and a projection of the first active pattern on the substrate overlaps a projection of the third sub-data portion on the substrate.

[0034] In a possible implementation, the array substrate further comprises a plurality of drive transistors located in the peripheral area; the drive transistor comprises a drive source electrode, a drive drain electrode, a drive gate electrode, and a drive active layer.

[0035] The drive source electrode, the drive drain electrode, and the first metal line are of the same layer and the same material.

[0036] In a possible implementation, the array substrate further comprises a plurality of light shielding portions located in the display area; a projection of the light shielding portion on the substrate overlaps a portion of a projection of the first active pattern on the substrate.

[0037] The light shielding portion and the drive gate electrode are of the same layer and the same material; or the light shielding portion and the drive active layer are of the same layer and the same material.

[0038] The display device provided in the embodiments of the present disclosure can also comprise the array substrate provided in the embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0039] FIG. 1A is a top view of an array substrate provided in the embodiments of the present disclosure;

[0040] FIG. 1B can be a single film layer diagram of the first metal layer in FIG. 1A;

[0041] FIG. 1C can be a diagram of the first metal line and the first via in FIG. 1A;

[0042] FIG. 1D can be a single film layer diagram of the first sub-electrode layer in FIG. 1A;

[0043] Figure 1E can be a schematic diagram of a single film layer of the first active layer in Figure 1A;

[0044] Figure 1F can be a schematic diagram of a single film layer of the second metal layer in Figure 1A;

[0045] Figure 1G can be a schematic diagram of a single film layer of the second insulating layer in Figure 1A;

[0046] Figure 1H can be a schematic diagram of film layers of the second sub-electrode and the third sub-electrode in Figure 1A;

[0047] Figure 2 can be a schematic diagram of a cross-section of Figure 1A along the dotted line e;

[0048] Figure 3 is a schematic diagram of Figure 1A with the second insulating layer removed;

[0049] Figure 4A is a second schematic diagram of an array substrate from above according to an embodiment of the present disclosure;

[0050] Figure 4B is a schematic diagram of a single film layer of the common electrode layer in Figure 4A;

[0051] Figure 5 is a first schematic diagram of a cross-section of an array substrate according to an embodiment of the present disclosure;

[0052] Figure 6 is a second schematic diagram of a cross-section of an array substrate according to an embodiment of the present disclosure;

[0053] Figure 7 is a third schematic diagram of a cross-section of an array substrate according to an embodiment of the present disclosure;

[0054] Figure 8 is a fourth schematic diagram of a cross-section of an array substrate according to an embodiment of the present disclosure;

[0055] Figure 9 is a fifth schematic diagram of a cross-section of an array substrate according to an embodiment of the present disclosure;

[0056] Figure 10 is a sixth schematic diagram of a cross-section of an array substrate according to an embodiment of the present disclosure;

[0057] Figure 11 is a third schematic diagram of an array substrate from above according to an embodiment of the present disclosure;

[0058] Figure 12A is a schematic diagram of a cross-section of an array substrate structure in which a drive active layer is formed;

[0059] Figure 12B is a schematic diagram of a cross-section of an array substrate structure in which a first sub-insulating layer is formed;

[0060] Figure 12C is a schematic diagram of a cross-section of an array substrate structure in which a second sub-insulating layer is formed;

[0061] Figure 12D is a schematic diagram of a cross-section of an array substrate structure in which a first sub-electrode is formed;

[0062] Figure 12E is a schematic diagram of an array substrate structure from above in which a first sub-electrode is formed;

[0063] FIG. 12F is a cross-sectional schematic view of an array substrate structure in which a first active pattern is formed;

[0064] FIG. 12G is a top view schematic view of an array substrate structure in which a first active pattern is formed;

[0065] FIG. 12H is a top view schematic view of an array substrate structure in which a second metal line is formed;

[0066] FIG. 12I is a cross-sectional schematic view of an array substrate structure in which a second sub-electrode is formed;

[0067] FIG. 12J is a top view schematic view of an array substrate structure in which a second sub-electrode is formed;

[0068] FIG. 12K is a cross-sectional schematic view of an array substrate structure in which a spacer is formed;

[0069] FIG. 12L is a cross-sectional schematic view of an array substrate structure in which a common electrode is formed. DETAILED DESCRIPTION

[0070] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of the present disclosure.

[0071] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning of the terms to a person of ordinary skill in the art to which the present disclosure belongs. The terms “first”, “second” and similar terms used in the present disclosure do not denote any order, quantity or importance, but are used to distinguish different components. The terms “include” or “contain” and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms “connect” or “connected” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper”, “lower”, “left”, “right” and the like are only used to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0072] As used herein, "about" or "approximately" means within a range that is acceptable to one of ordinary skill in the art given the measurement and error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ± 30%, 20%, 10%, 5% of the stated value.

[0073] In the drawings, the thicknesses of layers, films, panels, regions, etc., are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an area illustrated or described as flat can typically have rough and / or nonlinear features. Moreover, sharp angles that are illustrated can be rounded. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present claims.

[0074] In order to keep the following description of the embodiments of the present disclosure clear and concise, the detailed description of known functions and known components will be omitted.

[0075] The current best choice for ultra-high PPI is Liquid Crystal Display (LCD) technology, because in the LCD display structure, the pixel area circuit only has one switch transistor (Thin Film Transistor, TFT), which is very beneficial to realize high PPI, but the LCD transmittance is low, and it is necessary to develop a high aperture ratio backplane process scheme, especially when the PPI reaches 2000 or more, various line widths, line spacings and via sizes all reach the limit of display manufacturing equipment. With the increase of PPI to 2500 or more, the size of the metal trace needs to be further compressed (for example, it will decrease from the existing 1.5um level to 1.0um or lower), the data line can be reduced, but the size of the gate line determines the channel length of the TFT device, which usually needs to be 2.0um or more, and the oxide TFT device characteristics are unstable, when the channel length is reduced to 1.5um or less, the device is prone to conductorization problem, resulting in device failure.

[0076] In view of this, the array substrate is provided by the embodiments of the present disclosure, as shown in FIGS. 1A-1H, FIG. 2, and FIG. 3. FIG. 1B can be a schematic diagram of a single film layer of the first metal layer in FIG. 1A, FIG. 1C can be a schematic diagram of the first metal line and the first via in FIG. 1A, FIG. 1D can be a schematic diagram of a single film layer of the first sub-electrode layer in FIG. 1A, FIG. 1E can be a schematic diagram of a single film layer of the first active layer in FIG. 1A, FIG. 1F can be a schematic diagram of a single film layer of the second metal layer in FIG. 1A, FIG. 1G can be a schematic diagram of a single film layer of the second insulating layer in FIG. 1A, FIG. 1H can be a schematic diagram of the film layers of the second sub-electrode and the third sub-electrode in FIG. 1A, FIG. 2 can be a schematic diagram of a cross section of FIG. 1A along the dotted line e, and FIG. 3 is obtained by removing the second insulating layer in FIG. 1A for the purpose of clearly showing the film layers below the second insulating layer. In combination with FIG. 2, the array substrate has a display area AA and a peripheral area BB located at the periphery of the display area AA, and includes:

[0077] a substrate 1;

[0078] a first metal layer 2 located on one side of the substrate 1, the first metal layer 2 including a plurality of first metal lines 21 located in the display area AA; optionally, the first metal lines 21 can be data lines; optionally, the first metal lines 21 can be straight lines extending along the second direction Y; optionally, the first metal lines 21 can also be polyline-shaped, the main body extending along the second direction Y, and there can be a bend in some areas;

[0079] a first active layer 3 located on a side of the first metal layer 2 away from the substrate 1, the first active layer 3 including a plurality of first active patterns 31 located in the display area AA;

[0080] a first insulating layer F1 located on a side of the first active layer 3 facing the substrate 1, the first insulating layer F1 including a first sub-insulating layer F11 located between the first metal layer 2 and the substrate 1, and a second sub-insulating layer F12 located between the first metal layer 2 and the first active layer 3; the first insulating layer F1 has a plurality of first vias K1 located in the display area AA; the first via K1 penetrates the second sub-insulating layer F12, exposes part of the first metal line 21, and exposes part of the first sub-insulating layer F11 on at least one side of the first metal line 21; the first active pattern 31 partially covers the first metal line 21 and the first insulating layer F11 on the side edge of the first metal line 21 through the first via K1;

[0081] a second metal layer 4 located on a side of the first active layer 3 away from the first insulating layer F1, the second metal layer 4 including a plurality of second metal lines 41 located in the display area AA and extending along the first direction X; the second metal line 41 covers the projection of the first via K1 on the substrate 1. Optionally, the second metal line 41 can be a gate line.

[0082] In the embodiments of the present disclosure, the region of the first active pattern 31 that overlaps with the orthographic projection of the second metal line 41 can form a channel region, the first active pattern 31 covers the part of the first metal line 21 exposed by the first via K1 and part of the first insulating layer F11, and the orthographic projection of the second metal line 41 on the substrate 1 covers the orthographic projection of the first via K1 on the substrate 1, that is, the channel region of the first active pattern 31 at least includes: the part covering the side surface of the first metal line 21 away from the substrate 1, the part covering the side surface of the second sub-insulating layer F12 away from the substrate 1, and the part covering the sidewall of the first via K1. The channel region includes not only the part parallel to the surface of the substrate 1, but also the part perpendicular to the surface of the substrate 1, that is, the sidewall of the first via K1 is used to increase the channel length, and the composition of the channel region is L 总 = L 垂直 + L 水平 , L 垂直 The depth of the first via K1 is determined by the thickness of the second sub-insulating layer F12, so that the channel length of the device can be increased by increasing the depth of the first via K1 without increasing the line width of the gate line, thereby improving the problem that the high-resolution display panel may be conductive due to the shortening of the channel length, resulting in device failure. The size of the pixel region transistor can be reduced, and the second metal line 41 (gate line) is no longer restricted by the channel size, and has further space for reduction, which is beneficial to improve the resolution. In addition, in the related art, the top gate structure used by the pixel region transistor, because the first metal line 21 (data line) is thinner than the first via K1, the first metal line 21 (data line) is prone to deformation at the position of the first via K1, resulting in metal diffraction depolarization and light leakage. In the embodiments of the present disclosure, the first metal line 21 (data line) is at the bottom of the first via K1, which can ensure that the topography of the first metal line 21 (data line) is not distorted, and is beneficial to improve the light leakage problem and improve the contrast of the display panel.

[0083] In a possible implementation, referring to FIG. 2, the first sub-insulating layer F11 has a first surface S1 away from the substrate 1, and the first via K1 exposes part of the first surface S1; and the first active pattern 51 covers part of the first surface S1. In the embodiments of the present disclosure, as shown in FIG. 2, the first via K1 only penetrates the second sub-insulating layer F12 and does not extend downward to the inside of the first sub-insulating layer F11, the depth of the first via K1 is the same as the thickness of the second sub-insulating layer F12, and the L 垂直 part of the channel region is determined by the thickness of the second sub-insulating layer F12, and increasing the thickness of the second sub-insulating layer F12 can increase the length of the channel region, thereby increasing the channel length of the device without increasing the line width of the gate line.

[0084] Optionally, as shown in FIG. 2 and FIG. 3, the first via K1 exposes part of the first metal line 21, and exposes part of the first sub-insulating layer F11 on both sides of the first metal line 21; the first active pattern 31 covers the surface of the first metal line 21 exposed by the first via K1 away from the substrate 1, and covers part of the surface of the first sub-insulating layer F11 on both sides of the first metal line 21, and covers the sidewall of the second sub-insulating layer F12 exposed by the first via K1, and covers part of the surface of the second sub-insulating layer F12, that is, the first active pattern 31 covers the surface of the first metal line 21, and covers the area at the bottom of the first via K1, excluding the first metal line 21, and extends along the sidewall of the first via K1 to part of the surface of the second sub-insulating layer F12.

[0085] In a possible implementation, as shown in FIG. 6, the first sub-insulating layer F11 has a first surface S1 away from the substrate 1; the first via K1 penetrates the first surface S1 and extends to the inside of the first sub-insulating layer F11 through the first surface S1. In the embodiment of the present disclosure, the first via K1 not only penetrates the second sub-insulating layer F12, but also continues to extend downward to the inside of the first sub-insulating layer F11 below the first metal line 21. The thickness limit of the second sub-insulating layer F12 can be broken through, deep hole etching can be performed, the channel length can be further extended, and the transistor size can be further reduced, which is beneficial to realize higher resolution.

[0086] Optionally, as shown in FIG. 6, the first via K1 can only expose the second sub-insulating layer F12 and the first sub-insulating layer F11 on one side of the first metal line, that is, the first via K1 and the first metal line 21 can be designed to be misaligned, so that a greater depth of the first via K1 can be achieved. Optionally, the center of the orthographic projection of the substrate 1 of the first via K1 can be misaligned with the center of the orthographic projection of the substrate 1 of the first metal line 21.

[0087] Optionally, as shown in FIG. 6, the first active pattern 31 can cover part of the surface of the first metal line 21, extend to the bottom of the first via K1 along the sidewall on one side of the first via K1, and extend to part of the surface of the second sub-insulating layer F12 along the sidewall on the other side of the first via K1.

[0088] Optionally, as shown in FIG. 2 or FIG. 6, the first sub-insulating layer F11 can include: a first buffer layer F113, a first gate insulating layer F112 located away from the substrate 1 on one side of the first buffer layer F113, and a first interlayer dielectric layer F111 located away from the substrate 1 on one side of the first gate insulating layer F112; optionally, as shown in FIG. 6, the first via K1 can penetrate the second sub-insulating layer F12 and extend to the inside of the first interlayer dielectric layer F111.

[0089] Optionally, referring to FIG. 6, the first via K1 can have a depth greater than the thickness of the second sub-insulating layer F12 and less than the sum of the thicknesses of the second sub-insulating layer F12 and the first interlayer dielectric layer F111.

[0090] In a possible implementation, referring to FIG. 6, the array substrate further includes a light shielding layer G on the side of the first insulating layer F1 facing the substrate 1; the light shielding layer G has a hollow portion G0; the hollow portion G0 covers the orthographic projection of the first active pattern 31 on the substrate 1. In the embodiments of the present disclosure, the light shielding layer G has the hollow portion G0; the hollow portion G0 covers the orthographic projection of the first active pattern 31 on the substrate 1, that is, in the vertical region between the first active pattern 31 and the substrate 1, no light shielding portion can be arranged, so as to avoid that the first via K1 extends downward and penetrates to the light shielding portion, resulting in the connection between the first active pattern and the light shielding portion.

[0091] In a possible implementation, referring to FIGS. 1A-1H, 2 and 3, the array substrate further includes a plurality of pixel electrodes 5 in the display area; the pixel electrode 5 includes a first sub-electrode 51; and the first active pattern 31 further covers part of the first sub-electrode 51.

[0092] In a possible implementation, referring to FIGS. 1A, 1D, 2 and 3, the first sub-electrode 51 includes a first sub-portion 511 and a second sub-portion 512 connected to the first sub-portion 511; the orthographic projection of the first sub-portion 511 on the substrate 1 is located in the region between the orthographic projections of the two adjacent first metal lines 21 on the substrate 1; and the orthographic projection of the second sub-portion 512 on the substrate 1 overlaps the orthographic projection of the first metal line 21 on the substrate 1.

[0093] Optionally, referring to FIGS. 1D and 3, the orthographic projection of the first sub-portion 511 on the substrate 1 can be block-shaped; and the orthographic projection of the second sub-portion 512 on the substrate 1 can be strip-shaped, and the second sub-portion 512 can extend along a third direction Z, and optionally, the included angle between the third direction Z and the second direction Y ranges from 0° to 90°, and optionally, the included angle between the third direction Z and the second direction Y ranges from 30° to 60°.

[0094] In a possible implementation, referring to FIGS. 1A, 1D, 2 and 3, the pixel electrode 5 further includes a second sub-electrode 52 on the side of the second metal layer 4 away from the substrate 1, and a third sub-electrode 53 on the side of the second sub-electrode 52 away from the substrate 1 and partially laminated with the second sub-electrode 52; and optionally, referring to FIGS. 3 and 2, the first sub-electrode 51 can be overlapped with the first active pattern 31 through the second sub-portion 512, and the first sub-electrode 51 can be overlapped with the second sub-electrode 52 through the first sub-portion 511.

[0095] In a possible implementation, as shown in FIG. 1A, FIG. 1F, FIG. 2, and FIG. 3, the second metal line 41 includes a first outer edge w1 and a second outer edge w2; the first outer edge w1 is located on a side of the second outer edge w2 in a projection of the substrate 1 toward the first sub-electrode 51, that is, as shown in FIG. 3, the first outer edge w1 can be a lower edge of the second metal line 41, and the second outer edge w2 can be an upper edge of the second metal line 41; the third outer edge w3 of the second sub-portion 512 is located on a side of the first sub-portion 511 away from the first sub-portion 511, and the third outer edge w3 extends along the first direction X; the third outer edge w3 in the projection of the substrate 1 coincides with the first outer edge w1 in the projection of the substrate 1. In the embodiment of the present disclosure, the third outer edge w3 of the second sub-portion 512 coincides with the first outer edge w1 of the second metal line 41, which can avoid the pixel electrode 5 and the second metal line 41 from forming an overlapping capacitance, thereby affecting the normal display of the display panel.

[0096] It can be understood that the first outer edge w1 of the second metal line 41 in the projection of the substrate 1 is located on a side of the second outer edge w2 in the projection of the substrate 1 toward the first sub-electrode 51, and the second metal line 41 and the first sub-electrode 51 can be electrically connected to the same transistor.

[0097] In a possible implementation, as shown in FIG. 1A, FIG. 1F, FIG. 2, and FIG. 3, the first sub-electrode 51 in the projection of the substrate 1 does not overlap with the first via K1 in the projection of the substrate 1.

[0098] In a possible implementation, the first sub-electrode 51 can be a single film layer, for example, as shown in FIG. 1A, FIG. 1F, FIG. 2, and FIG. 3, the first sub-electrode 51 is located between the first active layer 3 and the second sub-insulating layer F12. Alternatively, the first sub-electrode 51 can be a transparent conductive layer, and the material can be indium tin oxide.

[0099] In a possible implementation, the first sub-electrode 51 can also reuse part of the first active pattern 31, for example, as shown in FIG. 7 and FIG. 8, the first active pattern 31 includes a first pattern portion 311 and a second pattern portion 312; the first pattern portion 311 in the projection of the substrate 1 overlaps with the second metal line 41 in the projection of the substrate 1; the second pattern portion 312 in the projection of the substrate 1 does not overlap with the second metal line 41 in the projection of the substrate 1; the first sub-electrode 51 reuses the second pattern portion 312, and the conductive performance of the second pattern portion 312 is higher than that of the first pattern portion 311. In the embodiment of the present disclosure, the first sub-electrode 51 reuses part of the first active pattern 31, which can omit the separate manufacturing of the first sub-electrode 51, reduce a mask process, and reduce the manufacturing cost of the array substrate.

[0100] In a possible implementation, as shown in FIG. 7, in the manufacturing process, the ion implantation process can be used to make part of the first active pattern 31 conductive as the first sub-electrode 51. In another possible implementation, as shown in FIG. 8, in the manufacturing process, after the second metal line 41 is etched, the surface of part of the first active pattern 31 can be treated by plasma to form a conductive electrode. Compared with the embodiment shown in FIG. 7, the ion implantation step can be reduced.

[0101] Optionally, as shown in FIGS. 2, 5-8, the first active pattern 31 and the second metal line 41 further have a second gate insulating layer F23; optionally, as shown in FIG. 8, the pattern of the second gate insulating layer F23 can be the same as that of the second metal line 41; optionally, the orthographic projection of the second gate insulating layer F23 on the substrate 1 can coincide with the orthographic projection of the second metal line 41 on the substrate 1.

[0102] In a possible implementation, as shown in FIGS. 1A, 1G, 2 and 3, the array substrate further includes a second insulating layer F2 between the first sub-electrode 51 and the second sub-electrode 52; the second insulating layer F2 has a second via K2, and the second sub-electrode 52 is overlapped with the first sub-portion 511 of the first sub-electrode 51 through the second via K2. In the embodiment of the present disclosure, the pixel region can be provided with only two vias, i.e., the first via K1 and the second via K2, compared with the related art in which three vias are needed in the pixel region. In the embodiment of the present disclosure, the number of vias is reduced, which is conducive to improving light leakage and improving high resolution.

[0103] Optionally, as shown in FIGS. 1A and 1G, the second vias K2 of the plurality of sub-pixels can be an integral communication structure, which is conducive to making the array substrate relatively flat at the second via K2 and the peripheral region.

[0104] Optionally, as shown in FIG. 2, the second insulating layer F2 can include a second gate insulating layer F23, a second interlayer dielectric layer F22 located on the side of the second gate insulating layer F23 away from the substrate 1, and a first planarization layer F21 located on the side of the second interlayer dielectric layer F22 away from the substrate 1; the second via K2 can penetrate the first planarization layer F21, the second interlayer dielectric layer F22, and the second gate insulating layer F23.

[0105] Optionally, as shown in FIG. 2, the array substrate can further include a third insulating layer F3 filled in the second via K2, so as to realize planarization at the position of the second via K2. Optionally, the third insulating layer F3 can be a second planarization layer.

[0106] Optionally, as shown in FIG. 2 and FIG. 3, the third sub-electrode 53 can cover the third insulating layer F3 in the orthographic projection of the substrate 1. Optionally, as shown in FIG. 2 and FIG. 3, the combination of the second sub-electrode 52 and the third sub-electrode 53 can be in a strip shape, and located in the region formed by the intersection of the adjacent two first metal lines 21 and the adjacent two second metal lines 41.

[0107] In a possible implementation, as shown in FIG. 1A, FIG. 1F, FIG. 2 and FIG. 3, the second metal line 41 includes a second metal line main part 411 and a second metal line protruding part 412; the second metal line main part 411 extends along the first direction X; the second metal line protruding part 412 protrudes from the second metal line main part 411 along a direction perpendicular to the first direction; and the orthographic projection of the second metal line protruding part 412 on the substrate 1 overlaps with the orthographic projection of the part of the first metal line 21 on the substrate 1. In the embodiment of the present disclosure, the second metal line 41 is provided with the second metal line protruding part 412 at the position corresponding to the first metal line 21, that is, the second metal line 41 increases the edge at the position corresponding to the first metal line 21 along the first metal line 21, so as to prolong the length of the transistor device channel along the first metal line 21, and ensure the stability of the transistor device characteristics.

[0108] Optionally, the width of the second metal line protruding part 412 along the first direction X can be the same as the width of the first metal line 21 along the first direction X.

[0109] In a possible implementation, as shown in FIG. 1A, FIG. 1E and FIG. 3, the first active pattern 31 extends along the second direction Y, and the orthographic projection of the first active pattern 31 on the substrate 1 overlaps with the orthographic projection of the first metal line 21 on the substrate 1 and the orthographic projection of the second metal line 41 on the substrate 1. That is, the first active pattern 31 is located at the position where the first metal line 21 and the second metal line 41 overlap; that is, in the embodiment of the present disclosure, the transistor is located at the position where the first metal line 21 and the second metal line 41 overlap.

[0110] Optionally, as shown in FIG. 1A, FIG. 1E and FIG. 3, the orthographic projection of the first active pattern 31 on the substrate 1 can be a rectangle; optionally, the orthographic projection of the first active pattern 31 on the substrate 1 can cover the orthographic projection of the first via K1 on the substrate 1; optionally, the width of the first active pattern 31 along the first direction X can be the same as the width of the first via K1 along the first direction X; and optionally, the length of the first active pattern 31 along the second direction Y can be greater than the length of the first via K1 along the second direction Y.

[0111] In a possible implementation, as shown in FIG. 1A, FIG. 1E and FIG. 3, the maximum width a1 of the first active pattern 31 along the first direction X is greater than the maximum width a2 of the first metal line 21 along the first direction X.

[0112] In a possible implementation, as shown in FIG. 1A and FIG. 3, the maximum width a3 of the first via K1 in the first direction X is greater than the maximum width a2 of the first metal line 21 in the first direction X. That is, the first via K1 exposes not only the part of the first metal line 21, but also the part of the periphery of the first metal line 21.

[0113] In a possible implementation, as shown in FIG. 1A, the first metal line 21 is in a straight line shape, and the pixel can adopt a Real RGB arrangement.

[0114] In a possible implementation, as shown in FIG. 11, the first metal line 21 includes: a first sub-data part 211, a second sub-data part 212, and a third sub-data part 213; the first sub-data part 211 and the second sub-data part 212 both extend along the second direction Y, and the outer edge extension line f of the first sub-data part 211 extending along the second direction Y does not overlap with the second sub-data part 212; the third sub-data part 213 extends along the first direction X, and one end of the third sub-data part 213 is connected with the first sub-data part 211, and the other end is connected with the second sub-data part 212. Optionally, as shown in FIG. 11, in the second direction Y, the second sub-electrode 52 and the third sub-electrode 53 can be located between two adjacent segments of the first sub-data part 211; in the first direction X, the second sub-electrode 52 and the third sub-electrode 53 can be located between two adjacent segments of the second sub-data part 212. In the embodiment of the present disclosure, the pixel arrangement can adopt a Delta RGB arrangement, and the pixel space can be increased.

[0115] In a possible implementation, as shown in FIG. 11, the orthographic projection of the first via K1 on the substrate 1 overlaps with the orthographic projection of the third sub-data part 213 on the substrate 1; the orthographic projection of the first active pattern 31 on the substrate 1 overlaps with the orthographic projection of the third sub-data part 213 on the substrate 1.

[0116] Optionally, as shown in FIG. 11, the first active pattern 31 extends along the second direction Y; optionally, as shown in FIG. 11, in two adjacent rows of sub-pixels, the second sub-part 512 of the first sub-electrode 51 can be opposite in direction.

[0117] In a possible implementation, as shown in FIG. 5-FIG. 10, the array substrate further includes: a plurality of driving transistors QT located in the peripheral area BB; the driving transistor QT includes: a driving source electrode QTA, a driving drain electrode QTB, a driving gate electrode QTC, and a driving active layer QTD; the driving source electrode QTA and the driving drain electrode QTB are of the same layer and the same material as the first metal line 21.

[0118] In a possible implementation, referring to FIGS. 5, 7-9, the array substrate further includes a plurality of light shielding portions G1 in the display area AA; a projection of the light shielding portion G1 on the substrate 1 overlaps with a portion of the first active pattern 31 projected on the substrate 1. In the embodiment of the present disclosure, the array substrate further includes the plurality of light shielding portions G1, and the increase of the light shielding portions G1 does not cause a loss of aperture ratio, and meanwhile, the light stability of the transistor is improved.

[0119] In a possible implementation, referring to FIGS. 5, 7, and 8, the light shielding portion G1 is of the same layer and material as the drive gate QTC. In this way, the light shielding portion G1 can be formed at the same time as the drive gate QTC, thereby simplifying the manufacturing process of the display panel and reducing the manufacturing cost of the display panel.

[0120] In a possible implementation, referring to FIG. 9, the light shielding portion G1 is of the same layer and material as the drive active layer QTD. In the embodiment of the present disclosure, the light shielding portion G1 can be of the same layer and material as the drive active layer QTD, and since the drive active layer QTD is of Poly-Si, it can be thinner and can absorb ultraviolet light, thereby playing a role of a shielding layer, which is beneficial to the improvement of aperture ratio and the reduction of the gap. In this way, the light shielding portion G1 can be formed at the same time as the drive active layer QTD, thereby simplifying the manufacturing process of the display panel and reducing the manufacturing cost of the display panel.

[0121] In a possible implementation, referring to FIGS. 6 or 9, the array substrate can not be provided with the light shielding portion, and the first active pattern 31 is of a metal oxide material with high light stability, and the light shielding portion can be removed.

[0122] In a possible implementation, the material of the drive active layer QTD in the peripheral area BB includes polycrystalline silicon. The material of the first active layer 3 in the display area AA can include an oxide active layer, that is, in the embodiment of the present disclosure, the transistor in the non-display area BB can be of a polycrystalline silicon active layer, which has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. The low-temperature polycrystalline silicon thin film transistor and the oxide thin film transistor are integrated on one display panel to form a low-temperature polycrystalline oxide display panel, and the advantages of both are utilized to realize high resolution (Pixel Per Inch, PPI), low-frequency driving, reduce power consumption, and improve display quality.

[0123] In a possible implementation, referring to FIGS. 4A-4B and FIG. 5, the array substrate can further include: a common electrode 7 located on the side of the pixel electrode 5 away from the substrate 1; the common electrode 7 includes: a plurality of hollows 70. In a possible implementation, the orthogonal projection of the pixel electrode 5 on the substrate 1 overlaps with the orthogonal projection of the hollows 70 on the substrate 1. Optionally, the hollows 70 can extend obliquely and cross the extending direction of the second direction Y.

[0124] In a possible implementation, referring to FIG. 5, the array substrate can further include: a second light shielding layer 81 located on the side of the common electrode 7 away from the pixel electrode 5 and directly contacting the common electrode 7, and a spacer 82 located on the side of the second light shielding layer 81 away from the pixel electrode 5; the orthogonal projection of the common electrode 7 on the substrate 1 covers the orthogonal projection of the second light shielding layer 81 on the substrate 1, and the line width of the second light shielding layer 81 is smaller than the line width of the common electrode 7; the orthogonal projection of the second light shielding layer 81 on the substrate 1 covers the orthogonal projection of the spacer 82 on the substrate 1, and the line width of the spacer 82 is smaller than the line width of the second light shielding layer 81.

[0125] Optionally, the second light shielding layer 81 can be made of blackened metal material, the spacer 82 can be made of molybdenum or aluminum (i.e., can be made of material that can be etched by wet etching), the second light shielding layer 81 and the spacer 82 can be formed by one mask process, wet etching plus dry etching, and the difference in etching bias between the spacer 82 and the second light shielding layer 81 is used to form a stepped shape of the second light shielding layer 81 and the spacer 82.

[0126] Specifically, the thickness of the second light shielding layer 81 can be 30 nm-80 nm, and the thickness of the spacer 82 can be 0.4 μm-1 μm. The second light shielding layer 81 can be used to shield the second metal line 41 and the first metal line 21, and can also be used to reduce the resistance of the common electrode 7.

[0127] In a possible implementation, the orthogonal projection of the second light shielding layer 81 on the substrate 1 covers the orthogonal projection of the first metal line 21 on the substrate 1 and the orthogonal projection of the second metal line 41 on the substrate 1; the orthogonal projection of the spacer 82 on the substrate 1 covers the orthogonal projection of the first metal line 21 on the substrate 1 and the orthogonal projection of the second metal line 41 on the substrate 1.

[0128] Specifically, the shape of the second light shielding layer 81 and the spacer 82 can be similar to the pattern shape of the common electrode 7. The second light shielding layer 81 can include first light shielding portions extending along the first direction X and second light shielding portions extending along the second direction Y, and the first light shielding portions and the second light shielding portions intersect to form a mesh structure. The spacer 82 can include first spacer portions extending along the first direction X and second spacer portions extending along the second direction Y, and the first spacer portions and the second spacer portions intersect to form a mesh structure. The mesh structure of the spacer 82 can be designed to have a relatively narrow line width, which is beneficial to improving the aperture ratio of the display panel.

[0129] In a possible implementation, referring to FIG. 5, the array substrate can further include a fourth insulating layer F4 between the pixel electrode 5 and the common electrode 7. Optionally, the fourth insulating layer F4 can be a passivation layer.

[0130] Based on the same inventive concept, the embodiments of the present disclosure further provide a display panel, which includes the array substrate provided by the embodiments of the present disclosure.

[0131] Based on the same inventive concept, the embodiments of the present disclosure further provide a display device, which includes the display panel provided by the embodiments of the present disclosure. The implementation of the display device can refer to the above-mentioned embodiments of the display panel, and the repeated parts will not be described herein.

[0132] In the embodiments of the present disclosure, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like. Other essential components of the display device should be understood by those skilled in the art, and will not be described herein, and should not be regarded as a limitation on the present disclosure.

[0133] Based on the same inventive concept, referring to FIGS. 12A-12L, the embodiments of the present disclosure further provide a manufacturing method of the display panel provided by the embodiments of the present disclosure, which includes the following steps.

[0134] Step one, forming a first buffer layer F113 and an aSi layer on a substrate 1 (the substrate 1 can be a glass substrate for example), then performing a laser annealing process and the like, and then forming a Poly-Si layer (as a driving active layer QTD) through patterning and etching, as shown in FIG. 12A;

[0135] Step two, sequentially completing a first gate insulating layer F112, a driving gate QTC of a peripheral region BB, and simultaneously, manufacturing a light shielding portion G1 of an oxide TFT in a display region AA, completing a first layer of a dielectric layer F111, and then performing a patterning and etching process, as shown in FIG. 12B;

[0136] Step three, continue to complete the first metal line 21 of display area AA, and the drive source QTA and the drive drain QTB of the peripheral area BB, which can share the first metal layer 2, then perform the film formation of the second buffer layer F12, which adopts SiO2 or SiN / SiO2 stack, or organic siloxane material, etc., and the thickness is 200nm-800nm, because the thickness of the second buffer layer F12 determines the channel length of the oxide transistor, which can be increased according to the actual device characteristics requirements, then perform the via etching of the second buffer layer F12, as shown in FIG. 12C;

[0137] Step four, complete the first sub-electrode 51, which extends to the pixel opening area and the starting position is flush with the lower edge of the subsequent second metal line 41 (gate line), as shown in FIG. 12D and FIG. 12E;

[0138] Step five, deposit the first active layer, which can select indium gallium zinc oxide (IGZO), IGTO (In-Ga-Sn-based oxide), or other doped indium zinc oxide (IZO) or indium tin zinc oxide (ITZO) material, and perform patterning as the first active pattern 31; the first active pattern 31 overlaps the first metal line 21 and the first sub-electrode 51, then deposit the second gate insulating layer F23, which selects SiO2 and the thickness is 80nm-150nm, then deposit the second metal line 41 (gate line), which selects Mo, Al, Cu or other alloy materials, and the second metal line 41 (gate line) and the first metal line 21 (data line) are perpendicular to each other, and the second metal line 41 (gate line) is specially compensated by adding a border along the first metal line 21 (data line) at the first via K1 position, so as to extend the channel length of the transistor device to ensure the device characteristics, as shown in FIG. 12F, 12G, and 12H;

[0139] Step six, complete the deposition of the second layer dielectric layer F22 and the first planarization layer F21, wherein the second layer dielectric layer F22 selects SiO2 / SiN and the thickness range is selected to be 300nm-600nm, and the first planarization layer F21 can select acrylic material or organic resin material, which requires good planarization performance and high transmittance, and the first planarization layer F21 adopts a trench design and the thickness range can be 1.0μm-2.0μm, and the second layer dielectric layer F22 is etched by taking the first planarization layer F21 as a mask, then perform the film formation and patterning of the second sub-electrode 52, as shown in FIG. 12I and FIG. 12J;

[0140] Step seven, after the subsequent third insulating layer F3 (second planarization layer) filling process and subsequent third sub-pixel electrode 53, common electrode 7 and the second light shielding layer 81 (Common metal, CM) layer, using a mask etching process to form a metal stack structure (pillow), as shown in Figure 12K, Figure 12L.

[0141] While the preferred embodiments of the disclosure have been described, additional modifications and changes can occur to those skilled in the art once they learn of the basic creative principles disclosed herein. Accordingly, it is intended that the appended claims shall cover all such modifications and changes as fall within the true spirit and scope of the disclosure.

[0142] Obviously, various modifications and changes can be made to the present application by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that the present application embrace all such modifications and changes as fall within the scope of the appended claims and their equivalents.

Claims

1. An array substrate, wherein, The array substrate comprises: a display area and a peripheral area located outside the display area; the array substrate comprises: a substrate; a first metal layer located on one side of the substrate, the first metal layer comprising a plurality of first metal lines located in the display area; a first active layer located on a side of the first metal layer away from the substrate, the first active layer comprising a plurality of first active patterns located in the display area; a first insulating layer located on a side of the first active layer facing the substrate; the first insulating layer comprising a first sub-insulating layer located between the first metal layer and the substrate, and a second sub-insulating layer located between the first metal layer and the first active layer; the first insulating layer having a plurality of first vias located in the display area, the first vias penetrating through the second sub-insulating layer, exposing part of the first metal lines, and exposing part of the first sub-insulating layer on at least one side of the first metal lines; the first active patterns partially covering the first metal lines and the first insulating layer on the side of the first metal lines through the first vias; 2. The array substrate of claim 1, wherein, a second metal layer located on a side of the first active layer away from the first insulating layer, the second metal layer comprising a plurality of second metal lines located in the display area and extending in a first direction; the second metal lines covering the first vias in the orthographic projection of the substrate in the orthographic projection of the substrate.

3. The array substrate of claim 1, wherein, The first sub-insulating layer has a first surface on a side away from the substrate, and the first vias expose part of the first surface; the first active patterns cover part of the first surface.

4. The array substrate of claim 3, wherein, The first sub-insulating layer has a first surface on a side away from the substrate; the first vias penetrate through the first surface and extend to the interior of the first sub-insulating layer through the first surface. The array substrate further comprises a light-shielding layer located on a side of the first insulating layer facing the substrate; 5. The array substrate of any one of claims 2-4, wherein, The light-shielding layer has a hollow part; the hollow part covers the first active patterns in the orthographic projection of the substrate in the orthographic projection of the substrate.

6. The array substrate of claim 5, wherein, The array substrate further comprises a plurality of pixel electrodes located in the display area; the pixel electrodes comprise a first sub-electrode; the first active patterns further cover part of the first sub-electrode. The first sub-electrode comprises a first sub-part and a second sub-part connected to the first sub-part; 7. The array substrate of claim 5, wherein, The first sub-part is located in the area between the orthographic projections of two adjacent first metal lines on the substrate in the orthographic projection of the substrate; the second sub-part overlaps the orthographic projections of the first metal lines on the substrate in the orthographic projection of the substrate. The second metal lines comprise a first outer edge and a second outer edge; the first outer edge is located on a side of the second outer edge in the orthographic projection of the substrate facing the first sub-electrode; The second sub-part has a third outer edge on a side away from the first sub-part, the third outer edge extending in the first direction; the third outer edge coincides with the first outer edge in the orthographic projection of the substrate in the orthographic projection of the substrate.

8. The array substrate of any one of claims 5-7, wherein, The first sub-electrode is not overlapped with the first via hole in the orthographic projection of the substrate.

9. The array substrate of any one of claims 5-8, wherein, The first sub-electrode is located between the first active layer and the second sub-insulating layer.

10. The array substrate of any one of claims 5-8, wherein, The first active pattern includes a first pattern part and a second pattern part; the first pattern part is overlapped with the second metal line in the orthographic projection of the substrate; the second pattern part is not overlapped with the second metal line in the orthographic projection of the substrate. The first sub-electrode is multiplexed with the second pattern part, and the second pattern part has a higher conductive performance than the first pattern part.

11. The array substrate of any one of claims 6-10, wherein, The pixel electrode further includes a second sub-electrode located on the side of the second metal layer away from the substrate, and a third sub-electrode located on the side of the second sub-electrode away from the substrate and arranged in a partial stack with the second sub-electrode. The array substrate further includes a second insulating layer located between the second metal layer and the second sub-electrode; the second insulating layer has a second via hole exposing part of the first sub-part, and the second sub-electrode is overlapped with the first sub-part of the first sub-electrode through the second via hole.

12. The array substrate of any of claims 1-11, wherein, The second metal line includes a second metal line main part and a second metal line protruding part; the second metal line main part extends along the first direction; the second metal line protruding part protrudes from the second metal line main part along a direction perpendicular to the first direction. The second metal line protruding part is overlapped with part of the first metal line in the orthographic projection of the substrate.

13. The array substrate of claim 12, wherein, The first active pattern extends along a second direction, and the orthographic projection of the first active pattern on the substrate is overlapped with the orthographic projection of the first metal line on the substrate and with the orthographic projection of the second metal line on the substrate.

14. The array substrate of claim 13, wherein, The maximum width of the first active pattern in the first direction is greater than the maximum width of the first metal line in the first direction.

15. The array substrate of any of claims 1-14, wherein, The maximum width of the first via hole in the first direction is greater than the maximum width of the first metal line in the first direction.

16. The array substrate of any of claims 1-15, wherein, The first metal line includes a first sub-data part, a second sub-data part, and a third sub-data part. The first sub-data part and the second sub-data part both extend along a second direction, and the outer edge extension line of the first sub-data part extending along the second direction is not overlapped with the second sub-data part; the third sub-data part extends along the first direction, and one end of the third sub-data part is connected with the first sub-data part and the other end is connected with the second sub-data part.

17. The array substrate of claim 16, wherein, The orthographic projection of the second via hole on the substrate is overlapped with the orthographic projection of the third sub-data part on the substrate. The orthographic projection of the first active pattern on the substrate is overlapped with the orthographic projection of the third sub-data part on the substrate.

18. The array substrate of any of claims 1-3, 5-17, wherein, The array substrate further includes a plurality of drive transistors located in the peripheral area; the drive transistor includes a drive source electrode, a drive drain electrode, a drive gate electrode, and a drive active layer. The drive source electrode, the drive drain electrode, and the first metal line are of the same layer and the same material.

19. The array substrate of claim 18, wherein, The array substrate further comprises a plurality of light shielding portions in the display area; the light shielding portions in the orthographic projection of the substrate overlap with the part of the first active pattern in the orthographic projection of the substrate; The light shielding portions are of the same layer and material as the driving gate electrodes; or the light shielding portions are of the same layer and material as the driving active layers.

20. A display device comprising: An array substrate as claimed in any of claims 1 to 19.

Images